2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
42 #include <sys/limits.h>
44 #include <sys/memdesc.h>
45 #include <sys/mutex.h>
47 #include <sys/rwlock.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
55 #include <vm/vm_extern.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_object.h>
58 #include <vm/vm_page.h>
59 #include <vm/vm_pager.h>
60 #include <vm/vm_map.h>
61 #include <machine/atomic.h>
62 #include <machine/bus.h>
63 #include <machine/md_var.h>
64 #include <machine/specialreg.h>
65 #include <x86/include/busdma_impl.h>
66 #include <x86/iommu/intel_reg.h>
67 #include <x86/iommu/busdma_dmar.h>
68 #include <x86/iommu/intel_dmar.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
72 static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context");
73 static MALLOC_DEFINE(M_DMAR_DOMAIN, "dmar_dom", "Intel DMAR Domain");
75 static void dmar_domain_unload_task(void *arg, int pending);
76 static void dmar_unref_domain_locked(struct dmar_unit *dmar,
77 struct dmar_domain *domain);
78 static void dmar_domain_destroy(struct dmar_domain *domain);
81 dmar_ensure_ctx_page(struct dmar_unit *dmar, int bus)
84 dmar_root_entry_t *re;
88 * Allocated context page must be linked.
90 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, DMAR_PGF_NOALLOC);
95 * Page not present, allocate and link. Note that other
96 * thread might execute this sequence in parallel. This
97 * should be safe, because the context entries written by both
100 TD_PREP_PINNED_ASSERT;
101 ctxm = dmar_pgalloc(dmar->ctx_obj, 1 + bus, DMAR_PGF_ZERO |
103 re = dmar_map_pgtbl(dmar->ctx_obj, 0, DMAR_PGF_NOALLOC, &sf);
105 dmar_pte_store(&re->r1, DMAR_ROOT_R1_P | (DMAR_ROOT_R1_CTP_MASK &
106 VM_PAGE_TO_PHYS(ctxm)));
107 dmar_flush_root_to_ram(dmar, re);
108 dmar_unmap_pgtbl(sf);
112 static dmar_ctx_entry_t *
113 dmar_map_ctx_entry(struct dmar_ctx *ctx, struct sf_buf **sfp)
115 dmar_ctx_entry_t *ctxp;
117 ctxp = dmar_map_pgtbl(ctx->domain->dmar->ctx_obj, 1 +
118 PCI_RID2BUS(ctx->rid), DMAR_PGF_NOALLOC | DMAR_PGF_WAITOK, sfp);
119 ctxp += ctx->rid & 0xff;
124 ctx_tag_init(struct dmar_ctx *ctx, device_t dev)
128 maxaddr = MIN(ctx->domain->end, BUS_SPACE_MAXADDR);
129 ctx->ctx_tag.common.ref_count = 1; /* Prevent free */
130 ctx->ctx_tag.common.impl = &bus_dma_dmar_impl;
131 ctx->ctx_tag.common.boundary = PCI_DMA_BOUNDARY;
132 ctx->ctx_tag.common.lowaddr = maxaddr;
133 ctx->ctx_tag.common.highaddr = maxaddr;
134 ctx->ctx_tag.common.maxsize = maxaddr;
135 ctx->ctx_tag.common.nsegments = BUS_SPACE_UNRESTRICTED;
136 ctx->ctx_tag.common.maxsegsz = maxaddr;
137 ctx->ctx_tag.ctx = ctx;
138 ctx->ctx_tag.owner = dev;
142 ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move)
144 struct dmar_unit *unit;
145 struct dmar_domain *domain;
148 domain = ctx->domain;
150 KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0),
151 ("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",
152 unit->unit, pci_get_bus(ctx->ctx_tag.owner),
153 pci_get_slot(ctx->ctx_tag.owner),
154 pci_get_function(ctx->ctx_tag.owner),
155 ctxp->ctx1, ctxp->ctx2));
157 * For update due to move, the store is not atomic. It is
158 * possible that DMAR read upper doubleword, while low
159 * doubleword is not yet updated. The domain id is stored in
160 * the upper doubleword, while the table pointer in the lower.
162 * There is no good solution, for the same reason it is wrong
163 * to clear P bit in the ctx entry for update.
165 dmar_pte_store1(&ctxp->ctx2, DMAR_CTX2_DID(domain->domain) |
167 if ((domain->flags & DMAR_DOMAIN_IDMAP) != 0 &&
168 (unit->hw_ecap & DMAR_ECAP_PT) != 0) {
169 KASSERT(domain->pgtbl_obj == NULL,
170 ("ctx %p non-null pgtbl_obj", ctx));
171 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_PASS | DMAR_CTX1_P);
173 ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0, DMAR_PGF_NOALLOC);
174 dmar_pte_store1(&ctxp->ctx1, DMAR_CTX1_T_UNTR |
175 (DMAR_CTX1_ASR_MASK & VM_PAGE_TO_PHYS(ctx_root)) |
178 dmar_flush_ctx_to_ram(unit, ctxp);
182 dmar_flush_for_ctx_entry(struct dmar_unit *dmar, bool force)
187 * If dmar declares Caching Mode as Set, follow 11.5 "Caching
188 * Mode Consideration" and do the (global) invalidation of the
189 * negative TLB entries.
191 if ((dmar->hw_cap & DMAR_CAP_CM) == 0 && !force)
193 if (dmar->qi_enabled) {
194 dmar_qi_invalidate_ctx_glob_locked(dmar);
195 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force)
196 dmar_qi_invalidate_iotlb_glob_locked(dmar);
199 error = dmar_inv_ctx_glob(dmar);
200 if (error == 0 && ((dmar->hw_ecap & DMAR_ECAP_DI) != 0 || force))
201 error = dmar_inv_iotlb_glob(dmar);
206 domain_init_rmrr(struct dmar_domain *domain, device_t dev)
208 struct dmar_map_entries_tailq rmrr_entries;
209 struct dmar_map_entry *entry, *entry1;
211 dmar_gaddr_t start, end;
216 TAILQ_INIT(&rmrr_entries);
217 dmar_dev_parse_rmrr(domain, dev, &rmrr_entries);
218 TAILQ_FOREACH_SAFE(entry, &rmrr_entries, unroll_link, entry1) {
220 * VT-d specification requires that the start of an
221 * RMRR entry is 4k-aligned. Buggy BIOSes put
222 * anything into the start and end fields. Truncate
223 * and round as neccesary.
225 * We also allow the overlapping RMRR entries, see
226 * dmar_gas_alloc_region().
228 start = entry->start;
230 entry->start = trunc_page(start);
231 entry->end = round_page(end);
232 if (entry->start == entry->end) {
233 /* Workaround for some AMI (?) BIOSes */
235 device_printf(dev, "BIOS bug: dmar%d RMRR "
236 "region (%jx, %jx) corrected\n",
237 domain->dmar->unit, start, end);
239 entry->end += DMAR_PAGE_SIZE * 0x20;
241 size = OFF_TO_IDX(entry->end - entry->start);
242 ma = malloc(sizeof(vm_page_t) * size, M_TEMP, M_WAITOK);
243 for (i = 0; i < size; i++) {
244 ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i,
247 error1 = dmar_gas_map_region(domain, entry,
248 DMAR_MAP_ENTRY_READ | DMAR_MAP_ENTRY_WRITE,
249 DMAR_GM_CANWAIT, ma);
251 * Non-failed RMRR entries are owned by context rb
252 * tree. Get rid of the failed entry, but do not stop
253 * the loop. Rest of the parsed RMRR entries are
254 * loaded and removed on the context destruction.
256 if (error1 == 0 && entry->end != entry->start) {
257 DMAR_LOCK(domain->dmar);
258 domain->refs++; /* XXXKIB prevent free */
259 domain->flags |= DMAR_DOMAIN_RMRR;
260 DMAR_UNLOCK(domain->dmar);
264 "dmar%d failed to map RMRR region (%jx, %jx) %d\n",
265 domain->dmar->unit, start, end, error1);
268 TAILQ_REMOVE(&rmrr_entries, entry, unroll_link);
269 dmar_gas_free_entry(domain, entry);
271 for (i = 0; i < size; i++)
272 vm_page_putfake(ma[i]);
278 static struct dmar_domain *
279 dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped)
281 struct dmar_domain *domain;
284 id = alloc_unr(dmar->domids);
287 domain = malloc(sizeof(*domain), M_DMAR_DOMAIN, M_WAITOK | M_ZERO);
289 LIST_INIT(&domain->contexts);
290 RB_INIT(&domain->rb_root);
291 TAILQ_INIT(&domain->unload_entries);
292 TASK_INIT(&domain->unload_task, 0, dmar_domain_unload_task, domain);
293 mtx_init(&domain->lock, "dmardom", NULL, MTX_DEF);
297 * For now, use the maximal usable physical address of the
298 * installed memory to calculate the mgaw on id_mapped domain.
299 * It is useful for the identity mapping, and less so for the
300 * virtualized bus address space.
302 domain->end = id_mapped ? ptoa(Maxmem) : BUS_SPACE_MAXADDR;
303 mgaw = dmar_maxaddr2mgaw(dmar, domain->end, !id_mapped);
304 error = domain_set_agaw(domain, mgaw);
308 /* Use all supported address space for remapping. */
309 domain->end = 1ULL << (domain->agaw - 1);
311 dmar_gas_init_domain(domain);
314 if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) {
315 domain->pgtbl_obj = domain_get_idmap_pgtbl(domain,
318 domain->flags |= DMAR_DOMAIN_IDMAP;
320 error = domain_alloc_pgtbl(domain);
323 /* Disable local apic region access */
324 error = dmar_gas_reserve_region(domain, 0xfee00000,
332 dmar_domain_destroy(domain);
336 static struct dmar_ctx *
337 dmar_ctx_alloc(struct dmar_domain *domain, uint16_t rid)
339 struct dmar_ctx *ctx;
341 ctx = malloc(sizeof(*ctx), M_DMAR_CTX, M_WAITOK | M_ZERO);
342 ctx->domain = domain;
349 dmar_ctx_link(struct dmar_ctx *ctx)
351 struct dmar_domain *domain;
353 domain = ctx->domain;
354 DMAR_ASSERT_LOCKED(domain->dmar);
355 KASSERT(domain->refs >= domain->ctx_cnt,
356 ("dom %p ref underflow %d %d", domain, domain->refs,
360 LIST_INSERT_HEAD(&domain->contexts, ctx, link);
364 dmar_ctx_unlink(struct dmar_ctx *ctx)
366 struct dmar_domain *domain;
368 domain = ctx->domain;
369 DMAR_ASSERT_LOCKED(domain->dmar);
370 KASSERT(domain->refs > 0,
371 ("domain %p ctx dtr refs %d", domain, domain->refs));
372 KASSERT(domain->ctx_cnt >= domain->refs,
373 ("domain %p ctx dtr refs %d ctx_cnt %d", domain,
374 domain->refs, domain->ctx_cnt));
377 LIST_REMOVE(ctx, link);
381 dmar_domain_destroy(struct dmar_domain *domain)
384 KASSERT(TAILQ_EMPTY(&domain->unload_entries),
385 ("unfinished unloads %p", domain));
386 KASSERT(LIST_EMPTY(&domain->contexts),
387 ("destroying dom %p with contexts", domain));
388 KASSERT(domain->ctx_cnt == 0,
389 ("destroying dom %p with ctx_cnt %d", domain, domain->ctx_cnt));
390 KASSERT(domain->refs == 0,
391 ("destroying dom %p with refs %d", domain, domain->refs));
392 if ((domain->flags & DMAR_DOMAIN_GAS_INITED) != 0) {
393 DMAR_DOMAIN_LOCK(domain);
394 dmar_gas_fini_domain(domain);
395 DMAR_DOMAIN_UNLOCK(domain);
397 if ((domain->flags & DMAR_DOMAIN_PGTBL_INITED) != 0) {
398 if (domain->pgtbl_obj != NULL)
399 DMAR_DOMAIN_PGLOCK(domain);
400 domain_free_pgtbl(domain);
402 mtx_destroy(&domain->lock);
403 free_unr(domain->dmar->domids, domain->domain);
404 free(domain, M_DMAR_DOMAIN);
408 dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev, uint16_t rid,
409 bool id_mapped, bool rmrr_init)
411 struct dmar_domain *domain, *domain1;
412 struct dmar_ctx *ctx, *ctx1;
413 dmar_ctx_entry_t *ctxp;
415 int bus, slot, func, error;
418 bus = pci_get_bus(dev);
419 slot = pci_get_slot(dev);
420 func = pci_get_function(dev);
422 TD_PREP_PINNED_ASSERT;
424 ctx = dmar_find_ctx_locked(dmar, rid);
428 * Perform the allocations which require sleep or have
429 * higher chance to succeed if the sleep is allowed.
432 dmar_ensure_ctx_page(dmar, PCI_RID2BUS(rid));
433 domain1 = dmar_domain_alloc(dmar, id_mapped);
434 if (domain1 == NULL) {
439 error = domain_init_rmrr(domain1, dev);
441 dmar_domain_destroy(domain1);
446 ctx1 = dmar_ctx_alloc(domain1, rid);
447 ctxp = dmar_map_ctx_entry(ctx1, &sf);
451 * Recheck the contexts, other thread might have
452 * already allocated needed one.
454 ctx = dmar_find_ctx_locked(dmar, rid);
459 ctx->ctx_tag.owner = dev;
460 ctx_tag_init(ctx, dev);
463 * This is the first activated context for the
464 * DMAR unit. Enable the translation after
465 * everything is set up.
467 if (LIST_EMPTY(&dmar->domains))
469 LIST_INSERT_HEAD(&dmar->domains, domain, link);
470 ctx_id_entry_init(ctx, ctxp, false);
472 "dmar%d pci%d:%d:%d:%d rid %x domain %d mgaw %d "
473 "agaw %d %s-mapped\n",
474 dmar->unit, dmar->segment, bus, slot,
475 func, rid, domain->domain, domain->mgaw,
476 domain->agaw, id_mapped ? "id" : "re");
477 dmar_unmap_pgtbl(sf);
479 dmar_unmap_pgtbl(sf);
480 dmar_domain_destroy(domain1);
481 /* Nothing needs to be done to destroy ctx1. */
482 free(ctx1, M_DMAR_CTX);
483 domain = ctx->domain;
484 ctx->refs++; /* tag referenced us */
487 domain = ctx->domain;
488 ctx->refs++; /* tag referenced us */
491 error = dmar_flush_for_ctx_entry(dmar, enable);
493 dmar_free_ctx_locked(dmar, ctx);
499 * The dmar lock was potentially dropped between check for the
500 * empty context list and now. Recheck the state of GCMD_TE
501 * to avoid unneeded command.
503 if (enable && !rmrr_init && (dmar->hw_gcmd & DMAR_GCMD_TE) == 0) {
504 error = dmar_enable_translation(dmar);
506 dmar_free_ctx_locked(dmar, ctx);
517 dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx)
519 struct dmar_unit *dmar;
520 struct dmar_domain *old_domain;
521 dmar_ctx_entry_t *ctxp;
526 old_domain = ctx->domain;
527 if (domain == old_domain)
529 KASSERT(old_domain->dmar == dmar,
530 ("domain %p %u moving between dmars %u %u", domain,
531 domain->domain, old_domain->dmar->unit, domain->dmar->unit));
532 TD_PREP_PINNED_ASSERT;
534 ctxp = dmar_map_ctx_entry(ctx, &sf);
536 dmar_ctx_unlink(ctx);
537 ctx->domain = domain;
539 ctx_id_entry_init(ctx, ctxp, true);
540 dmar_unmap_pgtbl(sf);
541 error = dmar_flush_for_ctx_entry(dmar, true);
542 /* If flush failed, rolling back would not work as well. */
543 printf("dmar%d rid %x domain %d->%d %s-mapped\n",
544 dmar->unit, ctx->rid, old_domain->domain, domain->domain,
545 (domain->flags & DMAR_DOMAIN_IDMAP) != 0 ? "id" : "re");
546 dmar_unref_domain_locked(dmar, old_domain);
552 dmar_unref_domain_locked(struct dmar_unit *dmar, struct dmar_domain *domain)
555 DMAR_ASSERT_LOCKED(dmar);
556 KASSERT(domain->refs >= 1,
557 ("dmar %d domain %p refs %u", dmar->unit, domain, domain->refs));
558 KASSERT(domain->refs > domain->ctx_cnt,
559 ("dmar %d domain %p refs %d ctx_cnt %d", dmar->unit, domain,
560 domain->refs, domain->ctx_cnt));
562 if (domain->refs > 1) {
568 KASSERT((domain->flags & DMAR_DOMAIN_RMRR) == 0,
569 ("lost ref on RMRR domain %p", domain));
571 LIST_REMOVE(domain, link);
574 taskqueue_drain(dmar->delayed_taskqueue, &domain->unload_task);
575 dmar_domain_destroy(domain);
579 dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx)
582 dmar_ctx_entry_t *ctxp;
583 struct dmar_domain *domain;
585 DMAR_ASSERT_LOCKED(dmar);
586 KASSERT(ctx->refs >= 1,
587 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs));
590 * If our reference is not last, only the dereference should
599 KASSERT((ctx->flags & DMAR_CTX_DISABLED) == 0,
600 ("lost ref on disabled ctx %p", ctx));
603 * Otherwise, the context entry must be cleared before the
604 * page table is destroyed. The mapping of the context
605 * entries page could require sleep, unlock the dmar.
608 TD_PREP_PINNED_ASSERT;
609 ctxp = dmar_map_ctx_entry(ctx, &sf);
611 KASSERT(ctx->refs >= 1,
612 ("dmar %p ctx %p refs %u", dmar, ctx, ctx->refs));
615 * Other thread might have referenced the context, in which
616 * case again only the dereference should be performed.
621 dmar_unmap_pgtbl(sf);
626 KASSERT((ctx->flags & DMAR_CTX_DISABLED) == 0,
627 ("lost ref on disabled ctx %p", ctx));
630 * Clear the context pointer and flush the caches.
631 * XXXKIB: cannot do this if any RMRR entries are still present.
633 dmar_pte_clear(&ctxp->ctx1);
635 dmar_flush_ctx_to_ram(dmar, ctxp);
636 dmar_inv_ctx_glob(dmar);
637 if ((dmar->hw_ecap & DMAR_ECAP_DI) != 0) {
638 if (dmar->qi_enabled)
639 dmar_qi_invalidate_iotlb_glob_locked(dmar);
641 dmar_inv_iotlb_glob(dmar);
643 dmar_unmap_pgtbl(sf);
644 domain = ctx->domain;
645 dmar_ctx_unlink(ctx);
646 free(ctx, M_DMAR_CTX);
647 dmar_unref_domain_locked(dmar, domain);
652 dmar_free_ctx(struct dmar_ctx *ctx)
654 struct dmar_unit *dmar;
656 dmar = ctx->domain->dmar;
658 dmar_free_ctx_locked(dmar, ctx);
662 * Returns with the domain locked.
665 dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid)
667 struct dmar_domain *domain;
668 struct dmar_ctx *ctx;
670 DMAR_ASSERT_LOCKED(dmar);
672 LIST_FOREACH(domain, &dmar->domains, link) {
673 LIST_FOREACH(ctx, &domain->contexts, link) {
682 dmar_domain_free_entry(struct dmar_map_entry *entry, bool free)
684 struct dmar_domain *domain;
686 domain = entry->domain;
687 DMAR_DOMAIN_LOCK(domain);
688 if ((entry->flags & DMAR_MAP_ENTRY_RMRR) != 0)
689 dmar_gas_free_region(domain, entry);
691 dmar_gas_free_space(domain, entry);
692 DMAR_DOMAIN_UNLOCK(domain);
694 dmar_gas_free_entry(domain, entry);
700 dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free)
702 struct dmar_unit *unit;
704 unit = entry->domain->dmar;
705 if (unit->qi_enabled) {
707 dmar_qi_invalidate_locked(entry->domain, entry->start,
708 entry->end - entry->start, &entry->gseq, true);
710 entry->flags |= DMAR_MAP_ENTRY_QI_NF;
711 TAILQ_INSERT_TAIL(&unit->tlb_flush_entries, entry, dmamap_link);
714 domain_flush_iotlb_sync(entry->domain, entry->start,
715 entry->end - entry->start);
716 dmar_domain_free_entry(entry, free);
721 dmar_domain_unload_emit_wait(struct dmar_domain *domain,
722 struct dmar_map_entry *entry)
725 if (TAILQ_NEXT(entry, dmamap_link) == NULL)
727 return (domain->batch_no++ % dmar_batch_coalesce == 0);
731 dmar_domain_unload(struct dmar_domain *domain,
732 struct dmar_map_entries_tailq *entries, bool cansleep)
734 struct dmar_unit *unit;
735 struct dmar_map_entry *entry, *entry1;
740 TAILQ_FOREACH_SAFE(entry, entries, dmamap_link, entry1) {
741 KASSERT((entry->flags & DMAR_MAP_ENTRY_MAP) != 0,
742 ("not mapped entry %p %p", domain, entry));
743 error = domain_unmap_buf(domain, entry->start, entry->end -
744 entry->start, cansleep ? DMAR_PGF_WAITOK : 0);
745 KASSERT(error == 0, ("unmap %p error %d", domain, error));
746 if (!unit->qi_enabled) {
747 domain_flush_iotlb_sync(domain, entry->start,
748 entry->end - entry->start);
749 TAILQ_REMOVE(entries, entry, dmamap_link);
750 dmar_domain_free_entry(entry, true);
753 if (TAILQ_EMPTY(entries))
756 KASSERT(unit->qi_enabled, ("loaded entry left"));
758 TAILQ_FOREACH(entry, entries, dmamap_link) {
759 dmar_qi_invalidate_locked(domain, entry->start, entry->end -
760 entry->start, &entry->gseq,
761 dmar_domain_unload_emit_wait(domain, entry));
763 TAILQ_CONCAT(&unit->tlb_flush_entries, entries, dmamap_link);
768 dmar_domain_unload_task(void *arg, int pending)
770 struct dmar_domain *domain;
771 struct dmar_map_entries_tailq entries;
774 TAILQ_INIT(&entries);
777 DMAR_DOMAIN_LOCK(domain);
778 TAILQ_SWAP(&domain->unload_entries, &entries, dmar_map_entry,
780 DMAR_DOMAIN_UNLOCK(domain);
781 if (TAILQ_EMPTY(&entries))
783 dmar_domain_unload(domain, &entries, true);