2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #ifndef __X86_IOMMU_INTEL_DMAR_H
35 #define __X86_IOMMU_INTEL_DMAR_H
37 /* Host or physical memory address, after translation. */
38 typedef uint64_t dmar_haddr_t;
39 /* Guest or bus address, before translation. */
40 typedef uint64_t dmar_gaddr_t;
42 struct dmar_qi_genseq {
47 struct dmar_map_entry {
50 dmar_gaddr_t first; /* Least start in subtree */
51 dmar_gaddr_t last; /* Greatest end in subtree */
52 dmar_gaddr_t free_down; /* Max free space below the
53 current R/B tree node */
55 TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */
56 RB_ENTRY(dmar_map_entry) rb_entry; /* Links for domain entries */
57 TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after
58 dmamap_load failure */
59 struct dmar_domain *domain;
60 struct dmar_qi_genseq gseq;
63 RB_HEAD(dmar_gas_entries_tree, dmar_map_entry);
64 RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
65 dmar_gas_cmp_entries);
67 #define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */
68 #define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by
70 #define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by
72 #define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */
73 #define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */
74 #define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */
75 #define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */
76 #define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */
77 #define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */
80 * Locking annotations:
81 * (u) - Protected by dmar unit lock
82 * (d) - Protected by domain lock
83 * (c) - Immutable after initialization
87 * The domain abstraction. Most non-constant members of the domain
88 * are protected by owning dmar unit lock, not by the domain lock.
89 * Most important, the dmar lock protects the contexts list.
91 * The domain lock protects the address map for the domain, and list
92 * of unload entries delayed.
94 * Page tables pages and pages content is protected by the vm object
95 * lock pgtbl_obj, which contains the page tables pages.
98 int domain; /* (c) DID, written in context entry */
99 int mgaw; /* (c) Real max address width */
100 int agaw; /* (c) Adjusted guest address width */
101 int pglvl; /* (c) The pagelevel */
102 int awlvl; /* (c) The pagelevel as the bitmask,
103 to set in context entry */
104 dmar_gaddr_t end; /* (c) Highest address + 1 in
106 u_int ctx_cnt; /* (u) Number of contexts owned */
107 u_int refs; /* (u) Refs, including ctx */
108 struct dmar_unit *dmar; /* (c) */
109 struct mtx lock; /* (c) */
110 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */
111 LIST_HEAD(, dmar_ctx) contexts; /* (u) */
112 vm_object_t pgtbl_obj; /* (c) Page table pages */
113 u_int flags; /* (u) */
114 u_int entries_cnt; /* (d) */
115 struct dmar_gas_entries_tree rb_root; /* (d) */
116 struct dmar_map_entries_tailq unload_entries; /* (d) Entries to
118 struct dmar_map_entry *first_place, *last_place; /* (d) */
119 struct task unload_task; /* (c) */
124 struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */
125 uint16_t rid; /* (c) pci RID */
126 uint64_t last_fault_rec[2]; /* Last fault reported */
127 struct dmar_domain *domain; /* (c) */
128 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */
129 u_int refs; /* (u) References from tags */
130 u_int flags; /* (u) */
131 u_long loads; /* atomic updates, for stat only */
132 u_long unloads; /* same */
135 #define DMAR_DOMAIN_GAS_INITED 0x0001
136 #define DMAR_DOMAIN_PGTBL_INITED 0x0002
137 #define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity
139 #define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry,
140 cannot be turned off */
142 /* struct dmar_ctx flags */
143 #define DMAR_CTX_FAULTED 0x0001 /* Fault was reported,
144 last_fault_rec is valid */
145 #define DMAR_CTX_DISABLED 0x0002 /* Device is disabled, the
146 ephemeral reference is kept
147 to prevent context destruction */
149 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj)
150 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
151 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj)
152 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \
153 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj)
155 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->lock)
156 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock)
157 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED)
159 struct dmar_msi_data {
162 struct resource *irq_res;
164 int (*handler)(void *);
168 void (*enable_intr)(struct dmar_unit *);
169 void (*disable_intr)(struct dmar_unit *);
173 #define DMAR_INTR_FAULT 0
174 #define DMAR_INTR_QI 1
175 #define DMAR_INTR_TOTAL 2
185 struct resource *regs;
187 struct dmar_msi_data intrs[DMAR_INTR_TOTAL];
189 /* Hardware registers cache */
195 /* Data for being a dmar */
197 LIST_HEAD(, dmar_domain) domains;
198 struct unrhdr *domids;
202 /* Fault handler data */
203 struct mtx fault_lock;
208 struct task fault_task;
209 struct taskqueue *fault_taskqueue;
213 vm_offset_t inv_queue;
214 vm_size_t inv_queue_size;
215 uint32_t inv_queue_avail;
216 uint32_t inv_queue_tail;
217 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
219 uint64_t inv_waitd_seq_hw_phys;
220 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
221 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */
222 u_int inv_seq_waiters; /* count of waiters for seq */
223 u_int inv_queue_full; /* informational counter */
232 /* Delayed freeing of map entries queue processing */
233 struct dmar_map_entries_tailq tlb_flush_entries;
235 struct taskqueue *qi_taskqueue;
237 /* Busdma delayed map load */
238 struct task dmamap_load_task;
239 TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps;
240 struct taskqueue *delayed_taskqueue;
245 * Bitmap of buses for which context must ignore slot:func,
246 * duplicating the page table pointer into all context table
247 * entries. This is a client-controlled quirk to support some
250 uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
254 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock)
255 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock)
256 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED)
258 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock)
259 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock)
260 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
262 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
263 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
264 #define DMAR_X2APIC(dmar) \
265 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
268 #define DMAR_BARRIER_RMRR 0
269 #define DMAR_BARRIER_USEQ 1
271 struct dmar_unit *dmar_find(device_t dev, bool verbose);
272 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid);
273 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid);
275 u_int dmar_nd2mask(u_int nd);
276 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
277 int domain_set_agaw(struct dmar_domain *domain, int mgaw);
278 int dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr,
280 vm_pindex_t pglvl_max_pages(int pglvl);
281 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl);
282 dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl);
283 dmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl);
284 int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
285 dmar_gaddr_t *isizep);
286 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags);
287 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags);
288 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
290 void dmar_unmap_pgtbl(struct sf_buf *sf);
291 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
292 int dmar_inv_ctx_glob(struct dmar_unit *unit);
293 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
294 int dmar_flush_write_bufs(struct dmar_unit *unit);
295 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst);
296 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
297 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
298 int dmar_enable_translation(struct dmar_unit *unit);
299 int dmar_disable_translation(struct dmar_unit *unit);
300 int dmar_load_irt_ptr(struct dmar_unit *unit);
301 int dmar_enable_ir(struct dmar_unit *unit);
302 int dmar_disable_ir(struct dmar_unit *unit);
303 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
304 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id);
305 uint64_t dmar_get_timeout(void);
306 void dmar_update_timeout(uint64_t newval);
308 int dmar_fault_intr(void *arg);
309 void dmar_enable_fault_intr(struct dmar_unit *unit);
310 void dmar_disable_fault_intr(struct dmar_unit *unit);
311 int dmar_init_fault_log(struct dmar_unit *unit);
312 void dmar_fini_fault_log(struct dmar_unit *unit);
314 int dmar_qi_intr(void *arg);
315 void dmar_enable_qi_intr(struct dmar_unit *unit);
316 void dmar_disable_qi_intr(struct dmar_unit *unit);
317 int dmar_init_qi(struct dmar_unit *unit);
318 void dmar_fini_qi(struct dmar_unit *unit);
319 void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start,
320 dmar_gaddr_t size, struct dmar_qi_genseq *psec, bool emit_wait);
321 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
322 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
323 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit);
324 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt);
326 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain,
327 dmar_gaddr_t maxaddr);
328 void put_idmap_pgtbl(vm_object_t obj);
329 int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base,
330 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags);
331 int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
332 dmar_gaddr_t size, int flags);
333 void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
335 int domain_alloc_pgtbl(struct dmar_domain *domain);
336 void domain_free_pgtbl(struct dmar_domain *domain);
338 int dmar_dev_depth(device_t child);
339 void dmar_dev_path(device_t child, int *busno, void *path1, int depth);
341 struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
343 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev,
344 uint16_t rid, bool id_mapped, bool rmrr_init);
345 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid,
346 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len,
347 bool id_mapped, bool rmrr_init);
348 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx);
349 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
350 void dmar_free_ctx(struct dmar_ctx *ctx);
351 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
352 void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free);
353 void dmar_domain_unload(struct dmar_domain *domain,
354 struct dmar_map_entries_tailq *entries, bool cansleep);
355 void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free);
357 int dmar_init_busdma(struct dmar_unit *unit);
358 void dmar_fini_busdma(struct dmar_unit *unit);
359 device_t dmar_get_requester(device_t dev, uint16_t *rid);
361 void dmar_gas_init_domain(struct dmar_domain *domain);
362 void dmar_gas_fini_domain(struct dmar_domain *domain);
363 struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain,
365 void dmar_gas_free_entry(struct dmar_domain *domain,
366 struct dmar_map_entry *entry);
367 void dmar_gas_free_space(struct dmar_domain *domain,
368 struct dmar_map_entry *entry);
369 int dmar_gas_map(struct dmar_domain *domain,
370 const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset,
371 u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res);
372 void dmar_gas_free_region(struct dmar_domain *domain,
373 struct dmar_map_entry *entry);
374 int dmar_gas_map_region(struct dmar_domain *domain,
375 struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma);
376 int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start,
379 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain,
380 int dev_busno, const void *dev_path, int dev_path_len,
381 struct dmar_map_entries_tailq *rmrr_entries);
382 int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar);
384 void dmar_quirks_post_ident(struct dmar_unit *dmar);
385 void dmar_quirks_pre_use(struct dmar_unit *dmar);
387 int dmar_init_irt(struct dmar_unit *unit);
388 void dmar_fini_irt(struct dmar_unit *unit);
390 void dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno);
391 bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
393 #define DMAR_GM_CANWAIT 0x0001
394 #define DMAR_GM_CANSPLIT 0x0002
395 #define DMAR_GM_RMRR 0x0004
397 #define DMAR_PGF_WAITOK 0x0001
398 #define DMAR_PGF_ZERO 0x0002
399 #define DMAR_PGF_ALLOC 0x0004
400 #define DMAR_PGF_NOALLOC 0x0008
401 #define DMAR_PGF_OBJL 0x0010
403 extern dmar_haddr_t dmar_high;
405 extern int dmar_tbl_pagecnt;
406 extern int dmar_batch_coalesce;
407 extern int dmar_check_free;
409 static inline uint32_t
410 dmar_read4(const struct dmar_unit *unit, int reg)
413 return (bus_read_4(unit->regs, reg));
416 static inline uint64_t
417 dmar_read8(const struct dmar_unit *unit, int reg)
422 low = bus_read_4(unit->regs, reg);
423 high = bus_read_4(unit->regs, reg + 4);
424 return (low | ((uint64_t)high << 32));
426 return (bus_read_8(unit->regs, reg));
431 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)
434 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==
435 (unit->hw_gcmd & DMAR_GCMD_TE),
436 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit,
437 unit->hw_gcmd, val));
438 bus_write_4(unit->regs, reg, val);
442 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)
445 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));
451 bus_write_4(unit->regs, reg, low);
452 bus_write_4(unit->regs, reg + 4, high);
454 bus_write_8(unit->regs, reg, val);
459 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes
460 * are issued in the correct order. For store, the lower word,
461 * containing the P or R and W bits, is set only after the high word
462 * is written. For clear, the P bit is cleared first, then the high
465 * dmar_pte_update updates the pte. For amd64, the update is atomic.
466 * For i386, it first disables the entry by clearing the word
467 * containing the P bit, and then defer to dmar_pte_store. The locked
468 * cmpxchg8b is probably available on any machine having DMAR support,
469 * but interrupt translation table may be mapped uncached.
472 dmar_pte_store1(volatile uint64_t *dst, uint64_t val)
475 volatile uint32_t *p;
480 p = (volatile uint32_t *)dst;
489 dmar_pte_store(volatile uint64_t *dst, uint64_t val)
492 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx",
493 dst, (uintmax_t)*dst, (uintmax_t)val));
494 dmar_pte_store1(dst, val);
498 dmar_pte_update(volatile uint64_t *dst, uint64_t val)
502 volatile uint32_t *p;
504 p = (volatile uint32_t *)dst;
507 dmar_pte_store1(dst, val);
511 dmar_pte_clear(volatile uint64_t *dst)
514 volatile uint32_t *p;
516 p = (volatile uint32_t *)dst;
525 dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size,
526 dmar_gaddr_t boundary)
531 return (start + size <= ((start + boundary) & ~(boundary - 1)));
534 extern struct timespec dmar_hw_timeout;
536 #define DMAR_WAIT_UNTIL(cond) \
538 struct timespec last, curr; \
541 if (dmar_hw_timeout.tv_sec == 0 && \
542 dmar_hw_timeout.tv_nsec == 0) { \
547 timespecadd(&curr, &dmar_hw_timeout, &last); \
555 if (!forever && timespeccmp(&last, &curr, <)) { \
564 #define TD_PREP_PINNED_ASSERT \
566 old_td_pinned = curthread->td_pinned
567 #define TD_PINNED_ASSERT \
568 KASSERT(curthread->td_pinned == old_td_pinned, \
569 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \
570 old_td_pinned, __FILE__, __LINE__))
572 #define TD_PREP_PINNED_ASSERT
573 #define TD_PINNED_ASSERT