2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 #if defined(__amd64__)
43 #include <sys/param.h>
45 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/memdesc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
52 #include <sys/rwlock.h>
54 #include <sys/taskqueue.h>
57 #include <machine/bus.h>
58 #include <machine/pci_cfgreg.h>
59 #include <contrib/dev/acpica/include/acpi.h>
60 #include <contrib/dev/acpica/include/accommon.h>
61 #include <dev/acpica/acpivar.h>
63 #include <vm/vm_extern.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_object.h>
66 #include <vm/vm_page.h>
67 #include <vm/vm_pager.h>
68 #include <vm/vm_map.h>
69 #include <x86/include/busdma_impl.h>
70 #include <x86/iommu/intel_reg.h>
71 #include <dev/iommu/busdma_iommu.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <x86/iommu/intel_dmar.h>
78 #include <machine/intr_machdep.h>
79 #include <x86/apicreg.h>
80 #include <x86/apicvar.h>
83 #define DMAR_FAULT_IRQ_RID 0
84 #define DMAR_QI_IRQ_RID 1
85 #define DMAR_REG_RID 2
87 static devclass_t dmar_devclass;
88 static device_t *dmar_devs;
89 static int dmar_devcnt;
91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
94 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
96 ACPI_TABLE_DMAR *dmartbl;
97 ACPI_DMAR_HEADER *dmarh;
101 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
102 if (ACPI_FAILURE(status))
104 ptr = (char *)dmartbl + sizeof(*dmartbl);
105 ptrend = (char *)dmartbl + dmartbl->Header.Length;
109 dmarh = (ACPI_DMAR_HEADER *)ptr;
110 if (dmarh->Length <= 0) {
111 printf("dmar_identify: corrupted DMAR table, l %d\n",
115 ptr += dmarh->Length;
116 if (!iter(dmarh, arg))
119 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
122 struct find_iter_args {
124 ACPI_DMAR_HARDWARE_UNIT *res;
128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
130 struct find_iter_args *fia;
132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
144 static ACPI_DMAR_HARDWARE_UNIT *
145 dmar_find_by_index(int idx)
147 struct find_iter_args fia;
151 dmar_iterate_tbl(dmar_find_iter, &fia);
156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
164 static int dmar_enable = 0;
166 dmar_identify(driver_t *driver, device_t parent)
168 ACPI_TABLE_DMAR *dmartbl;
169 ACPI_DMAR_HARDWARE_UNIT *dmarh;
173 if (acpi_disabled("dmar"))
175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
178 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
179 if (ACPI_FAILURE(status))
181 haw = dmartbl->Width + 1;
182 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
183 dmar_high = BUS_SPACE_MAXADDR;
185 dmar_high = 1ULL << (haw + 1);
187 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
188 (unsigned)dmartbl->Flags,
189 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
191 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
193 dmar_iterate_tbl(dmar_count_iter, NULL);
194 if (dmar_devcnt == 0)
196 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
198 for (i = 0; i < dmar_devcnt; i++) {
199 dmarh = dmar_find_by_index(i);
201 printf("dmar_identify: cannot find HWUNIT %d\n", i);
204 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
205 if (dmar_devs[i] == NULL) {
206 printf("dmar_identify: cannot create instance %d\n", i);
209 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
210 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
213 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
214 i, (uintmax_t)dmarh->Address, error);
215 device_delete_child(parent, dmar_devs[i]);
222 dmar_probe(device_t dev)
225 if (acpi_get_handle(dev) != NULL)
227 device_set_desc(dev, "DMA remap");
228 return (BUS_PROBE_NOWILDCARD);
232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
234 struct dmar_msi_data *dmd;
236 dmd = &unit->intrs[idx];
239 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
240 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
241 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
242 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
248 dmar_release_resources(device_t dev, struct dmar_unit *unit)
252 iommu_fini_busdma(&unit->iommu);
255 dmar_fini_fault_log(unit);
256 for (i = 0; i < DMAR_INTR_TOTAL; i++)
257 dmar_release_intr(dev, unit, i);
258 if (unit->regs != NULL) {
259 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
261 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
265 if (unit->domids != NULL) {
266 delete_unrhdr(unit->domids);
269 if (unit->ctx_obj != NULL) {
270 vm_object_deallocate(unit->ctx_obj);
271 unit->ctx_obj = NULL;
276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
279 struct dmar_msi_data *dmd;
284 dmd = &unit->intrs[idx];
285 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
286 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
288 device_printf(dev, "cannot allocate %s interrupt, %d\n",
292 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
295 device_printf(dev, "cannot set %s interrupt resource, %d\n",
299 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
300 &dmd->irq_rid, RF_ACTIVE);
301 if (dmd->irq_res == NULL) {
303 "cannot allocate resource for %s interrupt\n", dmd->name);
307 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
308 dmd->handler, NULL, unit, &dmd->intr_handle);
310 device_printf(dev, "cannot setup %s interrupt, %d\n",
314 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
315 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
317 device_printf(dev, "cannot map %s interrupt, %d\n",
321 dmar_write4(unit, dmd->msi_data_reg, msi_data);
322 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
323 /* Only for xAPIC mode */
324 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
328 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
330 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
332 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
334 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
342 dmar_remap_intr(device_t dev, device_t child, u_int irq)
344 struct dmar_unit *unit;
345 struct dmar_msi_data *dmd;
350 unit = device_get_softc(dev);
351 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
352 dmd = &unit->intrs[i];
353 if (irq == dmd->irq) {
354 error = PCIB_MAP_MSI(device_get_parent(
355 device_get_parent(dev)),
356 dev, irq, &msi_addr, &msi_data);
360 (dmd->disable_intr)(unit);
361 dmar_write4(unit, dmd->msi_data_reg, msi_data);
362 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
363 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
364 (dmd->enable_intr)(unit);
374 dmar_print_caps(device_t dev, struct dmar_unit *unit,
375 ACPI_DMAR_HARDWARE_UNIT *dmaru)
377 uint32_t caphi, ecaphi;
379 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
380 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
381 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
382 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
383 caphi = unit->hw_cap >> 32;
384 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
385 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
386 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
387 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
388 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
389 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
390 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
391 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
392 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
394 ecaphi = unit->hw_ecap >> 32;
395 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
396 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
397 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
398 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
399 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
400 DMAR_ECAP_IRO(unit->hw_ecap));
404 dmar_attach(device_t dev)
406 struct dmar_unit *unit;
407 ACPI_DMAR_HARDWARE_UNIT *dmaru;
411 unit = device_get_softc(dev);
413 unit->iommu.unit = device_get_unit(dev);
414 dmaru = dmar_find_by_index(unit->iommu.unit);
417 unit->segment = dmaru->Segment;
418 unit->base = dmaru->Address;
419 unit->reg_rid = DMAR_REG_RID;
420 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
421 &unit->reg_rid, RF_ACTIVE);
422 if (unit->regs == NULL) {
423 device_printf(dev, "cannot allocate register window\n");
426 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
427 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
428 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
430 dmar_print_caps(dev, unit, dmaru);
431 dmar_quirks_post_ident(unit);
433 timeout = dmar_get_timeout();
434 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
435 dmar_update_timeout(timeout);
437 for (i = 0; i < DMAR_INTR_TOTAL; i++)
438 unit->intrs[i].irq = -1;
440 unit->intrs[DMAR_INTR_FAULT].name = "fault";
441 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
442 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
443 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
444 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
445 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
446 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
447 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
448 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
450 dmar_release_resources(dev, unit);
453 if (DMAR_HAS_QI(unit)) {
454 unit->intrs[DMAR_INTR_QI].name = "qi";
455 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
456 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
457 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
458 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
459 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
460 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
461 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
462 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
464 dmar_release_resources(dev, unit);
469 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
470 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
472 LIST_INIT(&unit->domains);
475 * 9.2 "Context Entry":
476 * When Caching Mode (CM) field is reported as Set, the
477 * domain-id value of zero is architecturally reserved.
478 * Software must not use domain-id value of zero
481 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
482 alloc_unr_specific(unit->domids, 0);
484 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
485 DMAR_CTX_CNT), 0, 0, NULL);
488 * Allocate and load the root entry table pointer. Enable the
489 * address translation after the required invalidations are
492 dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
494 error = dmar_load_root_entry_ptr(unit);
497 dmar_release_resources(dev, unit);
500 error = dmar_inv_ctx_glob(unit);
503 dmar_release_resources(dev, unit);
506 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
507 error = dmar_inv_iotlb_glob(unit);
510 dmar_release_resources(dev, unit);
516 error = dmar_init_fault_log(unit);
518 dmar_release_resources(dev, unit);
521 error = dmar_init_qi(unit);
523 dmar_release_resources(dev, unit);
526 error = dmar_init_irt(unit);
528 dmar_release_resources(dev, unit);
531 error = iommu_init_busdma(&unit->iommu);
533 dmar_release_resources(dev, unit);
539 error = dmar_enable_translation(unit);
542 dmar_release_resources(dev, unit);
552 dmar_detach(device_t dev)
559 dmar_suspend(device_t dev)
566 dmar_resume(device_t dev)
573 static device_method_t dmar_methods[] = {
574 DEVMETHOD(device_identify, dmar_identify),
575 DEVMETHOD(device_probe, dmar_probe),
576 DEVMETHOD(device_attach, dmar_attach),
577 DEVMETHOD(device_detach, dmar_detach),
578 DEVMETHOD(device_suspend, dmar_suspend),
579 DEVMETHOD(device_resume, dmar_resume),
581 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
586 static driver_t dmar_driver = {
589 sizeof(struct dmar_unit),
592 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
593 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
596 iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
599 MPASS(busno <= PCI_BUSMAX);
601 unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
602 1 << (busno % (NBBY * sizeof(uint32_t)));
607 iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno)
610 MPASS(busno <= PCI_BUSMAX);
611 return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
612 (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
616 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
620 printf("[%d, ", busno);
621 for (i = 0; i < depth; i++) {
624 printf("(%d, %d)", path[i].Device, path[i].Function);
630 dmar_dev_depth(device_t child)
632 devclass_t pci_class;
636 pci_class = devclass_find("pci");
637 for (depth = 1; ; depth++) {
638 bus = device_get_parent(child);
639 pcib = device_get_parent(bus);
640 if (device_get_devclass(device_get_parent(pcib)) !=
648 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
650 devclass_t pci_class;
652 ACPI_DMAR_PCI_PATH *path;
654 pci_class = devclass_find("pci");
656 for (depth--; depth != -1; depth--) {
657 path[depth].Device = pci_get_slot(child);
658 path[depth].Function = pci_get_function(child);
659 bus = device_get_parent(child);
660 pcib = device_get_parent(bus);
661 if (device_get_devclass(device_get_parent(pcib)) !=
663 /* reached a host bridge */
664 *busno = pcib_get_bus(bus);
669 panic("wrong depth");
673 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
674 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
675 enum AcpiDmarScopeType scope_type)
679 if (busno1 != busno2)
681 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
686 for (i = 0; i < depth; i++) {
687 if (path1[i].Device != path2[i].Device ||
688 path1[i].Function != path2[i].Function)
695 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
696 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
698 ACPI_DMAR_PCI_PATH *path;
701 if (devscope->Length < sizeof(*devscope)) {
702 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
706 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
707 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
709 path_len = devscope->Length - sizeof(*devscope);
710 if (path_len % 2 != 0) {
711 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
716 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
718 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
723 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
724 dev_path, dev_path_len, devscope->EntryType));
728 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
729 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
731 ACPI_DMAR_HARDWARE_UNIT *dmarh;
732 ACPI_DMAR_DEVICE_SCOPE *devscope;
736 dmarh = dmar_find_by_index(unit->iommu.unit);
739 if (dmarh->Segment != dev_domain)
741 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
743 *banner = "INCLUDE_ALL";
746 ptr = (char *)dmarh + sizeof(*dmarh);
747 ptrend = (char *)dmarh + dmarh->Header.Length;
748 while (ptr < ptrend) {
749 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
750 ptr += devscope->Length;
751 match = dmar_match_devscope(devscope, dev_busno, dev_path,
757 *banner = "specific match";
764 static struct dmar_unit *
765 dmar_find_by_scope(int dev_domain, int dev_busno,
766 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
768 struct dmar_unit *unit;
771 for (i = 0; i < dmar_devcnt; i++) {
772 if (dmar_devs[i] == NULL)
774 unit = device_get_softc(dmar_devs[i]);
775 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
783 dmar_find(device_t dev, bool verbose)
786 struct dmar_unit *unit;
788 int i, dev_domain, dev_busno, dev_path_len;
791 * This function can only handle PCI(e) devices.
793 if (device_get_devclass(device_get_parent(dev)) !=
794 devclass_find("pci"))
798 dev_domain = pci_get_domain(dev);
799 dev_path_len = dmar_dev_depth(dev);
800 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
801 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
804 for (i = 0; i < dmar_devcnt; i++) {
805 if (dmar_devs[i] == NULL)
807 unit = device_get_softc(dmar_devs[i]);
808 if (dmar_match_by_path(unit, dev_domain, dev_busno,
809 dev_path, dev_path_len, &banner))
812 if (i == dmar_devcnt)
816 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
817 dev_domain, pci_get_bus(dev), pci_get_slot(dev),
818 pci_get_function(dev), unit->iommu.unit, banner);
819 printf(" scope path ");
820 dmar_print_path(dev_busno, dev_path_len, dev_path);
826 static struct dmar_unit *
827 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
830 struct dmar_unit *unit;
831 ACPI_DMAR_HARDWARE_UNIT *dmarh;
832 ACPI_DMAR_DEVICE_SCOPE *devscope;
833 ACPI_DMAR_PCI_PATH *path;
840 for (i = 0; i < dmar_devcnt; i++) {
841 dmar_dev = dmar_devs[i];
842 if (dmar_dev == NULL)
844 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
845 dmarh = dmar_find_by_index(i);
848 ptr = (char *)dmarh + sizeof(*dmarh);
849 ptrend = (char *)dmarh + dmarh->Header.Length;
853 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
854 ptr += devscope->Length;
855 if (devscope->EntryType != entry_type)
857 if (devscope->EnumerationId != id)
860 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
861 error = ioapic_get_rid(id, rid);
863 * If our IOAPIC has PCI bindings then
864 * use the PCI device rid.
870 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
873 path = (ACPI_DMAR_PCI_PATH *)
875 *rid = PCI_RID(devscope->Bus,
876 path->Device, path->Function);
881 "dmar_find_nonpci: id %d type %d path length != 2\n",
891 dmar_find_hpet(device_t dev, uint16_t *rid)
894 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
899 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
902 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
905 struct rmrr_iter_args {
906 struct dmar_domain *domain;
909 const ACPI_DMAR_PCI_PATH *dev_path;
911 struct iommu_map_entries_tailq *rmrr_entries;
915 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
917 struct rmrr_iter_args *ria;
918 ACPI_DMAR_RESERVED_MEMORY *resmem;
919 ACPI_DMAR_DEVICE_SCOPE *devscope;
920 struct iommu_map_entry *entry;
924 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
928 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
929 if (resmem->Segment != ria->dev_domain)
932 ptr = (char *)resmem + sizeof(*resmem);
933 ptrend = (char *)resmem + resmem->Header.Length;
937 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
938 ptr += devscope->Length;
939 match = dmar_match_devscope(devscope, ria->dev_busno,
940 ria->dev_path, ria->dev_path_len);
942 entry = iommu_gas_alloc_entry(
943 (struct iommu_domain *)ria->domain,
945 entry->start = resmem->BaseAddress;
946 /* The RMRR entry end address is inclusive. */
947 entry->end = resmem->EndAddress;
948 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
957 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
958 const void *dev_path, int dev_path_len,
959 struct iommu_map_entries_tailq *rmrr_entries)
961 struct rmrr_iter_args ria;
964 ria.dev_domain = dev_domain;
965 ria.dev_busno = dev_busno;
966 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
967 ria.dev_path_len = dev_path_len;
968 ria.rmrr_entries = rmrr_entries;
969 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
972 struct inst_rmrr_iter_args {
973 struct dmar_unit *dmar;
977 dmar_path_dev(int segment, int path_len, int busno,
978 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
984 for (i = 0; i < path_len; i++) {
985 dev = pci_find_dbsf(segment, busno, path->Device,
987 if (i != path_len - 1) {
988 busno = pci_cfgregread(busno, path->Device,
989 path->Function, PCIR_SECBUS_1, 1);
993 *rid = PCI_RID(busno, path->Device, path->Function);
998 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
1000 const ACPI_DMAR_RESERVED_MEMORY *resmem;
1001 const ACPI_DMAR_DEVICE_SCOPE *devscope;
1002 struct inst_rmrr_iter_args *iria;
1003 const char *ptr, *ptrend;
1005 struct dmar_unit *unit;
1011 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
1014 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
1015 if (resmem->Segment != iria->dmar->segment)
1018 ptr = (const char *)resmem + sizeof(*resmem);
1019 ptrend = (const char *)resmem + resmem->Header.Length;
1023 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1024 ptr += devscope->Length;
1026 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1029 dev_path_len = (devscope->Length -
1030 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1031 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1033 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1036 printf("dmar%d no dev found for RMRR "
1037 "[%#jx, %#jx] rid %#x scope path ",
1038 iria->dmar->iommu.unit,
1039 (uintmax_t)resmem->BaseAddress,
1040 (uintmax_t)resmem->EndAddress,
1042 dmar_print_path(devscope->Bus, dev_path_len,
1043 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1046 unit = dmar_find_by_scope(resmem->Segment,
1048 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1050 if (iria->dmar != unit)
1052 dmar_get_ctx_for_devpath(iria->dmar, rid,
1053 resmem->Segment, devscope->Bus,
1054 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1055 dev_path_len, false, true);
1057 unit = dmar_find(dev, false);
1058 if (iria->dmar != unit)
1060 iommu_instantiate_ctx(&(iria)->dmar->iommu,
1070 * Pre-create all contexts for the DMAR which have RMRR entries.
1073 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
1075 struct dmar_unit *dmar;
1076 struct inst_rmrr_iter_args iria;
1079 dmar = (struct dmar_unit *)unit;
1081 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1086 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1088 if (!LIST_EMPTY(&dmar->domains)) {
1089 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1090 ("dmar%d: RMRR not handled but translation is already enabled",
1092 error = dmar_enable_translation(dmar);
1095 printf("dmar%d: enabled translation\n",
1098 printf("dmar%d: enabling translation failed, "
1099 "error %d\n", dmar->iommu.unit, error);
1103 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1108 #include <ddb/ddb.h>
1109 #include <ddb/db_lex.h>
1112 dmar_print_domain_entry(const struct iommu_map_entry *entry)
1114 struct iommu_map_entry *l, *r;
1117 " start %jx end %jx first %jx last %jx free_down %jx flags %x ",
1118 entry->start, entry->end, entry->first, entry->last,
1119 entry->free_down, entry->flags);
1121 l = RB_LEFT(entry, rb_entry);
1125 db_printf("%jx ", l->start);
1126 db_printf("right ");
1127 r = RB_RIGHT(entry, rb_entry);
1131 db_printf("%jx", r->start);
1136 dmar_print_ctx(struct dmar_ctx *ctx)
1140 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1141 ctx, pci_get_bus(ctx->context.tag->owner),
1142 pci_get_slot(ctx->context.tag->owner),
1143 pci_get_function(ctx->context.tag->owner), ctx->refs,
1144 ctx->context.flags, ctx->context.loads, ctx->context.unloads);
1148 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1150 struct iommu_domain *iodom;
1151 struct iommu_map_entry *entry;
1152 struct dmar_ctx *ctx;
1154 iodom = (struct iommu_domain *)domain;
1157 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1158 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1159 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1160 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
1161 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
1162 if (!LIST_EMPTY(&domain->contexts)) {
1163 db_printf(" Contexts:\n");
1164 LIST_FOREACH(ctx, &domain->contexts, link)
1165 dmar_print_ctx(ctx);
1169 db_printf(" mapped:\n");
1170 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) {
1171 dmar_print_domain_entry(entry);
1177 db_printf(" unloading:\n");
1178 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) {
1179 dmar_print_domain_entry(entry);
1185 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1187 struct dmar_unit *unit;
1188 struct dmar_domain *domain;
1189 struct dmar_ctx *ctx;
1190 bool show_mappings, valid;
1191 int pci_domain, bus, device, function, i, t;
1197 t = db_read_token();
1199 t = db_read_token();
1201 db_printf("Bad modifier\n");
1206 show_mappings = strchr(db_tok_string, 'm') != NULL;
1207 t = db_read_token();
1209 show_mappings = false;
1212 pci_domain = db_tok_number;
1213 t = db_read_token();
1215 bus = db_tok_number;
1216 t = db_read_token();
1218 device = db_tok_number;
1219 t = db_read_token();
1221 function = db_tok_number;
1230 db_printf("usage: show dmar_domain [/m] "
1231 "<domain> <bus> <device> <func>\n");
1234 for (i = 0; i < dmar_devcnt; i++) {
1235 unit = device_get_softc(dmar_devs[i]);
1236 LIST_FOREACH(domain, &unit->domains, link) {
1237 LIST_FOREACH(ctx, &domain->contexts, link) {
1238 if (pci_domain == unit->segment &&
1239 bus == pci_get_bus(ctx->context.tag->owner) &&
1241 pci_get_slot(ctx->context.tag->owner) &&
1243 pci_get_function(ctx->context.tag->owner)) {
1244 dmar_print_domain(domain,
1255 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1257 struct dmar_unit *unit;
1258 struct dmar_domain *domain;
1261 unit = device_get_softc(dmar_devs[idx]);
1262 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
1263 unit, dmar_read8(unit, DMAR_RTADDR_REG),
1264 dmar_read4(unit, DMAR_VER_REG));
1265 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1266 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1267 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1268 dmar_read4(unit, DMAR_GSTS_REG),
1269 dmar_read4(unit, DMAR_FSTS_REG),
1270 dmar_read4(unit, DMAR_FECTL_REG));
1271 if (unit->ir_enabled) {
1272 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1273 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1275 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1276 dmar_read4(unit, DMAR_FEDATA_REG),
1277 dmar_read4(unit, DMAR_FEADDR_REG),
1278 dmar_read4(unit, DMAR_FEUADDR_REG));
1279 db_printf("primary fault log:\n");
1280 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1281 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1282 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1283 (uintmax_t)dmar_read8(unit, frir),
1284 (uintmax_t)dmar_read8(unit, frir + 8));
1286 if (DMAR_HAS_QI(unit)) {
1287 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1288 dmar_read4(unit, DMAR_IEDATA_REG),
1289 dmar_read4(unit, DMAR_IEADDR_REG),
1290 dmar_read4(unit, DMAR_IEUADDR_REG));
1291 if (unit->qi_enabled) {
1292 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1294 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1295 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1296 (uintmax_t)unit->inv_queue,
1297 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1298 (uintmax_t)unit->inv_queue_size,
1299 dmar_read4(unit, DMAR_IQH_REG),
1300 dmar_read4(unit, DMAR_IQT_REG),
1301 unit->inv_queue_avail,
1302 dmar_read4(unit, DMAR_ICS_REG),
1303 dmar_read4(unit, DMAR_IECTL_REG),
1304 unit->inv_waitd_seq_hw,
1305 &unit->inv_waitd_seq_hw,
1306 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1307 unit->inv_waitd_seq,
1308 unit->inv_waitd_gen);
1310 db_printf("qi is disabled\n");
1314 db_printf("domains:\n");
1315 LIST_FOREACH(domain, &unit->domains, link) {
1316 dmar_print_domain(domain, show_mappings);
1323 DB_SHOW_COMMAND(dmar, db_dmar_print)
1325 bool show_domains, show_mappings;
1327 show_domains = strchr(modif, 'd') != NULL;
1328 show_mappings = strchr(modif, 'm') != NULL;
1330 db_printf("usage: show dmar [/d] [/m] index\n");
1333 dmar_print_one((int)addr, show_domains, show_mappings);
1336 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1339 bool show_domains, show_mappings;
1341 show_domains = strchr(modif, 'd') != NULL;
1342 show_mappings = strchr(modif, 'm') != NULL;
1344 for (i = 0; i < dmar_devcnt; i++) {
1345 dmar_print_one(i, show_domains, show_mappings);
1353 iommu_find(device_t dev, bool verbose)
1355 struct dmar_unit *dmar;
1357 dmar = dmar_find(dev, verbose);
1359 return (&dmar->iommu);