2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 #if defined(__amd64__)
43 #include <sys/param.h>
45 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/memdesc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
52 #include <sys/rwlock.h>
54 #include <sys/taskqueue.h>
57 #include <machine/bus.h>
58 #include <machine/pci_cfgreg.h>
59 #include <contrib/dev/acpica/include/acpi.h>
60 #include <contrib/dev/acpica/include/accommon.h>
61 #include <dev/acpica/acpivar.h>
63 #include <vm/vm_extern.h>
64 #include <vm/vm_kern.h>
65 #include <vm/vm_object.h>
66 #include <vm/vm_page.h>
67 #include <vm/vm_pager.h>
68 #include <vm/vm_map.h>
69 #include <x86/include/busdma_impl.h>
70 #include <x86/iommu/intel_reg.h>
71 #include <x86/iommu/busdma_dmar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <x86/iommu/intel_dmar.h>
78 #include <machine/intr_machdep.h>
79 #include <x86/apicreg.h>
80 #include <x86/apicvar.h>
83 #define DMAR_FAULT_IRQ_RID 0
84 #define DMAR_QI_IRQ_RID 1
85 #define DMAR_REG_RID 2
87 static devclass_t dmar_devclass;
88 static device_t *dmar_devs;
89 static int dmar_devcnt;
91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
94 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
96 ACPI_TABLE_DMAR *dmartbl;
97 ACPI_DMAR_HEADER *dmarh;
101 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
102 if (ACPI_FAILURE(status))
104 ptr = (char *)dmartbl + sizeof(*dmartbl);
105 ptrend = (char *)dmartbl + dmartbl->Header.Length;
109 dmarh = (ACPI_DMAR_HEADER *)ptr;
110 if (dmarh->Length <= 0) {
111 printf("dmar_identify: corrupted DMAR table, l %d\n",
115 ptr += dmarh->Length;
116 if (!iter(dmarh, arg))
119 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
122 struct find_iter_args {
124 ACPI_DMAR_HARDWARE_UNIT *res;
128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
130 struct find_iter_args *fia;
132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
144 static ACPI_DMAR_HARDWARE_UNIT *
145 dmar_find_by_index(int idx)
147 struct find_iter_args fia;
151 dmar_iterate_tbl(dmar_find_iter, &fia);
156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
164 static int dmar_enable = 0;
166 dmar_identify(driver_t *driver, device_t parent)
168 ACPI_TABLE_DMAR *dmartbl;
169 ACPI_DMAR_HARDWARE_UNIT *dmarh;
173 if (acpi_disabled("dmar"))
175 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
179 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
181 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
182 if (ACPI_FAILURE(status))
184 haw = dmartbl->Width + 1;
185 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
186 dmar_high = BUS_SPACE_MAXADDR;
188 dmar_high = 1ULL << (haw + 1);
190 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
191 (unsigned)dmartbl->Flags,
192 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
194 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
196 dmar_iterate_tbl(dmar_count_iter, NULL);
197 if (dmar_devcnt == 0)
199 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
201 for (i = 0; i < dmar_devcnt; i++) {
202 dmarh = dmar_find_by_index(i);
204 printf("dmar_identify: cannot find HWUNIT %d\n", i);
207 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
208 if (dmar_devs[i] == NULL) {
209 printf("dmar_identify: cannot create instance %d\n", i);
212 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
213 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
216 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
217 i, (uintmax_t)dmarh->Address, error);
218 device_delete_child(parent, dmar_devs[i]);
225 dmar_probe(device_t dev)
228 if (acpi_get_handle(dev) != NULL)
230 device_set_desc(dev, "DMA remap");
231 return (BUS_PROBE_NOWILDCARD);
235 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
237 struct dmar_msi_data *dmd;
239 dmd = &unit->intrs[idx];
242 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
243 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
244 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
245 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
251 dmar_release_resources(device_t dev, struct dmar_unit *unit)
255 dmar_fini_busdma(unit);
258 dmar_fini_fault_log(unit);
259 for (i = 0; i < DMAR_INTR_TOTAL; i++)
260 dmar_release_intr(dev, unit, i);
261 if (unit->regs != NULL) {
262 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
264 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
268 if (unit->domids != NULL) {
269 delete_unrhdr(unit->domids);
272 if (unit->ctx_obj != NULL) {
273 vm_object_deallocate(unit->ctx_obj);
274 unit->ctx_obj = NULL;
279 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
282 struct dmar_msi_data *dmd;
287 dmd = &unit->intrs[idx];
288 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
289 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
291 device_printf(dev, "cannot allocate %s interrupt, %d\n",
295 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
298 device_printf(dev, "cannot set %s interrupt resource, %d\n",
302 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
303 &dmd->irq_rid, RF_ACTIVE);
304 if (dmd->irq_res == NULL) {
306 "cannot allocate resource for %s interrupt\n", dmd->name);
310 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
311 dmd->handler, NULL, unit, &dmd->intr_handle);
313 device_printf(dev, "cannot setup %s interrupt, %d\n",
317 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
318 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
320 device_printf(dev, "cannot map %s interrupt, %d\n",
324 dmar_write4(unit, dmd->msi_data_reg, msi_data);
325 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
326 /* Only for xAPIC mode */
327 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
331 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
333 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
335 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
337 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
345 dmar_remap_intr(device_t dev, device_t child, u_int irq)
347 struct dmar_unit *unit;
348 struct dmar_msi_data *dmd;
353 unit = device_get_softc(dev);
354 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
355 dmd = &unit->intrs[i];
356 if (irq == dmd->irq) {
357 error = PCIB_MAP_MSI(device_get_parent(
358 device_get_parent(dev)),
359 dev, irq, &msi_addr, &msi_data);
363 (dmd->disable_intr)(unit);
364 dmar_write4(unit, dmd->msi_data_reg, msi_data);
365 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
366 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
367 (dmd->enable_intr)(unit);
377 dmar_print_caps(device_t dev, struct dmar_unit *unit,
378 ACPI_DMAR_HARDWARE_UNIT *dmaru)
380 uint32_t caphi, ecaphi;
382 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
383 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
384 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
385 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
386 caphi = unit->hw_cap >> 32;
387 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
388 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
389 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
390 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
391 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
392 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
393 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
394 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
395 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
397 ecaphi = unit->hw_ecap >> 32;
398 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
399 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
400 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
401 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
402 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
403 DMAR_ECAP_IRO(unit->hw_ecap));
407 dmar_attach(device_t dev)
409 struct dmar_unit *unit;
410 ACPI_DMAR_HARDWARE_UNIT *dmaru;
414 unit = device_get_softc(dev);
416 unit->unit = device_get_unit(dev);
417 dmaru = dmar_find_by_index(unit->unit);
420 unit->segment = dmaru->Segment;
421 unit->base = dmaru->Address;
422 unit->reg_rid = DMAR_REG_RID;
423 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
424 &unit->reg_rid, RF_ACTIVE);
425 if (unit->regs == NULL) {
426 device_printf(dev, "cannot allocate register window\n");
429 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
430 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
431 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
433 dmar_print_caps(dev, unit, dmaru);
434 dmar_quirks_post_ident(unit);
436 timeout = dmar_get_timeout();
437 TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
438 dmar_update_timeout(timeout);
440 for (i = 0; i < DMAR_INTR_TOTAL; i++)
441 unit->intrs[i].irq = -1;
443 unit->intrs[DMAR_INTR_FAULT].name = "fault";
444 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
445 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
446 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
447 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
448 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
449 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
450 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
451 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
453 dmar_release_resources(dev, unit);
456 if (DMAR_HAS_QI(unit)) {
457 unit->intrs[DMAR_INTR_QI].name = "qi";
458 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
459 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
460 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
461 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
462 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
463 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
464 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
465 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
467 dmar_release_resources(dev, unit);
472 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
473 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
475 LIST_INIT(&unit->domains);
478 * 9.2 "Context Entry":
479 * When Caching Mode (CM) field is reported as Set, the
480 * domain-id value of zero is architecturally reserved.
481 * Software must not use domain-id value of zero
484 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
485 alloc_unr_specific(unit->domids, 0);
487 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
488 DMAR_CTX_CNT), 0, 0, NULL);
491 * Allocate and load the root entry table pointer. Enable the
492 * address translation after the required invalidations are
495 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
497 error = dmar_load_root_entry_ptr(unit);
500 dmar_release_resources(dev, unit);
503 error = dmar_inv_ctx_glob(unit);
506 dmar_release_resources(dev, unit);
509 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
510 error = dmar_inv_iotlb_glob(unit);
513 dmar_release_resources(dev, unit);
519 error = dmar_init_fault_log(unit);
521 dmar_release_resources(dev, unit);
524 error = dmar_init_qi(unit);
526 dmar_release_resources(dev, unit);
529 error = dmar_init_irt(unit);
531 dmar_release_resources(dev, unit);
534 error = dmar_init_busdma(unit);
536 dmar_release_resources(dev, unit);
542 error = dmar_enable_translation(unit);
545 dmar_release_resources(dev, unit);
555 dmar_detach(device_t dev)
562 dmar_suspend(device_t dev)
569 dmar_resume(device_t dev)
576 static device_method_t dmar_methods[] = {
577 DEVMETHOD(device_identify, dmar_identify),
578 DEVMETHOD(device_probe, dmar_probe),
579 DEVMETHOD(device_attach, dmar_attach),
580 DEVMETHOD(device_detach, dmar_detach),
581 DEVMETHOD(device_suspend, dmar_suspend),
582 DEVMETHOD(device_resume, dmar_resume),
584 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
589 static driver_t dmar_driver = {
592 sizeof(struct dmar_unit),
595 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
596 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
599 dmar_set_buswide_ctx(struct dmar_unit *unit, u_int busno)
602 MPASS(busno <= PCI_BUSMAX);
604 unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
605 1 << (busno % (NBBY * sizeof(uint32_t)));
610 dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
613 MPASS(busno <= PCI_BUSMAX);
614 return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
615 (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
619 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
623 printf("[%d, ", busno);
624 for (i = 0; i < depth; i++) {
627 printf("(%d, %d)", path[i].Device, path[i].Function);
633 dmar_dev_depth(device_t child)
635 devclass_t pci_class;
639 pci_class = devclass_find("pci");
640 for (depth = 1; ; depth++) {
641 bus = device_get_parent(child);
642 pcib = device_get_parent(bus);
643 if (device_get_devclass(device_get_parent(pcib)) !=
651 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
653 devclass_t pci_class;
655 ACPI_DMAR_PCI_PATH *path;
657 pci_class = devclass_find("pci");
659 for (depth--; depth != -1; depth--) {
660 path[depth].Device = pci_get_slot(child);
661 path[depth].Function = pci_get_function(child);
662 bus = device_get_parent(child);
663 pcib = device_get_parent(bus);
664 if (device_get_devclass(device_get_parent(pcib)) !=
666 /* reached a host bridge */
667 *busno = pcib_get_bus(bus);
672 panic("wrong depth");
676 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
677 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
678 enum AcpiDmarScopeType scope_type)
682 if (busno1 != busno2)
684 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
689 for (i = 0; i < depth; i++) {
690 if (path1[i].Device != path2[i].Device ||
691 path1[i].Function != path2[i].Function)
698 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
699 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
701 ACPI_DMAR_PCI_PATH *path;
704 if (devscope->Length < sizeof(*devscope)) {
705 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
709 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
710 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
712 path_len = devscope->Length - sizeof(*devscope);
713 if (path_len % 2 != 0) {
714 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
719 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
721 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
726 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
727 dev_path, dev_path_len, devscope->EntryType));
731 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
732 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
734 ACPI_DMAR_HARDWARE_UNIT *dmarh;
735 ACPI_DMAR_DEVICE_SCOPE *devscope;
739 dmarh = dmar_find_by_index(unit->unit);
742 if (dmarh->Segment != dev_domain)
744 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
746 *banner = "INCLUDE_ALL";
749 ptr = (char *)dmarh + sizeof(*dmarh);
750 ptrend = (char *)dmarh + dmarh->Header.Length;
751 while (ptr < ptrend) {
752 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
753 ptr += devscope->Length;
754 match = dmar_match_devscope(devscope, dev_busno, dev_path,
760 *banner = "specific match";
767 static struct dmar_unit *
768 dmar_find_by_scope(int dev_domain, int dev_busno,
769 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
771 struct dmar_unit *unit;
774 for (i = 0; i < dmar_devcnt; i++) {
775 if (dmar_devs[i] == NULL)
777 unit = device_get_softc(dmar_devs[i]);
778 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
786 dmar_find(device_t dev, bool verbose)
789 struct dmar_unit *unit;
791 int i, dev_domain, dev_busno, dev_path_len;
794 * This function can only handle PCI(e) devices.
796 if (device_get_devclass(device_get_parent(dev)) !=
797 devclass_find("pci"))
801 dev_domain = pci_get_domain(dev);
802 dev_path_len = dmar_dev_depth(dev);
803 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
804 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
807 for (i = 0; i < dmar_devcnt; i++) {
808 if (dmar_devs[i] == NULL)
810 unit = device_get_softc(dmar_devs[i]);
811 if (dmar_match_by_path(unit, dev_domain, dev_busno,
812 dev_path, dev_path_len, &banner))
815 if (i == dmar_devcnt)
819 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
820 dev_domain, pci_get_bus(dev), pci_get_slot(dev),
821 pci_get_function(dev), unit->unit, banner);
822 printf(" scope path ");
823 dmar_print_path(dev_busno, dev_path_len, dev_path);
829 static struct dmar_unit *
830 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
833 struct dmar_unit *unit;
834 ACPI_DMAR_HARDWARE_UNIT *dmarh;
835 ACPI_DMAR_DEVICE_SCOPE *devscope;
836 ACPI_DMAR_PCI_PATH *path;
843 for (i = 0; i < dmar_devcnt; i++) {
844 dmar_dev = dmar_devs[i];
845 if (dmar_dev == NULL)
847 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
848 dmarh = dmar_find_by_index(i);
851 ptr = (char *)dmarh + sizeof(*dmarh);
852 ptrend = (char *)dmarh + dmarh->Header.Length;
856 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
857 ptr += devscope->Length;
858 if (devscope->EntryType != entry_type)
860 if (devscope->EnumerationId != id)
863 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
864 error = ioapic_get_rid(id, rid);
866 * If our IOAPIC has PCI bindings then
867 * use the PCI device rid.
873 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
876 path = (ACPI_DMAR_PCI_PATH *)
878 *rid = PCI_RID(devscope->Bus,
879 path->Device, path->Function);
884 "dmar_find_nonpci: id %d type %d path length != 2\n",
894 dmar_find_hpet(device_t dev, uint16_t *rid)
897 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
902 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
905 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
908 struct rmrr_iter_args {
909 struct dmar_domain *domain;
912 const ACPI_DMAR_PCI_PATH *dev_path;
914 struct dmar_map_entries_tailq *rmrr_entries;
918 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
920 struct rmrr_iter_args *ria;
921 ACPI_DMAR_RESERVED_MEMORY *resmem;
922 ACPI_DMAR_DEVICE_SCOPE *devscope;
923 struct dmar_map_entry *entry;
927 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
931 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
932 if (resmem->Segment != ria->dev_domain)
935 ptr = (char *)resmem + sizeof(*resmem);
936 ptrend = (char *)resmem + resmem->Header.Length;
940 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
941 ptr += devscope->Length;
942 match = dmar_match_devscope(devscope, ria->dev_busno,
943 ria->dev_path, ria->dev_path_len);
945 entry = dmar_gas_alloc_entry(ria->domain,
947 entry->start = resmem->BaseAddress;
948 /* The RMRR entry end address is inclusive. */
949 entry->end = resmem->EndAddress;
950 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
959 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
960 const void *dev_path, int dev_path_len,
961 struct dmar_map_entries_tailq *rmrr_entries)
963 struct rmrr_iter_args ria;
966 ria.dev_domain = dev_domain;
967 ria.dev_busno = dev_busno;
968 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
969 ria.dev_path_len = dev_path_len;
970 ria.rmrr_entries = rmrr_entries;
971 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
974 struct inst_rmrr_iter_args {
975 struct dmar_unit *dmar;
979 dmar_path_dev(int segment, int path_len, int busno,
980 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
986 for (i = 0; i < path_len; i++) {
987 dev = pci_find_dbsf(segment, busno, path->Device,
989 if (i != path_len - 1) {
990 busno = pci_cfgregread(busno, path->Device,
991 path->Function, PCIR_SECBUS_1, 1);
995 *rid = PCI_RID(busno, path->Device, path->Function);
1000 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
1002 const ACPI_DMAR_RESERVED_MEMORY *resmem;
1003 const ACPI_DMAR_DEVICE_SCOPE *devscope;
1004 struct inst_rmrr_iter_args *iria;
1005 const char *ptr, *ptrend;
1007 struct dmar_unit *unit;
1013 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
1016 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
1017 if (resmem->Segment != iria->dmar->segment)
1020 ptr = (const char *)resmem + sizeof(*resmem);
1021 ptrend = (const char *)resmem + resmem->Header.Length;
1025 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1026 ptr += devscope->Length;
1028 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1031 dev_path_len = (devscope->Length -
1032 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1033 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1035 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1038 printf("dmar%d no dev found for RMRR "
1039 "[%#jx, %#jx] rid %#x scope path ",
1041 (uintmax_t)resmem->BaseAddress,
1042 (uintmax_t)resmem->EndAddress,
1044 dmar_print_path(devscope->Bus, dev_path_len,
1045 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1048 unit = dmar_find_by_scope(resmem->Segment,
1050 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1052 if (iria->dmar != unit)
1054 dmar_get_ctx_for_devpath(iria->dmar, rid,
1055 resmem->Segment, devscope->Bus,
1056 (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1057 dev_path_len, false, true);
1059 unit = dmar_find(dev, false);
1060 if (iria->dmar != unit)
1062 dmar_instantiate_ctx(iria->dmar, dev, true);
1071 * Pre-create all contexts for the DMAR which have RMRR entries.
1074 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
1076 struct inst_rmrr_iter_args iria;
1079 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1084 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1086 if (!LIST_EMPTY(&dmar->domains)) {
1087 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1088 ("dmar%d: RMRR not handled but translation is already enabled",
1090 error = dmar_enable_translation(dmar);
1093 printf("dmar%d: enabled translation\n",
1096 printf("dmar%d: enabling translation failed, "
1097 "error %d\n", dmar->unit, error);
1101 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1106 #include <ddb/ddb.h>
1107 #include <ddb/db_lex.h>
1110 dmar_print_domain_entry(const struct dmar_map_entry *entry)
1112 struct dmar_map_entry *l, *r;
1115 " start %jx end %jx first %jx last %jx free_down %jx flags %x ",
1116 entry->start, entry->end, entry->first, entry->last,
1117 entry->free_down, entry->flags);
1119 l = RB_LEFT(entry, rb_entry);
1123 db_printf("%jx ", l->start);
1124 db_printf("right ");
1125 r = RB_RIGHT(entry, rb_entry);
1129 db_printf("%jx", r->start);
1134 dmar_print_ctx(struct dmar_ctx *ctx)
1138 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1139 ctx, pci_get_bus(ctx->ctx_tag.owner),
1140 pci_get_slot(ctx->ctx_tag.owner),
1141 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
1142 ctx->loads, ctx->unloads);
1146 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1148 struct dmar_map_entry *entry;
1149 struct dmar_ctx *ctx;
1152 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1153 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1154 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1155 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
1156 domain->flags, domain->pgtbl_obj, domain->entries_cnt);
1157 if (!LIST_EMPTY(&domain->contexts)) {
1158 db_printf(" Contexts:\n");
1159 LIST_FOREACH(ctx, &domain->contexts, link)
1160 dmar_print_ctx(ctx);
1164 db_printf(" mapped:\n");
1165 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
1166 dmar_print_domain_entry(entry);
1172 db_printf(" unloading:\n");
1173 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
1174 dmar_print_domain_entry(entry);
1180 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1182 struct dmar_unit *unit;
1183 struct dmar_domain *domain;
1184 struct dmar_ctx *ctx;
1185 bool show_mappings, valid;
1186 int pci_domain, bus, device, function, i, t;
1192 t = db_read_token();
1194 t = db_read_token();
1196 db_printf("Bad modifier\n");
1201 show_mappings = strchr(db_tok_string, 'm') != NULL;
1202 t = db_read_token();
1204 show_mappings = false;
1207 pci_domain = db_tok_number;
1208 t = db_read_token();
1210 bus = db_tok_number;
1211 t = db_read_token();
1213 device = db_tok_number;
1214 t = db_read_token();
1216 function = db_tok_number;
1225 db_printf("usage: show dmar_domain [/m] "
1226 "<domain> <bus> <device> <func>\n");
1229 for (i = 0; i < dmar_devcnt; i++) {
1230 unit = device_get_softc(dmar_devs[i]);
1231 LIST_FOREACH(domain, &unit->domains, link) {
1232 LIST_FOREACH(ctx, &domain->contexts, link) {
1233 if (pci_domain == unit->segment &&
1234 bus == pci_get_bus(ctx->ctx_tag.owner) &&
1236 pci_get_slot(ctx->ctx_tag.owner) &&
1238 pci_get_function(ctx->ctx_tag.owner)) {
1239 dmar_print_domain(domain,
1250 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1252 struct dmar_unit *unit;
1253 struct dmar_domain *domain;
1256 unit = device_get_softc(dmar_devs[idx]);
1257 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1258 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1259 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1260 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1261 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1262 dmar_read4(unit, DMAR_GSTS_REG),
1263 dmar_read4(unit, DMAR_FSTS_REG),
1264 dmar_read4(unit, DMAR_FECTL_REG));
1265 if (unit->ir_enabled) {
1266 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1267 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1269 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1270 dmar_read4(unit, DMAR_FEDATA_REG),
1271 dmar_read4(unit, DMAR_FEADDR_REG),
1272 dmar_read4(unit, DMAR_FEUADDR_REG));
1273 db_printf("primary fault log:\n");
1274 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1275 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1276 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1277 (uintmax_t)dmar_read8(unit, frir),
1278 (uintmax_t)dmar_read8(unit, frir + 8));
1280 if (DMAR_HAS_QI(unit)) {
1281 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1282 dmar_read4(unit, DMAR_IEDATA_REG),
1283 dmar_read4(unit, DMAR_IEADDR_REG),
1284 dmar_read4(unit, DMAR_IEUADDR_REG));
1285 if (unit->qi_enabled) {
1286 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1288 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1289 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1290 (uintmax_t)unit->inv_queue,
1291 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1292 (uintmax_t)unit->inv_queue_size,
1293 dmar_read4(unit, DMAR_IQH_REG),
1294 dmar_read4(unit, DMAR_IQT_REG),
1295 unit->inv_queue_avail,
1296 dmar_read4(unit, DMAR_ICS_REG),
1297 dmar_read4(unit, DMAR_IECTL_REG),
1298 unit->inv_waitd_seq_hw,
1299 &unit->inv_waitd_seq_hw,
1300 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1301 unit->inv_waitd_seq,
1302 unit->inv_waitd_gen);
1304 db_printf("qi is disabled\n");
1308 db_printf("domains:\n");
1309 LIST_FOREACH(domain, &unit->domains, link) {
1310 dmar_print_domain(domain, show_mappings);
1317 DB_SHOW_COMMAND(dmar, db_dmar_print)
1319 bool show_domains, show_mappings;
1321 show_domains = strchr(modif, 'd') != NULL;
1322 show_mappings = strchr(modif, 'm') != NULL;
1324 db_printf("usage: show dmar [/d] [/m] index\n");
1327 dmar_print_one((int)addr, show_domains, show_mappings);
1330 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1333 bool show_domains, show_mappings;
1335 show_domains = strchr(modif, 'd') != NULL;
1336 show_mappings = strchr(modif, 'm') != NULL;
1338 for (i = 0; i < dmar_devcnt; i++) {
1339 dmar_print_one(i, show_domains, show_mappings);