2 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #if defined(__amd64__)
41 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/memdesc.h>
47 #include <sys/module.h>
49 #include <sys/rwlock.h>
51 #include <sys/taskqueue.h>
54 #include <machine/bus.h>
55 #include <contrib/dev/acpica/include/acpi.h>
56 #include <contrib/dev/acpica/include/accommon.h>
57 #include <dev/acpica/acpivar.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_object.h>
62 #include <vm/vm_page.h>
63 #include <vm/vm_pager.h>
64 #include <vm/vm_map.h>
65 #include <x86/include/busdma_impl.h>
66 #include <x86/iommu/intel_reg.h>
67 #include <x86/iommu/busdma_dmar.h>
68 #include <x86/iommu/intel_dmar.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
76 #define DMAR_FAULT_IRQ_RID 0
77 #define DMAR_QI_IRQ_RID 1
78 #define DMAR_REG_RID 2
80 static devclass_t dmar_devclass;
81 static device_t *dmar_devs;
82 static int dmar_devcnt;
84 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
87 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
89 ACPI_TABLE_DMAR *dmartbl;
90 ACPI_DMAR_HEADER *dmarh;
94 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
95 if (ACPI_FAILURE(status))
97 ptr = (char *)dmartbl + sizeof(*dmartbl);
98 ptrend = (char *)dmartbl + dmartbl->Header.Length;
102 dmarh = (ACPI_DMAR_HEADER *)ptr;
103 if (dmarh->Length <= 0) {
104 printf("dmar_identify: corrupted DMAR table, l %d\n",
108 ptr += dmarh->Length;
109 if (!iter(dmarh, arg))
112 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
115 struct find_iter_args {
117 ACPI_DMAR_HARDWARE_UNIT *res;
121 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
123 struct find_iter_args *fia;
125 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
130 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
137 static ACPI_DMAR_HARDWARE_UNIT *
138 dmar_find_by_index(int idx)
140 struct find_iter_args fia;
144 dmar_iterate_tbl(dmar_find_iter, &fia);
149 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
152 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
157 static int dmar_enable = 0;
159 dmar_identify(driver_t *driver, device_t parent)
161 ACPI_TABLE_DMAR *dmartbl;
162 ACPI_DMAR_HARDWARE_UNIT *dmarh;
166 if (acpi_disabled("dmar"))
168 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
172 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
174 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose);
175 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
176 if (ACPI_FAILURE(status))
178 haw = dmartbl->Width + 1;
179 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
180 dmar_high = BUS_SPACE_MAXADDR;
182 dmar_high = 1ULL << (haw + 1);
184 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
185 (unsigned)dmartbl->Flags,
186 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
188 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
190 dmar_iterate_tbl(dmar_count_iter, NULL);
191 if (dmar_devcnt == 0)
193 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
195 for (i = 0; i < dmar_devcnt; i++) {
196 dmarh = dmar_find_by_index(i);
198 printf("dmar_identify: cannot find HWUNIT %d\n", i);
201 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
202 if (dmar_devs[i] == NULL) {
203 printf("dmar_identify: cannot create instance %d\n", i);
206 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
207 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
210 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
211 i, (uintmax_t)dmarh->Address, error);
212 device_delete_child(parent, dmar_devs[i]);
219 dmar_probe(device_t dev)
222 if (acpi_get_handle(dev) != NULL)
224 device_set_desc(dev, "DMA remap");
225 return (BUS_PROBE_NOWILDCARD);
229 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
231 struct dmar_msi_data *dmd;
233 dmd = &unit->intrs[idx];
236 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
237 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
238 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
239 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
245 dmar_release_resources(device_t dev, struct dmar_unit *unit)
249 dmar_fini_busdma(unit);
252 dmar_fini_fault_log(unit);
253 for (i = 0; i < DMAR_INTR_TOTAL; i++)
254 dmar_release_intr(dev, unit, i);
255 if (unit->regs != NULL) {
256 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
258 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
262 if (unit->domids != NULL) {
263 delete_unrhdr(unit->domids);
266 if (unit->ctx_obj != NULL) {
267 vm_object_deallocate(unit->ctx_obj);
268 unit->ctx_obj = NULL;
273 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
276 struct dmar_msi_data *dmd;
281 dmd = &unit->intrs[idx];
282 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
283 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
285 device_printf(dev, "cannot allocate %s interrupt, %d\n",
289 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
292 device_printf(dev, "cannot set %s interrupt resource, %d\n",
296 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
297 &dmd->irq_rid, RF_ACTIVE);
298 if (dmd->irq_res == NULL) {
300 "cannot allocate resource for %s interrupt\n", dmd->name);
304 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
305 dmd->handler, NULL, unit, &dmd->intr_handle);
307 device_printf(dev, "cannot setup %s interrupt, %d\n",
311 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
312 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
314 device_printf(dev, "cannot map %s interrupt, %d\n",
318 dmar_write4(unit, dmd->msi_data_reg, msi_data);
319 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
320 /* Only for xAPIC mode */
321 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
325 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
327 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
329 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
331 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
339 dmar_remap_intr(device_t dev, device_t child, u_int irq)
341 struct dmar_unit *unit;
342 struct dmar_msi_data *dmd;
347 unit = device_get_softc(dev);
348 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
349 dmd = &unit->intrs[i];
350 if (irq == dmd->irq) {
351 error = PCIB_MAP_MSI(device_get_parent(
352 device_get_parent(dev)),
353 dev, irq, &msi_addr, &msi_data);
357 (dmd->disable_intr)(unit);
358 dmar_write4(unit, dmd->msi_data_reg, msi_data);
359 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
360 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
361 (dmd->enable_intr)(unit);
371 dmar_print_caps(device_t dev, struct dmar_unit *unit,
372 ACPI_DMAR_HARDWARE_UNIT *dmaru)
374 uint32_t caphi, ecaphi;
376 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
377 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
378 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
379 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
380 caphi = unit->hw_cap >> 32;
381 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
382 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
383 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
384 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
385 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
386 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
387 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
388 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
389 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
391 ecaphi = unit->hw_ecap >> 32;
392 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
393 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
394 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
395 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
396 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
397 DMAR_ECAP_IRO(unit->hw_ecap));
401 dmar_attach(device_t dev)
403 struct dmar_unit *unit;
404 ACPI_DMAR_HARDWARE_UNIT *dmaru;
407 unit = device_get_softc(dev);
409 unit->unit = device_get_unit(dev);
410 dmaru = dmar_find_by_index(unit->unit);
413 unit->segment = dmaru->Segment;
414 unit->base = dmaru->Address;
415 unit->reg_rid = DMAR_REG_RID;
416 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
417 &unit->reg_rid, RF_ACTIVE);
418 if (unit->regs == NULL) {
419 device_printf(dev, "cannot allocate register window\n");
422 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
423 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
424 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
426 dmar_print_caps(dev, unit, dmaru);
427 dmar_quirks_post_ident(unit);
429 for (i = 0; i < DMAR_INTR_TOTAL; i++)
430 unit->intrs[i].irq = -1;
432 unit->intrs[DMAR_INTR_FAULT].name = "fault";
433 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
434 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
435 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
436 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
437 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
438 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
439 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
440 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
442 dmar_release_resources(dev, unit);
445 if (DMAR_HAS_QI(unit)) {
446 unit->intrs[DMAR_INTR_QI].name = "qi";
447 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
448 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
449 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
450 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
451 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
452 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
453 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
454 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
456 dmar_release_resources(dev, unit);
461 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
462 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
464 LIST_INIT(&unit->domains);
467 * 9.2 "Context Entry":
468 * When Caching Mode (CM) field is reported as Set, the
469 * domain-id value of zero is architecturally reserved.
470 * Software must not use domain-id value of zero
473 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
474 alloc_unr_specific(unit->domids, 0);
476 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
477 DMAR_CTX_CNT), 0, 0, NULL);
480 * Allocate and load the root entry table pointer. Enable the
481 * address translation after the required invalidations are
484 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
486 error = dmar_load_root_entry_ptr(unit);
489 dmar_release_resources(dev, unit);
492 error = dmar_inv_ctx_glob(unit);
495 dmar_release_resources(dev, unit);
498 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
499 error = dmar_inv_iotlb_glob(unit);
502 dmar_release_resources(dev, unit);
508 error = dmar_init_fault_log(unit);
510 dmar_release_resources(dev, unit);
513 error = dmar_init_qi(unit);
515 dmar_release_resources(dev, unit);
518 error = dmar_init_irt(unit);
520 dmar_release_resources(dev, unit);
523 error = dmar_init_busdma(unit);
525 dmar_release_resources(dev, unit);
531 error = dmar_enable_translation(unit);
534 dmar_release_resources(dev, unit);
544 dmar_detach(device_t dev)
551 dmar_suspend(device_t dev)
558 dmar_resume(device_t dev)
565 static device_method_t dmar_methods[] = {
566 DEVMETHOD(device_identify, dmar_identify),
567 DEVMETHOD(device_probe, dmar_probe),
568 DEVMETHOD(device_attach, dmar_attach),
569 DEVMETHOD(device_detach, dmar_detach),
570 DEVMETHOD(device_suspend, dmar_suspend),
571 DEVMETHOD(device_resume, dmar_resume),
573 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
578 static driver_t dmar_driver = {
581 sizeof(struct dmar_unit),
584 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
585 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
588 dmar_print_path(device_t dev, const char *banner, int busno, int depth,
589 const ACPI_DMAR_PCI_PATH *path)
593 device_printf(dev, "%s [%d, ", banner, busno);
594 for (i = 0; i < depth; i++) {
597 printf("(%d, %d)", path[i].Device, path[i].Function);
603 dmar_dev_depth(device_t child)
605 devclass_t pci_class;
609 pci_class = devclass_find("pci");
610 for (depth = 1; ; depth++) {
611 bus = device_get_parent(child);
612 pcib = device_get_parent(bus);
613 if (device_get_devclass(device_get_parent(pcib)) !=
621 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth)
623 devclass_t pci_class;
626 pci_class = devclass_find("pci");
627 for (depth--; depth != -1; depth--) {
628 path[depth].Device = pci_get_slot(child);
629 path[depth].Function = pci_get_function(child);
630 bus = device_get_parent(child);
631 pcib = device_get_parent(bus);
632 if (device_get_devclass(device_get_parent(pcib)) !=
634 /* reached a host bridge */
635 *busno = pcib_get_bus(bus);
640 panic("wrong depth");
644 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
645 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
646 enum AcpiDmarScopeType scope_type)
650 if (busno1 != busno2)
652 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
657 for (i = 0; i < depth; i++) {
658 if (path1[i].Device != path2[i].Device ||
659 path1[i].Function != path2[i].Function)
666 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev,
667 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
669 ACPI_DMAR_PCI_PATH *path;
672 if (devscope->Length < sizeof(*devscope)) {
673 printf("dmar_find: corrupted DMAR table, dl %d\n",
677 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
678 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
680 path_len = devscope->Length - sizeof(*devscope);
681 if (path_len % 2 != 0) {
682 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n",
687 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
689 printf("dmar_find: corrupted DMAR table, dl %d\n",
693 if (dmar_match_verbose)
694 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path);
696 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
697 dev_path, dev_path_len, devscope->EntryType));
701 dmar_find(device_t dev)
704 ACPI_DMAR_HARDWARE_UNIT *dmarh;
705 ACPI_DMAR_DEVICE_SCOPE *devscope;
707 int i, match, dev_domain, dev_busno, dev_path_len;
710 dev_domain = pci_get_domain(dev);
711 dev_path_len = dmar_dev_depth(dev);
712 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
713 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
714 if (dmar_match_verbose)
715 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path);
717 for (i = 0; i < dmar_devcnt; i++) {
718 if (dmar_devs[i] == NULL)
720 dmarh = dmar_find_by_index(i);
723 if (dmarh->Segment != dev_domain)
725 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
726 dmar_dev = dmar_devs[i];
727 if (dmar_match_verbose) {
729 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n",
730 dev_domain, pci_get_bus(dev),
732 pci_get_function(dev),
733 ((struct dmar_unit *)device_get_softc(
738 ptr = (char *)dmarh + sizeof(*dmarh);
739 ptrend = (char *)dmarh + dmarh->Header.Length;
743 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
744 ptr += devscope->Length;
745 if (dmar_match_verbose) {
747 "pci%d:%d:%d:%d matching dmar%d\n",
748 dev_domain, pci_get_bus(dev),
750 pci_get_function(dev),
751 ((struct dmar_unit *)device_get_softc(
752 dmar_devs[i]))->unit);
754 match = dmar_match_devscope(devscope, dev, dev_busno,
755 dev_path, dev_path_len);
756 if (dmar_match_verbose) {
758 printf("table error\n");
760 printf("not matched\n");
766 else if (match == 1) {
767 dmar_dev = dmar_devs[i];
774 return (device_get_softc(dmar_dev));
777 static struct dmar_unit *
778 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
781 struct dmar_unit *unit;
782 ACPI_DMAR_HARDWARE_UNIT *dmarh;
783 ACPI_DMAR_DEVICE_SCOPE *devscope;
784 ACPI_DMAR_PCI_PATH *path;
788 for (i = 0; i < dmar_devcnt; i++) {
789 dmar_dev = dmar_devs[i];
790 if (dmar_dev == NULL)
792 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
793 dmarh = dmar_find_by_index(i);
796 ptr = (char *)dmarh + sizeof(*dmarh);
797 ptrend = (char *)dmarh + dmarh->Header.Length;
801 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
802 ptr += devscope->Length;
803 if (devscope->EntryType != entry_type)
805 if (devscope->EnumerationId != id)
807 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
810 path = (ACPI_DMAR_PCI_PATH *)
812 *rid = PCI_RID(devscope->Bus,
813 path->Device, path->Function);
819 "dmar_find_nonpci: id %d type %d path length != 2\n",
829 dmar_find_hpet(device_t dev, uint16_t *rid)
832 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
837 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
840 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
843 struct rmrr_iter_args {
844 struct dmar_domain *domain;
848 ACPI_DMAR_PCI_PATH *dev_path;
850 struct dmar_map_entries_tailq *rmrr_entries;
854 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
856 struct rmrr_iter_args *ria;
857 ACPI_DMAR_RESERVED_MEMORY *resmem;
858 ACPI_DMAR_DEVICE_SCOPE *devscope;
859 struct dmar_map_entry *entry;
863 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
867 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
868 if (dmar_match_verbose) {
869 printf("RMRR [%jx,%jx] segment %d\n",
870 (uintmax_t)resmem->BaseAddress,
871 (uintmax_t)resmem->EndAddress,
874 if (resmem->Segment != ria->dev_domain)
877 ptr = (char *)resmem + sizeof(*resmem);
878 ptrend = (char *)resmem + resmem->Header.Length;
882 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
883 ptr += devscope->Length;
884 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno,
885 ria->dev_path, ria->dev_path_len);
887 if (dmar_match_verbose)
889 entry = dmar_gas_alloc_entry(ria->domain,
891 entry->start = resmem->BaseAddress;
892 /* The RMRR entry end address is inclusive. */
893 entry->end = resmem->EndAddress;
894 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
896 } else if (dmar_match_verbose) {
897 printf("not matched, err %d\n", match);
905 dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev,
906 struct dmar_map_entries_tailq *rmrr_entries)
908 struct rmrr_iter_args ria;
910 ria.dev_domain = pci_get_domain(dev);
911 ria.dev_path_len = dmar_dev_depth(dev);
912 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len];
913 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len);
915 if (dmar_match_verbose) {
916 device_printf(dev, "parsing RMRR entries for ");
917 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len,
923 ria.dev_path = dev_path;
924 ria.rmrr_entries = rmrr_entries;
925 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
928 struct inst_rmrr_iter_args {
929 struct dmar_unit *dmar;
933 dmar_path_dev(int segment, int path_len, int busno,
934 const ACPI_DMAR_PCI_PATH *path)
936 devclass_t pci_class;
937 device_t bus, pcib, dev;
940 pci_class = devclass_find("pci");
942 for (i = 0; i < path_len; i++, path++) {
943 dev = pci_find_dbsf(segment, busno, path->Device,
947 if (i != path_len - 1) {
948 bus = device_get_parent(dev);
949 pcib = device_get_parent(bus);
950 if (device_get_devclass(device_get_parent(pcib)) !=
954 busno = pcib_get_bus(dev);
960 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
962 const ACPI_DMAR_RESERVED_MEMORY *resmem;
963 const ACPI_DMAR_DEVICE_SCOPE *devscope;
964 struct inst_rmrr_iter_args *iria;
965 const char *ptr, *ptrend;
966 struct dmar_unit *dev_dmar;
969 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
973 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
974 if (resmem->Segment != iria->dmar->segment)
976 if (dmar_match_verbose) {
977 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
978 (uintmax_t)resmem->BaseAddress,
979 (uintmax_t)resmem->EndAddress);
982 ptr = (const char *)resmem + sizeof(*resmem);
983 ptrend = (const char *)resmem + resmem->Header.Length;
987 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
988 ptr += devscope->Length;
990 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
992 if (dmar_match_verbose) {
993 dmar_print_path(iria->dmar->dev, "RMRR scope",
994 devscope->Bus, (devscope->Length -
995 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
996 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
998 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
999 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
1000 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1002 if (dmar_match_verbose)
1003 printf("null dev\n");
1006 dev_dmar = dmar_find(dev);
1007 if (dev_dmar != iria->dmar) {
1008 if (dmar_match_verbose) {
1009 printf("dmar%d matched, skipping\n",
1014 if (dmar_match_verbose)
1015 printf("matched, instantiating RMRR context\n");
1016 dmar_instantiate_ctx(iria->dmar, dev, true);
1024 * Pre-create all contexts for the DMAR which have RMRR entries.
1027 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
1029 struct inst_rmrr_iter_args iria;
1032 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1037 if (dmar_match_verbose)
1038 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
1039 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1041 if (!LIST_EMPTY(&dmar->domains)) {
1042 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1043 ("dmar%d: RMRR not handled but translation is already enabled",
1045 error = dmar_enable_translation(dmar);
1047 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1052 #include <ddb/ddb.h>
1053 #include <ddb/db_lex.h>
1056 dmar_print_domain_entry(const struct dmar_map_entry *entry)
1058 struct dmar_map_entry *l, *r;
1061 " start %jx end %jx free_after %jx free_down %jx flags %x ",
1062 entry->start, entry->end, entry->free_after, entry->free_down,
1065 l = RB_LEFT(entry, rb_entry);
1069 db_printf("%jx ", l->start);
1070 db_printf("right ");
1071 r = RB_RIGHT(entry, rb_entry);
1075 db_printf("%jx", r->start);
1080 dmar_print_ctx(struct dmar_ctx *ctx)
1084 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1085 ctx, pci_get_bus(ctx->ctx_tag.owner),
1086 pci_get_slot(ctx->ctx_tag.owner),
1087 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
1088 ctx->loads, ctx->unloads);
1092 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1094 struct dmar_map_entry *entry;
1095 struct dmar_ctx *ctx;
1098 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1099 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1100 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1101 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
1102 domain->flags, domain->pgtbl_obj, domain->entries_cnt);
1103 if (!LIST_EMPTY(&domain->contexts)) {
1104 db_printf(" Contexts:\n");
1105 LIST_FOREACH(ctx, &domain->contexts, link)
1106 dmar_print_ctx(ctx);
1110 db_printf(" mapped:\n");
1111 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
1112 dmar_print_domain_entry(entry);
1118 db_printf(" unloading:\n");
1119 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
1120 dmar_print_domain_entry(entry);
1126 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1128 struct dmar_unit *unit;
1129 struct dmar_domain *domain;
1130 struct dmar_ctx *ctx;
1131 bool show_mappings, valid;
1132 int pci_domain, bus, device, function, i, t;
1138 t = db_read_token();
1140 t = db_read_token();
1142 db_printf("Bad modifier\n");
1147 show_mappings = strchr(db_tok_string, 'm') != NULL;
1148 t = db_read_token();
1150 show_mappings = false;
1153 pci_domain = db_tok_number;
1154 t = db_read_token();
1156 bus = db_tok_number;
1157 t = db_read_token();
1159 device = db_tok_number;
1160 t = db_read_token();
1162 function = db_tok_number;
1171 db_printf("usage: show dmar_domain [/m] "
1172 "<domain> <bus> <device> <func>\n");
1175 for (i = 0; i < dmar_devcnt; i++) {
1176 unit = device_get_softc(dmar_devs[i]);
1177 LIST_FOREACH(domain, &unit->domains, link) {
1178 LIST_FOREACH(ctx, &domain->contexts, link) {
1179 if (pci_domain == unit->segment &&
1180 bus == pci_get_bus(ctx->ctx_tag.owner) &&
1182 pci_get_slot(ctx->ctx_tag.owner) &&
1184 pci_get_function(ctx->ctx_tag.owner)) {
1185 dmar_print_domain(domain,
1196 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1198 struct dmar_unit *unit;
1199 struct dmar_domain *domain;
1202 unit = device_get_softc(dmar_devs[idx]);
1203 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1204 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1205 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1206 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1207 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1208 dmar_read4(unit, DMAR_GSTS_REG),
1209 dmar_read4(unit, DMAR_FSTS_REG),
1210 dmar_read4(unit, DMAR_FECTL_REG));
1211 if (unit->ir_enabled) {
1212 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1213 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1215 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1216 dmar_read4(unit, DMAR_FEDATA_REG),
1217 dmar_read4(unit, DMAR_FEADDR_REG),
1218 dmar_read4(unit, DMAR_FEUADDR_REG));
1219 db_printf("primary fault log:\n");
1220 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1221 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1222 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1223 (uintmax_t)dmar_read8(unit, frir),
1224 (uintmax_t)dmar_read8(unit, frir + 8));
1226 if (DMAR_HAS_QI(unit)) {
1227 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1228 dmar_read4(unit, DMAR_IEDATA_REG),
1229 dmar_read4(unit, DMAR_IEADDR_REG),
1230 dmar_read4(unit, DMAR_IEUADDR_REG));
1231 if (unit->qi_enabled) {
1232 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1234 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1235 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1236 (uintmax_t)unit->inv_queue,
1237 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1238 (uintmax_t)unit->inv_queue_size,
1239 dmar_read4(unit, DMAR_IQH_REG),
1240 dmar_read4(unit, DMAR_IQT_REG),
1241 unit->inv_queue_avail,
1242 dmar_read4(unit, DMAR_ICS_REG),
1243 dmar_read4(unit, DMAR_IECTL_REG),
1244 unit->inv_waitd_seq_hw,
1245 &unit->inv_waitd_seq_hw,
1246 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1247 unit->inv_waitd_seq,
1248 unit->inv_waitd_gen);
1250 db_printf("qi is disabled\n");
1254 db_printf("domains:\n");
1255 LIST_FOREACH(domain, &unit->domains, link) {
1256 dmar_print_domain(domain, show_mappings);
1263 DB_SHOW_COMMAND(dmar, db_dmar_print)
1265 bool show_domains, show_mappings;
1267 show_domains = strchr(modif, 'd') != NULL;
1268 show_mappings = strchr(modif, 'm') != NULL;
1270 db_printf("usage: show dmar [/d] [/m] index\n");
1273 dmar_print_one((int)addr, show_domains, show_mappings);
1276 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1279 bool show_domains, show_mappings;
1281 show_domains = strchr(modif, 'd') != NULL;
1282 show_mappings = strchr(modif, 'm') != NULL;
1284 for (i = 0; i < dmar_devcnt; i++) {
1285 dmar_print_one(i, show_domains, show_mappings);