sys/x86/iommu/intel_drv.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2013-2015 The FreeBSD Foundation
   5  * All rights reserved.
   6  *
   7  * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
   8  * under sponsorship from the FreeBSD Foundation.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include "opt_acpi.h"
  36 #if defined(__amd64__)
  37 #define DEV_APIC
  38 #else
  39 #include "opt_apic.h"
  40 #endif
  41 #include "opt_ddb.h"
  42
  43 #include <sys/param.h>
  44 #include <sys/bus.h>
  45 #include <sys/kernel.h>
  46 #include <sys/lock.h>
  47 #include <sys/malloc.h>
  48 #include <sys/memdesc.h>
  49 #include <sys/module.h>
  50 #include <sys/mutex.h>
  51 #include <sys/rman.h>
  52 #include <sys/rwlock.h>
  53 #include <sys/smp.h>
  54 #include <sys/taskqueue.h>
  55 #include <sys/tree.h>
  56 #include <sys/vmem.h>
  57 #include <vm/vm.h>
  58 #include <vm/vm_extern.h>
  59 #include <vm/vm_kern.h>
  60 #include <vm/vm_object.h>
  61 #include <vm/vm_page.h>
  62 #include <vm/vm_pager.h>
  63 #include <vm/vm_map.h>
  64 #include <contrib/dev/acpica/include/acpi.h>
  65 #include <contrib/dev/acpica/include/accommon.h>
  66 #include <dev/acpica/acpivar.h>
  67 #include <dev/pci/pcireg.h>
  68 #include <dev/pci/pcivar.h>
  69 #include <machine/bus.h>
  70 #include <machine/pci_cfgreg.h>
  71 #include <x86/include/busdma_impl.h>
  72 #include <dev/iommu/busdma_iommu.h>
  73 #include <x86/iommu/intel_reg.h>
  74 #include <x86/iommu/intel_dmar.h>
  75
  76 #ifdef DEV_APIC
  77 #include "pcib_if.h"
  78 #include <machine/intr_machdep.h>
  79 #include <x86/apicreg.h>
  80 #include <x86/apicvar.h>
  81 #endif
  82
  83 #define DMAR_FAULT_IRQ_RID      0
  84 #define DMAR_QI_IRQ_RID         1
  85 #define DMAR_REG_RID            2
  86
  87 static devclass_t dmar_devclass;
  88 static device_t *dmar_devs;
  89 static int dmar_devcnt;
  90
  91 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
  92
  93 static void
  94 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
  95 {
  96         ACPI_TABLE_DMAR *dmartbl;
  97         ACPI_DMAR_HEADER *dmarh;
  98         char *ptr, *ptrend;
  99         ACPI_STATUS status;
 100
 101         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
 102         if (ACPI_FAILURE(status))
 103                 return;
 104         ptr = (char *)dmartbl + sizeof(*dmartbl);
 105         ptrend = (char *)dmartbl + dmartbl->Header.Length;
 106         for (;;) {
 107                 if (ptr >= ptrend)
 108                         break;
 109                 dmarh = (ACPI_DMAR_HEADER *)ptr;
 110                 if (dmarh->Length <= 0) {
 111                         printf("dmar_identify: corrupted DMAR table, l %d\n",
 112                             dmarh->Length);
 113                         break;
 114                 }
 115                 ptr += dmarh->Length;
 116                 if (!iter(dmarh, arg))
 117                         break;
 118         }
 119         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
 120 }
 121
 122 struct find_iter_args {
 123         int i;
 124         ACPI_DMAR_HARDWARE_UNIT *res;
 125 };
 126
 127 static int
 128 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
 129 {
 130         struct find_iter_args *fia;
 131
 132         if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
 133                 return (1);
 134
 135         fia = arg;
 136         if (fia->i == 0) {
 137                 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
 138                 return (0);
 139         }
 140         fia->i--;
 141         return (1);
 142 }
 143
 144 static ACPI_DMAR_HARDWARE_UNIT *
 145 dmar_find_by_index(int idx)
 146 {
 147         struct find_iter_args fia;
 148
 149         fia.i = idx;
 150         fia.res = NULL;
 151         dmar_iterate_tbl(dmar_find_iter, &fia);
 152         return (fia.res);
 153 }
 154
 155 static int
 156 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
 157 {
 158
 159         if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
 160                 dmar_devcnt++;
 161         return (1);
 162 }
 163
 164 static int dmar_enable = 0;
 165 static void
 166 dmar_identify(driver_t *driver, device_t parent)
 167 {
 168         ACPI_TABLE_DMAR *dmartbl;
 169         ACPI_DMAR_HARDWARE_UNIT *dmarh;
 170         ACPI_STATUS status;
 171         int i, error;
 172
 173         if (acpi_disabled("dmar"))
 174                 return;
 175         TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
 176         if (!dmar_enable)
 177                 return;
 178         status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
 179         if (ACPI_FAILURE(status))
 180                 return;
 181         haw = dmartbl->Width + 1;
 182         if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
 183                 dmar_high = BUS_SPACE_MAXADDR;
 184         else
 185                 dmar_high = 1ULL << (haw + 1);
 186         if (bootverbose) {
 187                 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
 188                     (unsigned)dmartbl->Flags,
 189                     "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
 190         }
 191         AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl);
 192
 193         dmar_iterate_tbl(dmar_count_iter, NULL);
 194         if (dmar_devcnt == 0)
 195                 return;
 196         dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
 197             M_WAITOK | M_ZERO);
 198         for (i = 0; i < dmar_devcnt; i++) {
 199                 dmarh = dmar_find_by_index(i);
 200                 if (dmarh == NULL) {
 201                         printf("dmar_identify: cannot find HWUNIT %d\n", i);
 202                         continue;
 203                 }
 204                 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
 205                 if (dmar_devs[i] == NULL) {
 206                         printf("dmar_identify: cannot create instance %d\n", i);
 207                         continue;
 208                 }
 209                 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
 210                     DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
 211                 if (error != 0) {
 212                         printf(
 213         "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
 214                             i, (uintmax_t)dmarh->Address, error);
 215                         device_delete_child(parent, dmar_devs[i]);
 216                         dmar_devs[i] = NULL;
 217                 }
 218         }
 219 }
 220
 221 static int
 222 dmar_probe(device_t dev)
 223 {
 224
 225         if (acpi_get_handle(dev) != NULL)
 226                 return (ENXIO);
 227         device_set_desc(dev, "DMA remap");
 228         return (BUS_PROBE_NOWILDCARD);
 229 }
 230
 231 static void
 232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
 233 {
 234         struct dmar_msi_data *dmd;
 235
 236         dmd = &unit->intrs[idx];
 237         if (dmd->irq == -1)
 238                 return;
 239         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
 240         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
 241         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
 242         PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
 243             dev, dmd->irq);
 244         dmd->irq = -1;
 245 }
 246
 247 static void
 248 dmar_release_resources(device_t dev, struct dmar_unit *unit)
 249 {
 250         int i;
 251
 252         iommu_fini_busdma(&unit->iommu);
 253         dmar_fini_irt(unit);
 254         dmar_fini_qi(unit);
 255         dmar_fini_fault_log(unit);
 256         for (i = 0; i < DMAR_INTR_TOTAL; i++)
 257                 dmar_release_intr(dev, unit, i);
 258         if (unit->regs != NULL) {
 259                 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
 260                     unit->regs);
 261                 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
 262                     unit->regs);
 263                 unit->regs = NULL;
 264         }
 265         if (unit->domids != NULL) {
 266                 delete_unrhdr(unit->domids);
 267                 unit->domids = NULL;
 268         }
 269         if (unit->ctx_obj != NULL) {
 270                 vm_object_deallocate(unit->ctx_obj);
 271                 unit->ctx_obj = NULL;
 272         }
 273 }
 274
 275 static int
 276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
 277 {
 278         device_t pcib;
 279         struct dmar_msi_data *dmd;
 280         uint64_t msi_addr;
 281         uint32_t msi_data;
 282         int error;
 283
 284         dmd = &unit->intrs[idx];
 285         pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
 286         error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
 287         if (error != 0) {
 288                 device_printf(dev, "cannot allocate %s interrupt, %d\n",
 289                     dmd->name, error);
 290                 goto err1;
 291         }
 292         error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
 293             dmd->irq, 1);
 294         if (error != 0) {
 295                 device_printf(dev, "cannot set %s interrupt resource, %d\n",
 296                     dmd->name, error);
 297                 goto err2;
 298         }
 299         dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 300             &dmd->irq_rid, RF_ACTIVE);
 301         if (dmd->irq_res == NULL) {
 302                 device_printf(dev,
 303                     "cannot allocate resource for %s interrupt\n", dmd->name);
 304                 error = ENXIO;
 305                 goto err3;
 306         }
 307         error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
 308             dmd->handler, NULL, unit, &dmd->intr_handle);
 309         if (error != 0) {
 310                 device_printf(dev, "cannot setup %s interrupt, %d\n",
 311                     dmd->name, error);
 312                 goto err4;
 313         }
 314         bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
 315         error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
 316         if (error != 0) {
 317                 device_printf(dev, "cannot map %s interrupt, %d\n",
 318                     dmd->name, error);
 319                 goto err5;
 320         }
 321         dmar_write4(unit, dmd->msi_data_reg, msi_data);
 322         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
 323         /* Only for xAPIC mode */
 324         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
 325         return (0);
 326
 327 err5:
 328         bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
 329 err4:
 330         bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
 331 err3:
 332         bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
 333 err2:
 334         PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
 335         dmd->irq = -1;
 336 err1:
 337         return (error);
 338 }
 339
 340 #ifdef DEV_APIC
 341 static int
 342 dmar_remap_intr(device_t dev, device_t child, u_int irq)
 343 {
 344         struct dmar_unit *unit;
 345         struct dmar_msi_data *dmd;
 346         uint64_t msi_addr;
 347         uint32_t msi_data;
 348         int i, error;
 349
 350         unit = device_get_softc(dev);
 351         for (i = 0; i < DMAR_INTR_TOTAL; i++) {
 352                 dmd = &unit->intrs[i];
 353                 if (irq == dmd->irq) {
 354                         error = PCIB_MAP_MSI(device_get_parent(
 355                             device_get_parent(dev)),
 356                             dev, irq, &msi_addr, &msi_data);
 357                         if (error != 0)
 358                                 return (error);
 359                         DMAR_LOCK(unit);
 360                         (dmd->disable_intr)(unit);
 361                         dmar_write4(unit, dmd->msi_data_reg, msi_data);
 362                         dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
 363                         dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
 364                         (dmd->enable_intr)(unit);
 365                         DMAR_UNLOCK(unit);
 366                         return (0);
 367                 }
 368         }
 369         return (ENOENT);
 370 }
 371 #endif
 372
 373 static void
 374 dmar_print_caps(device_t dev, struct dmar_unit *unit,
 375     ACPI_DMAR_HARDWARE_UNIT *dmaru)
 376 {
 377         uint32_t caphi, ecaphi;
 378
 379         device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
 380             (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
 381             DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
 382             dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
 383         caphi = unit->hw_cap >> 32;
 384         device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
 385             "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
 386         printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
 387         printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
 388             DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
 389             DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
 390             DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
 391         if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
 392                 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
 393         printf("\n");
 394         ecaphi = unit->hw_ecap >> 32;
 395         device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
 396             "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
 397             "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
 398         printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
 399         printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
 400             DMAR_ECAP_IRO(unit->hw_ecap));
 401 }
 402
 403 static int
 404 dmar_attach(device_t dev)
 405 {
 406         struct dmar_unit *unit;
 407         ACPI_DMAR_HARDWARE_UNIT *dmaru;
 408         uint64_t timeout;
 409         int i, error;
 410
 411         unit = device_get_softc(dev);
 412         unit->dev = dev;
 413         unit->iommu.unit = device_get_unit(dev);
 414         dmaru = dmar_find_by_index(unit->iommu.unit);
 415         if (dmaru == NULL)
 416                 return (EINVAL);
 417         unit->segment = dmaru->Segment;
 418         unit->base = dmaru->Address;
 419         unit->reg_rid = DMAR_REG_RID;
 420         unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 421             &unit->reg_rid, RF_ACTIVE);
 422         if (unit->regs == NULL) {
 423                 device_printf(dev, "cannot allocate register window\n");
 424                 return (ENOMEM);
 425         }
 426         unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
 427         unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
 428         unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
 429         if (bootverbose)
 430                 dmar_print_caps(dev, unit, dmaru);
 431         dmar_quirks_post_ident(unit);
 432
 433         timeout = dmar_get_timeout();
 434         TUNABLE_UINT64_FETCH("hw.dmar.timeout", &timeout);
 435         dmar_update_timeout(timeout);
 436
 437         for (i = 0; i < DMAR_INTR_TOTAL; i++)
 438                 unit->intrs[i].irq = -1;
 439
 440         unit->intrs[DMAR_INTR_FAULT].name = "fault";
 441         unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
 442         unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
 443         unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
 444         unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
 445         unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
 446         unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
 447         unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
 448         error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
 449         if (error != 0) {
 450                 dmar_release_resources(dev, unit);
 451                 return (error);
 452         }
 453         if (DMAR_HAS_QI(unit)) {
 454                 unit->intrs[DMAR_INTR_QI].name = "qi";
 455                 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
 456                 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
 457                 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
 458                 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
 459                 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
 460                 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
 461                 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
 462                 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
 463                 if (error != 0) {
 464                         dmar_release_resources(dev, unit);
 465                         return (error);
 466                 }
 467         }
 468
 469         mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF);
 470         unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
 471             &unit->iommu.lock);
 472         LIST_INIT(&unit->domains);
 473
 474         /*
 475          * 9.2 "Context Entry":
 476          * When Caching Mode (CM) field is reported as Set, the
 477          * domain-id value of zero is architecturally reserved.
 478          * Software must not use domain-id value of zero
 479          * when CM is Set.
 480          */
 481         if ((unit->hw_cap & DMAR_CAP_CM) != 0)
 482                 alloc_unr_specific(unit->domids, 0);
 483
 484         unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
 485             DMAR_CTX_CNT), 0, 0, NULL);
 486
 487         /*
 488          * Allocate and load the root entry table pointer.  Enable the
 489          * address translation after the required invalidations are
 490          * done.
 491          */
 492         dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO);
 493         DMAR_LOCK(unit);
 494         error = dmar_load_root_entry_ptr(unit);
 495         if (error != 0) {
 496                 DMAR_UNLOCK(unit);
 497                 dmar_release_resources(dev, unit);
 498                 return (error);
 499         }
 500         error = dmar_inv_ctx_glob(unit);
 501         if (error != 0) {
 502                 DMAR_UNLOCK(unit);
 503                 dmar_release_resources(dev, unit);
 504                 return (error);
 505         }
 506         if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
 507                 error = dmar_inv_iotlb_glob(unit);
 508                 if (error != 0) {
 509                         DMAR_UNLOCK(unit);
 510                         dmar_release_resources(dev, unit);
 511                         return (error);
 512                 }
 513         }
 514
 515         DMAR_UNLOCK(unit);
 516         error = dmar_init_fault_log(unit);
 517         if (error != 0) {
 518                 dmar_release_resources(dev, unit);
 519                 return (error);
 520         }
 521         error = dmar_init_qi(unit);
 522         if (error != 0) {
 523                 dmar_release_resources(dev, unit);
 524                 return (error);
 525         }
 526         error = dmar_init_irt(unit);
 527         if (error != 0) {
 528                 dmar_release_resources(dev, unit);
 529                 return (error);
 530         }
 531         error = iommu_init_busdma(&unit->iommu);
 532         if (error != 0) {
 533                 dmar_release_resources(dev, unit);
 534                 return (error);
 535         }
 536
 537 #ifdef NOTYET
 538         DMAR_LOCK(unit);
 539         error = dmar_enable_translation(unit);
 540         if (error != 0) {
 541                 DMAR_UNLOCK(unit);
 542                 dmar_release_resources(dev, unit);
 543                 return (error);
 544         }
 545         DMAR_UNLOCK(unit);
 546 #endif
 547
 548         return (0);
 549 }
 550
 551 static int
 552 dmar_detach(device_t dev)
 553 {
 554
 555         return (EBUSY);
 556 }
 557
 558 static int
 559 dmar_suspend(device_t dev)
 560 {
 561
 562         return (0);
 563 }
 564
 565 static int
 566 dmar_resume(device_t dev)
 567 {
 568
 569         /* XXXKIB */
 570         return (0);
 571 }
 572
 573 static device_method_t dmar_methods[] = {
 574         DEVMETHOD(device_identify, dmar_identify),
 575         DEVMETHOD(device_probe, dmar_probe),
 576         DEVMETHOD(device_attach, dmar_attach),
 577         DEVMETHOD(device_detach, dmar_detach),
 578         DEVMETHOD(device_suspend, dmar_suspend),
 579         DEVMETHOD(device_resume, dmar_resume),
 580 #ifdef DEV_APIC
 581         DEVMETHOD(bus_remap_intr, dmar_remap_intr),
 582 #endif
 583         DEVMETHOD_END
 584 };
 585
 586 static driver_t dmar_driver = {
 587         "dmar",
 588         dmar_methods,
 589         sizeof(struct dmar_unit),
 590 };
 591
 592 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
 593 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
 594
 595 static void
 596 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
 597 {
 598         int i;
 599
 600         printf("[%d, ", busno);
 601         for (i = 0; i < depth; i++) {
 602                 if (i != 0)
 603                         printf(", ");
 604                 printf("(%d, %d)", path[i].Device, path[i].Function);
 605         }
 606         printf("]");
 607 }
 608
 609 int
 610 dmar_dev_depth(device_t child)
 611 {
 612         devclass_t pci_class;
 613         device_t bus, pcib;
 614         int depth;
 615
 616         pci_class = devclass_find("pci");
 617         for (depth = 1; ; depth++) {
 618                 bus = device_get_parent(child);
 619                 pcib = device_get_parent(bus);
 620                 if (device_get_devclass(device_get_parent(pcib)) !=
 621                     pci_class)
 622                         return (depth);
 623                 child = pcib;
 624         }
 625 }
 626
 627 void
 628 dmar_dev_path(device_t child, int *busno, void *path1, int depth)
 629 {
 630         devclass_t pci_class;
 631         device_t bus, pcib;
 632         ACPI_DMAR_PCI_PATH *path;
 633
 634         pci_class = devclass_find("pci");
 635         path = path1;
 636         for (depth--; depth != -1; depth--) {
 637                 path[depth].Device = pci_get_slot(child);
 638                 path[depth].Function = pci_get_function(child);
 639                 bus = device_get_parent(child);
 640                 pcib = device_get_parent(bus);
 641                 if (device_get_devclass(device_get_parent(pcib)) !=
 642                     pci_class) {
 643                         /* reached a host bridge */
 644                         *busno = pcib_get_bus(bus);
 645                         return;
 646                 }
 647                 child = pcib;
 648         }
 649         panic("wrong depth");
 650 }
 651
 652 static int
 653 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
 654     int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
 655     enum AcpiDmarScopeType scope_type)
 656 {
 657         int i, depth;
 658
 659         if (busno1 != busno2)
 660                 return (0);
 661         if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
 662                 return (0);
 663         depth = depth1;
 664         if (depth2 < depth)
 665                 depth = depth2;
 666         for (i = 0; i < depth; i++) {
 667                 if (path1[i].Device != path2[i].Device ||
 668                     path1[i].Function != path2[i].Function)
 669                         return (0);
 670         }
 671         return (1);
 672 }
 673
 674 static int
 675 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno,
 676     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
 677 {
 678         ACPI_DMAR_PCI_PATH *path;
 679         int path_len;
 680
 681         if (devscope->Length < sizeof(*devscope)) {
 682                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
 683                     devscope->Length);
 684                 return (-1);
 685         }
 686         if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
 687             devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
 688                 return (0);
 689         path_len = devscope->Length - sizeof(*devscope);
 690         if (path_len % 2 != 0) {
 691                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
 692                     devscope->Length);
 693                 return (-1);
 694         }
 695         path_len /= 2;
 696         path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
 697         if (path_len == 0) {
 698                 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n",
 699                     devscope->Length);
 700                 return (-1);
 701         }
 702
 703         return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
 704             dev_path, dev_path_len, devscope->EntryType));
 705 }
 706
 707 static bool
 708 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno,
 709     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner)
 710 {
 711         ACPI_DMAR_HARDWARE_UNIT *dmarh;
 712         ACPI_DMAR_DEVICE_SCOPE *devscope;
 713         char *ptr, *ptrend;
 714         int match;
 715
 716         dmarh = dmar_find_by_index(unit->iommu.unit);
 717         if (dmarh == NULL)
 718                 return (false);
 719         if (dmarh->Segment != dev_domain)
 720                 return (false);
 721         if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
 722                 if (banner != NULL)
 723                         *banner = "INCLUDE_ALL";
 724                 return (true);
 725         }
 726         ptr = (char *)dmarh + sizeof(*dmarh);
 727         ptrend = (char *)dmarh + dmarh->Header.Length;
 728         while (ptr < ptrend) {
 729                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
 730                 ptr += devscope->Length;
 731                 match = dmar_match_devscope(devscope, dev_busno, dev_path,
 732                     dev_path_len);
 733                 if (match == -1)
 734                         return (false);
 735                 if (match == 1) {
 736                         if (banner != NULL)
 737                                 *banner = "specific match";
 738                         return (true);
 739                 }
 740         }
 741         return (false);
 742 }
 743
 744 static struct dmar_unit *
 745 dmar_find_by_scope(int dev_domain, int dev_busno,
 746     const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
 747 {
 748         struct dmar_unit *unit;
 749         int i;
 750
 751         for (i = 0; i < dmar_devcnt; i++) {
 752                 if (dmar_devs[i] == NULL)
 753                         continue;
 754                 unit = device_get_softc(dmar_devs[i]);
 755                 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path,
 756                     dev_path_len, NULL))
 757                         return (unit);
 758         }
 759         return (NULL);
 760 }
 761
 762 struct dmar_unit *
 763 dmar_find(device_t dev, bool verbose)
 764 {
 765         device_t dmar_dev;
 766         struct dmar_unit *unit;
 767         const char *banner;
 768         int i, dev_domain, dev_busno, dev_path_len;
 769
 770         /*
 771          * This function can only handle PCI(e) devices.
 772          */
 773         if (device_get_devclass(device_get_parent(dev)) !=
 774             devclass_find("pci"))
 775                 return (NULL);
 776
 777         dmar_dev = NULL;
 778         dev_domain = pci_get_domain(dev);
 779         dev_path_len = dmar_dev_depth(dev);
 780         ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
 781         dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
 782         banner = "";
 783
 784         for (i = 0; i < dmar_devcnt; i++) {
 785                 if (dmar_devs[i] == NULL)
 786                         continue;
 787                 unit = device_get_softc(dmar_devs[i]);
 788                 if (dmar_match_by_path(unit, dev_domain, dev_busno,
 789                     dev_path, dev_path_len, &banner))
 790                         break;
 791         }
 792         if (i == dmar_devcnt)
 793                 return (NULL);
 794
 795         if (verbose) {
 796                 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s",
 797                     dev_domain, pci_get_bus(dev), pci_get_slot(dev),
 798                     pci_get_function(dev), unit->iommu.unit, banner);
 799                 printf(" scope path ");
 800                 dmar_print_path(dev_busno, dev_path_len, dev_path);
 801                 printf("\n");
 802         }
 803         return (unit);
 804 }
 805
 806 static struct dmar_unit *
 807 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
 808 {
 809         device_t dmar_dev;
 810         struct dmar_unit *unit;
 811         ACPI_DMAR_HARDWARE_UNIT *dmarh;
 812         ACPI_DMAR_DEVICE_SCOPE *devscope;
 813         ACPI_DMAR_PCI_PATH *path;
 814         char *ptr, *ptrend;
 815 #ifdef DEV_APIC
 816         int error;
 817 #endif
 818         int i;
 819
 820         for (i = 0; i < dmar_devcnt; i++) {
 821                 dmar_dev = dmar_devs[i];
 822                 if (dmar_dev == NULL)
 823                         continue;
 824                 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
 825                 dmarh = dmar_find_by_index(i);
 826                 if (dmarh == NULL)
 827                         continue;
 828                 ptr = (char *)dmarh + sizeof(*dmarh);
 829                 ptrend = (char *)dmarh + dmarh->Header.Length;
 830                 for (;;) {
 831                         if (ptr >= ptrend)
 832                                 break;
 833                         devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
 834                         ptr += devscope->Length;
 835                         if (devscope->EntryType != entry_type)
 836                                 continue;
 837                         if (devscope->EnumerationId != id)
 838                                 continue;
 839 #ifdef DEV_APIC
 840                         if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 841                                 error = ioapic_get_rid(id, rid);
 842                                 /*
 843                                  * If our IOAPIC has PCI bindings then
 844                                  * use the PCI device rid.
 845                                  */
 846                                 if (error == 0)
 847                                         return (unit);
 848                         }
 849 #endif
 850                         if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
 851                             == 2) {
 852                                 if (rid != NULL) {
 853                                         path = (ACPI_DMAR_PCI_PATH *)
 854                                             (devscope + 1);
 855                                         *rid = PCI_RID(devscope->Bus,
 856                                             path->Device, path->Function);
 857                                 }
 858                                 return (unit);
 859                         }
 860                         printf(
 861                            "dmar_find_nonpci: id %d type %d path length != 2\n",
 862                             id, entry_type);
 863                         break;
 864                 }
 865         }
 866         return (NULL);
 867 }
 868
 869
 870 struct dmar_unit *
 871 dmar_find_hpet(device_t dev, uint16_t *rid)
 872 {
 873
 874         return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
 875             rid));
 876 }
 877
 878 struct dmar_unit *
 879 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
 880 {
 881
 882         return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
 883 }
 884
 885 struct rmrr_iter_args {
 886         struct dmar_domain *domain;
 887         int dev_domain;
 888         int dev_busno;
 889         const ACPI_DMAR_PCI_PATH *dev_path;
 890         int dev_path_len;
 891         struct iommu_map_entries_tailq *rmrr_entries;
 892 };
 893
 894 static int
 895 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
 896 {
 897         struct rmrr_iter_args *ria;
 898         ACPI_DMAR_RESERVED_MEMORY *resmem;
 899         ACPI_DMAR_DEVICE_SCOPE *devscope;
 900         struct iommu_map_entry *entry;
 901         char *ptr, *ptrend;
 902         int match;
 903
 904         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
 905                 return (1);
 906
 907         ria = arg;
 908         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
 909         if (resmem->Segment != ria->dev_domain)
 910                 return (1);
 911
 912         ptr = (char *)resmem + sizeof(*resmem);
 913         ptrend = (char *)resmem + resmem->Header.Length;
 914         for (;;) {
 915                 if (ptr >= ptrend)
 916                         break;
 917                 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
 918                 ptr += devscope->Length;
 919                 match = dmar_match_devscope(devscope, ria->dev_busno,
 920                     ria->dev_path, ria->dev_path_len);
 921                 if (match == 1) {
 922                         entry = iommu_gas_alloc_entry(
 923                             (struct iommu_domain *)ria->domain,
 924                             IOMMU_PGF_WAITOK);
 925                         entry->start = resmem->BaseAddress;
 926                         /* The RMRR entry end address is inclusive. */
 927                         entry->end = resmem->EndAddress;
 928                         TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
 929                             unroll_link);
 930                 }
 931         }
 932
 933         return (1);
 934 }
 935
 936 void
 937 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno,
 938     const void *dev_path, int dev_path_len,
 939     struct iommu_map_entries_tailq *rmrr_entries)
 940 {
 941         struct rmrr_iter_args ria;
 942
 943         ria.domain = domain;
 944         ria.dev_domain = dev_domain;
 945         ria.dev_busno = dev_busno;
 946         ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path;
 947         ria.dev_path_len = dev_path_len;
 948         ria.rmrr_entries = rmrr_entries;
 949         dmar_iterate_tbl(dmar_rmrr_iter, &ria);
 950 }
 951
 952 struct inst_rmrr_iter_args {
 953         struct dmar_unit *dmar;
 954 };
 955
 956 static device_t
 957 dmar_path_dev(int segment, int path_len, int busno,
 958     const ACPI_DMAR_PCI_PATH *path, uint16_t *rid)
 959 {
 960         device_t dev;
 961         int i;
 962
 963         dev = NULL;
 964         for (i = 0; i < path_len; i++) {
 965                 dev = pci_find_dbsf(segment, busno, path->Device,
 966                     path->Function);
 967                 if (i != path_len - 1) {
 968                         busno = pci_cfgregread(busno, path->Device,
 969                             path->Function, PCIR_SECBUS_1, 1);
 970                         path++;
 971                 }
 972         }
 973         *rid = PCI_RID(busno, path->Device, path->Function);
 974         return (dev);
 975 }
 976
 977 static int
 978 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
 979 {
 980         const ACPI_DMAR_RESERVED_MEMORY *resmem;
 981         const ACPI_DMAR_DEVICE_SCOPE *devscope;
 982         struct inst_rmrr_iter_args *iria;
 983         const char *ptr, *ptrend;
 984         device_t dev;
 985         struct dmar_unit *unit;
 986         int dev_path_len;
 987         uint16_t rid;
 988
 989         iria = arg;
 990
 991         if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
 992                 return (1);
 993
 994         resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
 995         if (resmem->Segment != iria->dmar->segment)
 996                 return (1);
 997
 998         ptr = (const char *)resmem + sizeof(*resmem);
 999         ptrend = (const char *)resmem + resmem->Header.Length;
1000         for (;;) {
1001                 if (ptr >= ptrend)
1002                         break;
1003                 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
1004                 ptr += devscope->Length;
1005                 /* XXXKIB bridge */
1006                 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
1007                         continue;
1008                 rid = 0;
1009                 dev_path_len = (devscope->Length -
1010                     sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2;
1011                 dev = dmar_path_dev(resmem->Segment, dev_path_len,
1012                     devscope->Bus,
1013                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid);
1014                 if (dev == NULL) {
1015                         if (bootverbose) {
1016                                 printf("dmar%d no dev found for RMRR "
1017                                     "[%#jx, %#jx] rid %#x scope path ",
1018                                      iria->dmar->iommu.unit,
1019                                      (uintmax_t)resmem->BaseAddress,
1020                                      (uintmax_t)resmem->EndAddress,
1021                                      rid);
1022                                 dmar_print_path(devscope->Bus, dev_path_len,
1023                                     (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1024                                 printf("\n");
1025                         }
1026                         unit = dmar_find_by_scope(resmem->Segment,
1027                             devscope->Bus,
1028                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1029                             dev_path_len);
1030                         if (iria->dmar != unit)
1031                                 continue;
1032                         dmar_get_ctx_for_devpath(iria->dmar, rid,
1033                             resmem->Segment, devscope->Bus,
1034                             (const ACPI_DMAR_PCI_PATH *)(devscope + 1),
1035                             dev_path_len, false, true);
1036                 } else {
1037                         unit = dmar_find(dev, false);
1038                         if (iria->dmar != unit)
1039                                 continue;
1040                         iommu_instantiate_ctx(&(iria)->dmar->iommu,
1041                             dev, true);
1042                 }
1043         }
1044
1045         return (1);
1046
1047 }
1048
1049 /*
1050  * Pre-create all contexts for the DMAR which have RMRR entries.
1051  */
1052 int
1053 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
1054 {
1055         struct dmar_unit *dmar;
1056         struct inst_rmrr_iter_args iria;
1057         int error;
1058
1059         dmar = (struct dmar_unit *)unit;
1060
1061         if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1062                 return (0);
1063
1064         error = 0;
1065         iria.dmar = dmar;
1066         dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1067         DMAR_LOCK(dmar);
1068         if (!LIST_EMPTY(&dmar->domains)) {
1069                 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1070             ("dmar%d: RMRR not handled but translation is already enabled",
1071                     dmar->iommu.unit));
1072                 error = dmar_enable_translation(dmar);
1073                 if (bootverbose) {
1074                         if (error == 0) {
1075                                 printf("dmar%d: enabled translation\n",
1076                                     dmar->iommu.unit);
1077                         } else {
1078                                 printf("dmar%d: enabling translation failed, "
1079                                     "error %d\n", dmar->iommu.unit, error);
1080                         }
1081                 }
1082         }
1083         dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1084         return (error);
1085 }
1086
1087 #ifdef DDB
1088 #include <ddb/ddb.h>
1089 #include <ddb/db_lex.h>
1090
1091 static void
1092 dmar_print_domain_entry(const struct iommu_map_entry *entry)
1093 {
1094         struct iommu_map_entry *l, *r;
1095
1096         db_printf(
1097             "    start %jx end %jx first %jx last %jx free_down %jx flags %x ",
1098             entry->start, entry->end, entry->first, entry->last,
1099             entry->free_down, entry->flags);
1100         db_printf("left ");
1101         l = RB_LEFT(entry, rb_entry);
1102         if (l == NULL)
1103                 db_printf("NULL ");
1104         else
1105                 db_printf("%jx ", l->start);
1106         db_printf("right ");
1107         r = RB_RIGHT(entry, rb_entry);
1108         if (r == NULL)
1109                 db_printf("NULL");
1110         else
1111                 db_printf("%jx", r->start);
1112         db_printf("\n");
1113 }
1114
1115 static void
1116 dmar_print_ctx(struct dmar_ctx *ctx)
1117 {
1118
1119         db_printf(
1120             "    @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1121             ctx, pci_get_bus(ctx->context.tag->owner),
1122             pci_get_slot(ctx->context.tag->owner),
1123             pci_get_function(ctx->context.tag->owner), ctx->refs,
1124             ctx->context.flags, ctx->context.loads, ctx->context.unloads);
1125 }
1126
1127 static void
1128 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1129 {
1130         struct iommu_domain *iodom;
1131         struct iommu_map_entry *entry;
1132         struct dmar_ctx *ctx;
1133
1134         iodom = (struct iommu_domain *)domain;
1135
1136         db_printf(
1137             "  @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1138             "   ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1139             domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1140             (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt,
1141             domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt);
1142         if (!LIST_EMPTY(&domain->contexts)) {
1143                 db_printf("  Contexts:\n");
1144                 LIST_FOREACH(ctx, &domain->contexts, link)
1145                         dmar_print_ctx(ctx);
1146         }
1147         if (!show_mappings)
1148                 return;
1149         db_printf("    mapped:\n");
1150         RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) {
1151                 dmar_print_domain_entry(entry);
1152                 if (db_pager_quit)
1153                         break;
1154         }
1155         if (db_pager_quit)
1156                 return;
1157         db_printf("    unloading:\n");
1158         TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) {
1159                 dmar_print_domain_entry(entry);
1160                 if (db_pager_quit)
1161                         break;
1162         }
1163 }
1164
1165 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1166 {
1167         struct dmar_unit *unit;
1168         struct dmar_domain *domain;
1169         struct dmar_ctx *ctx;
1170         bool show_mappings, valid;
1171         int pci_domain, bus, device, function, i, t;
1172         db_expr_t radix;
1173
1174         valid = false;
1175         radix = db_radix;
1176         db_radix = 10;
1177         t = db_read_token();
1178         if (t == tSLASH) {
1179                 t = db_read_token();
1180                 if (t != tIDENT) {
1181                         db_printf("Bad modifier\n");
1182                         db_radix = radix;
1183                         db_skip_to_eol();
1184                         return;
1185                 }
1186                 show_mappings = strchr(db_tok_string, 'm') != NULL;
1187                 t = db_read_token();
1188         } else {
1189                 show_mappings = false;
1190         }
1191         if (t == tNUMBER) {
1192                 pci_domain = db_tok_number;
1193                 t = db_read_token();
1194                 if (t == tNUMBER) {
1195                         bus = db_tok_number;
1196                         t = db_read_token();
1197                         if (t == tNUMBER) {
1198                                 device = db_tok_number;
1199                                 t = db_read_token();
1200                                 if (t == tNUMBER) {
1201                                         function = db_tok_number;
1202                                         valid = true;
1203                                 }
1204                         }
1205                 }
1206         }
1207                         db_radix = radix;
1208         db_skip_to_eol();
1209         if (!valid) {
1210                 db_printf("usage: show dmar_domain [/m] "
1211                     "<domain> <bus> <device> <func>\n");
1212                 return;
1213         }
1214         for (i = 0; i < dmar_devcnt; i++) {
1215                 unit = device_get_softc(dmar_devs[i]);
1216                 LIST_FOREACH(domain, &unit->domains, link) {
1217                         LIST_FOREACH(ctx, &domain->contexts, link) {
1218                                 if (pci_domain == unit->segment &&
1219                                     bus == pci_get_bus(ctx->context.tag->owner) &&
1220                                     device ==
1221                                     pci_get_slot(ctx->context.tag->owner) &&
1222                                     function ==
1223                                     pci_get_function(ctx->context.tag->owner)) {
1224                                         dmar_print_domain(domain,
1225                                             show_mappings);
1226                                         goto out;
1227                                 }
1228                         }
1229                 }
1230         }
1231 out:;
1232 }
1233
1234 static void
1235 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1236 {
1237         struct dmar_unit *unit;
1238         struct dmar_domain *domain;
1239         int i, frir;
1240
1241         unit = device_get_softc(dmar_devs[idx]);
1242         db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit,
1243             unit, dmar_read8(unit, DMAR_RTADDR_REG),
1244             dmar_read4(unit, DMAR_VER_REG));
1245         db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1246             (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1247             (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1248             dmar_read4(unit, DMAR_GSTS_REG),
1249             dmar_read4(unit, DMAR_FSTS_REG),
1250             dmar_read4(unit, DMAR_FECTL_REG));
1251         if (unit->ir_enabled) {
1252                 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1253                     unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1254         }
1255         db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1256             dmar_read4(unit, DMAR_FEDATA_REG),
1257             dmar_read4(unit, DMAR_FEADDR_REG),
1258             dmar_read4(unit, DMAR_FEUADDR_REG));
1259         db_printf("primary fault log:\n");
1260         for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1261                 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1262                 db_printf("  %d at 0x%x: %jx %jx\n", i, frir,
1263                     (uintmax_t)dmar_read8(unit, frir),
1264                     (uintmax_t)dmar_read8(unit, frir + 8));
1265         }
1266         if (DMAR_HAS_QI(unit)) {
1267                 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1268                     dmar_read4(unit, DMAR_IEDATA_REG),
1269                     dmar_read4(unit, DMAR_IEADDR_REG),
1270                     dmar_read4(unit, DMAR_IEUADDR_REG));
1271                 if (unit->qi_enabled) {
1272                         db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1273                             "size 0x%jx\n"
1274                     "  head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1275                     "  hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1276                             (uintmax_t)unit->inv_queue,
1277                             (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1278                             (uintmax_t)unit->inv_queue_size,
1279                             dmar_read4(unit, DMAR_IQH_REG),
1280                             dmar_read4(unit, DMAR_IQT_REG),
1281                             unit->inv_queue_avail,
1282                             dmar_read4(unit, DMAR_ICS_REG),
1283                             dmar_read4(unit, DMAR_IECTL_REG),
1284                             unit->inv_waitd_seq_hw,
1285                             &unit->inv_waitd_seq_hw,
1286                             (uintmax_t)unit->inv_waitd_seq_hw_phys,
1287                             unit->inv_waitd_seq,
1288                             unit->inv_waitd_gen);
1289                 } else {
1290                         db_printf("qi is disabled\n");
1291                 }
1292         }
1293         if (show_domains) {
1294                 db_printf("domains:\n");
1295                 LIST_FOREACH(domain, &unit->domains, link) {
1296                         dmar_print_domain(domain, show_mappings);
1297                         if (db_pager_quit)
1298                                 break;
1299                 }
1300         }
1301 }
1302
1303 DB_SHOW_COMMAND(dmar, db_dmar_print)
1304 {
1305         bool show_domains, show_mappings;
1306
1307         show_domains = strchr(modif, 'd') != NULL;
1308         show_mappings = strchr(modif, 'm') != NULL;
1309         if (!have_addr) {
1310                 db_printf("usage: show dmar [/d] [/m] index\n");
1311                 return;
1312         }
1313         dmar_print_one((int)addr, show_domains, show_mappings);
1314 }
1315
1316 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1317 {
1318         int i;
1319         bool show_domains, show_mappings;
1320
1321         show_domains = strchr(modif, 'd') != NULL;
1322         show_mappings = strchr(modif, 'm') != NULL;
1323
1324         for (i = 0; i < dmar_devcnt; i++) {
1325                 dmar_print_one(i, show_domains, show_mappings);
1326                 if (db_pager_quit)
1327                         break;
1328         }
1329 }
1330 #endif
1331
1332 struct iommu_unit *
1333 iommu_find(device_t dev, bool verbose)
1334 {
1335         struct dmar_unit *dmar;
1336
1337         dmar = dmar_find(dev, verbose);
1338
1339         return (&dmar->iommu);
1340 }