2 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #if defined(__amd64__)
41 #include <sys/param.h>
43 #include <sys/kernel.h>
45 #include <sys/malloc.h>
46 #include <sys/memdesc.h>
47 #include <sys/module.h>
49 #include <sys/rwlock.h>
51 #include <sys/taskqueue.h>
54 #include <machine/bus.h>
55 #include <contrib/dev/acpica/include/acpi.h>
56 #include <contrib/dev/acpica/include/accommon.h>
57 #include <dev/acpica/acpivar.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_object.h>
62 #include <vm/vm_page.h>
63 #include <vm/vm_pager.h>
64 #include <vm/vm_map.h>
65 #include <x86/include/busdma_impl.h>
66 #include <x86/iommu/intel_reg.h>
67 #include <x86/iommu/busdma_dmar.h>
68 #include <x86/iommu/intel_dmar.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
76 #define DMAR_FAULT_IRQ_RID 0
77 #define DMAR_QI_IRQ_RID 1
78 #define DMAR_REG_RID 2
80 static devclass_t dmar_devclass;
81 static device_t *dmar_devs;
82 static int dmar_devcnt;
84 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
87 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
89 ACPI_TABLE_DMAR *dmartbl;
90 ACPI_DMAR_HEADER *dmarh;
94 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
95 if (ACPI_FAILURE(status))
97 ptr = (char *)dmartbl + sizeof(*dmartbl);
98 ptrend = (char *)dmartbl + dmartbl->Header.Length;
102 dmarh = (ACPI_DMAR_HEADER *)ptr;
103 if (dmarh->Length <= 0) {
104 printf("dmar_identify: corrupted DMAR table, l %d\n",
108 ptr += dmarh->Length;
109 if (!iter(dmarh, arg))
114 struct find_iter_args {
116 ACPI_DMAR_HARDWARE_UNIT *res;
120 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
122 struct find_iter_args *fia;
124 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
129 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
136 static ACPI_DMAR_HARDWARE_UNIT *
137 dmar_find_by_index(int idx)
139 struct find_iter_args fia;
143 dmar_iterate_tbl(dmar_find_iter, &fia);
148 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
151 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
156 static int dmar_enable = 0;
158 dmar_identify(driver_t *driver, device_t parent)
160 ACPI_TABLE_DMAR *dmartbl;
161 ACPI_DMAR_HARDWARE_UNIT *dmarh;
165 if (acpi_disabled("dmar"))
167 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
171 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
173 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose);
174 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
175 if (ACPI_FAILURE(status))
177 haw = dmartbl->Width + 1;
178 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
179 dmar_high = BUS_SPACE_MAXADDR;
181 dmar_high = 1ULL << (haw + 1);
183 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
184 (unsigned)dmartbl->Flags,
185 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
188 dmar_iterate_tbl(dmar_count_iter, NULL);
189 if (dmar_devcnt == 0)
191 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
193 for (i = 0; i < dmar_devcnt; i++) {
194 dmarh = dmar_find_by_index(i);
196 printf("dmar_identify: cannot find HWUNIT %d\n", i);
199 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
200 if (dmar_devs[i] == NULL) {
201 printf("dmar_identify: cannot create instance %d\n", i);
204 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
205 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
208 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
209 i, (uintmax_t)dmarh->Address, error);
210 device_delete_child(parent, dmar_devs[i]);
217 dmar_probe(device_t dev)
220 if (acpi_get_handle(dev) != NULL)
222 device_set_desc(dev, "DMA remap");
223 return (BUS_PROBE_NOWILDCARD);
227 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
229 struct dmar_msi_data *dmd;
231 dmd = &unit->intrs[idx];
234 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
235 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
236 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
237 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
243 dmar_release_resources(device_t dev, struct dmar_unit *unit)
247 dmar_fini_busdma(unit);
250 dmar_fini_fault_log(unit);
251 for (i = 0; i < DMAR_INTR_TOTAL; i++)
252 dmar_release_intr(dev, unit, i);
253 if (unit->regs != NULL) {
254 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
256 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
260 if (unit->domids != NULL) {
261 delete_unrhdr(unit->domids);
264 if (unit->ctx_obj != NULL) {
265 vm_object_deallocate(unit->ctx_obj);
266 unit->ctx_obj = NULL;
271 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
274 struct dmar_msi_data *dmd;
279 dmd = &unit->intrs[idx];
280 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
281 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
283 device_printf(dev, "cannot allocate %s interrupt, %d\n",
287 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
290 device_printf(dev, "cannot set %s interrupt resource, %d\n",
294 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
295 &dmd->irq_rid, RF_ACTIVE);
296 if (dmd->irq_res == NULL) {
298 "cannot allocate resource for %s interrupt\n", dmd->name);
302 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
303 dmd->handler, NULL, unit, &dmd->intr_handle);
305 device_printf(dev, "cannot setup %s interrupt, %d\n",
309 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name);
310 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
312 device_printf(dev, "cannot map %s interrupt, %d\n",
316 dmar_write4(unit, dmd->msi_data_reg, msi_data);
317 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
318 /* Only for xAPIC mode */
319 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
323 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
325 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
327 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
329 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
337 dmar_remap_intr(device_t dev, device_t child, u_int irq)
339 struct dmar_unit *unit;
340 struct dmar_msi_data *dmd;
345 unit = device_get_softc(dev);
346 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
347 dmd = &unit->intrs[i];
348 if (irq == dmd->irq) {
349 error = PCIB_MAP_MSI(device_get_parent(
350 device_get_parent(dev)),
351 dev, irq, &msi_addr, &msi_data);
355 (dmd->disable_intr)(unit);
356 dmar_write4(unit, dmd->msi_data_reg, msi_data);
357 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
358 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
359 (dmd->enable_intr)(unit);
369 dmar_print_caps(device_t dev, struct dmar_unit *unit,
370 ACPI_DMAR_HARDWARE_UNIT *dmaru)
372 uint32_t caphi, ecaphi;
374 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
375 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
376 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
377 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
378 caphi = unit->hw_cap >> 32;
379 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
380 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
381 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
382 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
383 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
384 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
385 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
386 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
387 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
389 ecaphi = unit->hw_ecap >> 32;
390 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
391 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
392 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
393 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
394 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
395 DMAR_ECAP_IRO(unit->hw_ecap));
399 dmar_attach(device_t dev)
401 struct dmar_unit *unit;
402 ACPI_DMAR_HARDWARE_UNIT *dmaru;
405 unit = device_get_softc(dev);
407 unit->unit = device_get_unit(dev);
408 dmaru = dmar_find_by_index(unit->unit);
411 unit->segment = dmaru->Segment;
412 unit->base = dmaru->Address;
413 unit->reg_rid = DMAR_REG_RID;
414 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
415 &unit->reg_rid, RF_ACTIVE);
416 if (unit->regs == NULL) {
417 device_printf(dev, "cannot allocate register window\n");
420 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
421 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
422 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
424 dmar_print_caps(dev, unit, dmaru);
425 dmar_quirks_post_ident(unit);
427 for (i = 0; i < DMAR_INTR_TOTAL; i++)
428 unit->intrs[i].irq = -1;
430 unit->intrs[DMAR_INTR_FAULT].name = "fault";
431 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
432 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
433 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
434 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
435 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
436 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
437 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
438 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
440 dmar_release_resources(dev, unit);
443 if (DMAR_HAS_QI(unit)) {
444 unit->intrs[DMAR_INTR_QI].name = "qi";
445 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
446 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
447 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
448 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
449 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
450 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
451 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
452 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
454 dmar_release_resources(dev, unit);
459 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
460 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
462 LIST_INIT(&unit->domains);
465 * 9.2 "Context Entry":
466 * When Caching Mode (CM) field is reported as Set, the
467 * domain-id value of zero is architecturally reserved.
468 * Software must not use domain-id value of zero
471 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
472 alloc_unr_specific(unit->domids, 0);
474 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
475 DMAR_CTX_CNT), 0, 0, NULL);
478 * Allocate and load the root entry table pointer. Enable the
479 * address translation after the required invalidations are
482 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
484 error = dmar_load_root_entry_ptr(unit);
487 dmar_release_resources(dev, unit);
490 error = dmar_inv_ctx_glob(unit);
493 dmar_release_resources(dev, unit);
496 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
497 error = dmar_inv_iotlb_glob(unit);
500 dmar_release_resources(dev, unit);
506 error = dmar_init_fault_log(unit);
508 dmar_release_resources(dev, unit);
511 error = dmar_init_qi(unit);
513 dmar_release_resources(dev, unit);
516 error = dmar_init_irt(unit);
518 dmar_release_resources(dev, unit);
521 error = dmar_init_busdma(unit);
523 dmar_release_resources(dev, unit);
529 error = dmar_enable_translation(unit);
532 dmar_release_resources(dev, unit);
542 dmar_detach(device_t dev)
549 dmar_suspend(device_t dev)
556 dmar_resume(device_t dev)
563 static device_method_t dmar_methods[] = {
564 DEVMETHOD(device_identify, dmar_identify),
565 DEVMETHOD(device_probe, dmar_probe),
566 DEVMETHOD(device_attach, dmar_attach),
567 DEVMETHOD(device_detach, dmar_detach),
568 DEVMETHOD(device_suspend, dmar_suspend),
569 DEVMETHOD(device_resume, dmar_resume),
571 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
576 static driver_t dmar_driver = {
579 sizeof(struct dmar_unit),
582 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
583 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
586 dmar_print_path(device_t dev, const char *banner, int busno, int depth,
587 const ACPI_DMAR_PCI_PATH *path)
591 device_printf(dev, "%s [%d, ", banner, busno);
592 for (i = 0; i < depth; i++) {
595 printf("(%d, %d)", path[i].Device, path[i].Function);
601 dmar_dev_depth(device_t child)
603 devclass_t pci_class;
607 pci_class = devclass_find("pci");
608 for (depth = 1; ; depth++) {
609 bus = device_get_parent(child);
610 pcib = device_get_parent(bus);
611 if (device_get_devclass(device_get_parent(pcib)) !=
619 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth)
621 devclass_t pci_class;
624 pci_class = devclass_find("pci");
625 for (depth--; depth != -1; depth--) {
626 path[depth].Device = pci_get_slot(child);
627 path[depth].Function = pci_get_function(child);
628 bus = device_get_parent(child);
629 pcib = device_get_parent(bus);
630 if (device_get_devclass(device_get_parent(pcib)) !=
632 /* reached a host bridge */
633 *busno = pcib_get_bus(bus);
638 panic("wrong depth");
642 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
643 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
644 enum AcpiDmarScopeType scope_type)
648 if (busno1 != busno2)
650 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
655 for (i = 0; i < depth; i++) {
656 if (path1[i].Device != path2[i].Device ||
657 path1[i].Function != path2[i].Function)
664 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev,
665 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
667 ACPI_DMAR_PCI_PATH *path;
670 if (devscope->Length < sizeof(*devscope)) {
671 printf("dmar_find: corrupted DMAR table, dl %d\n",
675 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
676 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
678 path_len = devscope->Length - sizeof(*devscope);
679 if (path_len % 2 != 0) {
680 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n",
685 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
687 printf("dmar_find: corrupted DMAR table, dl %d\n",
691 if (dmar_match_verbose)
692 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path);
694 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
695 dev_path, dev_path_len, devscope->EntryType));
699 dmar_find(device_t dev)
702 ACPI_DMAR_HARDWARE_UNIT *dmarh;
703 ACPI_DMAR_DEVICE_SCOPE *devscope;
705 int i, match, dev_domain, dev_busno, dev_path_len;
708 dev_domain = pci_get_domain(dev);
709 dev_path_len = dmar_dev_depth(dev);
710 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
711 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
712 if (dmar_match_verbose)
713 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path);
715 for (i = 0; i < dmar_devcnt; i++) {
716 if (dmar_devs[i] == NULL)
718 dmarh = dmar_find_by_index(i);
721 if (dmarh->Segment != dev_domain)
723 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
724 dmar_dev = dmar_devs[i];
725 if (dmar_match_verbose) {
727 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n",
728 dev_domain, pci_get_bus(dev),
730 pci_get_function(dev),
731 ((struct dmar_unit *)device_get_softc(
736 ptr = (char *)dmarh + sizeof(*dmarh);
737 ptrend = (char *)dmarh + dmarh->Header.Length;
741 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
742 ptr += devscope->Length;
743 if (dmar_match_verbose) {
745 "pci%d:%d:%d:%d matching dmar%d\n",
746 dev_domain, pci_get_bus(dev),
748 pci_get_function(dev),
749 ((struct dmar_unit *)device_get_softc(
750 dmar_devs[i]))->unit);
752 match = dmar_match_devscope(devscope, dev, dev_busno,
753 dev_path, dev_path_len);
754 if (dmar_match_verbose) {
756 printf("table error\n");
758 printf("not matched\n");
764 else if (match == 1) {
765 dmar_dev = dmar_devs[i];
772 return (device_get_softc(dmar_dev));
775 static struct dmar_unit *
776 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
779 struct dmar_unit *unit;
780 ACPI_DMAR_HARDWARE_UNIT *dmarh;
781 ACPI_DMAR_DEVICE_SCOPE *devscope;
782 ACPI_DMAR_PCI_PATH *path;
786 for (i = 0; i < dmar_devcnt; i++) {
787 dmar_dev = dmar_devs[i];
788 if (dmar_dev == NULL)
790 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
791 dmarh = dmar_find_by_index(i);
794 ptr = (char *)dmarh + sizeof(*dmarh);
795 ptrend = (char *)dmarh + dmarh->Header.Length;
799 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
800 ptr += devscope->Length;
801 if (devscope->EntryType != entry_type)
803 if (devscope->EnumerationId != id)
805 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
808 path = (ACPI_DMAR_PCI_PATH *)
810 *rid = PCI_RID(devscope->Bus,
811 path->Device, path->Function);
817 "dmar_find_nonpci: id %d type %d path length != 2\n",
827 dmar_find_hpet(device_t dev, uint16_t *rid)
830 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET,
835 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
838 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
841 struct rmrr_iter_args {
842 struct dmar_domain *domain;
846 ACPI_DMAR_PCI_PATH *dev_path;
848 struct dmar_map_entries_tailq *rmrr_entries;
852 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
854 struct rmrr_iter_args *ria;
855 ACPI_DMAR_RESERVED_MEMORY *resmem;
856 ACPI_DMAR_DEVICE_SCOPE *devscope;
857 struct dmar_map_entry *entry;
861 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
865 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
866 if (dmar_match_verbose) {
867 printf("RMRR [%jx,%jx] segment %d\n",
868 (uintmax_t)resmem->BaseAddress,
869 (uintmax_t)resmem->EndAddress,
872 if (resmem->Segment != ria->dev_domain)
875 ptr = (char *)resmem + sizeof(*resmem);
876 ptrend = (char *)resmem + resmem->Header.Length;
880 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
881 ptr += devscope->Length;
882 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno,
883 ria->dev_path, ria->dev_path_len);
885 if (dmar_match_verbose)
887 entry = dmar_gas_alloc_entry(ria->domain,
889 entry->start = resmem->BaseAddress;
890 /* The RMRR entry end address is inclusive. */
891 entry->end = resmem->EndAddress;
892 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
894 } else if (dmar_match_verbose) {
895 printf("not matched, err %d\n", match);
903 dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev,
904 struct dmar_map_entries_tailq *rmrr_entries)
906 struct rmrr_iter_args ria;
908 ria.dev_domain = pci_get_domain(dev);
909 ria.dev_path_len = dmar_dev_depth(dev);
910 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len];
911 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len);
913 if (dmar_match_verbose) {
914 device_printf(dev, "parsing RMRR entries for ");
915 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len,
921 ria.dev_path = dev_path;
922 ria.rmrr_entries = rmrr_entries;
923 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
926 struct inst_rmrr_iter_args {
927 struct dmar_unit *dmar;
931 dmar_path_dev(int segment, int path_len, int busno,
932 const ACPI_DMAR_PCI_PATH *path)
934 devclass_t pci_class;
935 device_t bus, pcib, dev;
938 pci_class = devclass_find("pci");
940 for (i = 0; i < path_len; i++, path++) {
941 dev = pci_find_dbsf(segment, busno, path->Device,
945 if (i != path_len - 1) {
946 bus = device_get_parent(dev);
947 pcib = device_get_parent(bus);
948 if (device_get_devclass(device_get_parent(pcib)) !=
952 busno = pcib_get_bus(dev);
958 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
960 const ACPI_DMAR_RESERVED_MEMORY *resmem;
961 const ACPI_DMAR_DEVICE_SCOPE *devscope;
962 struct inst_rmrr_iter_args *iria;
963 const char *ptr, *ptrend;
964 struct dmar_unit *dev_dmar;
967 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
971 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
972 if (resmem->Segment != iria->dmar->segment)
974 if (dmar_match_verbose) {
975 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
976 (uintmax_t)resmem->BaseAddress,
977 (uintmax_t)resmem->EndAddress);
980 ptr = (const char *)resmem + sizeof(*resmem);
981 ptrend = (const char *)resmem + resmem->Header.Length;
985 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
986 ptr += devscope->Length;
988 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
990 if (dmar_match_verbose) {
991 dmar_print_path(iria->dmar->dev, "RMRR scope",
992 devscope->Bus, (devscope->Length -
993 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
994 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
996 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
997 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
998 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1000 if (dmar_match_verbose)
1001 printf("null dev\n");
1004 dev_dmar = dmar_find(dev);
1005 if (dev_dmar != iria->dmar) {
1006 if (dmar_match_verbose) {
1007 printf("dmar%d matched, skipping\n",
1012 if (dmar_match_verbose)
1013 printf("matched, instantiating RMRR context\n");
1014 dmar_instantiate_ctx(iria->dmar, dev, true);
1022 * Pre-create all contexts for the DMAR which have RMRR entries.
1025 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
1027 struct inst_rmrr_iter_args iria;
1030 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1035 if (dmar_match_verbose)
1036 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
1037 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1039 if (!LIST_EMPTY(&dmar->domains)) {
1040 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1041 ("dmar%d: RMRR not handled but translation is already enabled",
1043 error = dmar_enable_translation(dmar);
1045 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1050 #include <ddb/ddb.h>
1051 #include <ddb/db_lex.h>
1054 dmar_print_domain_entry(const struct dmar_map_entry *entry)
1056 struct dmar_map_entry *l, *r;
1059 " start %jx end %jx free_after %jx free_down %jx flags %x ",
1060 entry->start, entry->end, entry->free_after, entry->free_down,
1063 l = RB_LEFT(entry, rb_entry);
1067 db_printf("%jx ", l->start);
1068 db_printf("right ");
1069 r = RB_RIGHT(entry, rb_entry);
1073 db_printf("%jx", r->start);
1078 dmar_print_ctx(struct dmar_ctx *ctx)
1082 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1083 ctx, pci_get_bus(ctx->ctx_tag.owner),
1084 pci_get_slot(ctx->ctx_tag.owner),
1085 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
1086 ctx->loads, ctx->unloads);
1090 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1092 struct dmar_map_entry *entry;
1093 struct dmar_ctx *ctx;
1096 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1097 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1098 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1099 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
1100 domain->flags, domain->pgtbl_obj, domain->entries_cnt);
1101 if (!LIST_EMPTY(&domain->contexts)) {
1102 db_printf(" Contexts:\n");
1103 LIST_FOREACH(ctx, &domain->contexts, link)
1104 dmar_print_ctx(ctx);
1108 db_printf(" mapped:\n");
1109 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
1110 dmar_print_domain_entry(entry);
1116 db_printf(" unloading:\n");
1117 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
1118 dmar_print_domain_entry(entry);
1124 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1126 struct dmar_unit *unit;
1127 struct dmar_domain *domain;
1128 struct dmar_ctx *ctx;
1129 bool show_mappings, valid;
1130 int pci_domain, bus, device, function, i, t;
1136 t = db_read_token();
1138 t = db_read_token();
1140 db_printf("Bad modifier\n");
1145 show_mappings = strchr(db_tok_string, 'm') != NULL;
1146 t = db_read_token();
1148 show_mappings = false;
1151 pci_domain = db_tok_number;
1152 t = db_read_token();
1154 bus = db_tok_number;
1155 t = db_read_token();
1157 device = db_tok_number;
1158 t = db_read_token();
1160 function = db_tok_number;
1169 db_printf("usage: show dmar_domain [/m] "
1170 "<domain> <bus> <device> <func>\n");
1173 for (i = 0; i < dmar_devcnt; i++) {
1174 unit = device_get_softc(dmar_devs[i]);
1175 LIST_FOREACH(domain, &unit->domains, link) {
1176 LIST_FOREACH(ctx, &domain->contexts, link) {
1177 if (pci_domain == unit->segment &&
1178 bus == pci_get_bus(ctx->ctx_tag.owner) &&
1180 pci_get_slot(ctx->ctx_tag.owner) &&
1182 pci_get_function(ctx->ctx_tag.owner)) {
1183 dmar_print_domain(domain,
1194 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1196 struct dmar_unit *unit;
1197 struct dmar_domain *domain;
1200 unit = device_get_softc(dmar_devs[idx]);
1201 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1202 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1203 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1204 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1205 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1206 dmar_read4(unit, DMAR_GSTS_REG),
1207 dmar_read4(unit, DMAR_FSTS_REG),
1208 dmar_read4(unit, DMAR_FECTL_REG));
1209 if (unit->ir_enabled) {
1210 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1211 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1213 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1214 dmar_read4(unit, DMAR_FEDATA_REG),
1215 dmar_read4(unit, DMAR_FEADDR_REG),
1216 dmar_read4(unit, DMAR_FEUADDR_REG));
1217 db_printf("primary fault log:\n");
1218 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1219 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1220 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1221 (uintmax_t)dmar_read8(unit, frir),
1222 (uintmax_t)dmar_read8(unit, frir + 8));
1224 if (DMAR_HAS_QI(unit)) {
1225 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1226 dmar_read4(unit, DMAR_IEDATA_REG),
1227 dmar_read4(unit, DMAR_IEADDR_REG),
1228 dmar_read4(unit, DMAR_IEUADDR_REG));
1229 if (unit->qi_enabled) {
1230 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1232 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1233 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1234 (uintmax_t)unit->inv_queue,
1235 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1236 (uintmax_t)unit->inv_queue_size,
1237 dmar_read4(unit, DMAR_IQH_REG),
1238 dmar_read4(unit, DMAR_IQT_REG),
1239 unit->inv_queue_avail,
1240 dmar_read4(unit, DMAR_ICS_REG),
1241 dmar_read4(unit, DMAR_IECTL_REG),
1242 unit->inv_waitd_seq_hw,
1243 &unit->inv_waitd_seq_hw,
1244 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1245 unit->inv_waitd_seq,
1246 unit->inv_waitd_gen);
1248 db_printf("qi is disabled\n");
1252 db_printf("domains:\n");
1253 LIST_FOREACH(domain, &unit->domains, link) {
1254 dmar_print_domain(domain, show_mappings);
1261 DB_SHOW_COMMAND(dmar, db_dmar_print)
1263 bool show_domains, show_mappings;
1265 show_domains = strchr(modif, 'd') != NULL;
1266 show_mappings = strchr(modif, 'm') != NULL;
1268 db_printf("usage: show dmar [/d] [/m] index\n");
1271 dmar_print_one((int)addr, show_domains, show_mappings);
1274 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1277 bool show_domains, show_mappings;
1279 show_domains = strchr(modif, 'd') != NULL;
1280 show_mappings = strchr(modif, 'm') != NULL;
1282 for (i = 0; i < dmar_devcnt; i++) {
1283 dmar_print_one(i, show_domains, show_mappings);