2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 The FreeBSD Foundation
7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
43 #include <sys/memdesc.h>
44 #include <sys/mutex.h>
46 #include <sys/rwlock.h>
48 #include <sys/sf_buf.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
55 #include <vm/vm_extern.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_object.h>
58 #include <vm/vm_page.h>
59 #include <vm/vm_pager.h>
60 #include <vm/vm_map.h>
61 #include <machine/atomic.h>
62 #include <machine/bus.h>
63 #include <machine/cpu.h>
64 #include <machine/md_var.h>
65 #include <machine/specialreg.h>
66 #include <x86/include/busdma_impl.h>
67 #include <x86/iommu/intel_reg.h>
68 #include <x86/iommu/busdma_dmar.h>
69 #include <x86/iommu/intel_dmar.h>
71 static int domain_unmap_buf_locked(struct dmar_domain *domain,
72 dmar_gaddr_t base, dmar_gaddr_t size, int flags);
75 * The cache of the identity mapping page tables for the DMARs. Using
76 * the cache saves significant amount of memory for page tables by
77 * reusing the page tables, since usually DMARs are identical and have
78 * the same capabilities. Still, cache records the information needed
79 * to match DMAR capabilities and page table format, to correctly
80 * handle different DMARs.
84 dmar_gaddr_t maxaddr; /* Page table covers the guest address
86 int pglvl; /* Total page table levels ignoring
88 int leaf; /* The last materialized page table
89 level, it is non-zero if superpages
91 vm_object_t pgtbl_obj; /* The page table pages */
92 LIST_ENTRY(idpgtbl) link;
95 static struct sx idpgtbl_lock;
96 SX_SYSINIT(idpgtbl, &idpgtbl_lock, "idpgtbl");
97 static LIST_HEAD(, idpgtbl) idpgtbls = LIST_HEAD_INITIALIZER(idpgtbls);
98 static MALLOC_DEFINE(M_DMAR_IDPGTBL, "dmar_idpgtbl",
99 "Intel DMAR Identity mappings cache elements");
102 * Build the next level of the page tables for the identity mapping.
103 * - lvl is the level to build;
104 * - idx is the index of the page table page in the pgtbl_obj, which is
105 * being allocated filled now;
106 * - addr is the starting address in the bus address space which is
107 * mapped by the page table page.
110 domain_idmap_nextlvl(struct idpgtbl *tbl, int lvl, vm_pindex_t idx,
116 dmar_gaddr_t f, pg_sz;
120 VM_OBJECT_ASSERT_LOCKED(tbl->pgtbl_obj);
121 if (addr >= tbl->maxaddr)
123 (void)dmar_pgalloc(tbl->pgtbl_obj, idx, DMAR_PGF_OBJL | DMAR_PGF_WAITOK |
125 base = idx * DMAR_NPTEPG + 1; /* Index of the first child page of idx */
126 pg_sz = pglvl_page_size(tbl->pglvl, lvl);
127 if (lvl != tbl->leaf) {
128 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz)
129 domain_idmap_nextlvl(tbl, lvl + 1, base + i, f);
131 VM_OBJECT_WUNLOCK(tbl->pgtbl_obj);
132 pte = dmar_map_pgtbl(tbl->pgtbl_obj, idx, DMAR_PGF_WAITOK, &sf);
133 if (lvl == tbl->leaf) {
134 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) {
135 if (f >= tbl->maxaddr)
137 pte[i].pte = (DMAR_PTE_ADDR_MASK & f) |
138 DMAR_PTE_R | DMAR_PTE_W;
141 for (i = 0, f = addr; i < DMAR_NPTEPG; i++, f += pg_sz) {
142 if (f >= tbl->maxaddr)
144 m1 = dmar_pgalloc(tbl->pgtbl_obj, base + i,
146 KASSERT(m1 != NULL, ("lost page table page"));
147 pte[i].pte = (DMAR_PTE_ADDR_MASK &
148 VM_PAGE_TO_PHYS(m1)) | DMAR_PTE_R | DMAR_PTE_W;
151 /* domain_get_idmap_pgtbl flushes CPU cache if needed. */
152 dmar_unmap_pgtbl(sf);
153 VM_OBJECT_WLOCK(tbl->pgtbl_obj);
157 * Find a ready and compatible identity-mapping page table in the
158 * cache. If not found, populate the identity-mapping page table for
159 * the context, up to the maxaddr. The maxaddr byte is allowed to be
160 * not mapped, which is aligned with the definition of Maxmem as the
161 * highest usable physical address + 1. If superpages are used, the
162 * maxaddr is typically mapped.
165 domain_get_idmap_pgtbl(struct dmar_domain *domain, dmar_gaddr_t maxaddr)
167 struct dmar_unit *unit;
173 leaf = 0; /* silence gcc */
176 * First, determine where to stop the paging structures.
178 for (i = 0; i < domain->pglvl; i++) {
179 if (i == domain->pglvl - 1 || domain_is_sp_lvl(domain, i)) {
186 * Search the cache for a compatible page table. Qualified
187 * page table must map up to maxaddr, its level must be
188 * supported by the DMAR and leaf should be equal to the
189 * calculated value. The later restriction could be lifted
190 * but I believe it is currently impossible to have any
191 * deviations for existing hardware.
193 sx_slock(&idpgtbl_lock);
194 LIST_FOREACH(tbl, &idpgtbls, link) {
195 if (tbl->maxaddr >= maxaddr &&
196 dmar_pglvl_supported(domain->dmar, tbl->pglvl) &&
198 res = tbl->pgtbl_obj;
199 vm_object_reference(res);
200 sx_sunlock(&idpgtbl_lock);
201 domain->pglvl = tbl->pglvl; /* XXXKIB ? */
207 * Not found in cache, relock the cache into exclusive mode to
208 * be able to add element, and recheck cache again after the
211 sx_sunlock(&idpgtbl_lock);
212 sx_xlock(&idpgtbl_lock);
213 LIST_FOREACH(tbl, &idpgtbls, link) {
214 if (tbl->maxaddr >= maxaddr &&
215 dmar_pglvl_supported(domain->dmar, tbl->pglvl) &&
217 res = tbl->pgtbl_obj;
218 vm_object_reference(res);
219 sx_xunlock(&idpgtbl_lock);
220 domain->pglvl = tbl->pglvl; /* XXXKIB ? */
226 * Still not found, create new page table.
228 tbl = malloc(sizeof(*tbl), M_DMAR_IDPGTBL, M_WAITOK);
229 tbl->pglvl = domain->pglvl;
231 tbl->maxaddr = maxaddr;
232 tbl->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL,
233 IDX_TO_OFF(pglvl_max_pages(tbl->pglvl)), 0, 0, NULL);
234 VM_OBJECT_WLOCK(tbl->pgtbl_obj);
235 domain_idmap_nextlvl(tbl, 0, 0, 0);
236 VM_OBJECT_WUNLOCK(tbl->pgtbl_obj);
237 LIST_INSERT_HEAD(&idpgtbls, tbl, link);
238 res = tbl->pgtbl_obj;
239 vm_object_reference(res);
240 sx_xunlock(&idpgtbl_lock);
244 * Table was found or created.
246 * If DMAR does not snoop paging structures accesses, flush
247 * CPU cache to memory. Note that dmar_unmap_pgtbl() coherent
248 * argument was possibly invalid at the time of the identity
249 * page table creation, since DMAR which was passed at the
250 * time of creation could be coherent, while current DMAR is
253 * If DMAR cannot look into the chipset write buffer, flush it
257 if (!DMAR_IS_COHERENT(unit)) {
258 VM_OBJECT_WLOCK(res);
259 for (m = vm_page_lookup(res, 0); m != NULL;
261 pmap_invalidate_cache_pages(&m, 1);
262 VM_OBJECT_WUNLOCK(res);
264 if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) {
266 dmar_flush_write_bufs(unit);
274 * Return a reference to the identity mapping page table to the cache.
277 put_idmap_pgtbl(vm_object_t obj)
279 struct idpgtbl *tbl, *tbl1;
282 sx_slock(&idpgtbl_lock);
283 KASSERT(obj->ref_count >= 2, ("lost cache reference"));
284 vm_object_deallocate(obj);
287 * Cache always owns one last reference on the page table object.
288 * If there is an additional reference, object must stay.
290 if (obj->ref_count > 1) {
291 sx_sunlock(&idpgtbl_lock);
296 * Cache reference is the last, remove cache element and free
297 * page table object, returning the page table pages to the
300 sx_sunlock(&idpgtbl_lock);
301 sx_xlock(&idpgtbl_lock);
302 LIST_FOREACH_SAFE(tbl, &idpgtbls, link, tbl1) {
303 rmobj = tbl->pgtbl_obj;
304 if (rmobj->ref_count == 1) {
305 LIST_REMOVE(tbl, link);
306 atomic_subtract_int(&dmar_tbl_pagecnt,
307 rmobj->resident_page_count);
308 vm_object_deallocate(rmobj);
309 free(tbl, M_DMAR_IDPGTBL);
312 sx_xunlock(&idpgtbl_lock);
316 * The core routines to map and unmap host pages at the given guest
317 * address. Support superpages.
321 * Index of the pte for the guest address base in the page table at
325 domain_pgtbl_pte_off(struct dmar_domain *domain, dmar_gaddr_t base, int lvl)
328 base >>= DMAR_PAGE_SHIFT + (domain->pglvl - lvl - 1) *
330 return (base & DMAR_PTEMASK);
334 * Returns the page index of the page table page in the page table
335 * object, which maps the given address base at the page table level
339 domain_pgtbl_get_pindex(struct dmar_domain *domain, dmar_gaddr_t base, int lvl)
341 vm_pindex_t idx, pidx;
344 KASSERT(lvl >= 0 && lvl < domain->pglvl,
345 ("wrong lvl %p %d", domain, lvl));
347 for (pidx = idx = 0, i = 0; i < lvl; i++, pidx = idx) {
348 idx = domain_pgtbl_pte_off(domain, base, i) +
349 pidx * DMAR_NPTEPG + 1;
355 domain_pgtbl_map_pte(struct dmar_domain *domain, dmar_gaddr_t base, int lvl,
356 int flags, vm_pindex_t *idxp, struct sf_buf **sf)
360 dmar_pte_t *pte, *ptep;
361 vm_pindex_t idx, idx1;
363 DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
364 KASSERT((flags & DMAR_PGF_OBJL) != 0, ("lost PGF_OBJL"));
366 idx = domain_pgtbl_get_pindex(domain, base, lvl);
367 if (*sf != NULL && idx == *idxp) {
368 pte = (dmar_pte_t *)sf_buf_kva(*sf);
371 dmar_unmap_pgtbl(*sf);
374 pte = dmar_map_pgtbl(domain->pgtbl_obj, idx, flags, sf);
377 ("lost root page table page %p", domain));
379 * Page table page does not exist, allocate
380 * it and create a pte in the preceeding page level
381 * to reference the allocated page table page.
383 m = dmar_pgalloc(domain->pgtbl_obj, idx, flags |
389 * Prevent potential free while pgtbl_obj is
390 * unlocked in the recursive call to
391 * domain_pgtbl_map_pte(), if other thread did
392 * pte write and clean while the lock is
398 ptep = domain_pgtbl_map_pte(domain, base, lvl - 1,
401 KASSERT(m->pindex != 0,
402 ("loosing root page %p", domain));
404 dmar_pgfree(domain->pgtbl_obj, m->pindex,
408 dmar_pte_store(&ptep->pte, DMAR_PTE_R | DMAR_PTE_W |
410 dmar_flush_pte_to_ram(domain->dmar, ptep);
411 sf_buf_page(sfp)->ref_count += 1;
413 dmar_unmap_pgtbl(sfp);
414 /* Only executed once. */
418 pte += domain_pgtbl_pte_off(domain, base, lvl);
423 domain_map_buf_locked(struct dmar_domain *domain, dmar_gaddr_t base,
424 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags)
428 dmar_gaddr_t pg_sz, base1, size1;
429 vm_pindex_t pi, c, idx, run_sz;
433 DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
437 flags |= DMAR_PGF_OBJL;
438 TD_PREP_PINNED_ASSERT;
440 for (sf = NULL, pi = 0; size > 0; base += pg_sz, size -= pg_sz,
442 for (lvl = 0, c = 0, superpage = false;; lvl++) {
443 pg_sz = domain_page_size(domain, lvl);
444 run_sz = pg_sz >> DMAR_PAGE_SHIFT;
445 if (lvl == domain->pglvl - 1)
448 * Check if the current base suitable for the
449 * superpage mapping. First, verify the level.
451 if (!domain_is_sp_lvl(domain, lvl))
454 * Next, look at the size of the mapping and
455 * alignment of both guest and host addresses.
457 if (size < pg_sz || (base & (pg_sz - 1)) != 0 ||
458 (VM_PAGE_TO_PHYS(ma[pi]) & (pg_sz - 1)) != 0)
460 /* All passed, check host pages contiguouty. */
462 for (c = 1; c < run_sz; c++) {
463 if (VM_PAGE_TO_PHYS(ma[pi + c]) !=
464 VM_PAGE_TO_PHYS(ma[pi + c - 1]) +
474 KASSERT(size >= pg_sz,
475 ("mapping loop overflow %p %jx %jx %jx", domain,
476 (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz));
477 KASSERT(pg_sz > 0, ("pg_sz 0 lvl %d", lvl));
478 pte = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf);
480 KASSERT((flags & DMAR_PGF_WAITOK) == 0,
481 ("failed waitable pte alloc %p", domain));
483 dmar_unmap_pgtbl(sf);
484 domain_unmap_buf_locked(domain, base1, base - base1,
489 dmar_pte_store(&pte->pte, VM_PAGE_TO_PHYS(ma[pi]) | pflags |
490 (superpage ? DMAR_PTE_SP : 0));
491 dmar_flush_pte_to_ram(domain->dmar, pte);
492 sf_buf_page(sf)->ref_count += 1;
495 dmar_unmap_pgtbl(sf);
501 domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base, dmar_gaddr_t size,
502 vm_page_t *ma, uint64_t pflags, int flags)
504 struct dmar_unit *unit;
509 KASSERT((domain->flags & DMAR_DOMAIN_IDMAP) == 0,
510 ("modifying idmap pagetable domain %p", domain));
511 KASSERT((base & DMAR_PAGE_MASK) == 0,
512 ("non-aligned base %p %jx %jx", domain, (uintmax_t)base,
514 KASSERT((size & DMAR_PAGE_MASK) == 0,
515 ("non-aligned size %p %jx %jx", domain, (uintmax_t)base,
517 KASSERT(size > 0, ("zero size %p %jx %jx", domain, (uintmax_t)base,
519 KASSERT(base < (1ULL << domain->agaw),
520 ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
521 (uintmax_t)size, domain->agaw));
522 KASSERT(base + size < (1ULL << domain->agaw),
523 ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
524 (uintmax_t)size, domain->agaw));
525 KASSERT(base + size > base,
526 ("size overflow %p %jx %jx", domain, (uintmax_t)base,
528 KASSERT((pflags & (DMAR_PTE_R | DMAR_PTE_W)) != 0,
529 ("neither read nor write %jx", (uintmax_t)pflags));
530 KASSERT((pflags & ~(DMAR_PTE_R | DMAR_PTE_W | DMAR_PTE_SNP |
532 ("invalid pte flags %jx", (uintmax_t)pflags));
533 KASSERT((pflags & DMAR_PTE_SNP) == 0 ||
534 (unit->hw_ecap & DMAR_ECAP_SC) != 0,
535 ("PTE_SNP for dmar without snoop control %p %jx",
536 domain, (uintmax_t)pflags));
537 KASSERT((pflags & DMAR_PTE_TM) == 0 ||
538 (unit->hw_ecap & DMAR_ECAP_DI) != 0,
539 ("PTE_TM for dmar without DIOTLB %p %jx",
540 domain, (uintmax_t)pflags));
541 KASSERT((flags & ~DMAR_PGF_WAITOK) == 0, ("invalid flags %x", flags));
543 DMAR_DOMAIN_PGLOCK(domain);
544 error = domain_map_buf_locked(domain, base, size, ma, pflags, flags);
545 DMAR_DOMAIN_PGUNLOCK(domain);
549 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
550 domain_flush_iotlb_sync(domain, base, size);
551 else if ((unit->hw_cap & DMAR_CAP_RWBF) != 0) {
552 /* See 11.1 Write Buffer Flushing. */
554 dmar_flush_write_bufs(unit);
560 static void domain_unmap_clear_pte(struct dmar_domain *domain,
561 dmar_gaddr_t base, int lvl, int flags, dmar_pte_t *pte,
562 struct sf_buf **sf, bool free_fs);
565 domain_free_pgtbl_pde(struct dmar_domain *domain, dmar_gaddr_t base,
573 pde = domain_pgtbl_map_pte(domain, base, lvl, flags, &idx, &sf);
574 domain_unmap_clear_pte(domain, base, lvl, flags, pde, &sf, true);
578 domain_unmap_clear_pte(struct dmar_domain *domain, dmar_gaddr_t base, int lvl,
579 int flags, dmar_pte_t *pte, struct sf_buf **sf, bool free_sf)
583 dmar_pte_clear(&pte->pte);
584 dmar_flush_pte_to_ram(domain->dmar, pte);
585 m = sf_buf_page(*sf);
587 dmar_unmap_pgtbl(*sf);
591 if (m->ref_count != 0)
594 ("lost reference (lvl) on root pg domain %p base %jx lvl %d",
595 domain, (uintmax_t)base, lvl));
596 KASSERT(m->pindex != 0,
597 ("lost reference (idx) on root pg domain %p base %jx lvl %d",
598 domain, (uintmax_t)base, lvl));
599 dmar_pgfree(domain->pgtbl_obj, m->pindex, flags);
600 domain_free_pgtbl_pde(domain, base, lvl - 1, flags);
604 * Assumes that the unmap is never partial.
607 domain_unmap_buf_locked(struct dmar_domain *domain, dmar_gaddr_t base,
608 dmar_gaddr_t size, int flags)
616 DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
620 KASSERT((domain->flags & DMAR_DOMAIN_IDMAP) == 0,
621 ("modifying idmap pagetable domain %p", domain));
622 KASSERT((base & DMAR_PAGE_MASK) == 0,
623 ("non-aligned base %p %jx %jx", domain, (uintmax_t)base,
625 KASSERT((size & DMAR_PAGE_MASK) == 0,
626 ("non-aligned size %p %jx %jx", domain, (uintmax_t)base,
628 KASSERT(base < (1ULL << domain->agaw),
629 ("base too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
630 (uintmax_t)size, domain->agaw));
631 KASSERT(base + size < (1ULL << domain->agaw),
632 ("end too high %p %jx %jx agaw %d", domain, (uintmax_t)base,
633 (uintmax_t)size, domain->agaw));
634 KASSERT(base + size > base,
635 ("size overflow %p %jx %jx", domain, (uintmax_t)base,
637 KASSERT((flags & ~DMAR_PGF_WAITOK) == 0, ("invalid flags %x", flags));
639 pg_sz = 0; /* silence gcc */
640 flags |= DMAR_PGF_OBJL;
641 TD_PREP_PINNED_ASSERT;
643 for (sf = NULL; size > 0; base += pg_sz, size -= pg_sz) {
644 for (lvl = 0; lvl < domain->pglvl; lvl++) {
645 if (lvl != domain->pglvl - 1 &&
646 !domain_is_sp_lvl(domain, lvl))
648 pg_sz = domain_page_size(domain, lvl);
651 pte = domain_pgtbl_map_pte(domain, base, lvl, flags,
654 ("sleeping or page missed %p %jx %d 0x%x",
655 domain, (uintmax_t)base, lvl, flags));
656 if ((pte->pte & DMAR_PTE_SP) != 0 ||
657 lvl == domain->pglvl - 1) {
658 domain_unmap_clear_pte(domain, base, lvl,
659 flags, pte, &sf, false);
663 KASSERT(size >= pg_sz,
664 ("unmapping loop overflow %p %jx %jx %jx", domain,
665 (uintmax_t)base, (uintmax_t)size, (uintmax_t)pg_sz));
668 dmar_unmap_pgtbl(sf);
670 * See 11.1 Write Buffer Flushing for an explanation why RWBF
671 * can be ignored there.
679 domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
680 dmar_gaddr_t size, int flags)
684 DMAR_DOMAIN_PGLOCK(domain);
685 error = domain_unmap_buf_locked(domain, base, size, flags);
686 DMAR_DOMAIN_PGUNLOCK(domain);
691 domain_alloc_pgtbl(struct dmar_domain *domain)
695 KASSERT(domain->pgtbl_obj == NULL,
696 ("already initialized %p", domain));
698 domain->pgtbl_obj = vm_pager_allocate(OBJT_PHYS, NULL,
699 IDX_TO_OFF(pglvl_max_pages(domain->pglvl)), 0, 0, NULL);
700 DMAR_DOMAIN_PGLOCK(domain);
701 m = dmar_pgalloc(domain->pgtbl_obj, 0, DMAR_PGF_WAITOK |
702 DMAR_PGF_ZERO | DMAR_PGF_OBJL);
703 /* No implicit free of the top level page table page. */
705 DMAR_DOMAIN_PGUNLOCK(domain);
706 DMAR_LOCK(domain->dmar);
707 domain->flags |= DMAR_DOMAIN_PGTBL_INITED;
708 DMAR_UNLOCK(domain->dmar);
713 domain_free_pgtbl(struct dmar_domain *domain)
718 obj = domain->pgtbl_obj;
720 KASSERT((domain->dmar->hw_ecap & DMAR_ECAP_PT) != 0 &&
721 (domain->flags & DMAR_DOMAIN_IDMAP) != 0,
722 ("lost pagetable object domain %p", domain));
725 DMAR_DOMAIN_ASSERT_PGLOCKED(domain);
726 domain->pgtbl_obj = NULL;
728 if ((domain->flags & DMAR_DOMAIN_IDMAP) != 0) {
729 put_idmap_pgtbl(obj);
730 domain->flags &= ~DMAR_DOMAIN_IDMAP;
734 /* Obliterate ref_counts */
735 VM_OBJECT_ASSERT_WLOCKED(obj);
736 for (m = vm_page_lookup(obj, 0); m != NULL; m = vm_page_next(m))
738 VM_OBJECT_WUNLOCK(obj);
739 vm_object_deallocate(obj);
742 static inline uint64_t
743 domain_wait_iotlb_flush(struct dmar_unit *unit, uint64_t wt, int iro)
747 dmar_write8(unit, iro + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
748 DMAR_IOTLB_DR | DMAR_IOTLB_DW | wt);
750 iotlbr = dmar_read8(unit, iro + DMAR_IOTLB_REG_OFF);
751 if ((iotlbr & DMAR_IOTLB_IVT) == 0)
759 domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
762 struct dmar_unit *unit;
768 KASSERT(!unit->qi_enabled, ("dmar%d: sync iotlb flush call",
770 iro = DMAR_ECAP_IRO(unit->hw_ecap) * 16;
772 if ((unit->hw_cap & DMAR_CAP_PSI) == 0 || size > 2 * 1024 * 1024) {
773 iotlbr = domain_wait_iotlb_flush(unit, DMAR_IOTLB_IIRG_DOM |
774 DMAR_IOTLB_DID(domain->domain), iro);
775 KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
776 DMAR_IOTLB_IAIG_INVLD,
777 ("dmar%d: invalidation failed %jx", unit->unit,
780 for (; size > 0; base += isize, size -= isize) {
781 am = calc_am(unit, base, size, &isize);
782 dmar_write8(unit, iro, base | am);
783 iotlbr = domain_wait_iotlb_flush(unit,
784 DMAR_IOTLB_IIRG_PAGE |
785 DMAR_IOTLB_DID(domain->domain), iro);
786 KASSERT((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
787 DMAR_IOTLB_IAIG_INVLD,
788 ("dmar%d: PSI invalidation failed "
789 "iotlbr 0x%jx base 0x%jx size 0x%jx am %d",
790 unit->unit, (uintmax_t)iotlbr,
791 (uintmax_t)base, (uintmax_t)size, am));
793 * Any non-page granularity covers whole guest
794 * address space for the domain.
796 if ((iotlbr & DMAR_IOTLB_IAIG_MASK) !=
797 DMAR_IOTLB_IAIG_PAGE)