2 * Copyright (c) 2015 The FreeBSD Foundation
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/memdesc.h>
40 #include <sys/mutex.h>
42 #include <sys/rwlock.h>
43 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/intr_machdep.h>
49 #include <vm/vm_extern.h>
50 #include <vm/vm_kern.h>
51 #include <vm/vm_object.h>
52 #include <vm/vm_page.h>
53 #include <x86/include/apicreg.h>
54 #include <x86/include/apicvar.h>
55 #include <x86/include/busdma_impl.h>
56 #include <x86/iommu/intel_reg.h>
57 #include <x86/iommu/busdma_dmar.h>
58 #include <dev/pci/pcireg.h>
59 #include <x86/iommu/intel_dmar.h>
60 #include <dev/pci/pcivar.h>
61 #include <x86/iommu/iommu_intrmap.h>
63 static struct dmar_unit *dmar_ir_find(device_t src, uint16_t *rid,
65 static void dmar_ir_program_irte(struct dmar_unit *unit, u_int idx,
66 uint64_t low, uint16_t rid);
67 static int dmar_ir_free_irte(struct dmar_unit *unit, u_int cookie);
70 iommu_alloc_msi_intr(device_t src, u_int *cookies, u_int count)
72 struct dmar_unit *unit;
77 unit = dmar_ir_find(src, NULL, NULL);
78 if (unit == NULL || !unit->ir_enabled) {
79 for (i = 0; i < count; i++)
84 error = vmem_alloc(unit->irtids, count, M_FIRSTFIT | M_NOWAIT,
87 KASSERT(error != EOPNOTSUPP,
88 ("impossible EOPNOTSUPP from vmem"));
92 for (i = 0; i < count; i++)
98 iommu_map_msi_intr(device_t src, u_int cpu, u_int vector, u_int cookie,
99 uint64_t *addr, uint32_t *data)
101 struct dmar_unit *unit;
106 unit = dmar_ir_find(src, &rid, &is_dmar);
108 KASSERT(unit == NULL, ("DMAR cannot translate itself"));
111 * See VT-d specification, 5.1.6 Remapping Hardware -
112 * Interrupt Programming.
115 *addr = MSI_INTEL_ADDR_BASE | ((cpu & 0xff) << 12);
117 *addr |= ((uint64_t)cpu & 0xffffff00) << 32;
119 KASSERT(cpu <= 0xff, ("cpu id too big %d", cpu));
122 if (unit == NULL || !unit->ir_enabled || cookie == -1)
125 low = (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
126 DMAR_IRTE1_DST_xAPIC(cpu)) | DMAR_IRTE1_V(vector) |
127 DMAR_IRTE1_DLM_FM | DMAR_IRTE1_TM_EDGE | DMAR_IRTE1_RH_DIRECT |
128 DMAR_IRTE1_DM_PHYSICAL | DMAR_IRTE1_P;
129 dmar_ir_program_irte(unit, cookie, low, rid);
133 * See VT-d specification, 5.1.5.2 MSI and MSI-X
134 * Register Programming.
136 *addr = MSI_INTEL_ADDR_BASE | ((cookie & 0x7fff) << 5) |
137 ((cookie & 0x8000) << 2) | 0x18;
144 iommu_unmap_msi_intr(device_t src, u_int cookie)
146 struct dmar_unit *unit;
150 unit = dmar_ir_find(src, NULL, NULL);
151 return (dmar_ir_free_irte(unit, cookie));
155 iommu_map_ioapic_intr(u_int ioapic_id, u_int cpu, u_int vector, bool edge,
156 bool activehi, int irq, u_int *cookie, uint32_t *hi, uint32_t *lo)
158 struct dmar_unit *unit;
159 vmem_addr_t vmem_res;
165 unit = dmar_find_ioapic(ioapic_id, &rid);
166 if (unit == NULL || !unit->ir_enabled) {
171 error = vmem_alloc(unit->irtids, 1, M_FIRSTFIT | M_NOWAIT, &vmem_res);
173 KASSERT(error != EOPNOTSUPP,
174 ("impossible EOPNOTSUPP from vmem"));
181 low |= DMAR_IRTE1_DLM_ExtINT;
184 low |= DMAR_IRTE1_DLM_NMI;
187 low |= DMAR_IRTE1_DLM_SMI;
190 KASSERT(vector != 0, ("No vector for IRQ %u", irq));
191 low |= DMAR_IRTE1_DLM_FM | DMAR_IRTE1_V(vector);
194 low |= (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
195 DMAR_IRTE1_DST_xAPIC(cpu)) |
196 (edge ? DMAR_IRTE1_TM_EDGE : DMAR_IRTE1_TM_LEVEL) |
197 DMAR_IRTE1_RH_DIRECT | DMAR_IRTE1_DM_PHYSICAL | DMAR_IRTE1_P;
198 dmar_ir_program_irte(unit, idx, low, rid);
202 * See VT-d specification, 5.1.5.1 I/OxAPIC
205 iorte = (1ULL << 48) | ((uint64_t)(idx & 0x7fff) << 49) |
206 ((idx & 0x8000) != 0 ? (1 << 11) : 0) |
207 (edge ? IOART_TRGREDG : IOART_TRGRLVL) |
208 (activehi ? IOART_INTAHI : IOART_INTALO) |
209 IOART_DELFIXED | vector;
218 iommu_unmap_ioapic_intr(u_int ioapic_id, u_int *cookie)
220 struct dmar_unit *unit;
227 unit = dmar_find_ioapic(ioapic_id, NULL);
228 KASSERT(unit != NULL && unit->ir_enabled,
229 ("unmap: cookie %d unit %p", idx, unit));
230 return (dmar_ir_free_irte(unit, idx));
233 static struct dmar_unit *
234 dmar_ir_find(device_t src, uint16_t *rid, int *is_dmar)
236 devclass_t src_class;
237 struct dmar_unit *unit;
240 * We need to determine if the interrupt source generates FSB
241 * interrupts. If yes, it is either DMAR, in which case
242 * interrupts are not remapped. Or it is HPET, and interrupts
243 * are remapped. For HPET, source id is reported by HPET
244 * record in DMAR ACPI table.
248 src_class = device_get_devclass(src);
249 if (src_class == devclass_find("dmar")) {
253 } else if (src_class == devclass_find("hpet")) {
254 unit = dmar_find_hpet(src, rid);
256 unit = dmar_find(src, bootverbose);
257 if (unit != NULL && rid != NULL)
258 dmar_get_requester(src, rid);
264 dmar_ir_program_irte(struct dmar_unit *unit, u_int idx, uint64_t low,
270 KASSERT(idx < unit->irte_cnt,
271 ("bad cookie %d %d", idx, unit->irte_cnt));
272 irte = &(unit->irt[idx]);
273 high = DMAR_IRTE2_SVT_RID | DMAR_IRTE2_SQ_RID |
274 DMAR_IRTE2_SID_RID(rid);
276 device_printf(unit->dev,
277 "programming irte[%d] rid %#x high %#jx low %#jx\n",
278 idx, rid, (uintmax_t)high, (uintmax_t)low);
281 if ((irte->irte1 & DMAR_IRTE1_P) != 0) {
283 * The rte is already valid. Assume that the request
284 * is to remap the interrupt for balancing. Only low
285 * word of rte needs to be changed. Assert that the
286 * high word contains expected value.
288 KASSERT(irte->irte2 == high,
289 ("irte2 mismatch, %jx %jx", (uintmax_t)irte->irte2,
291 dmar_pte_update(&irte->irte1, low);
293 dmar_pte_store(&irte->irte2, high);
294 dmar_pte_store(&irte->irte1, low);
296 dmar_qi_invalidate_iec(unit, idx, 1);
302 dmar_ir_free_irte(struct dmar_unit *unit, u_int cookie)
306 KASSERT(unit != NULL && unit->ir_enabled,
307 ("unmap: cookie %d unit %p", cookie, unit));
308 KASSERT(cookie < unit->irte_cnt,
309 ("bad cookie %u %u", cookie, unit->irte_cnt));
310 irte = &(unit->irt[cookie]);
311 dmar_pte_clear(&irte->irte1);
312 dmar_pte_clear(&irte->irte2);
314 dmar_qi_invalidate_iec(unit, cookie, 1);
316 vmem_free(unit->irtids, cookie, 1);
324 return (powerof2(v) ? v : 1 << fls(v));
328 dmar_init_irt(struct dmar_unit *unit)
331 if ((unit->hw_ecap & DMAR_ECAP_IR) == 0)
333 unit->ir_enabled = 1;
334 TUNABLE_INT_FETCH("hw.dmar.ir", &unit->ir_enabled);
335 if (!unit->ir_enabled)
337 if (!unit->qi_enabled) {
338 unit->ir_enabled = 0;
340 device_printf(unit->dev,
341 "QI disabled, disabling interrupt remapping\n");
344 unit->irte_cnt = clp2(num_io_irqs);
345 unit->irt = (dmar_irte_t *)(uintptr_t)kmem_alloc_contig(
346 unit->irte_cnt * sizeof(dmar_irte_t), M_ZERO | M_WAITOK, 0,
347 dmar_high, PAGE_SIZE, 0, DMAR_IS_COHERENT(unit) ?
348 VM_MEMATTR_DEFAULT : VM_MEMATTR_UNCACHEABLE);
349 if (unit->irt == NULL)
351 unit->irt_phys = pmap_kextract((vm_offset_t)unit->irt);
352 unit->irtids = vmem_create("dmarirt", 0, unit->irte_cnt, 1, 0,
353 M_FIRSTFIT | M_NOWAIT);
355 dmar_load_irt_ptr(unit);
356 dmar_qi_invalidate_iec_glob(unit);
360 * Initialize mappings for already configured interrupt pins.
361 * Required, because otherwise the interrupts fault without
367 dmar_enable_ir(unit);
373 dmar_fini_irt(struct dmar_unit *unit)
376 unit->ir_enabled = 0;
377 if (unit->irt != NULL) {
378 dmar_disable_ir(unit);
379 dmar_qi_invalidate_iec_glob(unit);
380 vmem_destroy(unit->irtids);
381 kmem_free((vm_offset_t)unit->irt, unit->irte_cnt *
382 sizeof(dmar_irte_t));