2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
48 #include <machine/cpufunc.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52 #include <machine/resource.h>
53 #include <machine/segments.h>
55 #include <dev/ic/i8259.h>
57 #include <amd64/isa/icu.h>
58 #include <amd64/isa/isa.h>
60 #include <i386/isa/icu.h>
62 #include <pc98/cbus/cbus.h>
64 #include <i386/isa/isa.h>
67 #include <isa/isavar.h>
70 #define SDT_ATPIC SDT_SYSIGT
73 #define SDT_ATPIC SDT_SYS386IGT
74 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
81 * PC-98 machines wire the slave 8259A to pin 7 on the master PIC, and
82 * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
91 * Determine the base master and slave modes not including auto EOI support.
92 * All machines that FreeBSD supports use 8086 mode.
96 * PC-98 machines do not support auto EOI on the second PIC. Also, it
97 * seems that PC-98 machine PICs use buffered mode, and the master PIC
98 * uses special fully nested mode.
100 #define BASE_MASTER_MODE (ICW4_SFNM | ICW4_BUF | ICW4_MS | ICW4_8086)
101 #define BASE_SLAVE_MODE (ICW4_BUF | ICW4_8086)
103 #define BASE_MASTER_MODE ICW4_8086
104 #define BASE_SLAVE_MODE ICW4_8086
107 /* Enable automatic EOI if requested. */
109 #define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
111 #define MASTER_MODE BASE_MASTER_MODE
114 #define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
116 #define SLAVE_MODE BASE_SLAVE_MODE
119 #define IRQ_MASK(irq) (1 << (irq))
120 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
122 #define NUM_ISA_IRQS 16
124 static void atpic_init(void *dummy);
126 unsigned int imen; /* XXX */
129 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
130 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
131 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
132 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
133 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
134 IDTVEC(atpic_intr15);
136 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
138 #define ATPIC(io, base, eoi, imenptr) \
139 { { atpic_enable_source, atpic_disable_source, (eoi), \
140 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
141 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
142 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
145 #define INTSRC(irq) \
146 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
157 struct atpic_intsrc {
158 struct intsrc at_intsrc;
160 int at_irq; /* Relative to PIC base. */
161 enum intr_trigger at_trigger;
163 u_long at_straycount;
166 static void atpic_enable_source(struct intsrc *isrc);
167 static void atpic_disable_source(struct intsrc *isrc, int eoi);
168 static void atpic_eoi_master(struct intsrc *isrc);
169 static void atpic_eoi_slave(struct intsrc *isrc);
170 static void atpic_enable_intr(struct intsrc *isrc);
171 static void atpic_disable_intr(struct intsrc *isrc);
172 static int atpic_vector(struct intsrc *isrc);
173 static void atpic_resume(struct pic *pic);
174 static int atpic_source_pending(struct intsrc *isrc);
175 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
176 enum intr_polarity pol);
177 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
178 static void i8259_init(struct atpic *pic, int slave);
180 static struct atpic atpics[] = {
181 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
182 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
185 static struct atpic_intsrc atintrs[] = {
204 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
207 _atpic_eoi_master(struct intsrc *isrc)
210 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
211 ("%s: mismatched pic", __func__));
213 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
218 * The data sheet says no auto-EOI on slave, but it sometimes works.
219 * So, if AUTO_EOI_2 is enabled, we use it.
222 _atpic_eoi_slave(struct intsrc *isrc)
225 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
226 ("%s: mismatched pic", __func__));
228 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
230 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
236 atpic_enable_source(struct intsrc *isrc)
238 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
239 struct atpic *ap = (struct atpic *)isrc->is_pic;
242 if (*ap->at_imen & IMEN_MASK(ai)) {
243 *ap->at_imen &= ~IMEN_MASK(ai);
244 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
250 atpic_disable_source(struct intsrc *isrc, int eoi)
252 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
253 struct atpic *ap = (struct atpic *)isrc->is_pic;
256 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
257 *ap->at_imen |= IMEN_MASK(ai);
258 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
262 * Take care to call these functions directly instead of through
263 * a function pointer. All of the referenced variables should
264 * still be hot in the cache.
266 if (eoi == PIC_EOI) {
267 if (isrc->is_pic == &atpics[MASTER].at_pic)
268 _atpic_eoi_master(isrc);
270 _atpic_eoi_slave(isrc);
277 atpic_eoi_master(struct intsrc *isrc)
281 _atpic_eoi_master(isrc);
287 atpic_eoi_slave(struct intsrc *isrc)
291 _atpic_eoi_slave(isrc);
297 atpic_enable_intr(struct intsrc *isrc)
302 atpic_disable_intr(struct intsrc *isrc)
308 atpic_vector(struct intsrc *isrc)
310 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
311 struct atpic *ap = (struct atpic *)isrc->is_pic;
313 return (IRQ(ap, ai));
317 atpic_source_pending(struct intsrc *isrc)
319 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
320 struct atpic *ap = (struct atpic *)isrc->is_pic;
322 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
326 atpic_resume(struct pic *pic)
328 struct atpic *ap = (struct atpic *)pic;
330 i8259_init(ap, ap == &atpics[SLAVE]);
332 if (ap == &atpics[SLAVE] && elcr_found)
338 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
339 enum intr_polarity pol)
341 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
344 /* Map conforming values to edge/hi and sanity check the values. */
345 if (trig == INTR_TRIGGER_CONFORM)
346 trig = INTR_TRIGGER_EDGE;
347 if (pol == INTR_POLARITY_CONFORM)
348 pol = INTR_POLARITY_HIGH;
349 vector = atpic_vector(isrc);
350 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
351 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
353 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
354 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
355 pol == INTR_POLARITY_HIGH ? "high" : "low");
359 /* If there is no change, just return. */
360 if (ai->at_trigger == trig)
364 if ((vector == 0 || vector == 1 || vector == 7 || vector == 8) &&
365 trig == INTR_TRIGGER_LEVEL) {
368 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
375 * Certain IRQs can never be level/lo, so don't try to set them
376 * that way if asked. At least some ELCR registers ignore setting
377 * these bits as well.
379 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
380 trig == INTR_TRIGGER_LEVEL) {
383 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
389 printf("atpic: No ELCR to configure IRQ%u as %s\n",
390 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
395 printf("atpic: Programming IRQ%u as %s\n", vector,
396 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
398 elcr_write_trigger(atpic_vector(isrc), trig);
399 ai->at_trigger = trig;
406 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
410 * 8259A's are only used in UP in which case all interrupts always
411 * go to the sole CPU and this function shouldn't even be called.
413 panic("%s: bad cookie", __func__);
417 i8259_init(struct atpic *pic, int slave)
421 /* Reset the PIC and program with next four bytes. */
424 /* MCA uses level triggered interrupts. */
426 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM);
429 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
430 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
433 outb(imr_addr, pic->at_intbase);
436 * Setup slave links. For the master pic, indicate what line
437 * the slave is configured on. For the slave indicate
438 * which line on the master we are connected to.
441 outb(imr_addr, ICU_SLAVEID);
443 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
447 outb(imr_addr, SLAVE_MODE);
449 outb(imr_addr, MASTER_MODE);
451 /* Set interrupt enable mask. */
452 outb(imr_addr, *pic->at_imen);
454 /* Reset is finished, default to IRR on read. */
455 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
458 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
460 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
468 struct atpic_intsrc *ai;
471 /* Start off with all interrupts disabled. */
473 i8259_init(&atpics[MASTER], 0);
474 i8259_init(&atpics[SLAVE], 1);
475 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
477 /* Install low-level interrupt handlers for all of our IRQs. */
478 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
479 if (i == ICU_SLAVEID)
481 ai->at_intsrc.is_count = &ai->at_count;
482 ai->at_intsrc.is_straycount = &ai->at_straycount;
483 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
484 ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
488 /* For MCA systems, all interrupts are level triggered. */
490 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
491 ai->at_trigger = INTR_TRIGGER_LEVEL;
496 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
502 ai->at_trigger = INTR_TRIGGER_EDGE;
505 ai->at_trigger = INTR_TRIGGER_LEVEL;
510 * Look for an ELCR. If we find one, update the trigger modes.
511 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
512 * edge triggered and that everything else is level triggered.
513 * We only use the trigger information to reprogram the ELCR if
514 * we have one and as an optimization to avoid masking edge
515 * triggered interrupts. For the case that we don't have an ELCR,
516 * it doesn't hurt to mask an edge triggered interrupt, so we
517 * assume level trigger for any interrupt that we aren't sure is
521 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
522 ai->at_trigger = elcr_read_trigger(i);
524 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
531 ai->at_trigger = INTR_TRIGGER_EDGE;
534 ai->at_trigger = INTR_TRIGGER_LEVEL;
542 atpic_init(void *dummy __unused)
544 struct atpic_intsrc *ai;
548 * Register our PICs, even if we aren't going to use any of their
549 * pins so that they are suspended and resumed.
551 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
552 intr_register_pic(&atpics[1].at_pic) != 0)
553 panic("Unable to register ATPICs");
556 * If any of the ISA IRQs have an interrupt source already, then
557 * assume that the APICs are being used and don't register any
558 * of our interrupt sources. This makes sure we don't accidentally
559 * use mixed mode. The "accidental" use could otherwise occur on
560 * machines that route the ACPI SCI interrupt to a different ISA
561 * IRQ (at least one machines routes it to IRQ 13) thus disabling
562 * that APIC ISA routing and allowing the ATPIC source for that IRQ
563 * to leak through. We used to depend on this feature for routing
564 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
566 for (i = 0; i < NUM_ISA_IRQS; i++)
567 if (intr_lookup_source(i) != NULL)
570 /* Loop through all interrupt sources and add them. */
571 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
572 if (i == ICU_SLAVEID)
574 intr_register_source(&ai->at_intsrc);
577 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
580 atpic_handle_intr(u_int vector, struct trapframe *frame)
584 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
585 isrc = &atintrs[vector].at_intsrc;
588 * If we don't have an event, see if this is a spurious
591 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
595 * Read the ISR register to see if IRQ 7/15 is really
596 * pending. Reset read register back to IRR when done.
598 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
600 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
602 outb(port, OCW3_SEL | OCW3_RR);
604 if ((isr & IRQ_MASK(7)) == 0)
607 intr_execute_handlers(isrc, frame);
612 * Bus attachment for the ISA PIC.
614 static struct isa_pnp_id atpic_ids[] = {
615 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
620 atpic_probe(device_t dev)
624 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
631 * We might be granted IRQ 2, as this is typically consumed by chaining
632 * between the two PIC components. If we're using the APIC, however,
633 * this may not be the case, and as such we should free the resource.
636 * The generic ISA attachment code will handle allocating any other resources
637 * that we don't explicitly claim here.
640 atpic_attach(device_t dev)
642 struct resource *res;
645 /* Try to allocate our IRQ and then free it. */
647 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
649 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
653 static device_method_t atpic_methods[] = {
654 /* Device interface */
655 DEVMETHOD(device_probe, atpic_probe),
656 DEVMETHOD(device_attach, atpic_attach),
657 DEVMETHOD(device_detach, bus_generic_detach),
658 DEVMETHOD(device_shutdown, bus_generic_shutdown),
659 DEVMETHOD(device_suspend, bus_generic_suspend),
660 DEVMETHOD(device_resume, bus_generic_resume),
664 static driver_t atpic_driver = {
670 static devclass_t atpic_devclass;
672 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
674 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
678 * Return a bitmap of the current interrupt requests. This is 8259-specific
679 * and is only suitable for use at probe time.
682 isa_irq_pending(void)
689 return ((irr2 << 8) | irr1);