2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_auto_eoi.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/interrupt.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
47 #include <machine/cpufunc.h>
48 #include <machine/frame.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/resource.h>
52 #include <machine/segments.h>
54 #include <dev/ic/i8259.h>
55 #include <x86/isa/icu.h>
56 #include <isa/isareg.h>
57 #include <isa/isavar.h>
60 #define SDT_ATPIC SDT_SYSIGT
63 #define SDT_ATPIC SDT_SYS386IGT
64 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
70 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
72 #define NUM_ISA_IRQS 16
74 static void atpic_init(void *dummy);
77 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
78 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
79 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
80 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
81 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
83 /* XXXKIB i386 uses stubs until pti comes */
85 IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti),
86 IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti),
87 IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti),
88 IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti),
89 IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti),
90 IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti),
91 IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti),
92 IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti);
94 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
96 #define ATPIC(io, base, eoi) { \
98 .pic_enable_source = atpic_enable_source, \
99 .pic_disable_source = atpic_disable_source, \
100 .pic_eoi_source = (eoi), \
101 .pic_enable_intr = atpic_enable_intr, \
102 .pic_disable_intr = atpic_disable_intr, \
103 .pic_vector = atpic_vector, \
104 .pic_source_pending = atpic_source_pending, \
105 .pic_resume = atpic_resume, \
106 .pic_config_intr = atpic_config_intr, \
107 .pic_assign_cpu = atpic_assign_cpu \
110 .at_irqbase = (base), \
111 .at_intbase = IDT_IO_INTS + (base), \
115 #define INTSRC(irq) \
116 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
117 IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 }
127 struct atpic_intsrc {
128 struct intsrc at_intsrc;
129 inthand_t *at_intr, *at_intr_pti;
130 int at_irq; /* Relative to PIC base. */
131 enum intr_trigger at_trigger;
133 u_long at_straycount;
136 static void atpic_enable_source(struct intsrc *isrc);
137 static void atpic_disable_source(struct intsrc *isrc, int eoi);
138 static void atpic_eoi_master(struct intsrc *isrc);
139 static void atpic_eoi_slave(struct intsrc *isrc);
140 static void atpic_enable_intr(struct intsrc *isrc);
141 static void atpic_disable_intr(struct intsrc *isrc);
142 static int atpic_vector(struct intsrc *isrc);
143 static void atpic_resume(struct pic *pic, bool suspend_cancelled);
144 static int atpic_source_pending(struct intsrc *isrc);
145 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
146 enum intr_polarity pol);
147 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
148 static void i8259_init(struct atpic *pic, int slave);
150 static struct atpic atpics[] = {
151 ATPIC(IO_ICU1, 0, atpic_eoi_master),
152 ATPIC(IO_ICU2, 8, atpic_eoi_slave)
155 static struct atpic_intsrc atintrs[] = {
174 CTASSERT(nitems(atintrs) == NUM_ISA_IRQS);
177 _atpic_eoi_master(struct intsrc *isrc)
180 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
181 ("%s: mismatched pic", __func__));
183 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
188 * The data sheet says no auto-EOI on slave, but it sometimes works.
189 * So, if AUTO_EOI_2 is enabled, we use it.
192 _atpic_eoi_slave(struct intsrc *isrc)
195 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
196 ("%s: mismatched pic", __func__));
198 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
200 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
206 atpic_enable_source(struct intsrc *isrc)
208 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
209 struct atpic *ap = (struct atpic *)isrc->is_pic;
212 if (ap->at_imen & IMEN_MASK(ai)) {
213 ap->at_imen &= ~IMEN_MASK(ai);
214 outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
220 atpic_disable_source(struct intsrc *isrc, int eoi)
222 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
223 struct atpic *ap = (struct atpic *)isrc->is_pic;
226 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
227 ap->at_imen |= IMEN_MASK(ai);
228 outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
232 * Take care to call these functions directly instead of through
233 * a function pointer. All of the referenced variables should
234 * still be hot in the cache.
236 if (eoi == PIC_EOI) {
237 if (isrc->is_pic == &atpics[MASTER].at_pic)
238 _atpic_eoi_master(isrc);
240 _atpic_eoi_slave(isrc);
247 atpic_eoi_master(struct intsrc *isrc)
251 _atpic_eoi_master(isrc);
257 atpic_eoi_slave(struct intsrc *isrc)
261 _atpic_eoi_slave(isrc);
267 atpic_enable_intr(struct intsrc *isrc)
272 atpic_disable_intr(struct intsrc *isrc)
278 atpic_vector(struct intsrc *isrc)
280 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
281 struct atpic *ap = (struct atpic *)isrc->is_pic;
283 return (IRQ(ap, ai));
287 atpic_source_pending(struct intsrc *isrc)
289 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
290 struct atpic *ap = (struct atpic *)isrc->is_pic;
292 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
296 atpic_resume(struct pic *pic, bool suspend_cancelled)
298 struct atpic *ap = (struct atpic *)pic;
300 i8259_init(ap, ap == &atpics[SLAVE]);
301 if (ap == &atpics[SLAVE] && elcr_found)
306 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
307 enum intr_polarity pol)
309 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
312 /* Map conforming values to edge/hi and sanity check the values. */
313 if (trig == INTR_TRIGGER_CONFORM)
314 trig = INTR_TRIGGER_EDGE;
315 if (pol == INTR_POLARITY_CONFORM)
316 pol = INTR_POLARITY_HIGH;
317 vector = atpic_vector(isrc);
318 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
319 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
321 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
322 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
323 pol == INTR_POLARITY_HIGH ? "high" : "low");
327 /* If there is no change, just return. */
328 if (ai->at_trigger == trig)
332 * Certain IRQs can never be level/lo, so don't try to set them
333 * that way if asked. At least some ELCR registers ignore setting
334 * these bits as well.
336 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
337 trig == INTR_TRIGGER_LEVEL) {
340 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
346 printf("atpic: No ELCR to configure IRQ%u as %s\n",
347 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
352 printf("atpic: Programming IRQ%u as %s\n", vector,
353 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
355 elcr_write_trigger(atpic_vector(isrc), trig);
356 ai->at_trigger = trig;
362 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
366 * 8259A's are only used in UP in which case all interrupts always
367 * go to the sole CPU and this function shouldn't even be called.
369 panic("%s: bad cookie", __func__);
373 i8259_init(struct atpic *pic, int slave)
377 /* Reset the PIC and program with next four bytes. */
379 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
380 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
383 outb(imr_addr, pic->at_intbase);
386 * Setup slave links. For the master pic, indicate what line
387 * the slave is configured on. For the slave indicate
388 * which line on the master we are connected to.
391 outb(imr_addr, ICU_SLAVEID);
393 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
397 outb(imr_addr, SLAVE_MODE);
399 outb(imr_addr, MASTER_MODE);
401 /* Set interrupt enable mask. */
402 outb(imr_addr, pic->at_imen);
404 /* Reset is finished, default to IRR on read. */
405 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
407 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
409 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
417 struct atpic_intsrc *ai;
420 /* Start off with all interrupts disabled. */
421 i8259_init(&atpics[MASTER], 0);
422 i8259_init(&atpics[SLAVE], 1);
423 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
425 /* Install low-level interrupt handlers for all of our IRQs. */
426 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
427 if (i == ICU_SLAVEID)
429 ai->at_intsrc.is_count = &ai->at_count;
430 ai->at_intsrc.is_straycount = &ai->at_straycount;
431 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
432 ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC,
433 SEL_KPL, GSEL_ATPIC);
437 * Look for an ELCR. If we find one, update the trigger modes.
438 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
439 * edge triggered and that everything else is level triggered.
440 * We only use the trigger information to reprogram the ELCR if
441 * we have one and as an optimization to avoid masking edge
442 * triggered interrupts. For the case that we don't have an ELCR,
443 * it doesn't hurt to mask an edge triggered interrupt, so we
444 * assume level trigger for any interrupt that we aren't sure is
448 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
449 ai->at_trigger = elcr_read_trigger(i);
451 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
458 ai->at_trigger = INTR_TRIGGER_EDGE;
461 ai->at_trigger = INTR_TRIGGER_LEVEL;
468 atpic_init(void *dummy __unused)
470 struct atpic_intsrc *ai;
474 * Register our PICs, even if we aren't going to use any of their
475 * pins so that they are suspended and resumed.
477 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
478 intr_register_pic(&atpics[1].at_pic) != 0)
479 panic("Unable to register ATPICs");
482 * If any of the ISA IRQs have an interrupt source already, then
483 * assume that the APICs are being used and don't register any
484 * of our interrupt sources. This makes sure we don't accidentally
485 * use mixed mode. The "accidental" use could otherwise occur on
486 * machines that route the ACPI SCI interrupt to a different ISA
487 * IRQ (at least one machines routes it to IRQ 13) thus disabling
488 * that APIC ISA routing and allowing the ATPIC source for that IRQ
489 * to leak through. We used to depend on this feature for routing
490 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
492 for (i = 0; i < NUM_ISA_IRQS; i++)
493 if (intr_lookup_source(i) != NULL)
496 /* Loop through all interrupt sources and add them. */
497 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
498 if (i == ICU_SLAVEID)
500 intr_register_source(&ai->at_intsrc);
503 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL);
506 atpic_handle_intr(u_int vector, struct trapframe *frame)
510 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
511 isrc = &atintrs[vector].at_intsrc;
514 * If we don't have an event, see if this is a spurious
517 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
521 * Read the ISR register to see if IRQ 7/15 is really
522 * pending. Reset read register back to IRR when done.
524 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
526 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
528 outb(port, OCW3_SEL | OCW3_RR);
530 if ((isr & IRQ_MASK(7)) == 0)
533 intr_execute_handlers(isrc, frame);
538 * Bus attachment for the ISA PIC.
540 static struct isa_pnp_id atpic_ids[] = {
541 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
546 atpic_probe(device_t dev)
550 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
557 * We might be granted IRQ 2, as this is typically consumed by chaining
558 * between the two PIC components. If we're using the APIC, however,
559 * this may not be the case, and as such we should free the resource.
562 * The generic ISA attachment code will handle allocating any other resources
563 * that we don't explicitly claim here.
566 atpic_attach(device_t dev)
568 struct resource *res;
571 /* Try to allocate our IRQ and then free it. */
573 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
575 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
580 * Return a bitmap of the current interrupt requests. This is 8259-specific
581 * and is only suitable for use at probe time.
584 isa_irq_pending(void)
591 return ((irr2 << 8) | irr1);
594 static device_method_t atpic_methods[] = {
595 /* Device interface */
596 DEVMETHOD(device_probe, atpic_probe),
597 DEVMETHOD(device_attach, atpic_attach),
598 DEVMETHOD(device_detach, bus_generic_detach),
599 DEVMETHOD(device_shutdown, bus_generic_shutdown),
600 DEVMETHOD(device_suspend, bus_generic_suspend),
601 DEVMETHOD(device_resume, bus_generic_resume),
605 static driver_t atpic_driver = {
611 static devclass_t atpic_devclass;
613 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
614 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
615 ISA_PNP_INFO(atpic_ids);