2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include "opt_auto_eoi.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <machine/cpufunc.h>
46 #include <machine/frame.h>
47 #include <machine/intr_machdep.h>
48 #include <machine/md_var.h>
49 #include <machine/resource.h>
50 #include <machine/segments.h>
52 #include <dev/ic/i8259.h>
53 #include <x86/isa/icu.h>
54 #include <isa/isareg.h>
55 #include <isa/isavar.h>
58 #define SDT_ATPIC SDT_SYSIGT
61 #define SDT_ATPIC SDT_SYS386IGT
62 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
68 #define NUM_ISA_IRQS 16
70 static void atpic_init(void *dummy);
72 unsigned int imen; /* XXX */
75 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
76 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
77 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
78 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
79 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
82 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
84 #define ATPIC(io, base, eoi, imenptr) \
85 { { atpic_enable_source, atpic_disable_source, (eoi), \
86 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
87 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
88 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
92 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
103 struct atpic_intsrc {
104 struct intsrc at_intsrc;
106 int at_irq; /* Relative to PIC base. */
107 enum intr_trigger at_trigger;
109 u_long at_straycount;
112 static void atpic_enable_source(struct intsrc *isrc);
113 static void atpic_disable_source(struct intsrc *isrc, int eoi);
114 static void atpic_eoi_master(struct intsrc *isrc);
115 static void atpic_eoi_slave(struct intsrc *isrc);
116 static void atpic_enable_intr(struct intsrc *isrc);
117 static void atpic_disable_intr(struct intsrc *isrc);
118 static int atpic_vector(struct intsrc *isrc);
119 static void atpic_resume(struct pic *pic, bool suspend_cancelled);
120 static int atpic_source_pending(struct intsrc *isrc);
121 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
122 enum intr_polarity pol);
123 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
124 static void i8259_init(struct atpic *pic, int slave);
126 static struct atpic atpics[] = {
127 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
128 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
131 static struct atpic_intsrc atintrs[] = {
150 CTASSERT(nitems(atintrs) == NUM_ISA_IRQS);
153 _atpic_eoi_master(struct intsrc *isrc)
156 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
157 ("%s: mismatched pic", __func__));
159 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
164 * The data sheet says no auto-EOI on slave, but it sometimes works.
165 * So, if AUTO_EOI_2 is enabled, we use it.
168 _atpic_eoi_slave(struct intsrc *isrc)
171 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
172 ("%s: mismatched pic", __func__));
174 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
176 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
182 atpic_enable_source(struct intsrc *isrc)
184 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
185 struct atpic *ap = (struct atpic *)isrc->is_pic;
188 if (*ap->at_imen & IMEN_MASK(ai)) {
189 *ap->at_imen &= ~IMEN_MASK(ai);
190 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
196 atpic_disable_source(struct intsrc *isrc, int eoi)
198 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
199 struct atpic *ap = (struct atpic *)isrc->is_pic;
202 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
203 *ap->at_imen |= IMEN_MASK(ai);
204 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
208 * Take care to call these functions directly instead of through
209 * a function pointer. All of the referenced variables should
210 * still be hot in the cache.
212 if (eoi == PIC_EOI) {
213 if (isrc->is_pic == &atpics[MASTER].at_pic)
214 _atpic_eoi_master(isrc);
216 _atpic_eoi_slave(isrc);
223 atpic_eoi_master(struct intsrc *isrc)
227 _atpic_eoi_master(isrc);
233 atpic_eoi_slave(struct intsrc *isrc)
237 _atpic_eoi_slave(isrc);
243 atpic_enable_intr(struct intsrc *isrc)
248 atpic_disable_intr(struct intsrc *isrc)
254 atpic_vector(struct intsrc *isrc)
256 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
257 struct atpic *ap = (struct atpic *)isrc->is_pic;
259 return (IRQ(ap, ai));
263 atpic_source_pending(struct intsrc *isrc)
265 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
266 struct atpic *ap = (struct atpic *)isrc->is_pic;
268 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
272 atpic_resume(struct pic *pic, bool suspend_cancelled)
274 struct atpic *ap = (struct atpic *)pic;
276 i8259_init(ap, ap == &atpics[SLAVE]);
277 if (ap == &atpics[SLAVE] && elcr_found)
282 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
283 enum intr_polarity pol)
285 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
288 /* Map conforming values to edge/hi and sanity check the values. */
289 if (trig == INTR_TRIGGER_CONFORM)
290 trig = INTR_TRIGGER_EDGE;
291 if (pol == INTR_POLARITY_CONFORM)
292 pol = INTR_POLARITY_HIGH;
293 vector = atpic_vector(isrc);
294 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
295 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
297 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
298 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
299 pol == INTR_POLARITY_HIGH ? "high" : "low");
303 /* If there is no change, just return. */
304 if (ai->at_trigger == trig)
308 * Certain IRQs can never be level/lo, so don't try to set them
309 * that way if asked. At least some ELCR registers ignore setting
310 * these bits as well.
312 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
313 trig == INTR_TRIGGER_LEVEL) {
316 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
322 printf("atpic: No ELCR to configure IRQ%u as %s\n",
323 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
328 printf("atpic: Programming IRQ%u as %s\n", vector,
329 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
331 elcr_write_trigger(atpic_vector(isrc), trig);
332 ai->at_trigger = trig;
338 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
342 * 8259A's are only used in UP in which case all interrupts always
343 * go to the sole CPU and this function shouldn't even be called.
345 panic("%s: bad cookie", __func__);
349 i8259_init(struct atpic *pic, int slave)
353 /* Reset the PIC and program with next four bytes. */
355 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
356 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
359 outb(imr_addr, pic->at_intbase);
362 * Setup slave links. For the master pic, indicate what line
363 * the slave is configured on. For the slave indicate
364 * which line on the master we are connected to.
367 outb(imr_addr, ICU_SLAVEID);
369 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
373 outb(imr_addr, SLAVE_MODE);
375 outb(imr_addr, MASTER_MODE);
377 /* Set interrupt enable mask. */
378 outb(imr_addr, *pic->at_imen);
380 /* Reset is finished, default to IRR on read. */
381 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
383 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
385 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
393 struct atpic_intsrc *ai;
396 /* Start off with all interrupts disabled. */
398 i8259_init(&atpics[MASTER], 0);
399 i8259_init(&atpics[SLAVE], 1);
400 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
402 /* Install low-level interrupt handlers for all of our IRQs. */
403 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
404 if (i == ICU_SLAVEID)
406 ai->at_intsrc.is_count = &ai->at_count;
407 ai->at_intsrc.is_straycount = &ai->at_straycount;
408 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
409 ai->at_irq, ai->at_intr, SDT_ATPIC, SEL_KPL, GSEL_ATPIC);
413 * Look for an ELCR. If we find one, update the trigger modes.
414 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
415 * edge triggered and that everything else is level triggered.
416 * We only use the trigger information to reprogram the ELCR if
417 * we have one and as an optimization to avoid masking edge
418 * triggered interrupts. For the case that we don't have an ELCR,
419 * it doesn't hurt to mask an edge triggered interrupt, so we
420 * assume level trigger for any interrupt that we aren't sure is
424 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
425 ai->at_trigger = elcr_read_trigger(i);
427 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
434 ai->at_trigger = INTR_TRIGGER_EDGE;
437 ai->at_trigger = INTR_TRIGGER_LEVEL;
444 atpic_init(void *dummy __unused)
446 struct atpic_intsrc *ai;
450 * Register our PICs, even if we aren't going to use any of their
451 * pins so that they are suspended and resumed.
453 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
454 intr_register_pic(&atpics[1].at_pic) != 0)
455 panic("Unable to register ATPICs");
458 * If any of the ISA IRQs have an interrupt source already, then
459 * assume that the APICs are being used and don't register any
460 * of our interrupt sources. This makes sure we don't accidentally
461 * use mixed mode. The "accidental" use could otherwise occur on
462 * machines that route the ACPI SCI interrupt to a different ISA
463 * IRQ (at least one machines routes it to IRQ 13) thus disabling
464 * that APIC ISA routing and allowing the ATPIC source for that IRQ
465 * to leak through. We used to depend on this feature for routing
466 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
468 for (i = 0; i < NUM_ISA_IRQS; i++)
469 if (intr_lookup_source(i) != NULL)
472 /* Loop through all interrupt sources and add them. */
473 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
474 if (i == ICU_SLAVEID)
476 intr_register_source(&ai->at_intsrc);
479 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL);
482 atpic_handle_intr(u_int vector, struct trapframe *frame)
486 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
487 isrc = &atintrs[vector].at_intsrc;
490 * If we don't have an event, see if this is a spurious
493 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
497 * Read the ISR register to see if IRQ 7/15 is really
498 * pending. Reset read register back to IRR when done.
500 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
502 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
504 outb(port, OCW3_SEL | OCW3_RR);
506 if ((isr & IRQ_MASK(7)) == 0)
509 intr_execute_handlers(isrc, frame);
514 * Bus attachment for the ISA PIC.
516 static struct isa_pnp_id atpic_ids[] = {
517 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
522 atpic_probe(device_t dev)
526 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
533 * We might be granted IRQ 2, as this is typically consumed by chaining
534 * between the two PIC components. If we're using the APIC, however,
535 * this may not be the case, and as such we should free the resource.
538 * The generic ISA attachment code will handle allocating any other resources
539 * that we don't explicitly claim here.
542 atpic_attach(device_t dev)
544 struct resource *res;
547 /* Try to allocate our IRQ and then free it. */
549 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
551 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
555 static device_method_t atpic_methods[] = {
556 /* Device interface */
557 DEVMETHOD(device_probe, atpic_probe),
558 DEVMETHOD(device_attach, atpic_attach),
559 DEVMETHOD(device_detach, bus_generic_detach),
560 DEVMETHOD(device_shutdown, bus_generic_shutdown),
561 DEVMETHOD(device_suspend, bus_generic_suspend),
562 DEVMETHOD(device_resume, bus_generic_resume),
566 static driver_t atpic_driver = {
572 static devclass_t atpic_devclass;
574 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
575 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
578 * Return a bitmap of the current interrupt requests. This is 8259-specific
579 * and is only suitable for use at probe time.
582 isa_irq_pending(void)
589 return ((irr2 << 8) | irr1);