2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "opt_auto_eoi.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/interrupt.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
47 #include <machine/cpufunc.h>
48 #include <machine/frame.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/resource.h>
52 #include <machine/segments.h>
54 #include <dev/ic/i8259.h>
55 #include <x86/isa/icu.h>
56 #include <isa/isareg.h>
57 #include <isa/isavar.h>
60 #define SDT_ATPIC SDT_SYSIGT
63 #define SDT_ATPIC SDT_SYS386IGT
64 #define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
70 #define NUM_ISA_IRQS 16
72 static void atpic_init(void *dummy);
74 unsigned int imen; /* XXX */
77 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
78 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
79 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
80 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
81 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
83 /* XXXKIB i386 uses stubs until pti comes */
85 IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti),
86 IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti),
87 IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti),
88 IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti),
89 IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti),
90 IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti),
91 IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti),
92 IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti);
94 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
96 #define ATPIC(io, base, eoi, imenptr) \
97 { { atpic_enable_source, atpic_disable_source, (eoi), \
98 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
99 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
100 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
103 #define INTSRC(irq) \
104 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
105 IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 }
115 struct atpic_intsrc {
116 struct intsrc at_intsrc;
117 inthand_t *at_intr, *at_intr_pti;
118 int at_irq; /* Relative to PIC base. */
119 enum intr_trigger at_trigger;
121 u_long at_straycount;
124 static void atpic_enable_source(struct intsrc *isrc);
125 static void atpic_disable_source(struct intsrc *isrc, int eoi);
126 static void atpic_eoi_master(struct intsrc *isrc);
127 static void atpic_eoi_slave(struct intsrc *isrc);
128 static void atpic_enable_intr(struct intsrc *isrc);
129 static void atpic_disable_intr(struct intsrc *isrc);
130 static int atpic_vector(struct intsrc *isrc);
131 static void atpic_resume(struct pic *pic, bool suspend_cancelled);
132 static int atpic_source_pending(struct intsrc *isrc);
133 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
134 enum intr_polarity pol);
135 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
136 static void i8259_init(struct atpic *pic, int slave);
138 static struct atpic atpics[] = {
139 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
140 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
143 static struct atpic_intsrc atintrs[] = {
162 CTASSERT(nitems(atintrs) == NUM_ISA_IRQS);
165 _atpic_eoi_master(struct intsrc *isrc)
168 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
169 ("%s: mismatched pic", __func__));
171 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
176 * The data sheet says no auto-EOI on slave, but it sometimes works.
177 * So, if AUTO_EOI_2 is enabled, we use it.
180 _atpic_eoi_slave(struct intsrc *isrc)
183 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
184 ("%s: mismatched pic", __func__));
186 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
188 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
194 atpic_enable_source(struct intsrc *isrc)
196 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
197 struct atpic *ap = (struct atpic *)isrc->is_pic;
200 if (*ap->at_imen & IMEN_MASK(ai)) {
201 *ap->at_imen &= ~IMEN_MASK(ai);
202 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
208 atpic_disable_source(struct intsrc *isrc, int eoi)
210 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
211 struct atpic *ap = (struct atpic *)isrc->is_pic;
214 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
215 *ap->at_imen |= IMEN_MASK(ai);
216 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
220 * Take care to call these functions directly instead of through
221 * a function pointer. All of the referenced variables should
222 * still be hot in the cache.
224 if (eoi == PIC_EOI) {
225 if (isrc->is_pic == &atpics[MASTER].at_pic)
226 _atpic_eoi_master(isrc);
228 _atpic_eoi_slave(isrc);
235 atpic_eoi_master(struct intsrc *isrc)
239 _atpic_eoi_master(isrc);
245 atpic_eoi_slave(struct intsrc *isrc)
249 _atpic_eoi_slave(isrc);
255 atpic_enable_intr(struct intsrc *isrc)
260 atpic_disable_intr(struct intsrc *isrc)
266 atpic_vector(struct intsrc *isrc)
268 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
269 struct atpic *ap = (struct atpic *)isrc->is_pic;
271 return (IRQ(ap, ai));
275 atpic_source_pending(struct intsrc *isrc)
277 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
278 struct atpic *ap = (struct atpic *)isrc->is_pic;
280 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
284 atpic_resume(struct pic *pic, bool suspend_cancelled)
286 struct atpic *ap = (struct atpic *)pic;
288 i8259_init(ap, ap == &atpics[SLAVE]);
289 if (ap == &atpics[SLAVE] && elcr_found)
294 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
295 enum intr_polarity pol)
297 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
300 /* Map conforming values to edge/hi and sanity check the values. */
301 if (trig == INTR_TRIGGER_CONFORM)
302 trig = INTR_TRIGGER_EDGE;
303 if (pol == INTR_POLARITY_CONFORM)
304 pol = INTR_POLARITY_HIGH;
305 vector = atpic_vector(isrc);
306 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
307 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
309 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
310 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
311 pol == INTR_POLARITY_HIGH ? "high" : "low");
315 /* If there is no change, just return. */
316 if (ai->at_trigger == trig)
320 * Certain IRQs can never be level/lo, so don't try to set them
321 * that way if asked. At least some ELCR registers ignore setting
322 * these bits as well.
324 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
325 trig == INTR_TRIGGER_LEVEL) {
328 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
334 printf("atpic: No ELCR to configure IRQ%u as %s\n",
335 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
340 printf("atpic: Programming IRQ%u as %s\n", vector,
341 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
343 elcr_write_trigger(atpic_vector(isrc), trig);
344 ai->at_trigger = trig;
350 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
354 * 8259A's are only used in UP in which case all interrupts always
355 * go to the sole CPU and this function shouldn't even be called.
357 panic("%s: bad cookie", __func__);
361 i8259_init(struct atpic *pic, int slave)
365 /* Reset the PIC and program with next four bytes. */
367 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
368 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
371 outb(imr_addr, pic->at_intbase);
374 * Setup slave links. For the master pic, indicate what line
375 * the slave is configured on. For the slave indicate
376 * which line on the master we are connected to.
379 outb(imr_addr, ICU_SLAVEID);
381 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
385 outb(imr_addr, SLAVE_MODE);
387 outb(imr_addr, MASTER_MODE);
389 /* Set interrupt enable mask. */
390 outb(imr_addr, *pic->at_imen);
392 /* Reset is finished, default to IRR on read. */
393 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
395 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
397 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
405 struct atpic_intsrc *ai;
408 /* Start off with all interrupts disabled. */
410 i8259_init(&atpics[MASTER], 0);
411 i8259_init(&atpics[SLAVE], 1);
412 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
414 /* Install low-level interrupt handlers for all of our IRQs. */
415 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
416 if (i == ICU_SLAVEID)
418 ai->at_intsrc.is_count = &ai->at_count;
419 ai->at_intsrc.is_straycount = &ai->at_straycount;
420 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
421 ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC,
422 SEL_KPL, GSEL_ATPIC);
426 * Look for an ELCR. If we find one, update the trigger modes.
427 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
428 * edge triggered and that everything else is level triggered.
429 * We only use the trigger information to reprogram the ELCR if
430 * we have one and as an optimization to avoid masking edge
431 * triggered interrupts. For the case that we don't have an ELCR,
432 * it doesn't hurt to mask an edge triggered interrupt, so we
433 * assume level trigger for any interrupt that we aren't sure is
437 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
438 ai->at_trigger = elcr_read_trigger(i);
440 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
447 ai->at_trigger = INTR_TRIGGER_EDGE;
450 ai->at_trigger = INTR_TRIGGER_LEVEL;
457 atpic_init(void *dummy __unused)
459 struct atpic_intsrc *ai;
463 * Register our PICs, even if we aren't going to use any of their
464 * pins so that they are suspended and resumed.
466 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
467 intr_register_pic(&atpics[1].at_pic) != 0)
468 panic("Unable to register ATPICs");
471 * If any of the ISA IRQs have an interrupt source already, then
472 * assume that the APICs are being used and don't register any
473 * of our interrupt sources. This makes sure we don't accidentally
474 * use mixed mode. The "accidental" use could otherwise occur on
475 * machines that route the ACPI SCI interrupt to a different ISA
476 * IRQ (at least one machines routes it to IRQ 13) thus disabling
477 * that APIC ISA routing and allowing the ATPIC source for that IRQ
478 * to leak through. We used to depend on this feature for routing
479 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
481 for (i = 0; i < NUM_ISA_IRQS; i++)
482 if (intr_lookup_source(i) != NULL)
485 /* Loop through all interrupt sources and add them. */
486 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
487 if (i == ICU_SLAVEID)
489 intr_register_source(&ai->at_intsrc);
492 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL);
495 atpic_handle_intr(u_int vector, struct trapframe *frame)
499 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
500 isrc = &atintrs[vector].at_intsrc;
503 * If we don't have an event, see if this is a spurious
506 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
510 * Read the ISR register to see if IRQ 7/15 is really
511 * pending. Reset read register back to IRR when done.
513 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
515 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
517 outb(port, OCW3_SEL | OCW3_RR);
519 if ((isr & IRQ_MASK(7)) == 0)
522 intr_execute_handlers(isrc, frame);
527 * Bus attachment for the ISA PIC.
529 static struct isa_pnp_id atpic_ids[] = {
530 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
535 atpic_probe(device_t dev)
539 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
546 * We might be granted IRQ 2, as this is typically consumed by chaining
547 * between the two PIC components. If we're using the APIC, however,
548 * this may not be the case, and as such we should free the resource.
551 * The generic ISA attachment code will handle allocating any other resources
552 * that we don't explicitly claim here.
555 atpic_attach(device_t dev)
557 struct resource *res;
560 /* Try to allocate our IRQ and then free it. */
562 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
564 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
569 * Return a bitmap of the current interrupt requests. This is 8259-specific
570 * and is only suitable for use at probe time.
573 isa_irq_pending(void)
580 return ((irr2 << 8) | irr1);
583 static device_method_t atpic_methods[] = {
584 /* Device interface */
585 DEVMETHOD(device_probe, atpic_probe),
586 DEVMETHOD(device_attach, atpic_attach),
587 DEVMETHOD(device_detach, bus_generic_detach),
588 DEVMETHOD(device_shutdown, bus_generic_shutdown),
589 DEVMETHOD(device_suspend, bus_generic_suspend),
590 DEVMETHOD(device_resume, bus_generic_resume),
594 static driver_t atpic_driver = {
600 static devclass_t atpic_devclass;
602 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
603 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
604 ISA_PNP_INFO(atpic_ids);