2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Routines to handle clock hardware.
43 #include "opt_clock.h"
47 #include <sys/param.h>
48 #include <sys/systm.h>
52 #include <sys/mutex.h>
54 #include <sys/kernel.h>
55 #include <sys/module.h>
57 #include <sys/sched.h>
59 #include <sys/sysctl.h>
60 #include <sys/timeet.h>
61 #include <sys/timetc.h>
63 #include <machine/clock.h>
64 #include <machine/cpu.h>
65 #include <machine/intr_machdep.h>
66 #include <machine/ppireg.h>
67 #include <machine/timerreg.h>
71 #include <pc98/pc98/pc98_machdep.h>
77 #include <pc98/cbus/cbus.h>
79 #include <isa/isareg.h>
81 #include <isa/isavar.h>
85 #include <i386/bios/mca_machdep.h>
91 #define TIMER_FREQ 2457600
93 #define TIMER_FREQ 1193182
96 u_int i8254_freq = TIMER_FREQ;
97 TUNABLE_INT("hw.i8254.freq", &i8254_freq);
99 static int i8254_timecounter = 1;
101 struct mtx clock_lock;
102 static struct intsrc *i8254_intsrc;
103 static uint16_t i8254_lastcount;
104 static uint16_t i8254_offset;
105 static int (*i8254_pending)(struct intsrc *);
106 static int i8254_ticked;
108 struct attimer_softc {
110 int port_rid, intr_rid;
111 struct resource *port_res;
112 struct resource *intr_res;
115 struct resource *port_res2;
118 struct timecounter tc;
119 struct eventtimer et;
122 #define MODE_PERIODIC 1
123 #define MODE_ONESHOT 2
126 static struct attimer_softc *attimer_sc = NULL;
128 static int timer0_period = -2;
129 static int timer0_mode = 0xffff;
130 static int timer0_last = 0xffff;
132 /* Values for timerX_state: */
134 #define RELEASE_PENDING 1
136 #define ACQUIRE_PENDING 3
138 static u_char timer2_state;
140 static unsigned i8254_get_timecount(struct timecounter *tc);
141 static void set_i8254_freq(int mode, uint32_t period);
146 /* Init the clock lock */
147 mtx_init(&clock_lock, "clk", NULL, MTX_SPIN | MTX_NOPROFILE);
148 /* Init the clock in order to use DELAY */
149 init_ops.early_clock_source_init();
155 struct attimer_softc *sc = (struct attimer_softc *)arg;
157 if (i8254_timecounter && sc->period != 0) {
158 mtx_lock_spin(&clock_lock);
162 i8254_offset += i8254_max_count;
166 mtx_unlock_spin(&clock_lock);
169 if (sc->et.et_active && sc->mode != MODE_STOP)
170 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
173 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
175 outb(0x61, inb(0x61) | 0x80);
177 return (FILTER_HANDLED);
181 timer_spkr_acquire(void)
186 mode = TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT;
188 mode = TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT;
191 if (timer2_state != RELEASED)
193 timer2_state = ACQUIRED;
196 * This access to the timer registers is as atomic as possible
197 * because it is a single instruction. We could do better if we
198 * knew the rate. Use of splclock() limits glitches to 10-100us,
199 * and this is probably good enough for timer2, so we aren't as
200 * careful with it as with timer0.
203 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f));
205 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
207 ppi_spkr_on(); /* enable counter2 output to speaker */
212 timer_spkr_release(void)
215 if (timer2_state != ACQUIRED)
217 timer2_state = RELEASED;
219 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT);
221 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
223 ppi_spkr_off(); /* disable counter2 output to speaker */
228 timer_spkr_setfreq(int freq)
231 freq = i8254_freq / freq;
232 mtx_lock_spin(&clock_lock);
234 outb(TIMER_CNTR1, freq & 0xff);
235 outb(TIMER_CNTR1, freq >> 8);
237 outb(TIMER_CNTR2, freq & 0xff);
238 outb(TIMER_CNTR2, freq >> 8);
240 mtx_unlock_spin(&clock_lock);
248 mtx_lock_spin(&clock_lock);
250 /* Select timer0 and latch counter value. */
251 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
253 low = inb(TIMER_CNTR0);
254 high = inb(TIMER_CNTR0);
256 mtx_unlock_spin(&clock_lock);
257 return ((high << 8) | low);
261 * Wait "n" microseconds.
262 * Relies on timer 1 counting down from (i8254_freq / hz)
263 * Note: timer had better have been programmed before this is first used!
268 int delta, prev_tick, tick, ticks_left;
272 static int state = 0;
276 for (n1 = 1; n1 <= 10000000; n1 *= 10)
281 printf("DELAY(%d)...", n);
284 * Read the counter first, so that the rest of the setup overhead is
285 * counted. Guess the initial overhead is 20 usec (on most systems it
286 * takes about 1.5 usec for each of the i/o's in getit(). The loop
287 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
288 * multiplications and divisions to scale the count take a while).
290 * However, if ddb is active then use a fake counter since reading
291 * the i8254 counter involves acquiring a lock. ddb must not do
292 * locking for many reasons, but it calls here for at least atkbd
301 n -= 0; /* XXX actually guess no initial overhead */
303 * Calculate (n * (i8254_freq / 1e6)) without using floating point
304 * and without any avoidable overflows.
310 * Use fixed point to avoid a slow division by 1000000.
311 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
312 * 2^15 is the first power of 2 that gives exact results
313 * for n between 0 and 256.
315 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
318 * Don't bother using fixed point, although gcc-2.7.2
319 * generates particularly poor code for the long long
320 * division, since even the slow way will complete long
321 * before the delay is up (unless we're interrupted).
323 ticks_left = ((u_int)n * (long long)i8254_freq + 999999)
326 while (ticks_left > 0) {
334 tick = prev_tick - 1;
336 tick = i8254_max_count;
343 delta = prev_tick - tick;
346 delta += i8254_max_count;
348 * Guard against i8254_max_count being wrong.
349 * This shouldn't happen in normal operation,
350 * but it may happen if set_i8254_freq() is
360 printf(" %d calls to getit() at %d usec each\n",
361 getit_calls, (n + 5) / getit_calls);
366 set_i8254_freq(int mode, uint32_t period)
368 int new_count, new_mode;
370 mtx_lock_spin(&clock_lock);
371 if (mode == MODE_STOP) {
372 if (i8254_timecounter) {
373 mode = MODE_PERIODIC;
378 new_count = min(((uint64_t)i8254_freq * period +
379 0x80000000LLU) >> 32, 0x10000);
381 if (new_count == timer0_period)
383 i8254_max_count = ((new_count & ~0xffff) != 0) ? 0xffff : new_count;
384 timer0_period = (mode == MODE_PERIODIC) ? new_count : -1;
387 new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT;
388 outb(TIMER_MODE, new_mode);
389 outb(TIMER_CNTR0, 0);
390 outb(TIMER_CNTR0, 0);
393 new_mode = TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT;
394 outb(TIMER_MODE, new_mode);
395 outb(TIMER_CNTR0, new_count & 0xff);
396 outb(TIMER_CNTR0, new_count >> 8);
399 if (new_count < 256 && timer0_last < 256) {
400 new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_LSB;
401 if (new_mode != timer0_mode)
402 outb(TIMER_MODE, new_mode);
403 outb(TIMER_CNTR0, new_count & 0xff);
406 new_mode = TIMER_SEL0 | TIMER_INTTC | TIMER_16BIT;
407 if (new_mode != timer0_mode)
408 outb(TIMER_MODE, new_mode);
409 outb(TIMER_CNTR0, new_count & 0xff);
410 outb(TIMER_CNTR0, new_count >> 8);
413 panic("set_i8254_freq: unknown operational mode");
415 timer0_mode = new_mode;
416 timer0_last = new_count;
418 mtx_unlock_spin(&clock_lock);
426 timer0_mode = 0xffff;
427 timer0_last = 0xffff;
428 if (attimer_sc != NULL)
429 set_i8254_freq(attimer_sc->mode, attimer_sc->period);
431 set_i8254_freq(MODE_STOP, 0);
436 * Restore all the timers non-atomically (XXX: should be atomically).
438 * This function is called from pmtimer_resume() to restore all the timers.
439 * This should not be necessary, but there are broken laptops that do not
440 * restore all the timers on resume. The APM spec was at best vague on the
442 * pmtimer is used only with the old APM power management, and not with
443 * acpi, which is required for amd64, so skip it in that case.
449 i8254_restore(); /* restore i8254_freq and hz */
451 atrtc_restore(); /* reenable RTC interrupts */
456 /* This is separate from startrtclock() so that it can be called early. */
462 if (pc98_machine_type & M_8M)
463 i8254_freq = 1996800L; /* 1.9968 MHz */
465 set_i8254_freq(MODE_STOP, 0);
478 #ifdef EARLY_AP_STARTUP
483 cpu_initclocks_bsp();
493 if (sched_is_bound(td))
497 cpu_initclocks_bsp();
502 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
508 * Use `i8254' instead of `timer' in external names because `timer'
509 * is too generic. Should use it everywhere.
512 error = sysctl_handle_int(oidp, &freq, 0, req);
513 if (error == 0 && req->newptr != NULL) {
515 if (attimer_sc != NULL) {
516 set_i8254_freq(attimer_sc->mode, attimer_sc->period);
517 attimer_sc->tc.tc_frequency = freq;
519 set_i8254_freq(MODE_STOP, 0);
525 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
526 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU",
527 "i8254 timer frequency");
530 i8254_get_timecount(struct timecounter *tc)
532 device_t dev = (device_t)tc->tc_priv;
533 struct attimer_softc *sc = device_get_softc(dev);
539 return (i8254_max_count - getit());
542 flags = read_rflags();
544 flags = read_eflags();
546 mtx_lock_spin(&clock_lock);
548 /* Select timer0 and latch counter value. */
549 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
551 low = inb(TIMER_CNTR0);
552 high = inb(TIMER_CNTR0);
553 count = i8254_max_count - ((high << 8) | low);
554 if (count < i8254_lastcount ||
555 (!i8254_ticked && (clkintr_pending ||
556 ((count < 20 || (!(flags & PSL_I) &&
557 count < i8254_max_count / 2u)) &&
558 i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
560 i8254_offset += i8254_max_count;
562 i8254_lastcount = count;
563 count += i8254_offset;
564 mtx_unlock_spin(&clock_lock);
569 attimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
571 device_t dev = (device_t)et->et_priv;
572 struct attimer_softc *sc = device_get_softc(dev);
575 sc->mode = MODE_PERIODIC;
578 sc->mode = MODE_ONESHOT;
582 i8254_intsrc->is_pic->pic_enable_source(i8254_intsrc);
585 set_i8254_freq(sc->mode, sc->period);
590 attimer_stop(struct eventtimer *et)
592 device_t dev = (device_t)et->et_priv;
593 struct attimer_softc *sc = device_get_softc(dev);
595 sc->mode = MODE_STOP;
597 set_i8254_freq(sc->mode, sc->period);
603 * Attach to the ISA PnP descriptors for the timer
605 static struct isa_pnp_id attimer_ids[] = {
606 { 0x0001d041 /* PNP0100 */, "AT timer" },
612 pc98_alloc_resource(device_t dev)
614 static bus_addr_t iat1[] = {0, 2, 4, 6};
615 static bus_addr_t iat2[] = {0, 4};
616 struct attimer_softc *sc;
618 sc = device_get_softc(dev);
621 bus_set_resource(dev, SYS_RES_IOPORT, sc->port_rid, IO_TIMER1, 1);
622 sc->port_res = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
623 &sc->port_rid, iat1, 4, RF_ACTIVE);
624 if (sc->port_res == NULL)
625 device_printf(dev, "Warning: Couldn't map I/O.\n");
627 isa_load_resourcev(sc->port_res, iat1, 4);
630 bus_set_resource(dev, SYS_RES_IOPORT, sc->port_rid2, TIMER_CNTR1, 1);
631 sc->port_res2 = isa_alloc_resourcev(dev, SYS_RES_IOPORT,
632 &sc->port_rid2, iat2, 2, RF_ACTIVE);
633 if (sc->port_res2 == NULL)
634 device_printf(dev, "Warning: Couldn't map I/O.\n");
636 isa_load_resourcev(sc->port_res2, iat2, 2);
640 pc98_release_resource(device_t dev)
642 struct attimer_softc *sc;
644 sc = device_get_softc(dev);
647 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
650 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid2,
656 attimer_probe(device_t dev)
660 result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids);
661 /* ENOENT means no PnP-ID, device is hinted. */
662 if (result == ENOENT) {
663 device_set_desc(dev, "AT timer");
665 /* To print resources correctly. */
666 pc98_alloc_resource(dev);
667 pc98_release_resource(dev);
669 return (BUS_PROBE_LOW_PRIORITY);
675 attimer_attach(device_t dev)
677 struct attimer_softc *sc;
681 attimer_sc = sc = device_get_softc(dev);
682 bzero(sc, sizeof(struct attimer_softc));
684 pc98_alloc_resource(dev);
686 if (!(sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
687 &sc->port_rid, IO_TIMER1, IO_TIMER1 + 3, 4, RF_ACTIVE)))
688 device_printf(dev,"Warning: Couldn't map I/O.\n");
690 i8254_intsrc = intr_lookup_source(0);
691 if (i8254_intsrc != NULL)
692 i8254_pending = i8254_intsrc->is_pic->pic_source_pending;
693 resource_int_value(device_get_name(dev), device_get_unit(dev),
694 "timecounter", &i8254_timecounter);
695 set_i8254_freq(MODE_STOP, 0);
696 if (i8254_timecounter) {
697 sc->tc.tc_get_timecount = i8254_get_timecount;
698 sc->tc.tc_counter_mask = 0xffff;
699 sc->tc.tc_frequency = i8254_freq;
700 sc->tc.tc_name = "i8254";
701 sc->tc.tc_quality = 0;
702 sc->tc.tc_priv = dev;
705 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
706 "clock", &i) != 0 || i != 0) {
708 while (bus_get_resource(dev, SYS_RES_IRQ, sc->intr_rid,
709 &s, NULL) == 0 && s != 0)
711 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
712 &sc->intr_rid, 0, 0, 1, RF_ACTIVE))) {
713 device_printf(dev,"Can't map interrupt.\n");
716 /* Dirty hack, to make bus_setup_intr to not enable source. */
717 i8254_intsrc->is_handlers++;
718 if ((bus_setup_intr(dev, sc->intr_res,
719 INTR_MPSAFE | INTR_TYPE_CLK,
720 (driver_filter_t *)clkintr, NULL,
721 sc, &sc->intr_handler))) {
722 device_printf(dev, "Can't setup interrupt.\n");
723 i8254_intsrc->is_handlers--;
726 i8254_intsrc->is_handlers--;
727 i8254_intsrc->is_pic->pic_enable_intr(i8254_intsrc);
728 sc->et.et_name = "i8254";
729 sc->et.et_flags = ET_FLAGS_PERIODIC;
730 if (!i8254_timecounter)
731 sc->et.et_flags |= ET_FLAGS_ONESHOT;
732 sc->et.et_quality = 100;
733 sc->et.et_frequency = i8254_freq;
734 sc->et.et_min_period = (0x0002LLU << 32) / i8254_freq;
735 sc->et.et_max_period = (0xfffeLLU << 32) / i8254_freq;
736 sc->et.et_start = attimer_start;
737 sc->et.et_stop = attimer_stop;
738 sc->et.et_priv = dev;
739 et_register(&sc->et);
745 attimer_resume(device_t dev)
752 static device_method_t attimer_methods[] = {
753 /* Device interface */
754 DEVMETHOD(device_probe, attimer_probe),
755 DEVMETHOD(device_attach, attimer_attach),
756 DEVMETHOD(device_detach, bus_generic_detach),
757 DEVMETHOD(device_shutdown, bus_generic_shutdown),
758 DEVMETHOD(device_suspend, bus_generic_suspend),
759 DEVMETHOD(device_resume, attimer_resume),
763 static driver_t attimer_driver = {
766 sizeof(struct attimer_softc),
769 static devclass_t attimer_devclass;
771 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
772 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);