2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * The ELCR is a register that controls the trigger mode and polarity of
33 * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only
34 * consulted for determining the appropriate trigger mode of EISA
35 * interrupts when using an APIC. However, it seems that almost all
36 * systems that include PCI also include an ELCR that manages the ISA
37 * IRQs 0 through 15. Thus, we check for the presence of an ELCR on
38 * every machine by checking to see if the values found at bootup are
39 * sane. Note that the polarity of ISA and EISA IRQs are linked to the
40 * trigger mode. All edge triggered IRQs use active-hi polarity, and
41 * all level triggered interrupts use active-lo polarity.
43 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
44 * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the
45 * associated IRQ is edge triggered. If the bit is one, the IRQ is
49 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <machine/intr_machdep.h>
54 #define ELCR_PORT 0x4d0
55 #define ELCR_MASK(irq) (1 << (irq))
57 static int elcr_status;
61 * Check to see if we have what looks like a valid ELCR. We do this by
62 * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
69 elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8;
70 if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) |
71 ELCR_MASK(8) | ELCR_MASK(13))) != 0)
74 printf("ELCR Found. ISA IRQs programmed as:\n");
75 for (i = 0; i < 16; i++)
78 for (i = 0; i < 16; i++)
79 if (elcr_status & ELCR_MASK(i))
85 if (resource_disabled("elcr", 0))
92 * Returns 1 for level trigger, 0 for edge.
95 elcr_read_trigger(u_int irq)
98 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
99 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
100 if (elcr_status & ELCR_MASK(irq))
101 return (INTR_TRIGGER_LEVEL);
103 return (INTR_TRIGGER_EDGE);
107 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
108 * and a mode of 1 means level triggered.
111 elcr_write_trigger(u_int irq, enum intr_trigger trigger)
115 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
116 KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq));
117 if (trigger == INTR_TRIGGER_LEVEL)
118 new_status = elcr_status | ELCR_MASK(irq);
120 new_status = elcr_status & ~ELCR_MASK(irq);
121 if (new_status == elcr_status)
123 elcr_status = new_status;
125 outb(ELCR_PORT + 1, elcr_status >> 8);
127 outb(ELCR_PORT, elcr_status & 0xff);
134 KASSERT(elcr_found, ("%s: no ELCR was found!", __func__));
135 outb(ELCR_PORT, elcr_status & 0xff);
136 outb(ELCR_PORT + 1, elcr_status >> 8);