2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/sysctl.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcib_private.h>
46 #include <isa/isavar.h>
48 #include <machine/md_var.h>
50 #include <x86/legacyvar.h>
51 #include <machine/pci_cfgreg.h>
52 #include <machine/resource.h>
57 legacy_pcib_maxslots(device_t dev)
62 /* read configuration space register */
65 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
68 return(pci_cfgregread(bus, slot, func, reg, bytes));
71 /* write configuration space register */
74 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
75 u_int reg, uint32_t data, int bytes)
77 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
83 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
87 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
88 pci_get_function(dev), pin));
90 /* No routing possible */
91 return (PCI_INVALID_IRQ);
95 /* Pass MSI requests up to the nexus. */
98 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
103 bus = device_get_parent(pcib);
104 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
109 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
113 bus = device_get_parent(pcib);
114 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
118 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
122 int error, func, slot;
124 bus = device_get_parent(pcib);
125 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
129 slot = legacy_get_pcislot(pcib);
130 func = legacy_get_pcifunc(pcib);
131 if (slot == -1 || func == -1)
133 hostb = pci_find_bsf(0, slot, func);
134 KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
136 pci_ht_map_msi(hostb, *addr);
141 legacy_pcib_is_host_bridge(int bus, int slot, int func,
142 uint32_t id, uint8_t class, uint8_t subclass,
146 const char *s = NULL;
147 static uint8_t pxb[4]; /* hack for 450nx */
153 s = "Intel 824?? host to PCI bridge";
154 /* XXX This is a guess */
155 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
159 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
162 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
165 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
168 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
171 s = "Intel 82443LX (440 LX) host to PCI bridge";
174 s = "Intel 82443BX (440 BX) host to PCI bridge";
177 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
180 s = "Intel 82443MX host to PCI bridge";
183 s = "Intel 82443GX host to PCI bridge";
186 s = "Intel 82443GX host to AGP bridge";
189 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
192 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
193 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
197 * For the 450nx chipset, there is a whole bundle of
198 * things pretending to be host bridges. The MIOC will
199 * be seen first and isn't really a pci bridge (the
200 * actual buses are attached to the PXB's). We need to
201 * read the registers of the MIOC to figure out the
202 * bus numbers for the PXB channels.
204 * Since the MIOC doesn't have a pci bus attached, we
205 * pretend it wasn't there.
207 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
208 0xd0, 1); /* BUSNO[0] */
209 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
210 0xd1, 1) + 1; /* SUBA[0]+1 */
211 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
212 0xd3, 1); /* BUSNO[1] */
213 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
214 0xd4, 1) + 1; /* SUBA[1]+1 */
219 s = "Intel 82454NX PXB#0, Bus#A";
223 s = "Intel 82454NX PXB#0, Bus#B";
227 s = "Intel 82454NX PXB#1, Bus#A";
231 s = "Intel 82454NX PXB#1, Bus#B";
237 s = "Intel 82845 Host to PCI bridge";
240 /* AMD -- vendor 0x1022 */
242 s = "AMD Elan SC520 host to PCI bridge";
244 init_AMD_Elan_sc520();
247 "*** WARNING: missing CPU_ELAN -- timekeeping may be wrong\n");
251 s = "AMD-751 host to PCI bridge";
254 s = "AMD-761 host to PCI bridge";
257 /* SiS -- vendor 0x1039 */
268 s = "SiS 5591 host to PCI bridge";
271 s = "SiS 5591 host to AGP bridge";
274 /* VLSI -- vendor 0x1004 */
276 s = "VLSI 82C592 Host to PCI bridge";
279 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
280 /* totally. Please let me know if anything wrong. -F */
281 /* XXX need info on the MVP3 -- any takers? */
283 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
286 /* AcerLabs -- vendor 0x10b9 */
287 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
288 /* id is '10b9" but the register always shows "10b9". -Foxfair */
290 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
293 /* OPTi -- vendor 0x1045 */
295 s = "OPTi 82C700 host to PCI bridge";
298 s = "OPTi 82C822 host to PCI Bridge";
301 /* ServerWorks -- vendor 0x1166 */
303 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
304 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
313 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
314 s = "ServerWorks host to PCI bridge";
315 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
319 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
320 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
324 s = "ServerWorks CIOB30 host to PCI bridge";
325 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
330 case 0x03021014: /* IBM re-badged ServerWorks chipset */
331 s = "ServerWorks CMIC-HE host to PCI-X bridge";
332 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
335 /* XXX unknown chipset, but working */
341 s = "ServerWorks host to PCI bridge(unknown chipset)";
342 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
345 /* Compaq/HP -- vendor 0x0e11 */
347 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
348 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
351 /* Integrated Micro Solutions -- vendor 0x10e0 */
353 s = "Integrated Micro Solutions VL Bridge";
357 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
358 s = "Host to PCI bridge";
364 const char *s = NULL;
367 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
368 s = "Host to PCI bridge";
374 * Scan the first pci bus for host-pci bridges and add pcib instances
375 * to the nexus for each bridge.
378 legacy_pcib_identify(driver_t *driver, device_t parent)
387 devclass_t pci_devclass;
389 if (pci_cfgregopen() == 0)
392 * Check to see if we haven't already had a PCI bus added
393 * via some other means. If we have, bail since otherwise
394 * we're going to end up duplicating it.
396 if ((pci_devclass = devclass_find("pci")) &&
397 devclass_get_device(pci_devclass, 0))
403 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
405 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
408 * When enumerating bus devices, the standard says that
409 * one should check the header type and ignore the slots whose
410 * header types that the software doesn't know about. We use
411 * this to filter out devices.
413 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
415 if ((hdrtype & PCIM_MFDEV) &&
416 (!found_orion || hdrtype != 0xff))
417 pcifunchigh = PCI_FUNCMAX;
420 for (func = 0; func <= pcifunchigh; func++) {
422 * Read the IDs and class from the device.
425 uint8_t class, subclass, busnum;
430 id = legacy_pcib_read_config(0, bus, slot, func,
434 class = legacy_pcib_read_config(0, bus, slot, func,
436 subclass = legacy_pcib_read_config(0, bus, slot, func,
439 s = legacy_pcib_is_host_bridge(bus, slot, func,
446 * Check to see if the physical bus has already
447 * been seen. Eg: hybrid 32 and 64 bit host
448 * bridges to the same logical bus.
450 if (device_get_children(parent, &devs, &ndevs) == 0) {
451 for (i = 0; s != NULL && i < ndevs; i++) {
452 if (strcmp(device_get_name(devs[i]),
455 if (legacy_get_pcibus(devs[i]) == busnum)
464 * Add at priority 100 to make sure we
465 * go after any motherboard resources
467 child = BUS_ADD_CHILD(parent, 100,
469 device_set_desc(child, s);
470 legacy_set_pcibus(child, busnum);
471 legacy_set_pcislot(child, slot);
472 legacy_set_pcifunc(child, func);
475 if (id == 0x12258086)
477 if (id == 0x84c48086)
481 if (found824xx && bus == 0) {
487 * Make sure we add at least one bridge since some old
488 * hardware doesn't actually have a host-pci bridge device.
489 * Note that pci_cfgregopen() thinks we have PCI devices..
494 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
495 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
496 legacy_set_pcibus(child, 0);
501 legacy_pcib_probe(device_t dev)
504 if (pci_cfgregopen() == 0)
510 legacy_pcib_attach(device_t dev)
517 bus = pcib_get_bus(dev);
520 * Look for a PCI BIOS interrupt routing table as that will be
521 * our method of routing interrupts if we have one.
523 if (pci_pir_probe(bus, 0)) {
524 pir = BUS_ADD_CHILD(device_get_parent(dev), 0, "pir", 0);
526 device_probe_and_attach(pir);
529 device_add_child(dev, "pci", -1);
530 return bus_generic_attach(dev);
534 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
539 case PCIB_IVAR_DOMAIN:
543 *result = legacy_get_pcibus(dev);
550 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
555 case PCIB_IVAR_DOMAIN:
558 legacy_set_pcibus(dev, value);
565 * Helper routine for x86 Host-PCI bridge driver resource allocation.
566 * This is used to adjust the start address of wildcard allocation
567 * requests to avoid low addresses that are known to be problematic.
569 * If no memory preference is given, use upper 32MB slot most BIOSes
570 * use for their memory window. This is typically only used on older
571 * laptops that don't have PCI buses behind a PCI bridge, so assuming
572 * > 32MB is likely OK.
574 * However, this can cause problems for other chipsets, so we make
575 * this tunable by hw.pci.host_mem_start.
577 SYSCTL_DECL(_hw_pci);
579 static unsigned long host_mem_start = 0x80000000;
580 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
581 0, "Limit the host bridge memory to being above this address.");
584 hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count)
587 if (start + count - 1 != end) {
588 if (type == SYS_RES_MEMORY && start < host_mem_start)
589 start = host_mem_start;
590 if (type == SYS_RES_IOPORT && start < 0x1000)
597 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
598 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
601 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
602 if (type == PCI_RES_BUS)
603 return (pci_domain_alloc_bus(0, child, rid, start, end, count,
606 start = hostb_alloc_start(type, start, end, count);
607 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
611 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
613 legacy_pcib_adjust_resource(device_t dev, device_t child, int type,
614 struct resource *r, rman_res_t start, rman_res_t end)
617 if (type == PCI_RES_BUS)
618 return (pci_domain_adjust_bus(0, child, r, start, end));
619 return (bus_generic_adjust_resource(dev, child, type, r, start, end));
623 legacy_pcib_release_resource(device_t dev, device_t child, int type, int rid,
627 if (type == PCI_RES_BUS)
628 return (pci_domain_release_bus(0, child, rid, r));
629 return (bus_generic_release_resource(dev, child, type, rid, r));
633 static device_method_t legacy_pcib_methods[] = {
634 /* Device interface */
635 DEVMETHOD(device_identify, legacy_pcib_identify),
636 DEVMETHOD(device_probe, legacy_pcib_probe),
637 DEVMETHOD(device_attach, legacy_pcib_attach),
638 DEVMETHOD(device_shutdown, bus_generic_shutdown),
639 DEVMETHOD(device_suspend, bus_generic_suspend),
640 DEVMETHOD(device_resume, bus_generic_resume),
643 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
644 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
645 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
646 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
647 DEVMETHOD(bus_adjust_resource, legacy_pcib_adjust_resource),
648 DEVMETHOD(bus_release_resource, legacy_pcib_release_resource),
650 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
651 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
653 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
654 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
655 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
656 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
659 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
660 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
661 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
662 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
663 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
664 DEVMETHOD(pcib_release_msi, pcib_release_msi),
665 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
666 DEVMETHOD(pcib_release_msix, pcib_release_msix),
667 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
668 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
673 static devclass_t hostb_devclass;
675 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
676 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
680 * Install placeholder to claim the resources owned by the
681 * PCI bus interface. This could be used to extract the
682 * config space registers in the extreme case where the PnP
683 * ID is available and the PCI BIOS isn't, but for now we just
684 * eat the PnP ID and do nothing else.
686 * we silence this probe, as it will generally confuse people.
688 static struct isa_pnp_id pcibus_pnp_ids[] = {
689 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
690 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
695 pcibus_pnp_probe(device_t dev)
699 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
705 pcibus_pnp_attach(device_t dev)
710 static device_method_t pcibus_pnp_methods[] = {
711 /* Device interface */
712 DEVMETHOD(device_probe, pcibus_pnp_probe),
713 DEVMETHOD(device_attach, pcibus_pnp_attach),
714 DEVMETHOD(device_detach, bus_generic_detach),
715 DEVMETHOD(device_shutdown, bus_generic_shutdown),
716 DEVMETHOD(device_suspend, bus_generic_suspend),
717 DEVMETHOD(device_resume, bus_generic_resume),
721 static devclass_t pcibus_pnp_devclass;
723 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
724 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);
728 * Provide a PCI-PCI bridge driver for PCI buses behind PCI-PCI bridges
729 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
730 * table for interrupt routing when possible.
732 static int pcibios_pcib_probe(device_t bus);
734 static device_method_t pcibios_pcib_pci_methods[] = {
735 /* Device interface */
736 DEVMETHOD(device_probe, pcibios_pcib_probe),
739 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
744 static devclass_t pcib_devclass;
746 DEFINE_CLASS_1(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
747 sizeof(struct pcib_softc), pcib_driver);
748 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, 0, 0);
749 ISA_PNP_INFO(pcibus_pnp_ids);
752 pcibios_pcib_probe(device_t dev)
756 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
757 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
759 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
762 if (!pci_pir_probe(bus, 1))
764 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");