sys/x86/pci/pci_early_quirks.h

   1 /*-
   2  * Copyright (c) 2018 Johannes Lundberg
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef _PCI_EARLY_QUIRKS_H_
  29 #define _PCI_EARLY_QUIRKS_H_
  30
  31 /*
  32  * TODO:
  33  * Make a common drm/gpu header that both base and out of tree
  34  * drm modules can use.
  35  */
  36
  37 #define PCI_ANY_ID              (-1)
  38 #define PCI_VENDOR_INTEL        0x8086
  39 #define PCI_CLASS_VGA           0x0300
  40
  41 #define INTEL_BSM               0x5c
  42 #define INTEL_BSM_MASK          (-(1u << 20))
  43
  44 #define INTEL_GMCH_CTRL         0x52
  45 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
  46 #define SNB_GMCH_CTRL           0x50
  47 #define SNB_GMCH_GGMS_SHIFT     8 /* GTT Graphics Memory Size */
  48 #define SNB_GMCH_GGMS_MASK      0x3
  49 #define SNB_GMCH_GMS_SHIFT      3 /* Graphics Mode Select */
  50 #define SNB_GMCH_GMS_MASK       0x1f
  51 #define BDW_GMCH_GGMS_SHIFT     6
  52 #define BDW_GMCH_GGMS_MASK      0x3
  53 #define BDW_GMCH_GMS_SHIFT      8
  54 #define BDW_GMCH_GMS_MASK       0xff
  55
  56 #define I830_GMCH_CTRL                  0x52
  57 #define I830_GMCH_GMS_MASK              0x70
  58 #define I830_GMCH_GMS_LOCAL             0x10
  59 #define I830_GMCH_GMS_STOLEN_512        0x20
  60 #define I830_GMCH_GMS_STOLEN_1024       0x30
  61 #define I830_GMCH_GMS_STOLEN_8192       0x40
  62
  63 #define I855_GMCH_GMS_MASK              0xF0
  64 #define I855_GMCH_GMS_STOLEN_0M         0x0
  65 #define I855_GMCH_GMS_STOLEN_1M         (0x1 << 4)
  66 #define I855_GMCH_GMS_STOLEN_4M         (0x2 << 4)
  67 #define I855_GMCH_GMS_STOLEN_8M         (0x3 << 4)
  68 #define I855_GMCH_GMS_STOLEN_16M        (0x4 << 4)
  69 #define I855_GMCH_GMS_STOLEN_32M        (0x5 << 4)
  70 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  71 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  72 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
  73 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
  74 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
  75 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
  76 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
  77 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
  78
  79 #define INTEL_VGA_DEVICE(id, info) {            \
  80         0x8086, id,                             \
  81         info }
  82
  83 #define INTEL_I810_IDS(info)                                    \
  84         INTEL_VGA_DEVICE(0x7121, info), /* I810 */              \
  85         INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */        \
  86         INTEL_VGA_DEVICE(0x7125, info)  /* I810_E */
  87
  88 #define INTEL_I815_IDS(info)                                    \
  89         INTEL_VGA_DEVICE(0x1132, info)  /* I815*/
  90
  91 #define INTEL_I830_IDS(info)                            \
  92         INTEL_VGA_DEVICE(0x3577, info)
  93
  94 #define INTEL_I845G_IDS(info)                           \
  95         INTEL_VGA_DEVICE(0x2562, info)
  96
  97 #define INTEL_I85X_IDS(info)                            \
  98         INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
  99         INTEL_VGA_DEVICE(0x358e, info)
 100
 101 #define INTEL_I865G_IDS(info)                           \
 102         INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
 103
 104 #define INTEL_I915G_IDS(info)                           \
 105         INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
 106         INTEL_VGA_DEVICE(0x258a, info)  /* E7221_G */
 107
 108 #define INTEL_I915GM_IDS(info)                          \
 109         INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
 110
 111 #define INTEL_I945G_IDS(info)                           \
 112         INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
 113
 114 #define INTEL_I945GM_IDS(info)                          \
 115         INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
 116         INTEL_VGA_DEVICE(0x27ae, info)  /* I945_GME */
 117
 118 #define INTEL_I965G_IDS(info)                           \
 119         INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */   \
 120         INTEL_VGA_DEVICE(0x2982, info), /* G35_G */     \
 121         INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */    \
 122         INTEL_VGA_DEVICE(0x29a2, info)  /* I965_G */
 123
 124 #define INTEL_G33_IDS(info)                             \
 125         INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
 126         INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
 127         INTEL_VGA_DEVICE(0x29d2, info)  /* Q33_G */
 128
 129 #define INTEL_I965GM_IDS(info)                          \
 130         INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
 131         INTEL_VGA_DEVICE(0x2a12, info)  /* I965_GME */
 132
 133 #define INTEL_GM45_IDS(info)                            \
 134         INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
 135
 136 #define INTEL_G45_IDS(info)                             \
 137         INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
 138         INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
 139         INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
 140         INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
 141         INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
 142         INTEL_VGA_DEVICE(0x2e92, info)  /* B43_G.1 */
 143
 144 #define INTEL_PINEVIEW_IDS(info)                        \
 145         INTEL_VGA_DEVICE(0xa001, info),                 \
 146         INTEL_VGA_DEVICE(0xa011, info)
 147
 148 #define INTEL_IRONLAKE_D_IDS(info) \
 149         INTEL_VGA_DEVICE(0x0042, info)
 150
 151 #define INTEL_IRONLAKE_M_IDS(info) \
 152         INTEL_VGA_DEVICE(0x0046, info)
 153
 154 #define INTEL_SNB_D_GT1_IDS(info) \
 155         INTEL_VGA_DEVICE(0x0102, info), \
 156         INTEL_VGA_DEVICE(0x010A, info)
 157
 158 #define INTEL_SNB_D_GT2_IDS(info) \
 159         INTEL_VGA_DEVICE(0x0112, info), \
 160         INTEL_VGA_DEVICE(0x0122, info)
 161
 162 #define INTEL_SNB_D_IDS(info) \
 163         INTEL_SNB_D_GT1_IDS(info), \
 164         INTEL_SNB_D_GT2_IDS(info)
 165
 166 #define INTEL_SNB_M_GT1_IDS(info) \
 167         INTEL_VGA_DEVICE(0x0106, info)
 168
 169 #define INTEL_SNB_M_GT2_IDS(info) \
 170         INTEL_VGA_DEVICE(0x0116, info), \
 171         INTEL_VGA_DEVICE(0x0126, info)
 172
 173 #define INTEL_SNB_M_IDS(info) \
 174         INTEL_SNB_M_GT1_IDS(info), \
 175         INTEL_SNB_M_GT2_IDS(info)
 176
 177 #define INTEL_IVB_M_GT1_IDS(info) \
 178         INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
 179
 180 #define INTEL_IVB_M_GT2_IDS(info) \
 181         INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
 182
 183 #define INTEL_IVB_M_IDS(info) \
 184         INTEL_IVB_M_GT1_IDS(info), \
 185         INTEL_IVB_M_GT2_IDS(info)
 186
 187 #define INTEL_IVB_D_GT1_IDS(info) \
 188         INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
 189         INTEL_VGA_DEVICE(0x015a, info)  /* GT1 server */
 190
 191 #define INTEL_IVB_D_GT2_IDS(info) \
 192         INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
 193         INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
 194
 195 #define INTEL_IVB_D_IDS(info) \
 196         INTEL_IVB_D_GT1_IDS(info), \
 197         INTEL_IVB_D_GT2_IDS(info)
 198
 199 #define INTEL_IVB_Q_IDS(info) \
 200         INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 201
 202 #define INTEL_HSW_GT1_IDS(info) \
 203         INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 204         INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
 205         INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
 206         INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
 207         INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
 208         INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 209         INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 210         INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
 211         INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
 212         INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
 213         INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
 214         INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
 215         INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 216         INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
 217         INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 218         INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 219         INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
 220         INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 221         INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
 222         INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
 223
 224 #define INTEL_HSW_GT2_IDS(info) \
 225         INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 226         INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
 227         INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
 228         INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
 229         INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
 230         INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 231         INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 232         INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
 233         INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
 234         INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
 235         INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
 236         INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
 237         INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 238         INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
 239         INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
 240         INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 241         INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
 242         INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
 243         INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
 244         INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
 245         INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
 246
 247 #define INTEL_HSW_GT3_IDS(info) \
 248         INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
 249         INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
 250         INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
 251         INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
 252         INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
 253         INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 254         INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 255         INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
 256         INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
 257         INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
 258         INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
 259         INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
 260         INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 261         INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 262         INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
 263         INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
 264         INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 265         INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
 266         INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 267
 268 #define INTEL_HSW_IDS(info) \
 269         INTEL_HSW_GT1_IDS(info), \
 270         INTEL_HSW_GT2_IDS(info), \
 271         INTEL_HSW_GT3_IDS(info)
 272
 273 #define INTEL_VLV_IDS(info) \
 274         INTEL_VGA_DEVICE(0x0f30, info), \
 275         INTEL_VGA_DEVICE(0x0f31, info), \
 276         INTEL_VGA_DEVICE(0x0f32, info), \
 277         INTEL_VGA_DEVICE(0x0f33, info), \
 278         INTEL_VGA_DEVICE(0x0157, info), \
 279         INTEL_VGA_DEVICE(0x0155, info)
 280
 281 #define INTEL_BDW_GT1_IDS(info)  \
 282         INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 283         INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
 284         INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
 285         INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
 286         INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 287         INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
 288
 289 #define INTEL_BDW_GT2_IDS(info)  \
 290         INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */  \
 291         INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
 292         INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
 293         INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
 294         INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 295         INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 296
 297 #define INTEL_BDW_GT3_IDS(info) \
 298         INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
 299         INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
 300         INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
 301         INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 302         INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 303         INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 304
 305 #define INTEL_BDW_RSVD_IDS(info) \
 306         INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
 307         INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
 308         INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
 309         INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
 310         INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 311         INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 312
 313 #define INTEL_BDW_IDS(info) \
 314         INTEL_BDW_GT1_IDS(info), \
 315         INTEL_BDW_GT2_IDS(info), \
 316         INTEL_BDW_GT3_IDS(info), \
 317         INTEL_BDW_RSVD_IDS(info)
 318
 319 #define INTEL_CHV_IDS(info) \
 320         INTEL_VGA_DEVICE(0x22b0, info), \
 321         INTEL_VGA_DEVICE(0x22b1, info), \
 322         INTEL_VGA_DEVICE(0x22b2, info), \
 323         INTEL_VGA_DEVICE(0x22b3, info)
 324
 325 #define INTEL_SKL_GT1_IDS(info) \
 326         INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
 327         INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
 328         INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
 329         INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
 330         INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
 331
 332 #define INTEL_SKL_GT2_IDS(info) \
 333         INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
 334         INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
 335         INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
 336         INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 337         INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 338         INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 339         INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 340
 341 #define INTEL_SKL_GT3_IDS(info) \
 342         INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
 343         INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
 344         INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
 345         INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
 346         INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
 347
 348 #define INTEL_SKL_GT4_IDS(info) \
 349         INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
 350         INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
 351         INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
 352         INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
 353         INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
 354
 355 #define INTEL_SKL_IDS(info)      \
 356         INTEL_SKL_GT1_IDS(info), \
 357         INTEL_SKL_GT2_IDS(info), \
 358         INTEL_SKL_GT3_IDS(info), \
 359         INTEL_SKL_GT4_IDS(info)
 360
 361 #define INTEL_BXT_IDS(info) \
 362         INTEL_VGA_DEVICE(0x0A84, info), \
 363         INTEL_VGA_DEVICE(0x1A84, info), \
 364         INTEL_VGA_DEVICE(0x1A85, info), \
 365         INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
 366         INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
 367
 368 #define INTEL_GLK_IDS(info) \
 369         INTEL_VGA_DEVICE(0x3184, info), \
 370         INTEL_VGA_DEVICE(0x3185, info)
 371
 372 #define INTEL_KBL_GT1_IDS(info) \
 373         INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
 374         INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
 375         INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
 376         INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
 377         INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 378         INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 379         INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 380         INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
 381
 382 #define INTEL_KBL_GT2_IDS(info) \
 383         INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
 384         INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 385         INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
 386         INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
 387         INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 388         INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 389         INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 390         INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 391
 392 #define INTEL_KBL_GT3_IDS(info) \
 393         INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
 394         INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
 395         INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
 396
 397 #define INTEL_KBL_GT4_IDS(info) \
 398         INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
 399
 400 #define INTEL_KBL_IDS(info) \
 401         INTEL_KBL_GT1_IDS(info), \
 402         INTEL_KBL_GT2_IDS(info), \
 403         INTEL_KBL_GT3_IDS(info), \
 404         INTEL_KBL_GT4_IDS(info)
 405
 406 /* CFL S */
 407 #define INTEL_CFL_S_GT1_IDS(info) \
 408         INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
 409         INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
 410         INTEL_VGA_DEVICE(0x3E99, info)  /* SRV GT1 */
 411
 412 #define INTEL_CFL_S_GT2_IDS(info) \
 413         INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
 414         INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
 415         INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
 416         INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */
 417
 418 /* CFL H */
 419 #define INTEL_CFL_H_GT2_IDS(info) \
 420         INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
 421         INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
 422
 423 /* CFL U GT1 */
 424 #define INTEL_CFL_U_GT1_IDS(info) \
 425         INTEL_VGA_DEVICE(0x3EA1, info), \
 426         INTEL_VGA_DEVICE(0x3EA4, info)
 427
 428 /* CFL U GT2 */
 429 #define INTEL_CFL_U_GT2_IDS(info) \
 430         INTEL_VGA_DEVICE(0x3EA0, info), \
 431         INTEL_VGA_DEVICE(0x3EA3, info), \
 432         INTEL_VGA_DEVICE(0x3EA9, info)
 433
 434 /* CFL U GT3 */
 435 #define INTEL_CFL_U_GT3_IDS(info) \
 436         INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \
 437         INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
 438         INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
 439         INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
 440         INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */
 441
 442 #define INTEL_CFL_IDS(info)        \
 443         INTEL_CFL_S_GT1_IDS(info), \
 444         INTEL_CFL_S_GT2_IDS(info), \
 445         INTEL_CFL_H_GT2_IDS(info), \
 446         INTEL_CFL_U_GT1_IDS(info), \
 447         INTEL_CFL_U_GT2_IDS(info), \
 448         INTEL_CFL_U_GT3_IDS(info)
 449
 450 /* CNL */
 451 #define INTEL_CNL_IDS(info) \
 452         INTEL_VGA_DEVICE(0x5A51, info), \
 453         INTEL_VGA_DEVICE(0x5A59, info), \
 454         INTEL_VGA_DEVICE(0x5A41, info), \
 455         INTEL_VGA_DEVICE(0x5A49, info), \
 456         INTEL_VGA_DEVICE(0x5A52, info), \
 457         INTEL_VGA_DEVICE(0x5A5A, info), \
 458         INTEL_VGA_DEVICE(0x5A42, info), \
 459         INTEL_VGA_DEVICE(0x5A4A, info), \
 460         INTEL_VGA_DEVICE(0x5A50, info), \
 461         INTEL_VGA_DEVICE(0x5A40, info), \
 462         INTEL_VGA_DEVICE(0x5A54, info), \
 463         INTEL_VGA_DEVICE(0x5A5C, info), \
 464         INTEL_VGA_DEVICE(0x5A44, info), \
 465         INTEL_VGA_DEVICE(0x5A4C, info)
 466
 467 /* ICL */
 468 #define INTEL_ICL_11_IDS(info) \
 469         INTEL_VGA_DEVICE(0x8A50, info), \
 470         INTEL_VGA_DEVICE(0x8A51, info), \
 471         INTEL_VGA_DEVICE(0x8A5C, info), \
 472         INTEL_VGA_DEVICE(0x8A5D, info), \
 473         INTEL_VGA_DEVICE(0x8A52, info), \
 474         INTEL_VGA_DEVICE(0x8A5A, info), \
 475         INTEL_VGA_DEVICE(0x8A5B, info), \
 476         INTEL_VGA_DEVICE(0x8A71, info), \
 477         INTEL_VGA_DEVICE(0x8A70, info)
 478
 479 #endif /* _PCI_EARLY_QUIRKS_H_ */