sys/x86/pci/pci_early_quirks.h

   1 /*-
   2  * Copyright (c) 2018 Johannes Lundberg
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef _PCI_EARLY_QUIRKS_H_
  29 #define _PCI_EARLY_QUIRKS_H_
  30
  31 /*
  32  * TODO:
  33  * Make a common drm/gpu header that both base and out of tree
  34  * drm modules can use.
  35  */
  36
  37 #define PCI_ANY_ID              (-1)
  38 #define PCI_VENDOR_INTEL        0x8086
  39 #define PCI_CLASS_VGA           0x0300
  40
  41 #define INTEL_BSM               0x5c
  42 #define INTEL_GEN11_BSM_DW0     0xc0
  43 #define INTEL_GEN11_BSM_DW1     0xc4
  44 #define INTEL_BSM_MASK          (-(1u << 20))
  45
  46 #define INTEL_GMCH_CTRL         0x52
  47 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
  48 #define SNB_GMCH_CTRL           0x50
  49 #define SNB_GMCH_GGMS_SHIFT     8 /* GTT Graphics Memory Size */
  50 #define SNB_GMCH_GGMS_MASK      0x3
  51 #define SNB_GMCH_GMS_SHIFT      3 /* Graphics Mode Select */
  52 #define SNB_GMCH_GMS_MASK       0x1f
  53 #define BDW_GMCH_GGMS_SHIFT     6
  54 #define BDW_GMCH_GGMS_MASK      0x3
  55 #define BDW_GMCH_GMS_SHIFT      8
  56 #define BDW_GMCH_GMS_MASK       0xff
  57
  58 #define I830_GMCH_CTRL                  0x52
  59 #define I830_GMCH_GMS_MASK              0x70
  60 #define I830_GMCH_GMS_LOCAL             0x10
  61 #define I830_GMCH_GMS_STOLEN_512        0x20
  62 #define I830_GMCH_GMS_STOLEN_1024       0x30
  63 #define I830_GMCH_GMS_STOLEN_8192       0x40
  64
  65 #define I855_GMCH_GMS_MASK              0xF0
  66 #define I855_GMCH_GMS_STOLEN_0M         0x0
  67 #define I855_GMCH_GMS_STOLEN_1M         (0x1 << 4)
  68 #define I855_GMCH_GMS_STOLEN_4M         (0x2 << 4)
  69 #define I855_GMCH_GMS_STOLEN_8M         (0x3 << 4)
  70 #define I855_GMCH_GMS_STOLEN_16M        (0x4 << 4)
  71 #define I855_GMCH_GMS_STOLEN_32M        (0x5 << 4)
  72 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  73 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  74 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
  75 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
  76 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
  77 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
  78 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
  79 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
  80
  81 #define INTEL_VGA_DEVICE(id, info) {            \
  82         0x8086, id,                             \
  83         info }
  84
  85 #define INTEL_I810_IDS(info)                                    \
  86         INTEL_VGA_DEVICE(0x7121, info), /* I810 */              \
  87         INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */        \
  88         INTEL_VGA_DEVICE(0x7125, info)  /* I810_E */
  89
  90 #define INTEL_I815_IDS(info)                                    \
  91         INTEL_VGA_DEVICE(0x1132, info)  /* I815*/
  92
  93 #define INTEL_I830_IDS(info)                            \
  94         INTEL_VGA_DEVICE(0x3577, info)
  95
  96 #define INTEL_I845G_IDS(info)                           \
  97         INTEL_VGA_DEVICE(0x2562, info)
  98
  99 #define INTEL_I85X_IDS(info)                            \
 100         INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
 101         INTEL_VGA_DEVICE(0x358e, info)
 102
 103 #define INTEL_I865G_IDS(info)                           \
 104         INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
 105
 106 #define INTEL_I915G_IDS(info)                           \
 107         INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
 108         INTEL_VGA_DEVICE(0x258a, info)  /* E7221_G */
 109
 110 #define INTEL_I915GM_IDS(info)                          \
 111         INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
 112
 113 #define INTEL_I945G_IDS(info)                           \
 114         INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
 115
 116 #define INTEL_I945GM_IDS(info)                          \
 117         INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
 118         INTEL_VGA_DEVICE(0x27ae, info)  /* I945_GME */
 119
 120 #define INTEL_I965G_IDS(info)                           \
 121         INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */   \
 122         INTEL_VGA_DEVICE(0x2982, info), /* G35_G */     \
 123         INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */    \
 124         INTEL_VGA_DEVICE(0x29a2, info)  /* I965_G */
 125
 126 #define INTEL_G33_IDS(info)                             \
 127         INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
 128         INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
 129         INTEL_VGA_DEVICE(0x29d2, info)  /* Q33_G */
 130
 131 #define INTEL_I965GM_IDS(info)                          \
 132         INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
 133         INTEL_VGA_DEVICE(0x2a12, info)  /* I965_GME */
 134
 135 #define INTEL_GM45_IDS(info)                            \
 136         INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
 137
 138 #define INTEL_G45_IDS(info)                             \
 139         INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
 140         INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
 141         INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
 142         INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
 143         INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
 144         INTEL_VGA_DEVICE(0x2e92, info)  /* B43_G.1 */
 145
 146 #define INTEL_PINEVIEW_IDS(info)                        \
 147         INTEL_VGA_DEVICE(0xa001, info),                 \
 148         INTEL_VGA_DEVICE(0xa011, info)
 149
 150 #define INTEL_IRONLAKE_D_IDS(info) \
 151         INTEL_VGA_DEVICE(0x0042, info)
 152
 153 #define INTEL_IRONLAKE_M_IDS(info) \
 154         INTEL_VGA_DEVICE(0x0046, info)
 155
 156 #define INTEL_SNB_D_GT1_IDS(info) \
 157         INTEL_VGA_DEVICE(0x0102, info), \
 158         INTEL_VGA_DEVICE(0x010A, info)
 159
 160 #define INTEL_SNB_D_GT2_IDS(info) \
 161         INTEL_VGA_DEVICE(0x0112, info), \
 162         INTEL_VGA_DEVICE(0x0122, info)
 163
 164 #define INTEL_SNB_D_IDS(info) \
 165         INTEL_SNB_D_GT1_IDS(info), \
 166         INTEL_SNB_D_GT2_IDS(info)
 167
 168 #define INTEL_SNB_M_GT1_IDS(info) \
 169         INTEL_VGA_DEVICE(0x0106, info)
 170
 171 #define INTEL_SNB_M_GT2_IDS(info) \
 172         INTEL_VGA_DEVICE(0x0116, info), \
 173         INTEL_VGA_DEVICE(0x0126, info)
 174
 175 #define INTEL_SNB_M_IDS(info) \
 176         INTEL_SNB_M_GT1_IDS(info), \
 177         INTEL_SNB_M_GT2_IDS(info)
 178
 179 #define INTEL_IVB_M_GT1_IDS(info) \
 180         INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
 181
 182 #define INTEL_IVB_M_GT2_IDS(info) \
 183         INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
 184
 185 #define INTEL_IVB_M_IDS(info) \
 186         INTEL_IVB_M_GT1_IDS(info), \
 187         INTEL_IVB_M_GT2_IDS(info)
 188
 189 #define INTEL_IVB_D_GT1_IDS(info) \
 190         INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
 191         INTEL_VGA_DEVICE(0x015a, info)  /* GT1 server */
 192
 193 #define INTEL_IVB_D_GT2_IDS(info) \
 194         INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
 195         INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
 196
 197 #define INTEL_IVB_D_IDS(info) \
 198         INTEL_IVB_D_GT1_IDS(info), \
 199         INTEL_IVB_D_GT2_IDS(info)
 200
 201 #define INTEL_IVB_Q_IDS(info) \
 202         INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 203
 204 #define INTEL_HSW_GT1_IDS(info) \
 205         INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 206         INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
 207         INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
 208         INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
 209         INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
 210         INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 211         INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 212         INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
 213         INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
 214         INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
 215         INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
 216         INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
 217         INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 218         INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
 219         INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 220         INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 221         INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
 222         INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 223         INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
 224         INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
 225
 226 #define INTEL_HSW_GT2_IDS(info) \
 227         INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 228         INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
 229         INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
 230         INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
 231         INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
 232         INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 233         INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 234         INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
 235         INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
 236         INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
 237         INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
 238         INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
 239         INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 240         INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
 241         INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
 242         INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 243         INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
 244         INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
 245         INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
 246         INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
 247         INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
 248
 249 #define INTEL_HSW_GT3_IDS(info) \
 250         INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
 251         INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
 252         INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
 253         INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
 254         INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
 255         INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 256         INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 257         INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
 258         INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
 259         INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
 260         INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
 261         INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
 262         INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 263         INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 264         INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
 265         INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
 266         INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 267         INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
 268         INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 269
 270 #define INTEL_HSW_IDS(info) \
 271         INTEL_HSW_GT1_IDS(info), \
 272         INTEL_HSW_GT2_IDS(info), \
 273         INTEL_HSW_GT3_IDS(info)
 274
 275 #define INTEL_VLV_IDS(info) \
 276         INTEL_VGA_DEVICE(0x0f30, info), \
 277         INTEL_VGA_DEVICE(0x0f31, info), \
 278         INTEL_VGA_DEVICE(0x0f32, info), \
 279         INTEL_VGA_DEVICE(0x0f33, info), \
 280         INTEL_VGA_DEVICE(0x0157, info), \
 281         INTEL_VGA_DEVICE(0x0155, info)
 282
 283 #define INTEL_BDW_GT1_IDS(info)  \
 284         INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 285         INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
 286         INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
 287         INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
 288         INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 289         INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
 290
 291 #define INTEL_BDW_GT2_IDS(info)  \
 292         INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */  \
 293         INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
 294         INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
 295         INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
 296         INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 297         INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 298
 299 #define INTEL_BDW_GT3_IDS(info) \
 300         INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
 301         INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
 302         INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
 303         INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 304         INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 305         INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 306
 307 #define INTEL_BDW_RSVD_IDS(info) \
 308         INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
 309         INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
 310         INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
 311         INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
 312         INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 313         INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 314
 315 #define INTEL_BDW_IDS(info) \
 316         INTEL_BDW_GT1_IDS(info), \
 317         INTEL_BDW_GT2_IDS(info), \
 318         INTEL_BDW_GT3_IDS(info), \
 319         INTEL_BDW_RSVD_IDS(info)
 320
 321 #define INTEL_CHV_IDS(info) \
 322         INTEL_VGA_DEVICE(0x22b0, info), \
 323         INTEL_VGA_DEVICE(0x22b1, info), \
 324         INTEL_VGA_DEVICE(0x22b2, info), \
 325         INTEL_VGA_DEVICE(0x22b3, info)
 326
 327 #define INTEL_SKL_GT1_IDS(info) \
 328         INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
 329         INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
 330         INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
 331         INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
 332         INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
 333
 334 #define INTEL_SKL_GT2_IDS(info) \
 335         INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
 336         INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
 337         INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
 338         INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 339         INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 340         INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 341         INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 342
 343 #define INTEL_SKL_GT3_IDS(info) \
 344         INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
 345         INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
 346         INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
 347         INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
 348         INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
 349
 350 #define INTEL_SKL_GT4_IDS(info) \
 351         INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
 352         INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
 353         INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
 354         INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
 355         INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
 356
 357 #define INTEL_SKL_IDS(info)      \
 358         INTEL_SKL_GT1_IDS(info), \
 359         INTEL_SKL_GT2_IDS(info), \
 360         INTEL_SKL_GT3_IDS(info), \
 361         INTEL_SKL_GT4_IDS(info)
 362
 363 #define INTEL_BXT_IDS(info) \
 364         INTEL_VGA_DEVICE(0x0A84, info), \
 365         INTEL_VGA_DEVICE(0x1A84, info), \
 366         INTEL_VGA_DEVICE(0x1A85, info), \
 367         INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
 368         INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
 369
 370 #define INTEL_GLK_IDS(info) \
 371         INTEL_VGA_DEVICE(0x3184, info), \
 372         INTEL_VGA_DEVICE(0x3185, info)
 373
 374 #define INTEL_KBL_GT1_IDS(info) \
 375         INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
 376         INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
 377         INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
 378         INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
 379         INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 380         INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 381         INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 382         INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
 383
 384 #define INTEL_KBL_GT2_IDS(info) \
 385         INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
 386         INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 387         INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
 388         INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
 389         INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 390         INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 391         INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 392         INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 393
 394 #define INTEL_KBL_GT3_IDS(info) \
 395         INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
 396         INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
 397         INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
 398
 399 #define INTEL_KBL_GT4_IDS(info) \
 400         INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
 401
 402 #define INTEL_KBL_IDS(info) \
 403         INTEL_KBL_GT1_IDS(info), \
 404         INTEL_KBL_GT2_IDS(info), \
 405         INTEL_KBL_GT3_IDS(info), \
 406         INTEL_KBL_GT4_IDS(info)
 407
 408 /* CFL S */
 409 #define INTEL_CFL_S_GT1_IDS(info) \
 410         INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
 411         INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
 412         INTEL_VGA_DEVICE(0x3E99, info)  /* SRV GT1 */
 413
 414 #define INTEL_CFL_S_GT2_IDS(info) \
 415         INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
 416         INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
 417         INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
 418         INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
 419         INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */
 420
 421 /* CFL H */
 422 #define INTEL_CFL_H_GT2_IDS(info) \
 423         INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
 424         INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
 425
 426 /* CFL U GT1 */
 427 #define INTEL_CFL_U_GT1_IDS(info) \
 428         INTEL_VGA_DEVICE(0x3EA1, info), \
 429         INTEL_VGA_DEVICE(0x3EA4, info)
 430
 431 /* CFL U GT2 */
 432 #define INTEL_CFL_U_GT2_IDS(info) \
 433         INTEL_VGA_DEVICE(0x3EA0, info), \
 434         INTEL_VGA_DEVICE(0x3EA3, info), \
 435         INTEL_VGA_DEVICE(0x3EA9, info)
 436
 437 /* CFL U GT3 */
 438 #define INTEL_CFL_U_GT3_IDS(info) \
 439         INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \
 440         INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
 441         INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
 442         INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
 443         INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */
 444
 445 #define INTEL_CFL_IDS(info)        \
 446         INTEL_CFL_S_GT1_IDS(info), \
 447         INTEL_CFL_S_GT2_IDS(info), \
 448         INTEL_CFL_H_GT2_IDS(info), \
 449         INTEL_CFL_U_GT1_IDS(info), \
 450         INTEL_CFL_U_GT2_IDS(info), \
 451         INTEL_CFL_U_GT3_IDS(info)
 452
 453 /* CNL */
 454 #define INTEL_CNL_IDS(info) \
 455         INTEL_VGA_DEVICE(0x5A51, info), \
 456         INTEL_VGA_DEVICE(0x5A59, info), \
 457         INTEL_VGA_DEVICE(0x5A41, info), \
 458         INTEL_VGA_DEVICE(0x5A49, info), \
 459         INTEL_VGA_DEVICE(0x5A52, info), \
 460         INTEL_VGA_DEVICE(0x5A5A, info), \
 461         INTEL_VGA_DEVICE(0x5A42, info), \
 462         INTEL_VGA_DEVICE(0x5A4A, info), \
 463         INTEL_VGA_DEVICE(0x5A50, info), \
 464         INTEL_VGA_DEVICE(0x5A40, info), \
 465         INTEL_VGA_DEVICE(0x5A54, info), \
 466         INTEL_VGA_DEVICE(0x5A5C, info), \
 467         INTEL_VGA_DEVICE(0x5A44, info), \
 468         INTEL_VGA_DEVICE(0x5A4C, info)
 469
 470 /* ICL */
 471 #define INTEL_ICL_11_IDS(info) \
 472         INTEL_VGA_DEVICE(0x8A50, info), \
 473         INTEL_VGA_DEVICE(0x8A51, info), \
 474         INTEL_VGA_DEVICE(0x8A5C, info), \
 475         INTEL_VGA_DEVICE(0x8A5D, info), \
 476         INTEL_VGA_DEVICE(0x8A52, info), \
 477         INTEL_VGA_DEVICE(0x8A5A, info), \
 478         INTEL_VGA_DEVICE(0x8A5B, info), \
 479         INTEL_VGA_DEVICE(0x8A71, info), \
 480         INTEL_VGA_DEVICE(0x8A70, info)
 481
 482 /* EHL */
 483 #define INTEL_EHL_IDS(info) \
 484         INTEL_VGA_DEVICE(0x4541, info), \
 485         INTEL_VGA_DEVICE(0x4551, info), \
 486         INTEL_VGA_DEVICE(0x4555, info), \
 487         INTEL_VGA_DEVICE(0x4557, info), \
 488         INTEL_VGA_DEVICE(0x4571, info)
 489
 490 /* JSL */
 491 #define INTEL_JSL_IDS(info) \
 492         INTEL_VGA_DEVICE(0x4E51, info), \
 493         INTEL_VGA_DEVICE(0x4E55, info), \
 494         INTEL_VGA_DEVICE(0x4E57, info), \
 495         INTEL_VGA_DEVICE(0x4E61, info), \
 496         INTEL_VGA_DEVICE(0x4E71, info)
 497
 498 /* TGL */
 499 #define INTEL_TGL_12_GT1_IDS(info) \
 500         INTEL_VGA_DEVICE(0x9A60, info), \
 501         INTEL_VGA_DEVICE(0x9A68, info), \
 502         INTEL_VGA_DEVICE(0x9A70, info)
 503
 504 #define INTEL_TGL_12_GT2_IDS(info) \
 505         INTEL_VGA_DEVICE(0x9A40, info), \
 506         INTEL_VGA_DEVICE(0x9A49, info), \
 507         INTEL_VGA_DEVICE(0x9A59, info), \
 508         INTEL_VGA_DEVICE(0x9A78, info), \
 509         INTEL_VGA_DEVICE(0x9AC0, info), \
 510         INTEL_VGA_DEVICE(0x9AC9, info), \
 511         INTEL_VGA_DEVICE(0x9AD9, info), \
 512         INTEL_VGA_DEVICE(0x9AF8, info)
 513
 514 #define INTEL_TGL_12_IDS(info) \
 515         INTEL_TGL_12_GT1_IDS(info), \
 516         INTEL_TGL_12_GT2_IDS(info)
 517
 518 /* RKL */
 519 #define INTEL_RKL_IDS(info) \
 520         INTEL_VGA_DEVICE(0x4C80, info), \
 521         INTEL_VGA_DEVICE(0x4C8A, info), \
 522         INTEL_VGA_DEVICE(0x4C8B, info), \
 523         INTEL_VGA_DEVICE(0x4C8C, info), \
 524         INTEL_VGA_DEVICE(0x4C90, info), \
 525         INTEL_VGA_DEVICE(0x4C9A, info)
 526
 527 /* DG1 */
 528 #define INTEL_DG1_IDS(info) \
 529         INTEL_VGA_DEVICE(0x4905, info), \
 530         INTEL_VGA_DEVICE(0x4906, info), \
 531         INTEL_VGA_DEVICE(0x4907, info), \
 532         INTEL_VGA_DEVICE(0x4908, info), \
 533         INTEL_VGA_DEVICE(0x4909, info)
 534
 535 /* ADL-S */
 536 #define INTEL_ADLS_IDS(info) \
 537         INTEL_VGA_DEVICE(0x4680, info), \
 538         INTEL_VGA_DEVICE(0x4682, info), \
 539         INTEL_VGA_DEVICE(0x4688, info), \
 540         INTEL_VGA_DEVICE(0x468A, info), \
 541         INTEL_VGA_DEVICE(0x4690, info), \
 542         INTEL_VGA_DEVICE(0x4692, info), \
 543         INTEL_VGA_DEVICE(0x4693, info)
 544
 545 /* ADL-P */
 546 #define INTEL_ADLP_IDS(info) \
 547         INTEL_VGA_DEVICE(0x46A0, info), \
 548         INTEL_VGA_DEVICE(0x46A1, info), \
 549         INTEL_VGA_DEVICE(0x46A2, info), \
 550         INTEL_VGA_DEVICE(0x46A3, info), \
 551         INTEL_VGA_DEVICE(0x46A6, info), \
 552         INTEL_VGA_DEVICE(0x46A8, info), \
 553         INTEL_VGA_DEVICE(0x46AA, info), \
 554         INTEL_VGA_DEVICE(0x462A, info), \
 555         INTEL_VGA_DEVICE(0x4626, info), \
 556         INTEL_VGA_DEVICE(0x4628, info), \
 557         INTEL_VGA_DEVICE(0x46B0, info), \
 558         INTEL_VGA_DEVICE(0x46B1, info), \
 559         INTEL_VGA_DEVICE(0x46B2, info), \
 560         INTEL_VGA_DEVICE(0x46B3, info), \
 561         INTEL_VGA_DEVICE(0x46C0, info), \
 562         INTEL_VGA_DEVICE(0x46C1, info), \
 563         INTEL_VGA_DEVICE(0x46C2, info), \
 564         INTEL_VGA_DEVICE(0x46C3, info)
 565
 566 /* RPL-S */
 567 #define INTEL_RPLS_IDS(info) \
 568         INTEL_VGA_DEVICE(0xA780, info), \
 569         INTEL_VGA_DEVICE(0xA781, info), \
 570         INTEL_VGA_DEVICE(0xA782, info), \
 571         INTEL_VGA_DEVICE(0xA783, info), \
 572         INTEL_VGA_DEVICE(0xA788, info), \
 573         INTEL_VGA_DEVICE(0xA789, info)
 574
 575 #endif /* _PCI_EARLY_QUIRKS_H_ */