2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 #include "opt_atpic.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_platform.h"
59 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/domainset.h>
66 #include <sys/kernel.h>
69 #include <sys/malloc.h>
70 #include <sys/mutex.h>
72 #include <sys/rwlock.h>
73 #include <sys/sched.h>
75 #include <sys/sysctl.h>
77 #include <machine/clock.h>
78 #include <machine/cpu.h>
79 #include <machine/cpufunc.h>
80 #include <machine/cputypes.h>
81 #include <machine/specialreg.h>
82 #include <machine/md_var.h>
83 #include <machine/mp_watchdog.h>
84 #include <machine/tss.h>
86 #include <machine/smp.h>
89 #include <machine/elan_mmcr.h>
91 #include <x86/acpica_machdep.h>
92 #include <x86/ifunc.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_kern.h>
97 #include <vm/vm_page.h>
98 #include <vm/vm_map.h>
99 #include <vm/vm_object.h>
100 #include <vm/vm_pager.h>
101 #include <vm/vm_param.h>
103 #include <isa/isareg.h>
105 #include <contrib/dev/acpica/include/acpi.h>
107 #define STATE_RUNNING 0x0
108 #define STATE_MWAIT 0x1
109 #define STATE_SLEEPING 0x2
112 static u_int cpu_reset_proxyid;
113 static volatile u_int cpu_reset_proxy_active;
124 x86_msr_op_one(void *argp)
126 struct msr_op_arg *a;
142 wrmsr(a->msr, a->arg1);
151 #define MSR_OP_EXMODE_MASK 0xf0000000
152 #define MSR_OP_OP_MASK 0x000000ff
153 #define MSR_OP_GET_CPUID(x) (((x) & ~MSR_OP_EXMODE_MASK) >> 8)
156 x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res)
162 int bound_cpu, cpu, i, is_bound;
164 a.op = op & MSR_OP_OP_MASK;
165 MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR ||
166 a.op == MSR_OP_WRITE || a.op == MSR_OP_READ);
167 exmode = op & MSR_OP_EXMODE_MASK;
168 MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED_ALL ||
169 exmode == MSR_OP_SCHED_ONE || exmode == MSR_OP_RENDEZVOUS_ALL ||
170 exmode == MSR_OP_RENDEZVOUS_ONE);
178 case MSR_OP_SCHED_ALL:
181 is_bound = sched_is_bound(td);
182 bound_cpu = td->td_oncpu;
188 sched_bind(td, bound_cpu);
193 case MSR_OP_SCHED_ONE:
195 cpu = MSR_OP_GET_CPUID(op);
197 is_bound = sched_is_bound(td);
198 bound_cpu = td->td_oncpu;
199 if (!is_bound || bound_cpu != cpu)
203 if (bound_cpu != cpu)
204 sched_bind(td, bound_cpu);
210 case MSR_OP_RENDEZVOUS_ALL:
211 smp_rendezvous(smp_no_rendezvous_barrier, x86_msr_op_one,
212 smp_no_rendezvous_barrier, &a);
214 case MSR_OP_RENDEZVOUS_ONE:
215 cpu = MSR_OP_GET_CPUID(op);
216 CPU_SETOF(cpu, &set);
217 smp_rendezvous_cpus(set, smp_no_rendezvous_barrier,
218 x86_msr_op_one, smp_no_rendezvous_barrier, &a);
224 * Automatically initialized per CPU errata in cpu_idle_tun below.
226 bool mwait_cpustop_broken = false;
227 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN,
228 &mwait_cpustop_broken, 0,
229 "Can not reliably wake MONITOR/MWAIT cpus without interrupts");
232 * Flush the D-cache for non-DMA I/O so that the I-cache can
233 * be made coherent later.
236 cpu_flush_dcache(void *ptr, size_t len)
245 __asm __volatile("sti; hlt");
249 * Use mwait to pause execution while waiting for an interrupt or
250 * another thread to signal that there is more work.
252 * NOTE: Interrupts will cause a wakeup; however, this function does
253 * not enable interrupt handling. The caller is responsible to enable
257 acpi_cpu_idle_mwait(uint32_t mwait_hint)
263 * A comment in Linux patch claims that 'CPUs run faster with
264 * speculation protection disabled. All CPU threads in a core
265 * must disable speculation protection for it to be
266 * disabled. Disable it while we are idle so the other
267 * hyperthread can run fast.'
269 * XXXKIB. Software coordination mode should be supported,
270 * but all Intel CPUs provide hardware coordination.
273 state = &PCPU_PTR(monitorbuf)->idle_state;
274 KASSERT(atomic_load_int(state) == STATE_SLEEPING,
275 ("cpu_mwait_cx: wrong monitorbuf state"));
276 atomic_store_int(state, STATE_MWAIT);
277 if (PCPU_GET(ibpb_set) || hw_ssb_active) {
278 v = rdmsr(MSR_IA32_SPEC_CTRL);
279 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS |
280 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD));
284 cpu_monitor(state, 0, 0);
285 if (atomic_load_int(state) == STATE_MWAIT)
286 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
289 * SSB cannot be disabled while we sleep, or rather, if it was
290 * disabled, the sysctl thread will bind to our cpu to tweak
294 wrmsr(MSR_IA32_SPEC_CTRL, v);
297 * We should exit on any event that interrupts mwait, because
298 * that event might be a wanted interrupt.
300 atomic_store_int(state, STATE_RUNNING);
303 /* Get current clock frequency for the given cpu id. */
305 cpu_est_clockrate(int cpu_id, uint64_t *rate)
308 uint64_t acnt, mcnt, perf;
311 if (pcpu_find(cpu_id) == NULL || rate == NULL)
314 if ((cpu_feature & CPUID_TSC) == 0)
319 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
320 * DELAY(9) based logic fails.
322 if (tsc_is_invariant && !tsc_perf_stat)
327 /* Schedule ourselves on the indicated cpu. */
328 thread_lock(curthread);
329 sched_bind(curthread, cpu_id);
330 thread_unlock(curthread);
334 /* Calibrate by measuring a short delay. */
335 reg = intr_disable();
336 if (tsc_is_invariant) {
341 mcnt = rdmsr(MSR_MPERF);
342 acnt = rdmsr(MSR_APERF);
345 perf = 1000 * acnt / mcnt;
346 *rate = (tsc2 - tsc1) * perf;
352 *rate = (tsc2 - tsc1) * 1000;
357 thread_lock(curthread);
358 sched_unbind(curthread);
359 thread_unlock(curthread);
367 * Shutdown the CPU as much as possible
379 struct region_descriptor null_idt;
384 if (elan_mmcr != NULL)
385 elan_mmcr->RESCFG = 1;
388 if (cpu == CPU_GEODE1100) {
389 /* Attempt Geode's own reset */
390 outl(0xcf8, 0x80009044ul);
394 #if !defined(BROKEN_KEYBOARD_RESET)
396 * Attempt to do a CPU reset via the keyboard controller,
397 * do not turn off GateA20, as any machine that fails
398 * to do the reset here would then end up in no man's land.
400 outb(IO_KBD + 4, 0xFE);
401 DELAY(500000); /* wait 0.5 sec to see if that did it */
405 * Attempt to force a reset via the Reset Control register at
406 * I/O port 0xcf9. Bit 2 forces a system reset when it
407 * transitions from 0 to 1. Bit 1 selects the type of reset
408 * to attempt: 0 selects a "soft" reset, and 1 selects a
409 * "hard" reset. We try a "hard" reset. The first write sets
410 * bit 1 to select a "hard" reset and clears bit 2. The
411 * second write forces a 0 -> 1 transition in bit 2 to trigger
416 DELAY(500000); /* wait 0.5 sec to see if that did it */
419 * Attempt to force a reset via the Fast A20 and Init register
420 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
421 * Bit 0 asserts INIT# when set to 1. We are careful to only
422 * preserve bit 1 while setting bit 0. We also must clear bit
423 * 0 before setting it if it isn't already clear.
428 outb(0x92, b & 0xfe);
430 DELAY(500000); /* wait 0.5 sec to see if that did it */
433 printf("No known reset method worked, attempting CPU shutdown\n");
434 DELAY(1000000); /* wait 1 sec for printf to complete */
437 null_idt.rd_limit = 0;
438 null_idt.rd_base = 0;
441 /* "good night, sweet prince .... <THUNK!>" */
450 cpu_reset_proxy(void)
453 cpu_reset_proxy_active = 1;
454 while (cpu_reset_proxy_active == 1)
455 ia32_pause(); /* Wait for other cpu to see that we've started */
457 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid);
467 struct monitorbuf *mb;
473 CPU_CLR(PCPU_GET(cpuid), &map);
474 CPU_ANDNOT(&map, &stopped_cpus);
475 if (!CPU_EMPTY(&map)) {
476 printf("cpu_reset: Stopping other CPUs\n");
480 if (PCPU_GET(cpuid) != 0) {
481 cpu_reset_proxyid = PCPU_GET(cpuid);
482 cpustop_restartfunc = cpu_reset_proxy;
483 cpu_reset_proxy_active = 0;
484 printf("cpu_reset: Restarting BSP\n");
486 /* Restart CPU #0. */
487 CPU_SETOF(0, &started_cpus);
488 mb = &pcpu_find(0)->pc_monitorbuf;
489 atomic_store_int(&mb->stop_state,
490 MONITOR_STOPSTATE_RUNNING);
493 while (cpu_reset_proxy_active == 0 && cnt < 10000000) {
495 cnt++; /* Wait for BSP to announce restart */
497 if (cpu_reset_proxy_active == 0) {
498 printf("cpu_reset: Failed to restart BSP\n");
500 cpu_reset_proxy_active = 2;
515 cpu_mwait_usable(void)
518 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
519 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
520 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
523 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
525 int cpu_amdc1e_bug = 0; /* AMD C1E APIC workaround required. */
527 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
528 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
529 0, "Use MONITOR/MWAIT for short idle");
532 cpu_idle_acpi(sbintime_t sbt)
536 state = &PCPU_PTR(monitorbuf)->idle_state;
537 atomic_store_int(state, STATE_SLEEPING);
539 /* See comments in cpu_idle_hlt(). */
541 if (sched_runnable())
543 else if (cpu_idle_hook)
547 atomic_store_int(state, STATE_RUNNING);
551 cpu_idle_hlt(sbintime_t sbt)
555 state = &PCPU_PTR(monitorbuf)->idle_state;
556 atomic_store_int(state, STATE_SLEEPING);
559 * Since we may be in a critical section from cpu_idle(), if
560 * an interrupt fires during that critical section we may have
561 * a pending preemption. If the CPU halts, then that thread
562 * may not execute until a later interrupt awakens the CPU.
563 * To handle this race, check for a runnable thread after
564 * disabling interrupts and immediately return if one is
565 * found. Also, we must absolutely guarentee that hlt is
566 * the next instruction after sti. This ensures that any
567 * interrupt that fires after the call to disable_intr() will
568 * immediately awaken the CPU from hlt. Finally, please note
569 * that on x86 this works fine because of interrupts enabled only
570 * after the instruction following sti takes place, while IF is set
571 * to 1 immediately, allowing hlt instruction to acknowledge the
575 if (sched_runnable())
579 atomic_store_int(state, STATE_RUNNING);
583 cpu_idle_mwait(sbintime_t sbt)
587 state = &PCPU_PTR(monitorbuf)->idle_state;
588 atomic_store_int(state, STATE_MWAIT);
590 /* See comments in cpu_idle_hlt(). */
592 if (sched_runnable()) {
593 atomic_store_int(state, STATE_RUNNING);
598 cpu_monitor(state, 0, 0);
599 if (atomic_load_int(state) == STATE_MWAIT)
600 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
603 atomic_store_int(state, STATE_RUNNING);
607 cpu_idle_spin(sbintime_t sbt)
612 state = &PCPU_PTR(monitorbuf)->idle_state;
613 atomic_store_int(state, STATE_RUNNING);
616 * The sched_runnable() call is racy but as long as there is
617 * a loop missing it one time will have just a little impact if any
618 * (and it is much better than missing the check at all).
620 for (i = 0; i < 1000; i++) {
621 if (sched_runnable())
627 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
635 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
638 ap_watchdog(PCPU_GET(cpuid));
641 /* If we are busy - try to use fast methods. */
643 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
644 cpu_idle_mwait(busy);
649 /* If we have time - switch timers into idle mode. */
652 sbt = cpu_idleclock();
655 /* Apply AMD APIC timer C1E workaround. */
656 if (cpu_amdc1e_bug && cpu_disable_c3_sleep) {
657 msr = rdmsr(MSR_AMDK8_IPM);
658 if ((msr & (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)) != 0)
659 wrmsr(MSR_AMDK8_IPM, msr & ~(AMDK8_SMIONCMPHALT |
660 AMDK8_C1EONCMPHALT));
663 /* Call main idle method. */
666 /* Switch timers back into active mode. */
672 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
676 static int cpu_idle_apl31_workaround;
677 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW,
678 &cpu_idle_apl31_workaround, 0,
679 "Apollo Lake APL31 MWAIT bug workaround");
682 cpu_idle_wakeup(int cpu)
684 struct monitorbuf *mb;
687 mb = &pcpu_find(cpu)->pc_monitorbuf;
688 state = &mb->idle_state;
689 switch (atomic_load_int(state)) {
693 atomic_store_int(state, STATE_RUNNING);
694 return (cpu_idle_apl31_workaround ? 0 : 1);
698 panic("bad monitor state");
704 * Ordered by speed/power consumption.
711 { .id_fn = cpu_idle_spin, .id_name = "spin" },
712 { .id_fn = cpu_idle_mwait, .id_name = "mwait",
713 .id_cpuid2_flag = CPUID2_MON },
714 { .id_fn = cpu_idle_hlt, .id_name = "hlt" },
715 { .id_fn = cpu_idle_acpi, .id_name = "acpi" },
719 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
725 avail = malloc(256, M_TEMP, M_WAITOK);
727 for (i = 0; i < nitems(idle_tbl); i++) {
728 if (idle_tbl[i].id_cpuid2_flag != 0 &&
729 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
731 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
732 cpu_idle_hook == NULL)
734 p += sprintf(p, "%s%s", p != avail ? ", " : "",
735 idle_tbl[i].id_name);
737 error = sysctl_handle_string(oidp, avail, 0, req);
742 SYSCTL_PROC(_machdep, OID_AUTO, idle_available,
743 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
744 0, 0, idle_sysctl_available, "A",
745 "list of available idle functions");
748 cpu_idle_selector(const char *new_idle_name)
752 for (i = 0; i < nitems(idle_tbl); i++) {
753 if (idle_tbl[i].id_cpuid2_flag != 0 &&
754 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
756 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
757 cpu_idle_hook == NULL)
759 if (strcmp(idle_tbl[i].id_name, new_idle_name))
761 cpu_idle_fn = idle_tbl[i].id_fn;
763 printf("CPU idle set to %s\n", idle_tbl[i].id_name);
770 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
776 for (i = 0; i < nitems(idle_tbl); i++) {
777 if (idle_tbl[i].id_fn == cpu_idle_fn) {
778 p = idle_tbl[i].id_name;
782 strncpy(buf, p, sizeof(buf));
783 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
784 if (error != 0 || req->newptr == NULL)
786 return (cpu_idle_selector(buf) ? 0 : EINVAL);
789 SYSCTL_PROC(_machdep, OID_AUTO, idle,
790 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
791 0, 0, cpu_idle_sysctl, "A",
792 "currently selected idle function");
795 cpu_idle_tun(void *unused __unused)
799 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
800 cpu_idle_selector(tunvar);
801 else if (cpu_vendor_id == CPU_VENDOR_AMD &&
802 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
803 /* Ryzen erratas 1057, 1109. */
804 cpu_idle_selector("hlt");
806 mwait_cpustop_broken = true;
809 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
811 * Apollo Lake errata APL31 (public errata APL30).
812 * Stores to the armed address range may not trigger
813 * MWAIT to resume execution. OS needs to use
814 * interrupts to wake processors from MWAIT-induced
817 cpu_idle_apl31_workaround = 1;
818 mwait_cpustop_broken = true;
820 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround);
822 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL);
824 static int panic_on_nmi = 0xff;
825 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
827 "Panic on NMI: 1 = H/W failure; 2 = unknown; 0xff = all");
828 int nmi_is_broadcast = 1;
829 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
830 &nmi_is_broadcast, 0,
831 "Chipset NMI is broadcast");
832 int (*apei_nmi)(void);
835 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
837 bool claimed = false;
840 /* machine/parity/power fail/"kitchen sink" faults */
841 if (isa_nmi(frame->tf_err)) {
843 if ((panic_on_nmi & 1) != 0)
844 panic("NMI indicates hardware failure");
848 /* ACPI Platform Error Interfaces callback. */
849 if (apei_nmi != NULL && (*apei_nmi)())
853 * NMIs can be useful for debugging. They can be hooked up to a
854 * pushbutton, usually on an ISA, PCI, or PCIe card. They can also be
855 * generated by an IPMI BMC, either manually or in response to a
856 * watchdog timeout. For example, see the "power diag" command in
857 * ports/sysutils/ipmitool. They can also be generated by a
858 * hypervisor; see "bhyvectl --inject-nmi".
862 if (!claimed && (panic_on_nmi & 2) != 0) {
863 if (debugger_on_panic) {
864 printf("NMI/cpu%d ... going to debugger\n", cpu);
865 claimed = kdb_trap(type, 0, frame);
870 if (!claimed && panic_on_nmi != 0)
875 nmi_handle_intr(u_int type, struct trapframe *frame)
879 if (nmi_is_broadcast) {
880 nmi_call_kdb_smp(type, frame);
884 nmi_call_kdb(PCPU_GET(cpuid), type, frame);
887 static int hw_ibrs_active;
888 int hw_ibrs_ibpb_active;
889 int hw_ibrs_disable = 1;
891 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
892 "Indirect Branch Restricted Speculation active");
894 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ibrs,
895 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
896 "Indirect Branch Restricted Speculation active");
898 SYSCTL_INT(_machdep_mitigations_ibrs, OID_AUTO, active, CTLFLAG_RD,
899 &hw_ibrs_active, 0, "Indirect Branch Restricted Speculation active");
902 hw_ibrs_recalculate(bool for_all_cpus)
904 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
905 x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ?
906 MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL) |
907 (hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR),
908 IA32_SPEC_CTRL_IBRS, NULL);
909 hw_ibrs_active = hw_ibrs_disable == 0;
910 hw_ibrs_ibpb_active = 0;
912 hw_ibrs_active = hw_ibrs_ibpb_active = (cpu_stdext_feature3 &
913 CPUID_STDEXT3_IBPB) != 0 && !hw_ibrs_disable;
918 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS)
922 val = hw_ibrs_disable;
923 error = sysctl_handle_int(oidp, &val, 0, req);
924 if (error != 0 || req->newptr == NULL)
926 hw_ibrs_disable = val != 0;
927 hw_ibrs_recalculate(true);
930 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
931 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
932 "Disable Indirect Branch Restricted Speculation");
934 SYSCTL_PROC(_machdep_mitigations_ibrs, OID_AUTO, disable, CTLTYPE_INT |
935 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
936 hw_ibrs_disable_handler, "I",
937 "Disable Indirect Branch Restricted Speculation");
942 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD,
944 "Speculative Store Bypass Disable active");
946 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ssb,
947 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
948 "Speculative Store Bypass Disable active");
950 SYSCTL_INT(_machdep_mitigations_ssb, OID_AUTO, active, CTLFLAG_RD,
951 &hw_ssb_active, 0, "Speculative Store Bypass Disable active");
954 hw_ssb_set(bool enable, bool for_all_cpus)
957 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) {
961 hw_ssb_active = enable;
962 x86_msr_op(MSR_IA32_SPEC_CTRL,
963 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
964 (for_all_cpus ? MSR_OP_SCHED_ALL : MSR_OP_LOCAL),
965 IA32_SPEC_CTRL_SSBD, NULL);
969 hw_ssb_recalculate(bool all_cpus)
972 switch (hw_ssb_disable) {
977 hw_ssb_set(false, all_cpus);
980 hw_ssb_set(true, all_cpus);
983 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ?
984 false : true, all_cpus);
990 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS)
994 val = hw_ssb_disable;
995 error = sysctl_handle_int(oidp, &val, 0, req);
996 if (error != 0 || req->newptr == NULL)
998 hw_ssb_disable = val;
999 hw_ssb_recalculate(true);
1002 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
1003 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1004 hw_ssb_disable_handler, "I",
1005 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
1007 SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT |
1008 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1009 hw_ssb_disable_handler, "I",
1010 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
1015 * Handler for Microarchitectural Data Sampling issues. Really not a
1016 * pointer to C function: on amd64 the code must not change any CPU
1017 * architectural state except possibly %rflags. Also, it is always
1018 * called with interrupts disabled.
1020 void mds_handler_void(void);
1021 void mds_handler_verw(void);
1022 void mds_handler_ivb(void);
1023 void mds_handler_bdw(void);
1024 void mds_handler_skl_sse(void);
1025 void mds_handler_skl_avx(void);
1026 void mds_handler_skl_avx512(void);
1027 void mds_handler_silvermont(void);
1028 void (*mds_handler)(void) = mds_handler_void;
1031 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS)
1035 if (mds_handler == mds_handler_void)
1037 else if (mds_handler == mds_handler_verw)
1039 else if (mds_handler == mds_handler_ivb)
1040 state = "software IvyBridge";
1041 else if (mds_handler == mds_handler_bdw)
1042 state = "software Broadwell";
1043 else if (mds_handler == mds_handler_skl_sse)
1044 state = "software Skylake SSE";
1045 else if (mds_handler == mds_handler_skl_avx)
1046 state = "software Skylake AVX";
1047 else if (mds_handler == mds_handler_skl_avx512)
1048 state = "software Skylake AVX512";
1049 else if (mds_handler == mds_handler_silvermont)
1050 state = "software Silvermont";
1053 return (SYSCTL_OUT(req, state, strlen(state)));
1056 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state,
1057 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1058 sysctl_hw_mds_disable_state_handler, "A",
1059 "Microarchitectural Data Sampling Mitigation state");
1061 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, mds,
1062 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1063 "Microarchitectural Data Sampling Mitigation state");
1065 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, state,
1066 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1067 sysctl_hw_mds_disable_state_handler, "A",
1068 "Microarchitectural Data Sampling Mitigation state");
1070 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512");
1073 hw_mds_recalculate(void)
1081 * Allow user to force VERW variant even if MD_CLEAR is not
1082 * reported. For instance, hypervisor might unknowingly
1083 * filter the cap out.
1084 * For the similar reasons, and for testing, allow to enable
1085 * mitigation even when MDS_NO cap is set.
1087 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 ||
1088 ((cpu_ia32_arch_caps & IA32_ARCH_CAP_MDS_NO) != 0 &&
1089 hw_mds_disable == 3)) {
1090 mds_handler = mds_handler_void;
1091 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 &&
1092 hw_mds_disable == 3) || hw_mds_disable == 1) {
1093 mds_handler = mds_handler_verw;
1094 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1095 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e ||
1096 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a ||
1097 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 ||
1098 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d ||
1099 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e ||
1100 CPUID_TO_MODEL(cpu_id) == 0x3a) &&
1101 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1103 * Nehalem, SandyBridge, IvyBridge
1107 if (pc->pc_mds_buf == NULL) {
1108 pc->pc_mds_buf = malloc_domainset(672, M_TEMP,
1109 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1110 bzero(pc->pc_mds_buf, 16);
1113 mds_handler = mds_handler_ivb;
1114 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1115 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c ||
1116 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 ||
1117 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f ||
1118 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) &&
1119 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1121 * Haswell, Broadwell
1125 if (pc->pc_mds_buf == NULL) {
1126 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP,
1127 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1128 bzero(pc->pc_mds_buf, 16);
1131 mds_handler = mds_handler_bdw;
1132 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1133 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id &
1134 CPUID_STEPPING) <= 5) ||
1135 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e ||
1136 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id &
1137 CPUID_STEPPING) <= 0xb) ||
1138 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id &
1139 CPUID_STEPPING) <= 0xc)) &&
1140 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1142 * Skylake, KabyLake, CoffeeLake, WhiskeyLake,
1147 if (pc->pc_mds_buf == NULL) {
1148 pc->pc_mds_buf = malloc_domainset(6 * 1024,
1149 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1151 b64 = (vm_offset_t)malloc_domainset(64 + 63,
1152 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1154 pc->pc_mds_buf64 = (void *)roundup2(b64, 64);
1155 bzero(pc->pc_mds_buf64, 64);
1159 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 &&
1160 (cpu_stdext_feature & CPUID_STDEXT_AVX512DQ) != 0)
1161 mds_handler = mds_handler_skl_avx512;
1162 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 &&
1163 (cpu_feature2 & CPUID2_AVX) != 0)
1164 mds_handler = mds_handler_skl_avx;
1166 mds_handler = mds_handler_skl_sse;
1167 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1168 ((CPUID_TO_MODEL(cpu_id) == 0x37 ||
1169 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1170 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1171 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1172 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1173 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1174 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1175 CPUID_TO_MODEL(cpu_id) == 0x65 ||
1176 CPUID_TO_MODEL(cpu_id) == 0x75 ||
1177 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1178 CPUID_TO_MODEL(cpu_id) == 0x26 ||
1179 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1180 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1181 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1182 CPUID_TO_MODEL(cpu_id) == 0x7a))) {
1183 /* Silvermont, Airmont */
1186 if (pc->pc_mds_buf == NULL)
1187 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK);
1189 mds_handler = mds_handler_silvermont;
1192 mds_handler = mds_handler_void;
1197 hw_mds_recalculate_boot(void *arg __unused)
1200 hw_mds_recalculate();
1202 SYSINIT(mds_recalc, SI_SUB_SMP, SI_ORDER_ANY, hw_mds_recalculate_boot, NULL);
1205 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS)
1209 val = hw_mds_disable;
1210 error = sysctl_handle_int(oidp, &val, 0, req);
1211 if (error != 0 || req->newptr == NULL)
1213 if (val < 0 || val > 3)
1215 hw_mds_disable = val;
1216 hw_mds_recalculate();
1220 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
1221 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1222 sysctl_mds_disable_handler, "I",
1223 "Microarchitectural Data Sampling Mitigation "
1224 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
1226 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT |
1227 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1228 sysctl_mds_disable_handler, "I",
1229 "Microarchitectural Data Sampling Mitigation "
1230 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
1233 * Intel Transactional Memory Asynchronous Abort Mitigation
1239 TAA_NONE = 0, /* No mitigation enabled */
1240 TAA_TSX_DISABLE = 1, /* Disable TSX via MSR */
1241 TAA_VERW = 2, /* Use VERW mitigation */
1242 TAA_AUTO = 3, /* Automatically select the mitigation */
1244 /* The states below are not selectable by the operator */
1246 TAA_TAA_UC = 4, /* Mitigation present in microcode */
1247 TAA_NOT_PRESENT = 5 /* TSX is not present */
1251 taa_set(bool enable, bool all)
1254 x86_msr_op(MSR_IA32_TSX_CTRL,
1255 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1256 (all ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
1257 IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR,
1262 x86_taa_recalculate(void)
1264 static int taa_saved_mds_disable = 0;
1265 int taa_need = 0, taa_state = 0;
1266 int mds_disable = 0, need_mds_recalc = 0;
1268 /* Check CPUID.07h.EBX.HLE and RTM for the presence of TSX */
1269 if ((cpu_stdext_feature & CPUID_STDEXT_HLE) == 0 ||
1270 (cpu_stdext_feature & CPUID_STDEXT_RTM) == 0) {
1271 /* TSX is not present */
1272 x86_taa_state = TAA_NOT_PRESENT;
1276 /* Check to see what mitigation options the CPU gives us */
1277 if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TAA_NO) {
1278 /* CPU is not suseptible to TAA */
1279 taa_need = TAA_TAA_UC;
1280 } else if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TSX_CTRL) {
1282 * CPU can turn off TSX. This is the next best option
1283 * if TAA_NO hardware mitigation isn't present
1285 taa_need = TAA_TSX_DISABLE;
1287 /* No TSX/TAA specific remedies are available. */
1288 if (x86_taa_enable == TAA_TSX_DISABLE) {
1290 printf("TSX control not available\n");
1293 taa_need = TAA_VERW;
1296 /* Can we automatically take action, or are we being forced? */
1297 if (x86_taa_enable == TAA_AUTO)
1298 taa_state = taa_need;
1300 taa_state = x86_taa_enable;
1302 /* No state change, nothing to do */
1303 if (taa_state == x86_taa_state) {
1305 printf("No TSX change made\n");
1309 /* Does the MSR need to be turned on or off? */
1310 if (taa_state == TAA_TSX_DISABLE)
1311 taa_set(true, true);
1312 else if (x86_taa_state == TAA_TSX_DISABLE)
1313 taa_set(false, true);
1315 /* Does MDS need to be set to turn on VERW? */
1316 if (taa_state == TAA_VERW) {
1317 taa_saved_mds_disable = hw_mds_disable;
1318 mds_disable = hw_mds_disable = 1;
1319 need_mds_recalc = 1;
1320 } else if (x86_taa_state == TAA_VERW) {
1321 mds_disable = hw_mds_disable = taa_saved_mds_disable;
1322 need_mds_recalc = 1;
1324 if (need_mds_recalc) {
1325 hw_mds_recalculate();
1326 if (mds_disable != hw_mds_disable) {
1328 printf("Cannot change MDS state for TAA\n");
1329 /* Don't update our state */
1334 x86_taa_state = taa_state;
1339 taa_recalculate_boot(void * arg __unused)
1342 x86_taa_recalculate();
1344 SYSINIT(taa_recalc, SI_SUB_SMP, SI_ORDER_ANY, taa_recalculate_boot, NULL);
1346 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, taa,
1347 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1348 "TSX Asynchronous Abort Mitigation");
1351 sysctl_taa_handler(SYSCTL_HANDLER_ARGS)
1355 val = x86_taa_enable;
1356 error = sysctl_handle_int(oidp, &val, 0, req);
1357 if (error != 0 || req->newptr == NULL)
1359 if (val < TAA_NONE || val > TAA_AUTO)
1361 x86_taa_enable = val;
1362 x86_taa_recalculate();
1366 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT |
1367 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1368 sysctl_taa_handler, "I",
1369 "TAA Mitigation enablement control "
1370 "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO)");
1373 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS)
1377 switch (x86_taa_state) {
1381 case TAA_TSX_DISABLE:
1382 state = "TSX disabled";
1388 state = "Mitigated in microcode";
1390 case TAA_NOT_PRESENT:
1391 state = "TSX not present";
1397 return (SYSCTL_OUT(req, state, strlen(state)));
1400 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, state,
1401 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1402 sysctl_taa_state_handler, "A",
1403 "TAA Mitigation state");
1405 int __read_frequently cpu_flush_rsb_ctxsw;
1406 SYSCTL_INT(_machdep_mitigations, OID_AUTO, flush_rsb_ctxsw,
1407 CTLFLAG_RW | CTLFLAG_NOFETCH, &cpu_flush_rsb_ctxsw, 0,
1408 "Flush Return Stack Buffer on context switch");
1410 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, rngds,
1411 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1412 "MCU Optimization, disable RDSEED mitigation");
1414 int x86_rngds_mitg_enable = 1;
1416 x86_rngds_mitg_recalculate(bool all_cpus)
1418 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0)
1420 x86_msr_op(MSR_IA32_MCU_OPT_CTRL,
1421 (x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1422 (all_cpus ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
1423 IA32_RNGDS_MITG_DIS, NULL);
1427 sysctl_rngds_mitg_enable_handler(SYSCTL_HANDLER_ARGS)
1431 val = x86_rngds_mitg_enable;
1432 error = sysctl_handle_int(oidp, &val, 0, req);
1433 if (error != 0 || req->newptr == NULL)
1435 x86_rngds_mitg_enable = val;
1436 x86_rngds_mitg_recalculate(true);
1439 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT |
1440 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1441 sysctl_rngds_mitg_enable_handler, "I",
1442 "MCU Optimization, disabling RDSEED mitigation control "
1443 "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled)");
1446 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS)
1450 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) {
1451 state = "Not applicable";
1452 } else if (x86_rngds_mitg_enable == 0) {
1453 state = "RDSEED not serialized";
1455 state = "Mitigated";
1457 return (SYSCTL_OUT(req, state, strlen(state)));
1459 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, state,
1460 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1461 sysctl_rngds_state_handler, "A",
1462 "MCU Optimization state");
1465 * Enable and restore kernel text write permissions.
1466 * Callers must ensure that disable_wp()/restore_wp() are executed
1467 * without rescheduling on the same core.
1475 if ((cr0 & CR0_WP) == 0)
1477 load_cr0(cr0 & ~CR0_WP);
1482 restore_wp(bool old_wp)
1486 load_cr0(rcr0() | CR0_WP);
1490 acpi_get_fadt_bootflags(uint16_t *flagsp)
1493 ACPI_TABLE_FADT *fadt;
1494 vm_paddr_t physaddr;
1496 physaddr = acpi_find_table(ACPI_SIG_FADT);
1499 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT);
1502 *flagsp = fadt->BootFlags;
1503 acpi_unmap_table(fadt);
1510 DEFINE_IFUNC(, uint64_t, rdtsc_ordered, (void))
1512 bool cpu_is_amd = cpu_vendor_id == CPU_VENDOR_AMD ||
1513 cpu_vendor_id == CPU_VENDOR_HYGON;
1515 if ((amd_feature & AMDID_RDTSCP) != 0)
1517 else if ((cpu_feature & CPUID_SSE2) != 0)
1518 return (cpu_is_amd ? rdtsc_ordered_mfence :
1519 rdtsc_ordered_lfence);