2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include "opt_atpic.h"
45 #include "opt_compat.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_perfmon.h"
55 #include "opt_platform.h"
61 #include <sys/param.h>
63 #include <sys/systm.h>
67 #include <sys/kernel.h>
70 #include <sys/malloc.h>
71 #include <sys/mutex.h>
73 #include <sys/rwlock.h>
74 #include <sys/sched.h>
78 #include <sys/sysctl.h>
80 #include <machine/clock.h>
81 #include <machine/cpu.h>
82 #include <machine/cputypes.h>
83 #include <machine/specialreg.h>
84 #include <machine/md_var.h>
85 #include <machine/mp_watchdog.h>
87 #include <machine/perfmon.h>
89 #include <machine/tss.h>
91 #include <machine/smp.h>
94 #include <machine/elan_mmcr.h>
96 #include <x86/acpica_machdep.h>
99 #include <vm/vm_extern.h>
100 #include <vm/vm_kern.h>
101 #include <vm/vm_page.h>
102 #include <vm/vm_map.h>
103 #include <vm/vm_object.h>
104 #include <vm/vm_pager.h>
105 #include <vm/vm_param.h>
108 #include <isa/isareg.h>
111 #define STATE_RUNNING 0x0
112 #define STATE_MWAIT 0x1
113 #define STATE_SLEEPING 0x2
116 static u_int cpu_reset_proxyid;
117 static volatile u_int cpu_reset_proxy_active;
122 * Machine dependent boot() routine
124 * I haven't seen anything to put here yet
125 * Possibly some stuff might be grafted back here from boot()
133 * Flush the D-cache for non-DMA I/O so that the I-cache can
134 * be made coherent later.
137 cpu_flush_dcache(void *ptr, size_t len)
146 __asm __volatile("sti; hlt");
150 * Use mwait to pause execution while waiting for an interrupt or
151 * another thread to signal that there is more work.
153 * NOTE: Interrupts will cause a wakeup; however, this function does
154 * not enable interrupt handling. The caller is responsible to enable
158 acpi_cpu_idle_mwait(uint32_t mwait_hint)
163 * A comment in Linux patch claims that 'CPUs run faster with
164 * speculation protection disabled. All CPU threads in a core
165 * must disable speculation protection for it to be
166 * disabled. Disable it while we are idle so the other
167 * hyperthread can run fast.'
169 * XXXKIB. Software coordination mode should be supported,
170 * but all Intel CPUs provide hardware coordination.
173 state = (int *)PCPU_PTR(monitorbuf);
174 KASSERT(atomic_load_int(state) == STATE_SLEEPING,
175 ("cpu_mwait_cx: wrong monitorbuf state"));
176 atomic_store_int(state, STATE_MWAIT);
178 cpu_monitor(state, 0, 0);
179 if (atomic_load_int(state) == STATE_MWAIT)
180 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
184 * We should exit on any event that interrupts mwait, because
185 * that event might be a wanted interrupt.
187 atomic_store_int(state, STATE_RUNNING);
190 /* Get current clock frequency for the given cpu id. */
192 cpu_est_clockrate(int cpu_id, uint64_t *rate)
195 uint64_t acnt, mcnt, perf;
198 if (pcpu_find(cpu_id) == NULL || rate == NULL)
201 if ((cpu_feature & CPUID_TSC) == 0)
206 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
207 * DELAY(9) based logic fails.
209 if (tsc_is_invariant && !tsc_perf_stat)
214 /* Schedule ourselves on the indicated cpu. */
215 thread_lock(curthread);
216 sched_bind(curthread, cpu_id);
217 thread_unlock(curthread);
221 /* Calibrate by measuring a short delay. */
222 reg = intr_disable();
223 if (tsc_is_invariant) {
228 mcnt = rdmsr(MSR_MPERF);
229 acnt = rdmsr(MSR_APERF);
232 perf = 1000 * acnt / mcnt;
233 *rate = (tsc2 - tsc1) * perf;
239 *rate = (tsc2 - tsc1) * 1000;
244 thread_lock(curthread);
245 sched_unbind(curthread);
246 thread_unlock(curthread);
254 * Shutdown the CPU as much as possible
266 struct region_descriptor null_idt;
273 if (elan_mmcr != NULL)
274 elan_mmcr->RESCFG = 1;
277 if (cpu == CPU_GEODE1100) {
278 /* Attempt Geode's own reset */
279 outl(0xcf8, 0x80009044ul);
285 * Attempt to do a CPU reset via CPU reset port.
287 if ((inb(0x35) & 0xa0) != 0xa0) {
288 outb(0x37, 0x0f); /* SHUT0 = 0. */
289 outb(0x37, 0x0b); /* SHUT1 = 0. */
291 outb(0xf0, 0x00); /* Reset. */
293 #if !defined(BROKEN_KEYBOARD_RESET)
295 * Attempt to do a CPU reset via the keyboard controller,
296 * do not turn off GateA20, as any machine that fails
297 * to do the reset here would then end up in no man's land.
299 outb(IO_KBD + 4, 0xFE);
300 DELAY(500000); /* wait 0.5 sec to see if that did it */
304 * Attempt to force a reset via the Reset Control register at
305 * I/O port 0xcf9. Bit 2 forces a system reset when it
306 * transitions from 0 to 1. Bit 1 selects the type of reset
307 * to attempt: 0 selects a "soft" reset, and 1 selects a
308 * "hard" reset. We try a "hard" reset. The first write sets
309 * bit 1 to select a "hard" reset and clears bit 2. The
310 * second write forces a 0 -> 1 transition in bit 2 to trigger
315 DELAY(500000); /* wait 0.5 sec to see if that did it */
318 * Attempt to force a reset via the Fast A20 and Init register
319 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
320 * Bit 0 asserts INIT# when set to 1. We are careful to only
321 * preserve bit 1 while setting bit 0. We also must clear bit
322 * 0 before setting it if it isn't already clear.
327 outb(0x92, b & 0xfe);
329 DELAY(500000); /* wait 0.5 sec to see if that did it */
333 printf("No known reset method worked, attempting CPU shutdown\n");
334 DELAY(1000000); /* wait 1 sec for printf to complete */
337 null_idt.rd_limit = 0;
338 null_idt.rd_base = 0;
341 /* "good night, sweet prince .... <THUNK!>" */
350 cpu_reset_proxy(void)
353 cpu_reset_proxy_active = 1;
354 while (cpu_reset_proxy_active == 1)
355 ia32_pause(); /* Wait for other cpu to see that we've started */
357 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid);
372 CPU_CLR(PCPU_GET(cpuid), &map);
373 CPU_NAND(&map, &stopped_cpus);
374 if (!CPU_EMPTY(&map)) {
375 printf("cpu_reset: Stopping other CPUs\n");
379 if (PCPU_GET(cpuid) != 0) {
380 cpu_reset_proxyid = PCPU_GET(cpuid);
381 cpustop_restartfunc = cpu_reset_proxy;
382 cpu_reset_proxy_active = 0;
383 printf("cpu_reset: Restarting BSP\n");
385 /* Restart CPU #0. */
386 CPU_SETOF(0, &started_cpus);
390 while (cpu_reset_proxy_active == 0 && cnt < 10000000) {
392 cnt++; /* Wait for BSP to announce restart */
394 if (cpu_reset_proxy_active == 0) {
395 printf("cpu_reset: Failed to restart BSP\n");
397 cpu_reset_proxy_active = 2;
412 cpu_mwait_usable(void)
415 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
416 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
417 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
420 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
421 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
422 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
423 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
424 0, "Use MONITOR/MWAIT for short idle");
428 cpu_idle_acpi(sbintime_t sbt)
432 state = (int *)PCPU_PTR(monitorbuf);
433 atomic_store_int(state, STATE_SLEEPING);
435 /* See comments in cpu_idle_hlt(). */
437 if (sched_runnable())
439 else if (cpu_idle_hook)
443 atomic_store_int(state, STATE_RUNNING);
448 cpu_idle_hlt(sbintime_t sbt)
452 state = (int *)PCPU_PTR(monitorbuf);
453 atomic_store_int(state, STATE_SLEEPING);
456 * Since we may be in a critical section from cpu_idle(), if
457 * an interrupt fires during that critical section we may have
458 * a pending preemption. If the CPU halts, then that thread
459 * may not execute until a later interrupt awakens the CPU.
460 * To handle this race, check for a runnable thread after
461 * disabling interrupts and immediately return if one is
462 * found. Also, we must absolutely guarentee that hlt is
463 * the next instruction after sti. This ensures that any
464 * interrupt that fires after the call to disable_intr() will
465 * immediately awaken the CPU from hlt. Finally, please note
466 * that on x86 this works fine because of interrupts enabled only
467 * after the instruction following sti takes place, while IF is set
468 * to 1 immediately, allowing hlt instruction to acknowledge the
472 if (sched_runnable())
476 atomic_store_int(state, STATE_RUNNING);
480 cpu_idle_mwait(sbintime_t sbt)
484 state = (int *)PCPU_PTR(monitorbuf);
485 atomic_store_int(state, STATE_MWAIT);
487 /* See comments in cpu_idle_hlt(). */
489 if (sched_runnable()) {
490 atomic_store_int(state, STATE_RUNNING);
495 cpu_monitor(state, 0, 0);
496 if (atomic_load_int(state) == STATE_MWAIT)
497 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
500 atomic_store_int(state, STATE_RUNNING);
504 cpu_idle_spin(sbintime_t sbt)
509 state = (int *)PCPU_PTR(monitorbuf);
510 atomic_store_int(state, STATE_RUNNING);
513 * The sched_runnable() call is racy but as long as there is
514 * a loop missing it one time will have just a little impact if any
515 * (and it is much better than missing the check at all).
517 for (i = 0; i < 1000; i++) {
518 if (sched_runnable())
525 * C1E renders the local APIC timer dead, so we disable it by
526 * reading the Interrupt Pending Message register and clearing
527 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
530 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
531 * #32559 revision 3.00+
533 #define MSR_AMDK8_IPM 0xc0010055
534 #define AMDK8_SMIONCMPHALT (1ULL << 27)
535 #define AMDK8_C1EONCMPHALT (1ULL << 28)
536 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
539 cpu_probe_amdc1e(void)
543 * Detect the presence of C1E capability mostly on latest
544 * dual-cores (or future) k8 family.
546 if (cpu_vendor_id == CPU_VENDOR_AMD &&
547 (cpu_id & 0x00000f00) == 0x00000f00 &&
548 (cpu_id & 0x0fff0000) >= 0x00040000) {
549 cpu_ident_amdc1e = 1;
553 #if defined(__i386__) && defined(PC98)
554 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_hlt;
556 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
565 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
568 ap_watchdog(PCPU_GET(cpuid));
571 /* If we are busy - try to use fast methods. */
573 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
574 cpu_idle_mwait(busy);
579 /* If we have time - switch timers into idle mode. */
582 sbt = cpu_idleclock();
585 /* Apply AMD APIC timer C1E workaround. */
586 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) {
587 msr = rdmsr(MSR_AMDK8_IPM);
588 if (msr & AMDK8_CMPHALT)
589 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
592 /* Call main idle method. */
595 /* Switch timers back into active mode. */
601 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
605 static int cpu_idle_apl31_workaround;
606 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW,
607 &cpu_idle_apl31_workaround, 0,
608 "Apollo Lake APL31 MWAIT bug workaround");
611 cpu_idle_wakeup(int cpu)
615 state = (int *)pcpu_find(cpu)->pc_monitorbuf;
616 switch (atomic_load_int(state)) {
620 atomic_store_int(state, STATE_RUNNING);
621 return (cpu_idle_apl31_workaround ? 0 : 1);
625 panic("bad monitor state");
631 * Ordered by speed/power consumption.
638 { .id_fn = cpu_idle_spin, .id_name = "spin" },
639 { .id_fn = cpu_idle_mwait, .id_name = "mwait",
640 .id_cpuid2_flag = CPUID2_MON },
641 { .id_fn = cpu_idle_hlt, .id_name = "hlt" },
642 #if !defined(__i386__) || !defined(PC98)
643 { .id_fn = cpu_idle_acpi, .id_name = "acpi" },
648 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
654 avail = malloc(256, M_TEMP, M_WAITOK);
656 for (i = 0; i < nitems(idle_tbl); i++) {
657 if (idle_tbl[i].id_cpuid2_flag != 0 &&
658 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
660 #if !defined(__i386__) || !defined(PC98)
661 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
662 cpu_idle_hook == NULL)
665 p += sprintf(p, "%s%s", p != avail ? ", " : "",
666 idle_tbl[i].id_name);
668 error = sysctl_handle_string(oidp, avail, 0, req);
673 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
674 0, 0, idle_sysctl_available, "A", "list of available idle functions");
677 cpu_idle_selector(const char *new_idle_name)
681 for (i = 0; i < nitems(idle_tbl); i++) {
682 if (idle_tbl[i].id_cpuid2_flag != 0 &&
683 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
685 #if !defined(__i386__) || !defined(PC98)
686 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
687 cpu_idle_hook == NULL)
690 if (strcmp(idle_tbl[i].id_name, new_idle_name))
692 cpu_idle_fn = idle_tbl[i].id_fn;
694 printf("CPU idle set to %s\n", idle_tbl[i].id_name);
701 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
707 for (i = 0; i < nitems(idle_tbl); i++) {
708 if (idle_tbl[i].id_fn == cpu_idle_fn) {
709 p = idle_tbl[i].id_name;
713 strncpy(buf, p, sizeof(buf));
714 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
715 if (error != 0 || req->newptr == NULL)
717 return (cpu_idle_selector(buf) ? 0 : EINVAL);
720 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
721 cpu_idle_sysctl, "A", "currently selected idle function");
724 cpu_idle_tun(void *unused __unused)
728 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
729 cpu_idle_selector(tunvar);
730 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
732 * Apollo Lake errata APL31 (public errata APL30).
733 * Stores to the armed address range may not trigger
734 * MWAIT to resume execution. OS needs to use
735 * interrupts to wake processors from MWAIT-induced
738 cpu_idle_apl31_workaround = 1;
740 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround);
742 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL);
744 static int panic_on_nmi = 1;
745 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
748 int nmi_is_broadcast = 1;
749 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
750 &nmi_is_broadcast, 0,
751 "Chipset NMI is broadcast");
754 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN,
761 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
764 /* machine/parity/power fail/"kitchen sink" faults */
765 if (isa_nmi(frame->tf_err) == 0) {
768 * NMI can be hooked up to a pushbutton for debugging.
771 printf("NMI/cpu%d ... going to debugger\n", cpu);
772 kdb_trap(type, 0, frame);
775 } else if (panic_on_nmi) {
776 panic("NMI indicates hardware failure");
782 nmi_handle_intr(u_int type, struct trapframe *frame)
787 if (nmi_is_broadcast) {
788 nmi_call_kdb_smp(type, frame);
792 nmi_call_kdb(PCPU_GET(cpuid), type, frame);
797 int hw_ibrs_disable = 1;
799 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
800 "Indirect Branch Restricted Speculation active");
803 hw_ibrs_recalculate(void)
807 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
808 if (hw_ibrs_disable) {
809 v = rdmsr(MSR_IA32_SPEC_CTRL);
810 v &= ~(uint64_t)IA32_SPEC_CTRL_IBRS;
811 wrmsr(MSR_IA32_SPEC_CTRL, v);
813 v = rdmsr(MSR_IA32_SPEC_CTRL);
814 v |= IA32_SPEC_CTRL_IBRS;
815 wrmsr(MSR_IA32_SPEC_CTRL, v);
819 hw_ibrs_active = (cpu_stdext_feature3 & CPUID_STDEXT3_IBPB) != 0 &&
824 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS)
828 val = hw_ibrs_disable;
829 error = sysctl_handle_int(oidp, &val, 0, req);
830 if (error != 0 || req->newptr == NULL)
832 hw_ibrs_disable = val != 0;
833 hw_ibrs_recalculate();
836 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
837 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
838 "Disable Indirect Branch Restricted Speculation");