2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 #include "opt_atpic.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_platform.h"
59 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/domainset.h>
66 #include <sys/kernel.h>
69 #include <sys/malloc.h>
70 #include <sys/mutex.h>
72 #include <sys/rwlock.h>
73 #include <sys/sched.h>
75 #include <sys/sysctl.h>
77 #include <machine/clock.h>
78 #include <machine/cpu.h>
79 #include <machine/cputypes.h>
80 #include <machine/specialreg.h>
81 #include <machine/md_var.h>
82 #include <machine/mp_watchdog.h>
83 #include <machine/tss.h>
85 #include <machine/smp.h>
88 #include <machine/elan_mmcr.h>
90 #include <x86/acpica_machdep.h>
93 #include <vm/vm_extern.h>
94 #include <vm/vm_kern.h>
95 #include <vm/vm_page.h>
96 #include <vm/vm_map.h>
97 #include <vm/vm_object.h>
98 #include <vm/vm_pager.h>
99 #include <vm/vm_param.h>
101 #include <isa/isareg.h>
103 #include <contrib/dev/acpica/include/acpi.h>
105 #define STATE_RUNNING 0x0
106 #define STATE_MWAIT 0x1
107 #define STATE_SLEEPING 0x2
110 static u_int cpu_reset_proxyid;
111 static volatile u_int cpu_reset_proxy_active;
115 * Automatically initialized per CPU errata in cpu_idle_tun below.
117 bool mwait_cpustop_broken = false;
118 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN,
119 &mwait_cpustop_broken, 0,
120 "Can not reliably wake MONITOR/MWAIT cpus without interrupts");
123 * Machine dependent boot() routine
125 * I haven't seen anything to put here yet
126 * Possibly some stuff might be grafted back here from boot()
134 * Flush the D-cache for non-DMA I/O so that the I-cache can
135 * be made coherent later.
138 cpu_flush_dcache(void *ptr, size_t len)
147 __asm __volatile("sti; hlt");
151 * Use mwait to pause execution while waiting for an interrupt or
152 * another thread to signal that there is more work.
154 * NOTE: Interrupts will cause a wakeup; however, this function does
155 * not enable interrupt handling. The caller is responsible to enable
159 acpi_cpu_idle_mwait(uint32_t mwait_hint)
165 * A comment in Linux patch claims that 'CPUs run faster with
166 * speculation protection disabled. All CPU threads in a core
167 * must disable speculation protection for it to be
168 * disabled. Disable it while we are idle so the other
169 * hyperthread can run fast.'
171 * XXXKIB. Software coordination mode should be supported,
172 * but all Intel CPUs provide hardware coordination.
175 state = &PCPU_PTR(monitorbuf)->idle_state;
176 KASSERT(atomic_load_int(state) == STATE_SLEEPING,
177 ("cpu_mwait_cx: wrong monitorbuf state"));
178 atomic_store_int(state, STATE_MWAIT);
179 if (PCPU_GET(ibpb_set) || hw_ssb_active) {
180 v = rdmsr(MSR_IA32_SPEC_CTRL);
181 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS |
182 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD));
186 cpu_monitor(state, 0, 0);
187 if (atomic_load_int(state) == STATE_MWAIT)
188 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
191 * SSB cannot be disabled while we sleep, or rather, if it was
192 * disabled, the sysctl thread will bind to our cpu to tweak
196 wrmsr(MSR_IA32_SPEC_CTRL, v);
199 * We should exit on any event that interrupts mwait, because
200 * that event might be a wanted interrupt.
202 atomic_store_int(state, STATE_RUNNING);
205 /* Get current clock frequency for the given cpu id. */
207 cpu_est_clockrate(int cpu_id, uint64_t *rate)
210 uint64_t acnt, mcnt, perf;
213 if (pcpu_find(cpu_id) == NULL || rate == NULL)
216 if ((cpu_feature & CPUID_TSC) == 0)
221 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
222 * DELAY(9) based logic fails.
224 if (tsc_is_invariant && !tsc_perf_stat)
229 /* Schedule ourselves on the indicated cpu. */
230 thread_lock(curthread);
231 sched_bind(curthread, cpu_id);
232 thread_unlock(curthread);
236 /* Calibrate by measuring a short delay. */
237 reg = intr_disable();
238 if (tsc_is_invariant) {
243 mcnt = rdmsr(MSR_MPERF);
244 acnt = rdmsr(MSR_APERF);
247 perf = 1000 * acnt / mcnt;
248 *rate = (tsc2 - tsc1) * perf;
254 *rate = (tsc2 - tsc1) * 1000;
259 thread_lock(curthread);
260 sched_unbind(curthread);
261 thread_unlock(curthread);
269 * Shutdown the CPU as much as possible
281 struct region_descriptor null_idt;
286 if (elan_mmcr != NULL)
287 elan_mmcr->RESCFG = 1;
290 if (cpu == CPU_GEODE1100) {
291 /* Attempt Geode's own reset */
292 outl(0xcf8, 0x80009044ul);
296 #if !defined(BROKEN_KEYBOARD_RESET)
298 * Attempt to do a CPU reset via the keyboard controller,
299 * do not turn off GateA20, as any machine that fails
300 * to do the reset here would then end up in no man's land.
302 outb(IO_KBD + 4, 0xFE);
303 DELAY(500000); /* wait 0.5 sec to see if that did it */
307 * Attempt to force a reset via the Reset Control register at
308 * I/O port 0xcf9. Bit 2 forces a system reset when it
309 * transitions from 0 to 1. Bit 1 selects the type of reset
310 * to attempt: 0 selects a "soft" reset, and 1 selects a
311 * "hard" reset. We try a "hard" reset. The first write sets
312 * bit 1 to select a "hard" reset and clears bit 2. The
313 * second write forces a 0 -> 1 transition in bit 2 to trigger
318 DELAY(500000); /* wait 0.5 sec to see if that did it */
321 * Attempt to force a reset via the Fast A20 and Init register
322 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
323 * Bit 0 asserts INIT# when set to 1. We are careful to only
324 * preserve bit 1 while setting bit 0. We also must clear bit
325 * 0 before setting it if it isn't already clear.
330 outb(0x92, b & 0xfe);
332 DELAY(500000); /* wait 0.5 sec to see if that did it */
335 printf("No known reset method worked, attempting CPU shutdown\n");
336 DELAY(1000000); /* wait 1 sec for printf to complete */
339 null_idt.rd_limit = 0;
340 null_idt.rd_base = 0;
343 /* "good night, sweet prince .... <THUNK!>" */
352 cpu_reset_proxy(void)
355 cpu_reset_proxy_active = 1;
356 while (cpu_reset_proxy_active == 1)
357 ia32_pause(); /* Wait for other cpu to see that we've started */
359 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid);
369 struct monitorbuf *mb;
375 CPU_CLR(PCPU_GET(cpuid), &map);
376 CPU_NAND(&map, &stopped_cpus);
377 if (!CPU_EMPTY(&map)) {
378 printf("cpu_reset: Stopping other CPUs\n");
382 if (PCPU_GET(cpuid) != 0) {
383 cpu_reset_proxyid = PCPU_GET(cpuid);
384 cpustop_restartfunc = cpu_reset_proxy;
385 cpu_reset_proxy_active = 0;
386 printf("cpu_reset: Restarting BSP\n");
388 /* Restart CPU #0. */
389 CPU_SETOF(0, &started_cpus);
390 mb = &pcpu_find(0)->pc_monitorbuf;
391 atomic_store_int(&mb->stop_state,
392 MONITOR_STOPSTATE_RUNNING);
396 while (cpu_reset_proxy_active == 0 && cnt < 10000000) {
398 cnt++; /* Wait for BSP to announce restart */
400 if (cpu_reset_proxy_active == 0) {
401 printf("cpu_reset: Failed to restart BSP\n");
403 cpu_reset_proxy_active = 2;
418 cpu_mwait_usable(void)
421 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
422 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
423 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
426 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
427 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
428 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
429 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
430 0, "Use MONITOR/MWAIT for short idle");
433 cpu_idle_acpi(sbintime_t sbt)
437 state = &PCPU_PTR(monitorbuf)->idle_state;
438 atomic_store_int(state, STATE_SLEEPING);
440 /* See comments in cpu_idle_hlt(). */
442 if (sched_runnable())
444 else if (cpu_idle_hook)
448 atomic_store_int(state, STATE_RUNNING);
452 cpu_idle_hlt(sbintime_t sbt)
456 state = &PCPU_PTR(monitorbuf)->idle_state;
457 atomic_store_int(state, STATE_SLEEPING);
460 * Since we may be in a critical section from cpu_idle(), if
461 * an interrupt fires during that critical section we may have
462 * a pending preemption. If the CPU halts, then that thread
463 * may not execute until a later interrupt awakens the CPU.
464 * To handle this race, check for a runnable thread after
465 * disabling interrupts and immediately return if one is
466 * found. Also, we must absolutely guarentee that hlt is
467 * the next instruction after sti. This ensures that any
468 * interrupt that fires after the call to disable_intr() will
469 * immediately awaken the CPU from hlt. Finally, please note
470 * that on x86 this works fine because of interrupts enabled only
471 * after the instruction following sti takes place, while IF is set
472 * to 1 immediately, allowing hlt instruction to acknowledge the
476 if (sched_runnable())
480 atomic_store_int(state, STATE_RUNNING);
484 cpu_idle_mwait(sbintime_t sbt)
488 state = &PCPU_PTR(monitorbuf)->idle_state;
489 atomic_store_int(state, STATE_MWAIT);
491 /* See comments in cpu_idle_hlt(). */
493 if (sched_runnable()) {
494 atomic_store_int(state, STATE_RUNNING);
499 cpu_monitor(state, 0, 0);
500 if (atomic_load_int(state) == STATE_MWAIT)
501 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
504 atomic_store_int(state, STATE_RUNNING);
508 cpu_idle_spin(sbintime_t sbt)
513 state = &PCPU_PTR(monitorbuf)->idle_state;
514 atomic_store_int(state, STATE_RUNNING);
517 * The sched_runnable() call is racy but as long as there is
518 * a loop missing it one time will have just a little impact if any
519 * (and it is much better than missing the check at all).
521 for (i = 0; i < 1000; i++) {
522 if (sched_runnable())
529 * C1E renders the local APIC timer dead, so we disable it by
530 * reading the Interrupt Pending Message register and clearing
531 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
534 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
535 * #32559 revision 3.00+
537 #define MSR_AMDK8_IPM 0xc0010055
538 #define AMDK8_SMIONCMPHALT (1ULL << 27)
539 #define AMDK8_C1EONCMPHALT (1ULL << 28)
540 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
543 cpu_probe_amdc1e(void)
547 * Detect the presence of C1E capability mostly on latest
548 * dual-cores (or future) k8 family.
550 if (cpu_vendor_id == CPU_VENDOR_AMD &&
551 (cpu_id & 0x00000f00) == 0x00000f00 &&
552 (cpu_id & 0x0fff0000) >= 0x00040000) {
553 cpu_ident_amdc1e = 1;
557 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
565 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
568 ap_watchdog(PCPU_GET(cpuid));
571 /* If we are busy - try to use fast methods. */
573 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
574 cpu_idle_mwait(busy);
579 /* If we have time - switch timers into idle mode. */
582 sbt = cpu_idleclock();
585 /* Apply AMD APIC timer C1E workaround. */
586 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) {
587 msr = rdmsr(MSR_AMDK8_IPM);
588 if (msr & AMDK8_CMPHALT)
589 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
592 /* Call main idle method. */
595 /* Switch timers back into active mode. */
601 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
605 static int cpu_idle_apl31_workaround;
606 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW,
607 &cpu_idle_apl31_workaround, 0,
608 "Apollo Lake APL31 MWAIT bug workaround");
611 cpu_idle_wakeup(int cpu)
613 struct monitorbuf *mb;
616 mb = &pcpu_find(cpu)->pc_monitorbuf;
617 state = &mb->idle_state;
618 switch (atomic_load_int(state)) {
622 atomic_store_int(state, STATE_RUNNING);
623 return (cpu_idle_apl31_workaround ? 0 : 1);
627 panic("bad monitor state");
633 * Ordered by speed/power consumption.
640 { .id_fn = cpu_idle_spin, .id_name = "spin" },
641 { .id_fn = cpu_idle_mwait, .id_name = "mwait",
642 .id_cpuid2_flag = CPUID2_MON },
643 { .id_fn = cpu_idle_hlt, .id_name = "hlt" },
644 { .id_fn = cpu_idle_acpi, .id_name = "acpi" },
648 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
654 avail = malloc(256, M_TEMP, M_WAITOK);
656 for (i = 0; i < nitems(idle_tbl); i++) {
657 if (idle_tbl[i].id_cpuid2_flag != 0 &&
658 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
660 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
661 cpu_idle_hook == NULL)
663 p += sprintf(p, "%s%s", p != avail ? ", " : "",
664 idle_tbl[i].id_name);
666 error = sysctl_handle_string(oidp, avail, 0, req);
671 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
672 0, 0, idle_sysctl_available, "A", "list of available idle functions");
675 cpu_idle_selector(const char *new_idle_name)
679 for (i = 0; i < nitems(idle_tbl); i++) {
680 if (idle_tbl[i].id_cpuid2_flag != 0 &&
681 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
683 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
684 cpu_idle_hook == NULL)
686 if (strcmp(idle_tbl[i].id_name, new_idle_name))
688 cpu_idle_fn = idle_tbl[i].id_fn;
690 printf("CPU idle set to %s\n", idle_tbl[i].id_name);
697 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
703 for (i = 0; i < nitems(idle_tbl); i++) {
704 if (idle_tbl[i].id_fn == cpu_idle_fn) {
705 p = idle_tbl[i].id_name;
709 strncpy(buf, p, sizeof(buf));
710 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
711 if (error != 0 || req->newptr == NULL)
713 return (cpu_idle_selector(buf) ? 0 : EINVAL);
716 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
717 cpu_idle_sysctl, "A", "currently selected idle function");
720 cpu_idle_tun(void *unused __unused)
724 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
725 cpu_idle_selector(tunvar);
726 else if (cpu_vendor_id == CPU_VENDOR_AMD &&
727 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
728 /* Ryzen erratas 1057, 1109. */
729 cpu_idle_selector("hlt");
731 mwait_cpustop_broken = true;
734 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
736 * Apollo Lake errata APL31 (public errata APL30).
737 * Stores to the armed address range may not trigger
738 * MWAIT to resume execution. OS needs to use
739 * interrupts to wake processors from MWAIT-induced
742 cpu_idle_apl31_workaround = 1;
743 mwait_cpustop_broken = true;
745 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround);
747 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL);
749 static int panic_on_nmi = 1;
750 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
752 "Panic on NMI raised by hardware failure");
753 int nmi_is_broadcast = 1;
754 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
755 &nmi_is_broadcast, 0,
756 "Chipset NMI is broadcast");
759 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN,
761 "Go to KDB on NMI with unknown source");
765 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
767 bool claimed = false;
770 /* machine/parity/power fail/"kitchen sink" faults */
771 if (isa_nmi(frame->tf_err)) {
774 panic("NMI indicates hardware failure");
778 if (!claimed && kdb_on_nmi) {
780 * NMI can be hooked up to a pushbutton for debugging.
782 printf("NMI/cpu%d ... going to debugger\n", cpu);
783 kdb_trap(type, 0, frame);
789 nmi_handle_intr(u_int type, struct trapframe *frame)
793 if (nmi_is_broadcast) {
794 nmi_call_kdb_smp(type, frame);
798 nmi_call_kdb(PCPU_GET(cpuid), type, frame);
802 int hw_ibrs_disable = 1;
804 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
805 "Indirect Branch Restricted Speculation active");
808 hw_ibrs_recalculate(void)
812 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
813 if (hw_ibrs_disable) {
814 v = rdmsr(MSR_IA32_SPEC_CTRL);
815 v &= ~(uint64_t)IA32_SPEC_CTRL_IBRS;
816 wrmsr(MSR_IA32_SPEC_CTRL, v);
818 v = rdmsr(MSR_IA32_SPEC_CTRL);
819 v |= IA32_SPEC_CTRL_IBRS;
820 wrmsr(MSR_IA32_SPEC_CTRL, v);
824 hw_ibrs_active = (cpu_stdext_feature3 & CPUID_STDEXT3_IBPB) != 0 &&
829 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS)
833 val = hw_ibrs_disable;
834 error = sysctl_handle_int(oidp, &val, 0, req);
835 if (error != 0 || req->newptr == NULL)
837 hw_ibrs_disable = val != 0;
838 hw_ibrs_recalculate();
841 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
842 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
843 "Disable Indirect Branch Restricted Speculation");
848 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD,
850 "Speculative Store Bypass Disable active");
853 hw_ssb_set_one(bool enable)
857 v = rdmsr(MSR_IA32_SPEC_CTRL);
859 v |= (uint64_t)IA32_SPEC_CTRL_SSBD;
861 v &= ~(uint64_t)IA32_SPEC_CTRL_SSBD;
862 wrmsr(MSR_IA32_SPEC_CTRL, v);
866 hw_ssb_set(bool enable, bool for_all_cpus)
869 int bound_cpu, i, is_bound;
871 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) {
875 hw_ssb_active = enable;
879 is_bound = sched_is_bound(td);
880 bound_cpu = td->td_oncpu;
883 hw_ssb_set_one(enable);
886 sched_bind(td, bound_cpu);
891 hw_ssb_set_one(enable);
896 hw_ssb_recalculate(bool all_cpus)
899 switch (hw_ssb_disable) {
904 hw_ssb_set(false, all_cpus);
907 hw_ssb_set(true, all_cpus);
910 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ?
911 false : true, all_cpus);
917 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS)
921 val = hw_ssb_disable;
922 error = sysctl_handle_int(oidp, &val, 0, req);
923 if (error != 0 || req->newptr == NULL)
925 hw_ssb_disable = val;
926 hw_ssb_recalculate(true);
929 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
930 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
931 hw_ssb_disable_handler, "I",
932 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
937 * Handler for Microarchitectural Data Sampling issues. Really not a
938 * pointer to C function: on amd64 the code must not change any CPU
939 * architectural state except possibly %rflags. Also, it is always
940 * called with interrupts disabled.
942 void (*mds_handler)(void);
943 void mds_handler_void(void);
944 void mds_handler_verw(void);
945 void mds_handler_ivb(void);
946 void mds_handler_bdw(void);
947 void mds_handler_skl_sse(void);
948 void mds_handler_skl_avx(void);
949 void mds_handler_skl_avx512(void);
950 void mds_handler_silvermont(void);
953 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS)
957 if (mds_handler == mds_handler_void)
959 else if (mds_handler == mds_handler_verw)
961 else if (mds_handler == mds_handler_ivb)
962 state = "software IvyBridge";
963 else if (mds_handler == mds_handler_bdw)
964 state = "software Broadwell";
965 else if (mds_handler == mds_handler_skl_sse)
966 state = "software Skylake SSE";
967 else if (mds_handler == mds_handler_skl_avx)
968 state = "software Skylake AVX";
969 else if (mds_handler == mds_handler_skl_avx512)
970 state = "software Skylake AVX512";
971 else if (mds_handler == mds_handler_silvermont)
972 state = "software Silvermont";
975 return (SYSCTL_OUT(req, state, strlen(state)));
978 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state,
979 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
980 sysctl_hw_mds_disable_state_handler, "A",
981 "Microarchitectural Data Sampling Mitigation state");
983 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512");
986 hw_mds_recalculate(void)
994 * Allow user to force VERW variant even if MD_CLEAR is not
995 * reported. For instance, hypervisor might unknowingly
996 * filter the cap out.
997 * For the similar reasons, and for testing, allow to enable
998 * mitigation even for RDCL_NO or MDS_NO caps.
1000 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 ||
1001 ((cpu_ia32_arch_caps & (IA32_ARCH_CAP_RDCL_NO |
1002 IA32_ARCH_CAP_MDS_NO)) != 0 && hw_mds_disable == 3)) {
1003 mds_handler = mds_handler_void;
1004 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 &&
1005 hw_mds_disable == 3) || hw_mds_disable == 1) {
1006 mds_handler = mds_handler_verw;
1007 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1008 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e ||
1009 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a ||
1010 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 ||
1011 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d ||
1012 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e ||
1013 CPUID_TO_MODEL(cpu_id) == 0x3a) &&
1014 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1016 * Nehalem, SandyBridge, IvyBridge
1020 if (pc->pc_mds_buf == NULL) {
1021 pc->pc_mds_buf = malloc_domainset(672, M_TEMP,
1022 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1023 bzero(pc->pc_mds_buf, 16);
1026 mds_handler = mds_handler_ivb;
1027 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1028 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c ||
1029 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 ||
1030 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f ||
1031 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) &&
1032 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1034 * Haswell, Broadwell
1038 if (pc->pc_mds_buf == NULL) {
1039 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP,
1040 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1041 bzero(pc->pc_mds_buf, 16);
1044 mds_handler = mds_handler_bdw;
1045 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1046 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id &
1047 CPUID_STEPPING) <= 5) ||
1048 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e ||
1049 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id &
1050 CPUID_STEPPING) <= 0xb) ||
1051 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id &
1052 CPUID_STEPPING) <= 0xc)) &&
1053 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1055 * Skylake, KabyLake, CoffeeLake, WhiskeyLake,
1060 if (pc->pc_mds_buf == NULL) {
1061 pc->pc_mds_buf = malloc_domainset(6 * 1024,
1062 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1064 b64 = (vm_offset_t)malloc_domainset(64 + 63,
1065 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1067 pc->pc_mds_buf64 = (void *)roundup2(b64, 64);
1068 bzero(pc->pc_mds_buf64, 64);
1072 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 &&
1073 (cpu_stdext_feature2 & CPUID_STDEXT_AVX512DQ) != 0)
1074 mds_handler = mds_handler_skl_avx512;
1075 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 &&
1076 (cpu_feature2 & CPUID2_AVX) != 0)
1077 mds_handler = mds_handler_skl_avx;
1079 mds_handler = mds_handler_skl_sse;
1080 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1081 ((CPUID_TO_MODEL(cpu_id) == 0x37 ||
1082 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1083 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1084 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1085 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1086 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1087 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1088 CPUID_TO_MODEL(cpu_id) == 0x65 ||
1089 CPUID_TO_MODEL(cpu_id) == 0x75 ||
1090 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1091 CPUID_TO_MODEL(cpu_id) == 0x26 ||
1092 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1093 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1094 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1095 CPUID_TO_MODEL(cpu_id) == 0x7a))) {
1096 /* Silvermont, Airmont */
1099 if (pc->pc_mds_buf == NULL)
1100 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK);
1102 mds_handler = mds_handler_silvermont;
1105 mds_handler = mds_handler_void;
1110 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS)
1114 val = hw_mds_disable;
1115 error = sysctl_handle_int(oidp, &val, 0, req);
1116 if (error != 0 || req->newptr == NULL)
1118 if (val < 0 || val > 3)
1120 hw_mds_disable = val;
1121 hw_mds_recalculate();
1125 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
1126 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1127 sysctl_mds_disable_handler, "I",
1128 "Microarchitectural Data Sampling Mitigation "
1129 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
1132 * Enable and restore kernel text write permissions.
1133 * Callers must ensure that disable_wp()/restore_wp() are executed
1134 * without rescheduling on the same core.
1142 if ((cr0 & CR0_WP) == 0)
1144 load_cr0(cr0 & ~CR0_WP);
1149 restore_wp(bool old_wp)
1153 load_cr0(rcr0() | CR0_WP);
1157 acpi_get_fadt_bootflags(uint16_t *flagsp)
1160 ACPI_TABLE_FADT *fadt;
1161 vm_paddr_t physaddr;
1163 physaddr = acpi_find_table(ACPI_SIG_FADT);
1166 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT);
1169 *flagsp = fadt->BootFlags;
1170 acpi_unmap_table(fadt);