2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 #include "opt_atpic.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_platform.h"
59 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/domainset.h>
66 #include <sys/kernel.h>
69 #include <sys/malloc.h>
70 #include <sys/mutex.h>
72 #include <sys/rwlock.h>
73 #include <sys/sched.h>
75 #include <sys/sysctl.h>
77 #include <machine/clock.h>
78 #include <machine/cpu.h>
79 #include <machine/cpufunc.h>
80 #include <machine/cputypes.h>
81 #include <machine/specialreg.h>
82 #include <machine/md_var.h>
83 #include <machine/mp_watchdog.h>
84 #include <machine/tss.h>
86 #include <machine/smp.h>
89 #include <machine/elan_mmcr.h>
91 #include <x86/acpica_machdep.h>
92 #include <x86/ifunc.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_kern.h>
97 #include <vm/vm_page.h>
98 #include <vm/vm_map.h>
99 #include <vm/vm_object.h>
100 #include <vm/vm_pager.h>
101 #include <vm/vm_param.h>
103 #include <isa/isareg.h>
105 #include <contrib/dev/acpica/include/acpi.h>
107 #define STATE_RUNNING 0x0
108 #define STATE_MWAIT 0x1
109 #define STATE_SLEEPING 0x2
112 static u_int cpu_reset_proxyid;
113 static volatile u_int cpu_reset_proxy_active;
117 SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0,
118 "System firmware boot method");
128 x86_msr_op_one(void *argp)
130 struct msr_op_arg *a;
146 wrmsr(a->msr, a->arg1);
155 #define MSR_OP_EXMODE_MASK 0xf0000000
156 #define MSR_OP_OP_MASK 0x000000ff
157 #define MSR_OP_GET_CPUID(x) (((x) & ~MSR_OP_EXMODE_MASK) >> 8)
160 x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res)
166 int bound_cpu, cpu, i, is_bound;
168 a.op = op & MSR_OP_OP_MASK;
169 MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR ||
170 a.op == MSR_OP_WRITE || a.op == MSR_OP_READ);
171 exmode = op & MSR_OP_EXMODE_MASK;
172 MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED_ALL ||
173 exmode == MSR_OP_SCHED_ONE || exmode == MSR_OP_RENDEZVOUS_ALL ||
174 exmode == MSR_OP_RENDEZVOUS_ONE);
182 case MSR_OP_SCHED_ALL:
185 is_bound = sched_is_bound(td);
186 bound_cpu = td->td_oncpu;
192 sched_bind(td, bound_cpu);
197 case MSR_OP_SCHED_ONE:
199 cpu = MSR_OP_GET_CPUID(op);
201 is_bound = sched_is_bound(td);
202 bound_cpu = td->td_oncpu;
203 if (!is_bound || bound_cpu != cpu)
207 if (bound_cpu != cpu)
208 sched_bind(td, bound_cpu);
214 case MSR_OP_RENDEZVOUS_ALL:
215 smp_rendezvous(smp_no_rendezvous_barrier, x86_msr_op_one,
216 smp_no_rendezvous_barrier, &a);
218 case MSR_OP_RENDEZVOUS_ONE:
219 cpu = MSR_OP_GET_CPUID(op);
220 CPU_SETOF(cpu, &set);
221 smp_rendezvous_cpus(set, smp_no_rendezvous_barrier,
222 x86_msr_op_one, smp_no_rendezvous_barrier, &a);
228 * Automatically initialized per CPU errata in cpu_idle_tun below.
230 bool mwait_cpustop_broken = false;
231 SYSCTL_BOOL(_machdep, OID_AUTO, mwait_cpustop_broken, CTLFLAG_RDTUN,
232 &mwait_cpustop_broken, 0,
233 "Can not reliably wake MONITOR/MWAIT cpus without interrupts");
236 * Flush the D-cache for non-DMA I/O so that the I-cache can
237 * be made coherent later.
240 cpu_flush_dcache(void *ptr, size_t len)
249 __asm __volatile("sti; hlt");
253 * Use mwait to pause execution while waiting for an interrupt or
254 * another thread to signal that there is more work.
256 * NOTE: Interrupts will cause a wakeup; however, this function does
257 * not enable interrupt handling. The caller is responsible to enable
261 acpi_cpu_idle_mwait(uint32_t mwait_hint)
267 * A comment in Linux patch claims that 'CPUs run faster with
268 * speculation protection disabled. All CPU threads in a core
269 * must disable speculation protection for it to be
270 * disabled. Disable it while we are idle so the other
271 * hyperthread can run fast.'
273 * XXXKIB. Software coordination mode should be supported,
274 * but all Intel CPUs provide hardware coordination.
277 state = &PCPU_PTR(monitorbuf)->idle_state;
278 KASSERT(atomic_load_int(state) == STATE_SLEEPING,
279 ("cpu_mwait_cx: wrong monitorbuf state"));
280 atomic_store_int(state, STATE_MWAIT);
281 if (PCPU_GET(ibpb_set) || hw_ssb_active) {
282 v = rdmsr(MSR_IA32_SPEC_CTRL);
283 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS |
284 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD));
288 cpu_monitor(state, 0, 0);
289 if (atomic_load_int(state) == STATE_MWAIT)
290 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
293 * SSB cannot be disabled while we sleep, or rather, if it was
294 * disabled, the sysctl thread will bind to our cpu to tweak
298 wrmsr(MSR_IA32_SPEC_CTRL, v);
301 * We should exit on any event that interrupts mwait, because
302 * that event might be a wanted interrupt.
304 atomic_store_int(state, STATE_RUNNING);
307 /* Get current clock frequency for the given cpu id. */
309 cpu_est_clockrate(int cpu_id, uint64_t *rate)
312 uint64_t acnt, mcnt, perf;
315 if (pcpu_find(cpu_id) == NULL || rate == NULL)
318 if ((cpu_feature & CPUID_TSC) == 0)
323 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
324 * DELAY(9) based logic fails.
326 if (tsc_is_invariant && !tsc_perf_stat)
331 /* Schedule ourselves on the indicated cpu. */
332 thread_lock(curthread);
333 sched_bind(curthread, cpu_id);
334 thread_unlock(curthread);
338 /* Calibrate by measuring a short delay. */
339 reg = intr_disable();
340 if (tsc_is_invariant) {
345 mcnt = rdmsr(MSR_MPERF);
346 acnt = rdmsr(MSR_APERF);
349 perf = 1000 * acnt / mcnt;
350 *rate = (tsc2 - tsc1) * perf;
356 *rate = (tsc2 - tsc1) * 1000;
361 thread_lock(curthread);
362 sched_unbind(curthread);
363 thread_unlock(curthread);
371 * Shutdown the CPU as much as possible
383 struct region_descriptor null_idt;
388 if (elan_mmcr != NULL)
389 elan_mmcr->RESCFG = 1;
392 if (cpu == CPU_GEODE1100) {
393 /* Attempt Geode's own reset */
394 outl(0xcf8, 0x80009044ul);
398 #if !defined(BROKEN_KEYBOARD_RESET)
400 * Attempt to do a CPU reset via the keyboard controller,
401 * do not turn off GateA20, as any machine that fails
402 * to do the reset here would then end up in no man's land.
404 outb(IO_KBD + 4, 0xFE);
405 DELAY(500000); /* wait 0.5 sec to see if that did it */
409 * Attempt to force a reset via the Reset Control register at
410 * I/O port 0xcf9. Bit 2 forces a system reset when it
411 * transitions from 0 to 1. Bit 1 selects the type of reset
412 * to attempt: 0 selects a "soft" reset, and 1 selects a
413 * "hard" reset. We try a "hard" reset. The first write sets
414 * bit 1 to select a "hard" reset and clears bit 2. The
415 * second write forces a 0 -> 1 transition in bit 2 to trigger
420 DELAY(500000); /* wait 0.5 sec to see if that did it */
423 * Attempt to force a reset via the Fast A20 and Init register
424 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
425 * Bit 0 asserts INIT# when set to 1. We are careful to only
426 * preserve bit 1 while setting bit 0. We also must clear bit
427 * 0 before setting it if it isn't already clear.
432 outb(0x92, b & 0xfe);
434 DELAY(500000); /* wait 0.5 sec to see if that did it */
437 printf("No known reset method worked, attempting CPU shutdown\n");
438 DELAY(1000000); /* wait 1 sec for printf to complete */
441 null_idt.rd_limit = 0;
442 null_idt.rd_base = 0;
445 /* "good night, sweet prince .... <THUNK!>" */
454 cpu_reset_proxy(void)
457 cpu_reset_proxy_active = 1;
458 while (cpu_reset_proxy_active == 1)
459 ia32_pause(); /* Wait for other cpu to see that we've started */
461 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid);
471 struct monitorbuf *mb;
477 CPU_CLR(PCPU_GET(cpuid), &map);
478 CPU_ANDNOT(&map, &map, &stopped_cpus);
479 if (!CPU_EMPTY(&map)) {
480 printf("cpu_reset: Stopping other CPUs\n");
484 if (PCPU_GET(cpuid) != 0) {
485 cpu_reset_proxyid = PCPU_GET(cpuid);
486 cpustop_restartfunc = cpu_reset_proxy;
487 cpu_reset_proxy_active = 0;
488 printf("cpu_reset: Restarting BSP\n");
490 /* Restart CPU #0. */
491 CPU_SETOF(0, &started_cpus);
492 mb = &pcpu_find(0)->pc_monitorbuf;
493 atomic_store_int(&mb->stop_state,
494 MONITOR_STOPSTATE_RUNNING);
497 while (cpu_reset_proxy_active == 0 && cnt < 10000000) {
499 cnt++; /* Wait for BSP to announce restart */
501 if (cpu_reset_proxy_active == 0) {
502 printf("cpu_reset: Failed to restart BSP\n");
504 cpu_reset_proxy_active = 2;
519 cpu_mwait_usable(void)
522 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
523 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
524 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
527 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
529 int cpu_amdc1e_bug = 0; /* AMD C1E APIC workaround required. */
531 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
532 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
533 0, "Use MONITOR/MWAIT for short idle");
536 cpu_idle_acpi(sbintime_t sbt)
540 state = &PCPU_PTR(monitorbuf)->idle_state;
541 atomic_store_int(state, STATE_SLEEPING);
543 /* See comments in cpu_idle_hlt(). */
545 if (sched_runnable())
547 else if (cpu_idle_hook)
551 atomic_store_int(state, STATE_RUNNING);
555 cpu_idle_hlt(sbintime_t sbt)
559 state = &PCPU_PTR(monitorbuf)->idle_state;
560 atomic_store_int(state, STATE_SLEEPING);
563 * Since we may be in a critical section from cpu_idle(), if
564 * an interrupt fires during that critical section we may have
565 * a pending preemption. If the CPU halts, then that thread
566 * may not execute until a later interrupt awakens the CPU.
567 * To handle this race, check for a runnable thread after
568 * disabling interrupts and immediately return if one is
569 * found. Also, we must absolutely guarentee that hlt is
570 * the next instruction after sti. This ensures that any
571 * interrupt that fires after the call to disable_intr() will
572 * immediately awaken the CPU from hlt. Finally, please note
573 * that on x86 this works fine because of interrupts enabled only
574 * after the instruction following sti takes place, while IF is set
575 * to 1 immediately, allowing hlt instruction to acknowledge the
579 if (sched_runnable())
583 atomic_store_int(state, STATE_RUNNING);
587 cpu_idle_mwait(sbintime_t sbt)
591 state = &PCPU_PTR(monitorbuf)->idle_state;
592 atomic_store_int(state, STATE_MWAIT);
594 /* See comments in cpu_idle_hlt(). */
596 if (sched_runnable()) {
597 atomic_store_int(state, STATE_RUNNING);
602 cpu_monitor(state, 0, 0);
603 if (atomic_load_int(state) == STATE_MWAIT)
604 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
607 atomic_store_int(state, STATE_RUNNING);
611 cpu_idle_spin(sbintime_t sbt)
616 state = &PCPU_PTR(monitorbuf)->idle_state;
617 atomic_store_int(state, STATE_RUNNING);
620 * The sched_runnable() call is racy but as long as there is
621 * a loop missing it one time will have just a little impact if any
622 * (and it is much better than missing the check at all).
624 for (i = 0; i < 1000; i++) {
625 if (sched_runnable())
631 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
639 CTR1(KTR_SPARE2, "cpu_idle(%d)", busy);
641 ap_watchdog(PCPU_GET(cpuid));
644 /* If we are busy - try to use fast methods. */
646 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
647 cpu_idle_mwait(busy);
652 /* If we have time - switch timers into idle mode. */
655 sbt = cpu_idleclock();
658 /* Apply AMD APIC timer C1E workaround. */
659 if (cpu_amdc1e_bug && cpu_disable_c3_sleep) {
660 msr = rdmsr(MSR_AMDK8_IPM);
661 if ((msr & (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)) != 0)
662 wrmsr(MSR_AMDK8_IPM, msr & ~(AMDK8_SMIONCMPHALT |
663 AMDK8_C1EONCMPHALT));
666 /* Call main idle method. */
669 /* Switch timers back into active mode. */
675 CTR1(KTR_SPARE2, "cpu_idle(%d) done", busy);
678 static int cpu_idle_apl31_workaround;
679 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW,
680 &cpu_idle_apl31_workaround, 0,
681 "Apollo Lake APL31 MWAIT bug workaround");
684 cpu_idle_wakeup(int cpu)
686 struct monitorbuf *mb;
689 mb = &pcpu_find(cpu)->pc_monitorbuf;
690 state = &mb->idle_state;
691 switch (atomic_load_int(state)) {
695 atomic_store_int(state, STATE_RUNNING);
696 return (cpu_idle_apl31_workaround ? 0 : 1);
700 panic("bad monitor state");
706 * Ordered by speed/power consumption.
713 { .id_fn = cpu_idle_spin, .id_name = "spin" },
714 { .id_fn = cpu_idle_mwait, .id_name = "mwait",
715 .id_cpuid2_flag = CPUID2_MON },
716 { .id_fn = cpu_idle_hlt, .id_name = "hlt" },
717 { .id_fn = cpu_idle_acpi, .id_name = "acpi" },
721 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
727 avail = malloc(256, M_TEMP, M_WAITOK);
729 for (i = 0; i < nitems(idle_tbl); i++) {
730 if (idle_tbl[i].id_cpuid2_flag != 0 &&
731 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
733 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
734 cpu_idle_hook == NULL)
736 p += sprintf(p, "%s%s", p != avail ? ", " : "",
737 idle_tbl[i].id_name);
739 error = sysctl_handle_string(oidp, avail, 0, req);
744 SYSCTL_PROC(_machdep, OID_AUTO, idle_available,
745 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
746 0, 0, idle_sysctl_available, "A",
747 "list of available idle functions");
750 cpu_idle_selector(const char *new_idle_name)
754 for (i = 0; i < nitems(idle_tbl); i++) {
755 if (idle_tbl[i].id_cpuid2_flag != 0 &&
756 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
758 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
759 cpu_idle_hook == NULL)
761 if (strcmp(idle_tbl[i].id_name, new_idle_name))
763 cpu_idle_fn = idle_tbl[i].id_fn;
765 printf("CPU idle set to %s\n", idle_tbl[i].id_name);
772 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
778 for (i = 0; i < nitems(idle_tbl); i++) {
779 if (idle_tbl[i].id_fn == cpu_idle_fn) {
780 p = idle_tbl[i].id_name;
784 strncpy(buf, p, sizeof(buf));
785 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
786 if (error != 0 || req->newptr == NULL)
788 return (cpu_idle_selector(buf) ? 0 : EINVAL);
791 SYSCTL_PROC(_machdep, OID_AUTO, idle,
792 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
793 0, 0, cpu_idle_sysctl, "A",
794 "currently selected idle function");
797 cpu_idle_tun(void *unused __unused)
801 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
802 cpu_idle_selector(tunvar);
803 else if (cpu_vendor_id == CPU_VENDOR_AMD &&
804 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
805 /* Ryzen erratas 1057, 1109. */
806 cpu_idle_selector("hlt");
808 mwait_cpustop_broken = true;
811 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
813 * Apollo Lake errata APL31 (public errata APL30).
814 * Stores to the armed address range may not trigger
815 * MWAIT to resume execution. OS needs to use
816 * interrupts to wake processors from MWAIT-induced
819 cpu_idle_apl31_workaround = 1;
820 mwait_cpustop_broken = true;
822 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround);
824 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL);
826 static int panic_on_nmi = 0xff;
827 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
829 "Panic on NMI: 1 = H/W failure; 2 = unknown; 0xff = all");
830 int nmi_is_broadcast = 1;
831 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
832 &nmi_is_broadcast, 0,
833 "Chipset NMI is broadcast");
834 int (*apei_nmi)(void);
837 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
839 bool claimed = false;
842 /* machine/parity/power fail/"kitchen sink" faults */
843 if (isa_nmi(frame->tf_err)) {
845 if ((panic_on_nmi & 1) != 0)
846 panic("NMI indicates hardware failure");
850 /* ACPI Platform Error Interfaces callback. */
851 if (apei_nmi != NULL && (*apei_nmi)())
855 * NMIs can be useful for debugging. They can be hooked up to a
856 * pushbutton, usually on an ISA, PCI, or PCIe card. They can also be
857 * generated by an IPMI BMC, either manually or in response to a
858 * watchdog timeout. For example, see the "power diag" command in
859 * ports/sysutils/ipmitool. They can also be generated by a
860 * hypervisor; see "bhyvectl --inject-nmi".
864 if (!claimed && (panic_on_nmi & 2) != 0) {
865 if (debugger_on_panic) {
866 printf("NMI/cpu%d ... going to debugger\n", cpu);
867 claimed = kdb_trap(type, 0, frame);
872 if (!claimed && panic_on_nmi != 0)
877 nmi_handle_intr(u_int type, struct trapframe *frame)
881 if (nmi_is_broadcast) {
882 nmi_call_kdb_smp(type, frame);
886 nmi_call_kdb(PCPU_GET(cpuid), type, frame);
889 static int hw_ibrs_active;
890 int hw_ibrs_ibpb_active;
891 int hw_ibrs_disable = 1;
893 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
894 "Indirect Branch Restricted Speculation active");
896 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ibrs,
897 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
898 "Indirect Branch Restricted Speculation active");
900 SYSCTL_INT(_machdep_mitigations_ibrs, OID_AUTO, active, CTLFLAG_RD,
901 &hw_ibrs_active, 0, "Indirect Branch Restricted Speculation active");
904 hw_ibrs_recalculate(bool for_all_cpus)
906 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
907 x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ?
908 MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL) |
909 (hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR),
910 IA32_SPEC_CTRL_IBRS, NULL);
911 hw_ibrs_active = hw_ibrs_disable == 0;
912 hw_ibrs_ibpb_active = 0;
914 hw_ibrs_active = hw_ibrs_ibpb_active = (cpu_stdext_feature3 &
915 CPUID_STDEXT3_IBPB) != 0 && !hw_ibrs_disable;
920 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS)
924 val = hw_ibrs_disable;
925 error = sysctl_handle_int(oidp, &val, 0, req);
926 if (error != 0 || req->newptr == NULL)
928 hw_ibrs_disable = val != 0;
929 hw_ibrs_recalculate(true);
932 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
933 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
934 "Disable Indirect Branch Restricted Speculation");
936 SYSCTL_PROC(_machdep_mitigations_ibrs, OID_AUTO, disable, CTLTYPE_INT |
937 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
938 hw_ibrs_disable_handler, "I",
939 "Disable Indirect Branch Restricted Speculation");
944 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD,
946 "Speculative Store Bypass Disable active");
948 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ssb,
949 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
950 "Speculative Store Bypass Disable active");
952 SYSCTL_INT(_machdep_mitigations_ssb, OID_AUTO, active, CTLFLAG_RD,
953 &hw_ssb_active, 0, "Speculative Store Bypass Disable active");
956 hw_ssb_set(bool enable, bool for_all_cpus)
959 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) {
963 hw_ssb_active = enable;
964 x86_msr_op(MSR_IA32_SPEC_CTRL,
965 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
966 (for_all_cpus ? MSR_OP_SCHED_ALL : MSR_OP_LOCAL),
967 IA32_SPEC_CTRL_SSBD, NULL);
971 hw_ssb_recalculate(bool all_cpus)
974 switch (hw_ssb_disable) {
979 hw_ssb_set(false, all_cpus);
982 hw_ssb_set(true, all_cpus);
985 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ?
986 false : true, all_cpus);
992 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS)
996 val = hw_ssb_disable;
997 error = sysctl_handle_int(oidp, &val, 0, req);
998 if (error != 0 || req->newptr == NULL)
1000 hw_ssb_disable = val;
1001 hw_ssb_recalculate(true);
1004 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
1005 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1006 hw_ssb_disable_handler, "I",
1007 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
1009 SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT |
1010 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1011 hw_ssb_disable_handler, "I",
1012 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto)");
1017 * Handler for Microarchitectural Data Sampling issues. Really not a
1018 * pointer to C function: on amd64 the code must not change any CPU
1019 * architectural state except possibly %rflags. Also, it is always
1020 * called with interrupts disabled.
1022 void mds_handler_void(void);
1023 void mds_handler_verw(void);
1024 void mds_handler_ivb(void);
1025 void mds_handler_bdw(void);
1026 void mds_handler_skl_sse(void);
1027 void mds_handler_skl_avx(void);
1028 void mds_handler_skl_avx512(void);
1029 void mds_handler_silvermont(void);
1030 void (*mds_handler)(void) = mds_handler_void;
1033 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS)
1037 if (mds_handler == mds_handler_void)
1039 else if (mds_handler == mds_handler_verw)
1041 else if (mds_handler == mds_handler_ivb)
1042 state = "software IvyBridge";
1043 else if (mds_handler == mds_handler_bdw)
1044 state = "software Broadwell";
1045 else if (mds_handler == mds_handler_skl_sse)
1046 state = "software Skylake SSE";
1047 else if (mds_handler == mds_handler_skl_avx)
1048 state = "software Skylake AVX";
1049 else if (mds_handler == mds_handler_skl_avx512)
1050 state = "software Skylake AVX512";
1051 else if (mds_handler == mds_handler_silvermont)
1052 state = "software Silvermont";
1055 return (SYSCTL_OUT(req, state, strlen(state)));
1058 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state,
1059 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1060 sysctl_hw_mds_disable_state_handler, "A",
1061 "Microarchitectural Data Sampling Mitigation state");
1063 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, mds,
1064 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1065 "Microarchitectural Data Sampling Mitigation state");
1067 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, state,
1068 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1069 sysctl_hw_mds_disable_state_handler, "A",
1070 "Microarchitectural Data Sampling Mitigation state");
1072 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512");
1075 hw_mds_recalculate(void)
1083 * Allow user to force VERW variant even if MD_CLEAR is not
1084 * reported. For instance, hypervisor might unknowingly
1085 * filter the cap out.
1086 * For the similar reasons, and for testing, allow to enable
1087 * mitigation even when MDS_NO cap is set.
1089 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 ||
1090 ((cpu_ia32_arch_caps & IA32_ARCH_CAP_MDS_NO) != 0 &&
1091 hw_mds_disable == 3)) {
1092 mds_handler = mds_handler_void;
1093 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 &&
1094 hw_mds_disable == 3) || hw_mds_disable == 1) {
1095 mds_handler = mds_handler_verw;
1096 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1097 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e ||
1098 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a ||
1099 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 ||
1100 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d ||
1101 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e ||
1102 CPUID_TO_MODEL(cpu_id) == 0x3a) &&
1103 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1105 * Nehalem, SandyBridge, IvyBridge
1109 if (pc->pc_mds_buf == NULL) {
1110 pc->pc_mds_buf = malloc_domainset(672, M_TEMP,
1111 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1112 bzero(pc->pc_mds_buf, 16);
1115 mds_handler = mds_handler_ivb;
1116 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1117 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c ||
1118 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 ||
1119 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f ||
1120 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) &&
1121 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1123 * Haswell, Broadwell
1127 if (pc->pc_mds_buf == NULL) {
1128 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP,
1129 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1130 bzero(pc->pc_mds_buf, 16);
1133 mds_handler = mds_handler_bdw;
1134 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1135 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id &
1136 CPUID_STEPPING) <= 5) ||
1137 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e ||
1138 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id &
1139 CPUID_STEPPING) <= 0xb) ||
1140 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id &
1141 CPUID_STEPPING) <= 0xc)) &&
1142 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1144 * Skylake, KabyLake, CoffeeLake, WhiskeyLake,
1149 if (pc->pc_mds_buf == NULL) {
1150 pc->pc_mds_buf = malloc_domainset(6 * 1024,
1151 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1153 b64 = (vm_offset_t)malloc_domainset(64 + 63,
1154 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1156 pc->pc_mds_buf64 = (void *)roundup2(b64, 64);
1157 bzero(pc->pc_mds_buf64, 64);
1161 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 &&
1162 (cpu_stdext_feature & CPUID_STDEXT_AVX512DQ) != 0)
1163 mds_handler = mds_handler_skl_avx512;
1164 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 &&
1165 (cpu_feature2 & CPUID2_AVX) != 0)
1166 mds_handler = mds_handler_skl_avx;
1168 mds_handler = mds_handler_skl_sse;
1169 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1170 ((CPUID_TO_MODEL(cpu_id) == 0x37 ||
1171 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1172 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1173 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1174 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1175 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1176 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1177 CPUID_TO_MODEL(cpu_id) == 0x65 ||
1178 CPUID_TO_MODEL(cpu_id) == 0x75 ||
1179 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1180 CPUID_TO_MODEL(cpu_id) == 0x26 ||
1181 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1182 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1183 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1184 CPUID_TO_MODEL(cpu_id) == 0x7a))) {
1185 /* Silvermont, Airmont */
1188 if (pc->pc_mds_buf == NULL)
1189 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK);
1191 mds_handler = mds_handler_silvermont;
1194 mds_handler = mds_handler_void;
1199 hw_mds_recalculate_boot(void *arg __unused)
1202 hw_mds_recalculate();
1204 SYSINIT(mds_recalc, SI_SUB_SMP, SI_ORDER_ANY, hw_mds_recalculate_boot, NULL);
1207 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS)
1211 val = hw_mds_disable;
1212 error = sysctl_handle_int(oidp, &val, 0, req);
1213 if (error != 0 || req->newptr == NULL)
1215 if (val < 0 || val > 3)
1217 hw_mds_disable = val;
1218 hw_mds_recalculate();
1222 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
1223 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1224 sysctl_mds_disable_handler, "I",
1225 "Microarchitectural Data Sampling Mitigation "
1226 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
1228 SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT |
1229 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1230 sysctl_mds_disable_handler, "I",
1231 "Microarchitectural Data Sampling Mitigation "
1232 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO)");
1235 * Intel Transactional Memory Asynchronous Abort Mitigation
1241 TAA_NONE = 0, /* No mitigation enabled */
1242 TAA_TSX_DISABLE = 1, /* Disable TSX via MSR */
1243 TAA_VERW = 2, /* Use VERW mitigation */
1244 TAA_AUTO = 3, /* Automatically select the mitigation */
1246 /* The states below are not selectable by the operator */
1248 TAA_TAA_UC = 4, /* Mitigation present in microcode */
1249 TAA_NOT_PRESENT = 5 /* TSX is not present */
1253 taa_set(bool enable, bool all)
1256 x86_msr_op(MSR_IA32_TSX_CTRL,
1257 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1258 (all ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
1259 IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR,
1264 x86_taa_recalculate(void)
1266 static int taa_saved_mds_disable = 0;
1267 int taa_need = 0, taa_state = 0;
1268 int mds_disable = 0, need_mds_recalc = 0;
1270 /* Check CPUID.07h.EBX.HLE and RTM for the presence of TSX */
1271 if ((cpu_stdext_feature & CPUID_STDEXT_HLE) == 0 ||
1272 (cpu_stdext_feature & CPUID_STDEXT_RTM) == 0) {
1273 /* TSX is not present */
1274 x86_taa_state = TAA_NOT_PRESENT;
1278 /* Check to see what mitigation options the CPU gives us */
1279 if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TAA_NO) {
1280 /* CPU is not suseptible to TAA */
1281 taa_need = TAA_TAA_UC;
1282 } else if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TSX_CTRL) {
1284 * CPU can turn off TSX. This is the next best option
1285 * if TAA_NO hardware mitigation isn't present
1287 taa_need = TAA_TSX_DISABLE;
1289 /* No TSX/TAA specific remedies are available. */
1290 if (x86_taa_enable == TAA_TSX_DISABLE) {
1292 printf("TSX control not available\n");
1295 taa_need = TAA_VERW;
1298 /* Can we automatically take action, or are we being forced? */
1299 if (x86_taa_enable == TAA_AUTO)
1300 taa_state = taa_need;
1302 taa_state = x86_taa_enable;
1304 /* No state change, nothing to do */
1305 if (taa_state == x86_taa_state) {
1307 printf("No TSX change made\n");
1311 /* Does the MSR need to be turned on or off? */
1312 if (taa_state == TAA_TSX_DISABLE)
1313 taa_set(true, true);
1314 else if (x86_taa_state == TAA_TSX_DISABLE)
1315 taa_set(false, true);
1317 /* Does MDS need to be set to turn on VERW? */
1318 if (taa_state == TAA_VERW) {
1319 taa_saved_mds_disable = hw_mds_disable;
1320 mds_disable = hw_mds_disable = 1;
1321 need_mds_recalc = 1;
1322 } else if (x86_taa_state == TAA_VERW) {
1323 mds_disable = hw_mds_disable = taa_saved_mds_disable;
1324 need_mds_recalc = 1;
1326 if (need_mds_recalc) {
1327 hw_mds_recalculate();
1328 if (mds_disable != hw_mds_disable) {
1330 printf("Cannot change MDS state for TAA\n");
1331 /* Don't update our state */
1336 x86_taa_state = taa_state;
1341 taa_recalculate_boot(void * arg __unused)
1344 x86_taa_recalculate();
1346 SYSINIT(taa_recalc, SI_SUB_SMP, SI_ORDER_ANY, taa_recalculate_boot, NULL);
1348 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, taa,
1349 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1350 "TSX Asynchronous Abort Mitigation");
1353 sysctl_taa_handler(SYSCTL_HANDLER_ARGS)
1357 val = x86_taa_enable;
1358 error = sysctl_handle_int(oidp, &val, 0, req);
1359 if (error != 0 || req->newptr == NULL)
1361 if (val < TAA_NONE || val > TAA_AUTO)
1363 x86_taa_enable = val;
1364 x86_taa_recalculate();
1368 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT |
1369 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1370 sysctl_taa_handler, "I",
1371 "TAA Mitigation enablement control "
1372 "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO)");
1375 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS)
1379 switch (x86_taa_state) {
1383 case TAA_TSX_DISABLE:
1384 state = "TSX disabled";
1390 state = "Mitigated in microcode";
1392 case TAA_NOT_PRESENT:
1393 state = "TSX not present";
1399 return (SYSCTL_OUT(req, state, strlen(state)));
1402 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, state,
1403 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1404 sysctl_taa_state_handler, "A",
1405 "TAA Mitigation state");
1407 int __read_frequently cpu_flush_rsb_ctxsw;
1408 SYSCTL_INT(_machdep_mitigations, OID_AUTO, flush_rsb_ctxsw,
1409 CTLFLAG_RW | CTLFLAG_NOFETCH, &cpu_flush_rsb_ctxsw, 0,
1410 "Flush Return Stack Buffer on context switch");
1412 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, rngds,
1413 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1414 "MCU Optimization, disable RDSEED mitigation");
1416 int x86_rngds_mitg_enable = 1;
1418 x86_rngds_mitg_recalculate(bool all_cpus)
1420 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0)
1422 x86_msr_op(MSR_IA32_MCU_OPT_CTRL,
1423 (x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1424 (all_cpus ? MSR_OP_RENDEZVOUS_ALL : MSR_OP_LOCAL),
1425 IA32_RNGDS_MITG_DIS, NULL);
1429 sysctl_rngds_mitg_enable_handler(SYSCTL_HANDLER_ARGS)
1433 val = x86_rngds_mitg_enable;
1434 error = sysctl_handle_int(oidp, &val, 0, req);
1435 if (error != 0 || req->newptr == NULL)
1437 x86_rngds_mitg_enable = val;
1438 x86_rngds_mitg_recalculate(true);
1441 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT |
1442 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1443 sysctl_rngds_mitg_enable_handler, "I",
1444 "MCU Optimization, disabling RDSEED mitigation control "
1445 "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled)");
1448 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS)
1452 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) {
1453 state = "Not applicable";
1454 } else if (x86_rngds_mitg_enable == 0) {
1455 state = "RDSEED not serialized";
1457 state = "Mitigated";
1459 return (SYSCTL_OUT(req, state, strlen(state)));
1461 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, state,
1462 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1463 sysctl_rngds_state_handler, "A",
1464 "MCU Optimization state");
1467 * Enable and restore kernel text write permissions.
1468 * Callers must ensure that disable_wp()/restore_wp() are executed
1469 * without rescheduling on the same core.
1477 if ((cr0 & CR0_WP) == 0)
1479 load_cr0(cr0 & ~CR0_WP);
1484 restore_wp(bool old_wp)
1488 load_cr0(rcr0() | CR0_WP);
1492 acpi_get_fadt_bootflags(uint16_t *flagsp)
1495 ACPI_TABLE_FADT *fadt;
1496 vm_paddr_t physaddr;
1498 physaddr = acpi_find_table(ACPI_SIG_FADT);
1501 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT);
1504 *flagsp = fadt->BootFlags;
1505 acpi_unmap_table(fadt);
1512 DEFINE_IFUNC(, uint64_t, rdtsc_ordered, (void))
1514 bool cpu_is_amd = cpu_vendor_id == CPU_VENDOR_AMD ||
1515 cpu_vendor_id == CPU_VENDOR_HYGON;
1517 if ((amd_feature & AMDID_RDTSCP) != 0)
1519 else if ((cpu_feature & CPUID_SSE2) != 0)
1520 return (cpu_is_amd ? rdtsc_ordered_mfence :
1521 rdtsc_ordered_lfence);