2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include "opt_atpic.h"
45 #include "opt_compat.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_platform.h"
60 #include <sys/param.h>
62 #include <sys/systm.h>
66 #include <sys/kernel.h>
69 #include <sys/malloc.h>
70 #include <sys/mutex.h>
72 #include <sys/rwlock.h>
73 #include <sys/sched.h>
77 #include <sys/sysctl.h>
79 #include <machine/clock.h>
80 #include <machine/cpu.h>
81 #include <machine/cputypes.h>
82 #include <machine/specialreg.h>
83 #include <machine/md_var.h>
84 #include <machine/mp_watchdog.h>
85 #include <machine/tss.h>
87 #include <machine/smp.h>
89 #include <x86/acpica_machdep.h>
92 #include <vm/vm_extern.h>
93 #include <vm/vm_kern.h>
94 #include <vm/vm_page.h>
95 #include <vm/vm_map.h>
96 #include <vm/vm_object.h>
97 #include <vm/vm_pager.h>
98 #include <vm/vm_param.h>
100 #define STATE_RUNNING 0x0
101 #define STATE_MWAIT 0x1
102 #define STATE_SLEEPING 0x2
105 * Machine dependent boot() routine
107 * I haven't seen anything to put here yet
108 * Possibly some stuff might be grafted back here from boot()
116 * Flush the D-cache for non-DMA I/O so that the I-cache can
117 * be made coherent later.
120 cpu_flush_dcache(void *ptr, size_t len)
129 __asm __volatile("sti; hlt");
133 * Use mwait to pause execution while waiting for an interrupt or
134 * another thread to signal that there is more work.
136 * NOTE: Interrupts will cause a wakeup; however, this function does
137 * not enable interrupt handling. The caller is responsible to enable
141 acpi_cpu_idle_mwait(uint32_t mwait_hint)
146 * XXXKIB. Software coordination mode should be supported,
147 * but all Intel CPUs provide hardware coordination.
150 state = (int *)PCPU_PTR(monitorbuf);
151 KASSERT(*state == STATE_SLEEPING,
152 ("cpu_mwait_cx: wrong monitorbuf state"));
153 *state = STATE_MWAIT;
154 cpu_monitor(state, 0, 0);
155 if (*state == STATE_MWAIT)
156 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
159 * We should exit on any event that interrupts mwait, because
160 * that event might be a wanted interrupt.
162 *state = STATE_RUNNING;
165 /* Get current clock frequency for the given cpu id. */
167 cpu_est_clockrate(int cpu_id, uint64_t *rate)
170 uint64_t acnt, mcnt, perf;
173 if (pcpu_find(cpu_id) == NULL || rate == NULL)
176 if ((cpu_feature & CPUID_TSC) == 0)
181 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
182 * DELAY(9) based logic fails.
184 if (tsc_is_invariant && !tsc_perf_stat)
189 /* Schedule ourselves on the indicated cpu. */
190 thread_lock(curthread);
191 sched_bind(curthread, cpu_id);
192 thread_unlock(curthread);
196 /* Calibrate by measuring a short delay. */
197 reg = intr_disable();
198 if (tsc_is_invariant) {
203 mcnt = rdmsr(MSR_MPERF);
204 acnt = rdmsr(MSR_APERF);
207 perf = 1000 * acnt / mcnt;
208 *rate = (tsc2 - tsc1) * perf;
214 *rate = (tsc2 - tsc1) * 1000;
219 thread_lock(curthread);
220 sched_unbind(curthread);
221 thread_unlock(curthread);
229 * Shutdown the CPU as much as possible
239 cpu_mwait_usable(void)
242 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
243 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
244 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
247 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
248 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
249 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
250 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
251 0, "Use MONITOR/MWAIT for short idle");
254 cpu_idle_acpi(sbintime_t sbt)
258 state = (int *)PCPU_PTR(monitorbuf);
259 *state = STATE_SLEEPING;
261 /* See comments in cpu_idle_hlt(). */
263 if (sched_runnable())
265 else if (cpu_idle_hook)
269 *state = STATE_RUNNING;
273 cpu_idle_hlt(sbintime_t sbt)
277 state = (int *)PCPU_PTR(monitorbuf);
278 *state = STATE_SLEEPING;
281 * Since we may be in a critical section from cpu_idle(), if
282 * an interrupt fires during that critical section we may have
283 * a pending preemption. If the CPU halts, then that thread
284 * may not execute until a later interrupt awakens the CPU.
285 * To handle this race, check for a runnable thread after
286 * disabling interrupts and immediately return if one is
287 * found. Also, we must absolutely guarentee that hlt is
288 * the next instruction after sti. This ensures that any
289 * interrupt that fires after the call to disable_intr() will
290 * immediately awaken the CPU from hlt. Finally, please note
291 * that on x86 this works fine because of interrupts enabled only
292 * after the instruction following sti takes place, while IF is set
293 * to 1 immediately, allowing hlt instruction to acknowledge the
297 if (sched_runnable())
301 *state = STATE_RUNNING;
305 cpu_idle_mwait(sbintime_t sbt)
309 state = (int *)PCPU_PTR(monitorbuf);
310 *state = STATE_MWAIT;
312 /* See comments in cpu_idle_hlt(). */
314 if (sched_runnable()) {
316 *state = STATE_RUNNING;
319 cpu_monitor(state, 0, 0);
320 if (*state == STATE_MWAIT)
321 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
324 *state = STATE_RUNNING;
328 cpu_idle_spin(sbintime_t sbt)
333 state = (int *)PCPU_PTR(monitorbuf);
334 *state = STATE_RUNNING;
337 * The sched_runnable() call is racy but as long as there is
338 * a loop missing it one time will have just a little impact if any
339 * (and it is much better than missing the check at all).
341 for (i = 0; i < 1000; i++) {
342 if (sched_runnable())
349 * C1E renders the local APIC timer dead, so we disable it by
350 * reading the Interrupt Pending Message register and clearing
351 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
354 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
355 * #32559 revision 3.00+
357 #define MSR_AMDK8_IPM 0xc0010055
358 #define AMDK8_SMIONCMPHALT (1ULL << 27)
359 #define AMDK8_C1EONCMPHALT (1ULL << 28)
360 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
363 cpu_probe_amdc1e(void)
367 * Detect the presence of C1E capability mostly on latest
368 * dual-cores (or future) k8 family.
370 if (cpu_vendor_id == CPU_VENDOR_AMD &&
371 (cpu_id & 0x00000f00) == 0x00000f00 &&
372 (cpu_id & 0x0fff0000) >= 0x00040000) {
373 cpu_ident_amdc1e = 1;
377 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
385 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
388 ap_watchdog(PCPU_GET(cpuid));
391 /* If we are busy - try to use fast methods. */
393 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
394 cpu_idle_mwait(busy);
399 /* If we have time - switch timers into idle mode. */
402 sbt = cpu_idleclock();
405 /* Apply AMD APIC timer C1E workaround. */
406 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) {
407 msr = rdmsr(MSR_AMDK8_IPM);
408 if (msr & AMDK8_CMPHALT)
409 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
412 /* Call main idle method. */
415 /* Switch timers back into active mode. */
421 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
426 cpu_idle_wakeup(int cpu)
431 pcpu = pcpu_find(cpu);
432 state = (int *)pcpu->pc_monitorbuf;
434 * This doesn't need to be atomic since missing the race will
435 * simply result in unnecessary IPIs.
437 if (*state == STATE_SLEEPING)
439 if (*state == STATE_MWAIT)
440 *state = STATE_RUNNING;
445 * Ordered by speed/power consumption.
451 { cpu_idle_spin, "spin" },
452 { cpu_idle_mwait, "mwait" },
453 { cpu_idle_hlt, "hlt" },
454 { cpu_idle_acpi, "acpi" },
459 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
465 avail = malloc(256, M_TEMP, M_WAITOK);
467 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
468 if (strstr(idle_tbl[i].id_name, "mwait") &&
469 (cpu_feature2 & CPUID2_MON) == 0)
471 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
472 cpu_idle_hook == NULL)
474 p += sprintf(p, "%s%s", p != avail ? ", " : "",
475 idle_tbl[i].id_name);
477 error = sysctl_handle_string(oidp, avail, 0, req);
482 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
483 0, 0, idle_sysctl_available, "A", "list of available idle functions");
486 idle_sysctl(SYSCTL_HANDLER_ARGS)
494 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
495 if (idle_tbl[i].id_fn == cpu_idle_fn) {
496 p = idle_tbl[i].id_name;
500 strncpy(buf, p, sizeof(buf));
501 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
502 if (error != 0 || req->newptr == NULL)
504 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
505 if (strstr(idle_tbl[i].id_name, "mwait") &&
506 (cpu_feature2 & CPUID2_MON) == 0)
508 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
509 cpu_idle_hook == NULL)
511 if (strcmp(idle_tbl[i].id_name, buf))
513 cpu_idle_fn = idle_tbl[i].id_fn;
519 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
520 idle_sysctl, "A", "currently selected idle function");
522 static int panic_on_nmi = 1;
523 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
526 int nmi_is_broadcast = 1;
527 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
528 &nmi_is_broadcast, 0,
529 "Chipset NMI is broadcast");
532 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN,
539 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
542 /* machine/parity/power fail/"kitchen sink" faults */
543 if (isa_nmi(frame->tf_err) == 0) {
546 * NMI can be hooked up to a pushbutton for debugging.
549 printf("NMI/cpu%d ... going to debugger\n", cpu);
550 kdb_trap(type, 0, frame);
553 } else if (panic_on_nmi) {
554 panic("NMI indicates hardware failure");
560 nmi_handle_intr(u_int type, struct trapframe *frame)
565 if (nmi_is_broadcast) {
566 nmi_call_kdb_smp(type, frame);
570 nmi_call_kdb(PCPU_GET(cpuid), type, frame);