2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
45 #include "opt_atpic.h"
51 #include "opt_kstack_pages.h"
52 #include "opt_maxmem.h"
53 #include "opt_mp_watchdog.h"
54 #include "opt_platform.h"
59 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/domainset.h>
66 #include <sys/kernel.h>
69 #include <sys/malloc.h>
70 #include <sys/mutex.h>
72 #include <sys/rwlock.h>
73 #include <sys/sched.h>
75 #include <sys/sysctl.h>
77 #include <machine/clock.h>
78 #include <machine/cpu.h>
79 #include <machine/cputypes.h>
80 #include <machine/specialreg.h>
81 #include <machine/md_var.h>
82 #include <machine/mp_watchdog.h>
83 #include <machine/tss.h>
85 #include <machine/smp.h>
88 #include <machine/elan_mmcr.h>
90 #include <x86/acpica_machdep.h>
93 #include <vm/vm_extern.h>
94 #include <vm/vm_kern.h>
95 #include <vm/vm_page.h>
96 #include <vm/vm_map.h>
97 #include <vm/vm_object.h>
98 #include <vm/vm_pager.h>
99 #include <vm/vm_param.h>
101 #include <isa/isareg.h>
103 #include <contrib/dev/acpica/include/acpi.h>
105 #define STATE_RUNNING 0x0
106 #define STATE_MWAIT 0x1
107 #define STATE_SLEEPING 0x2
110 static u_int cpu_reset_proxyid;
111 static volatile u_int cpu_reset_proxy_active;
121 x86_msr_op_one(void *argp)
123 struct msr_op_arg *a;
139 wrmsr(a->msr, a->arg1);
144 #define MSR_OP_EXMODE_MASK 0xf0000000
145 #define MSR_OP_OP_MASK 0x000000ff
148 x86_msr_op(u_int msr, u_int op, uint64_t arg1)
153 int bound_cpu, i, is_bound;
155 a.op = op & MSR_OP_OP_MASK;
156 MPASS(a.op == MSR_OP_ANDNOT || a.op == MSR_OP_OR ||
157 a.op == MSR_OP_WRITE);
158 exmode = op & MSR_OP_EXMODE_MASK;
159 MPASS(exmode == MSR_OP_LOCAL || exmode == MSR_OP_SCHED ||
160 exmode == MSR_OP_RENDEZVOUS);
170 is_bound = sched_is_bound(td);
171 bound_cpu = td->td_oncpu;
177 sched_bind(td, bound_cpu);
182 case MSR_OP_RENDEZVOUS:
183 smp_rendezvous(NULL, x86_msr_op_one, NULL, &a);
189 * Machine dependent boot() routine
191 * I haven't seen anything to put here yet
192 * Possibly some stuff might be grafted back here from boot()
200 * Flush the D-cache for non-DMA I/O so that the I-cache can
201 * be made coherent later.
204 cpu_flush_dcache(void *ptr, size_t len)
213 __asm __volatile("sti; hlt");
217 * Use mwait to pause execution while waiting for an interrupt or
218 * another thread to signal that there is more work.
220 * NOTE: Interrupts will cause a wakeup; however, this function does
221 * not enable interrupt handling. The caller is responsible to enable
225 acpi_cpu_idle_mwait(uint32_t mwait_hint)
231 * A comment in Linux patch claims that 'CPUs run faster with
232 * speculation protection disabled. All CPU threads in a core
233 * must disable speculation protection for it to be
234 * disabled. Disable it while we are idle so the other
235 * hyperthread can run fast.'
237 * XXXKIB. Software coordination mode should be supported,
238 * but all Intel CPUs provide hardware coordination.
241 state = (int *)PCPU_PTR(monitorbuf);
242 KASSERT(atomic_load_int(state) == STATE_SLEEPING,
243 ("cpu_mwait_cx: wrong monitorbuf state"));
244 atomic_store_int(state, STATE_MWAIT);
245 if (PCPU_GET(ibpb_set) || hw_ssb_active) {
246 v = rdmsr(MSR_IA32_SPEC_CTRL);
247 wrmsr(MSR_IA32_SPEC_CTRL, v & ~(IA32_SPEC_CTRL_IBRS |
248 IA32_SPEC_CTRL_STIBP | IA32_SPEC_CTRL_SSBD));
252 cpu_monitor(state, 0, 0);
253 if (atomic_load_int(state) == STATE_MWAIT)
254 cpu_mwait(MWAIT_INTRBREAK, mwait_hint);
257 * SSB cannot be disabled while we sleep, or rather, if it was
258 * disabled, the sysctl thread will bind to our cpu to tweak
262 wrmsr(MSR_IA32_SPEC_CTRL, v);
265 * We should exit on any event that interrupts mwait, because
266 * that event might be a wanted interrupt.
268 atomic_store_int(state, STATE_RUNNING);
271 /* Get current clock frequency for the given cpu id. */
273 cpu_est_clockrate(int cpu_id, uint64_t *rate)
276 uint64_t acnt, mcnt, perf;
279 if (pcpu_find(cpu_id) == NULL || rate == NULL)
282 if ((cpu_feature & CPUID_TSC) == 0)
287 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
288 * DELAY(9) based logic fails.
290 if (tsc_is_invariant && !tsc_perf_stat)
295 /* Schedule ourselves on the indicated cpu. */
296 thread_lock(curthread);
297 sched_bind(curthread, cpu_id);
298 thread_unlock(curthread);
302 /* Calibrate by measuring a short delay. */
303 reg = intr_disable();
304 if (tsc_is_invariant) {
309 mcnt = rdmsr(MSR_MPERF);
310 acnt = rdmsr(MSR_APERF);
313 perf = 1000 * acnt / mcnt;
314 *rate = (tsc2 - tsc1) * perf;
320 *rate = (tsc2 - tsc1) * 1000;
325 thread_lock(curthread);
326 sched_unbind(curthread);
327 thread_unlock(curthread);
335 * Shutdown the CPU as much as possible
347 struct region_descriptor null_idt;
352 if (elan_mmcr != NULL)
353 elan_mmcr->RESCFG = 1;
356 if (cpu == CPU_GEODE1100) {
357 /* Attempt Geode's own reset */
358 outl(0xcf8, 0x80009044ul);
362 #if !defined(BROKEN_KEYBOARD_RESET)
364 * Attempt to do a CPU reset via the keyboard controller,
365 * do not turn off GateA20, as any machine that fails
366 * to do the reset here would then end up in no man's land.
368 outb(IO_KBD + 4, 0xFE);
369 DELAY(500000); /* wait 0.5 sec to see if that did it */
373 * Attempt to force a reset via the Reset Control register at
374 * I/O port 0xcf9. Bit 2 forces a system reset when it
375 * transitions from 0 to 1. Bit 1 selects the type of reset
376 * to attempt: 0 selects a "soft" reset, and 1 selects a
377 * "hard" reset. We try a "hard" reset. The first write sets
378 * bit 1 to select a "hard" reset and clears bit 2. The
379 * second write forces a 0 -> 1 transition in bit 2 to trigger
384 DELAY(500000); /* wait 0.5 sec to see if that did it */
387 * Attempt to force a reset via the Fast A20 and Init register
388 * at I/O port 0x92. Bit 1 serves as an alternate A20 gate.
389 * Bit 0 asserts INIT# when set to 1. We are careful to only
390 * preserve bit 1 while setting bit 0. We also must clear bit
391 * 0 before setting it if it isn't already clear.
396 outb(0x92, b & 0xfe);
398 DELAY(500000); /* wait 0.5 sec to see if that did it */
401 printf("No known reset method worked, attempting CPU shutdown\n");
402 DELAY(1000000); /* wait 1 sec for printf to complete */
405 null_idt.rd_limit = 0;
406 null_idt.rd_base = 0;
409 /* "good night, sweet prince .... <THUNK!>" */
418 cpu_reset_proxy(void)
421 cpu_reset_proxy_active = 1;
422 while (cpu_reset_proxy_active == 1)
423 ia32_pause(); /* Wait for other cpu to see that we've started */
425 printf("cpu_reset_proxy: Stopped CPU %d\n", cpu_reset_proxyid);
440 CPU_CLR(PCPU_GET(cpuid), &map);
441 CPU_NAND(&map, &stopped_cpus);
442 if (!CPU_EMPTY(&map)) {
443 printf("cpu_reset: Stopping other CPUs\n");
447 if (PCPU_GET(cpuid) != 0) {
448 cpu_reset_proxyid = PCPU_GET(cpuid);
449 cpustop_restartfunc = cpu_reset_proxy;
450 cpu_reset_proxy_active = 0;
451 printf("cpu_reset: Restarting BSP\n");
453 /* Restart CPU #0. */
454 CPU_SETOF(0, &started_cpus);
457 while (cpu_reset_proxy_active == 0 && cnt < 10000000) {
459 cnt++; /* Wait for BSP to announce restart */
461 if (cpu_reset_proxy_active == 0) {
462 printf("cpu_reset: Failed to restart BSP\n");
464 cpu_reset_proxy_active = 2;
479 cpu_mwait_usable(void)
482 return ((cpu_feature2 & CPUID2_MON) != 0 && ((cpu_mon_mwait_flags &
483 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)) ==
484 (CPUID5_MON_MWAIT_EXT | CPUID5_MWAIT_INTRBREAK)));
487 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
488 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
489 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
490 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RWTUN, &idle_mwait,
491 0, "Use MONITOR/MWAIT for short idle");
494 cpu_idle_acpi(sbintime_t sbt)
498 state = (int *)PCPU_PTR(monitorbuf);
499 atomic_store_int(state, STATE_SLEEPING);
501 /* See comments in cpu_idle_hlt(). */
503 if (sched_runnable())
505 else if (cpu_idle_hook)
509 atomic_store_int(state, STATE_RUNNING);
513 cpu_idle_hlt(sbintime_t sbt)
517 state = (int *)PCPU_PTR(monitorbuf);
518 atomic_store_int(state, STATE_SLEEPING);
521 * Since we may be in a critical section from cpu_idle(), if
522 * an interrupt fires during that critical section we may have
523 * a pending preemption. If the CPU halts, then that thread
524 * may not execute until a later interrupt awakens the CPU.
525 * To handle this race, check for a runnable thread after
526 * disabling interrupts and immediately return if one is
527 * found. Also, we must absolutely guarentee that hlt is
528 * the next instruction after sti. This ensures that any
529 * interrupt that fires after the call to disable_intr() will
530 * immediately awaken the CPU from hlt. Finally, please note
531 * that on x86 this works fine because of interrupts enabled only
532 * after the instruction following sti takes place, while IF is set
533 * to 1 immediately, allowing hlt instruction to acknowledge the
537 if (sched_runnable())
541 atomic_store_int(state, STATE_RUNNING);
545 cpu_idle_mwait(sbintime_t sbt)
549 state = (int *)PCPU_PTR(monitorbuf);
550 atomic_store_int(state, STATE_MWAIT);
552 /* See comments in cpu_idle_hlt(). */
554 if (sched_runnable()) {
555 atomic_store_int(state, STATE_RUNNING);
560 cpu_monitor(state, 0, 0);
561 if (atomic_load_int(state) == STATE_MWAIT)
562 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
565 atomic_store_int(state, STATE_RUNNING);
569 cpu_idle_spin(sbintime_t sbt)
574 state = (int *)PCPU_PTR(monitorbuf);
575 atomic_store_int(state, STATE_RUNNING);
578 * The sched_runnable() call is racy but as long as there is
579 * a loop missing it one time will have just a little impact if any
580 * (and it is much better than missing the check at all).
582 for (i = 0; i < 1000; i++) {
583 if (sched_runnable())
590 * C1E renders the local APIC timer dead, so we disable it by
591 * reading the Interrupt Pending Message register and clearing
592 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
595 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
596 * #32559 revision 3.00+
598 #define MSR_AMDK8_IPM 0xc0010055
599 #define AMDK8_SMIONCMPHALT (1ULL << 27)
600 #define AMDK8_C1EONCMPHALT (1ULL << 28)
601 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
604 cpu_probe_amdc1e(void)
608 * Detect the presence of C1E capability mostly on latest
609 * dual-cores (or future) k8 family.
611 if (cpu_vendor_id == CPU_VENDOR_AMD &&
612 (cpu_id & 0x00000f00) == 0x00000f00 &&
613 (cpu_id & 0x0fff0000) >= 0x00040000) {
614 cpu_ident_amdc1e = 1;
618 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
626 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
629 ap_watchdog(PCPU_GET(cpuid));
632 /* If we are busy - try to use fast methods. */
634 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
635 cpu_idle_mwait(busy);
640 /* If we have time - switch timers into idle mode. */
643 sbt = cpu_idleclock();
646 /* Apply AMD APIC timer C1E workaround. */
647 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) {
648 msr = rdmsr(MSR_AMDK8_IPM);
649 if (msr & AMDK8_CMPHALT)
650 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
653 /* Call main idle method. */
656 /* Switch timers back into active mode. */
662 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
666 static int cpu_idle_apl31_workaround;
667 SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW,
668 &cpu_idle_apl31_workaround, 0,
669 "Apollo Lake APL31 MWAIT bug workaround");
672 cpu_idle_wakeup(int cpu)
676 state = (int *)pcpu_find(cpu)->pc_monitorbuf;
677 switch (atomic_load_int(state)) {
681 atomic_store_int(state, STATE_RUNNING);
682 return (cpu_idle_apl31_workaround ? 0 : 1);
686 panic("bad monitor state");
692 * Ordered by speed/power consumption.
699 { .id_fn = cpu_idle_spin, .id_name = "spin" },
700 { .id_fn = cpu_idle_mwait, .id_name = "mwait",
701 .id_cpuid2_flag = CPUID2_MON },
702 { .id_fn = cpu_idle_hlt, .id_name = "hlt" },
703 { .id_fn = cpu_idle_acpi, .id_name = "acpi" },
707 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
713 avail = malloc(256, M_TEMP, M_WAITOK);
715 for (i = 0; i < nitems(idle_tbl); i++) {
716 if (idle_tbl[i].id_cpuid2_flag != 0 &&
717 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
719 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
720 cpu_idle_hook == NULL)
722 p += sprintf(p, "%s%s", p != avail ? ", " : "",
723 idle_tbl[i].id_name);
725 error = sysctl_handle_string(oidp, avail, 0, req);
730 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
731 0, 0, idle_sysctl_available, "A", "list of available idle functions");
734 cpu_idle_selector(const char *new_idle_name)
738 for (i = 0; i < nitems(idle_tbl); i++) {
739 if (idle_tbl[i].id_cpuid2_flag != 0 &&
740 (cpu_feature2 & idle_tbl[i].id_cpuid2_flag) == 0)
742 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
743 cpu_idle_hook == NULL)
745 if (strcmp(idle_tbl[i].id_name, new_idle_name))
747 cpu_idle_fn = idle_tbl[i].id_fn;
749 printf("CPU idle set to %s\n", idle_tbl[i].id_name);
756 cpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
762 for (i = 0; i < nitems(idle_tbl); i++) {
763 if (idle_tbl[i].id_fn == cpu_idle_fn) {
764 p = idle_tbl[i].id_name;
768 strncpy(buf, p, sizeof(buf));
769 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
770 if (error != 0 || req->newptr == NULL)
772 return (cpu_idle_selector(buf) ? 0 : EINVAL);
775 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
776 cpu_idle_sysctl, "A", "currently selected idle function");
779 cpu_idle_tun(void *unused __unused)
783 if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar)))
784 cpu_idle_selector(tunvar);
785 else if (cpu_vendor_id == CPU_VENDOR_AMD &&
786 CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) {
787 /* Ryzen erratas 1057, 1109. */
788 cpu_idle_selector("hlt");
792 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) {
794 * Apollo Lake errata APL31 (public errata APL30).
795 * Stores to the armed address range may not trigger
796 * MWAIT to resume execution. OS needs to use
797 * interrupts to wake processors from MWAIT-induced
800 cpu_idle_apl31_workaround = 1;
802 TUNABLE_INT_FETCH("machdep.idle_apl31", &cpu_idle_apl31_workaround);
804 SYSINIT(cpu_idle_tun, SI_SUB_CPU, SI_ORDER_MIDDLE, cpu_idle_tun, NULL);
806 static int panic_on_nmi = 1;
807 SYSCTL_INT(_machdep, OID_AUTO, panic_on_nmi, CTLFLAG_RWTUN,
809 "Panic on NMI raised by hardware failure");
810 int nmi_is_broadcast = 1;
811 SYSCTL_INT(_machdep, OID_AUTO, nmi_is_broadcast, CTLFLAG_RWTUN,
812 &nmi_is_broadcast, 0,
813 "Chipset NMI is broadcast");
816 SYSCTL_INT(_machdep, OID_AUTO, kdb_on_nmi, CTLFLAG_RWTUN,
818 "Go to KDB on NMI with unknown source");
822 nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame)
824 bool claimed = false;
827 /* machine/parity/power fail/"kitchen sink" faults */
828 if (isa_nmi(frame->tf_err)) {
831 panic("NMI indicates hardware failure");
835 if (!claimed && kdb_on_nmi) {
837 * NMI can be hooked up to a pushbutton for debugging.
839 printf("NMI/cpu%d ... going to debugger\n", cpu);
840 kdb_trap(type, 0, frame);
846 nmi_handle_intr(u_int type, struct trapframe *frame)
850 if (nmi_is_broadcast) {
851 nmi_call_kdb_smp(type, frame);
855 nmi_call_kdb(PCPU_GET(cpuid), type, frame);
858 static int hw_ibrs_active;
859 int hw_ibrs_ibpb_active;
860 int hw_ibrs_disable = 1;
862 SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
863 "Indirect Branch Restricted Speculation active");
866 hw_ibrs_recalculate(bool for_all_cpus)
868 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_IBRS_ALL) != 0) {
869 x86_msr_op(MSR_IA32_SPEC_CTRL, (for_all_cpus ?
870 MSR_OP_RENDEZVOUS : MSR_OP_LOCAL) |
871 (hw_ibrs_disable != 0 ? MSR_OP_ANDNOT : MSR_OP_OR),
872 IA32_SPEC_CTRL_IBRS);
873 hw_ibrs_active = hw_ibrs_disable == 0;
874 hw_ibrs_ibpb_active = 0;
876 hw_ibrs_active = hw_ibrs_ibpb_active = (cpu_stdext_feature3 &
877 CPUID_STDEXT3_IBPB) != 0 && !hw_ibrs_disable;
882 hw_ibrs_disable_handler(SYSCTL_HANDLER_ARGS)
886 val = hw_ibrs_disable;
887 error = sysctl_handle_int(oidp, &val, 0, req);
888 if (error != 0 || req->newptr == NULL)
890 hw_ibrs_disable = val != 0;
891 hw_ibrs_recalculate(true);
894 SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
895 CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
896 "Disable Indirect Branch Restricted Speculation");
901 SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD,
903 "Speculative Store Bypass Disable active");
906 hw_ssb_set(bool enable, bool for_all_cpus)
909 if ((cpu_stdext_feature3 & CPUID_STDEXT3_SSBD) == 0) {
913 hw_ssb_active = enable;
914 x86_msr_op(MSR_IA32_SPEC_CTRL,
915 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
916 (for_all_cpus ? MSR_OP_SCHED : MSR_OP_LOCAL), IA32_SPEC_CTRL_SSBD);
920 hw_ssb_recalculate(bool all_cpus)
923 switch (hw_ssb_disable) {
928 hw_ssb_set(false, all_cpus);
931 hw_ssb_set(true, all_cpus);
934 hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ?
935 false : true, all_cpus);
941 hw_ssb_disable_handler(SYSCTL_HANDLER_ARGS)
945 val = hw_ssb_disable;
946 error = sysctl_handle_int(oidp, &val, 0, req);
947 if (error != 0 || req->newptr == NULL)
949 hw_ssb_disable = val;
950 hw_ssb_recalculate(true);
953 SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
954 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
955 hw_ssb_disable_handler, "I",
956 "Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
961 * Handler for Microarchitectural Data Sampling issues. Really not a
962 * pointer to C function: on amd64 the code must not change any CPU
963 * architectural state except possibly %rflags. Also, it is always
964 * called with interrupts disabled.
966 void mds_handler_void(void);
967 void mds_handler_verw(void);
968 void mds_handler_ivb(void);
969 void mds_handler_bdw(void);
970 void mds_handler_skl_sse(void);
971 void mds_handler_skl_avx(void);
972 void mds_handler_skl_avx512(void);
973 void mds_handler_silvermont(void);
974 void (*mds_handler)(void) = mds_handler_void;
977 sysctl_hw_mds_disable_state_handler(SYSCTL_HANDLER_ARGS)
981 if (mds_handler == mds_handler_void)
983 else if (mds_handler == mds_handler_verw)
985 else if (mds_handler == mds_handler_ivb)
986 state = "software IvyBridge";
987 else if (mds_handler == mds_handler_bdw)
988 state = "software Broadwell";
989 else if (mds_handler == mds_handler_skl_sse)
990 state = "software Skylake SSE";
991 else if (mds_handler == mds_handler_skl_avx)
992 state = "software Skylake AVX";
993 else if (mds_handler == mds_handler_skl_avx512)
994 state = "software Skylake AVX512";
995 else if (mds_handler == mds_handler_silvermont)
996 state = "software Silvermont";
999 return (SYSCTL_OUT(req, state, strlen(state)));
1002 SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state,
1003 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1004 sysctl_hw_mds_disable_state_handler, "A",
1005 "Microarchitectural Data Sampling Mitigation state");
1007 _Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512");
1010 hw_mds_recalculate(void)
1018 * Allow user to force VERW variant even if MD_CLEAR is not
1019 * reported. For instance, hypervisor might unknowingly
1020 * filter the cap out.
1021 * For the similar reasons, and for testing, allow to enable
1022 * mitigation even when MDS_NO cap is set.
1024 if (cpu_vendor_id != CPU_VENDOR_INTEL || hw_mds_disable == 0 ||
1025 ((cpu_ia32_arch_caps & IA32_ARCH_CAP_MDS_NO) != 0 &&
1026 hw_mds_disable == 3)) {
1027 mds_handler = mds_handler_void;
1028 } else if (((cpu_stdext_feature3 & CPUID_STDEXT3_MD_CLEAR) != 0 &&
1029 hw_mds_disable == 3) || hw_mds_disable == 1) {
1030 mds_handler = mds_handler_verw;
1031 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1032 (CPUID_TO_MODEL(cpu_id) == 0x2e || CPUID_TO_MODEL(cpu_id) == 0x1e ||
1033 CPUID_TO_MODEL(cpu_id) == 0x1f || CPUID_TO_MODEL(cpu_id) == 0x1a ||
1034 CPUID_TO_MODEL(cpu_id) == 0x2f || CPUID_TO_MODEL(cpu_id) == 0x25 ||
1035 CPUID_TO_MODEL(cpu_id) == 0x2c || CPUID_TO_MODEL(cpu_id) == 0x2d ||
1036 CPUID_TO_MODEL(cpu_id) == 0x2a || CPUID_TO_MODEL(cpu_id) == 0x3e ||
1037 CPUID_TO_MODEL(cpu_id) == 0x3a) &&
1038 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1040 * Nehalem, SandyBridge, IvyBridge
1044 if (pc->pc_mds_buf == NULL) {
1045 pc->pc_mds_buf = malloc_domainset(672, M_TEMP,
1046 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1047 bzero(pc->pc_mds_buf, 16);
1050 mds_handler = mds_handler_ivb;
1051 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1052 (CPUID_TO_MODEL(cpu_id) == 0x3f || CPUID_TO_MODEL(cpu_id) == 0x3c ||
1053 CPUID_TO_MODEL(cpu_id) == 0x45 || CPUID_TO_MODEL(cpu_id) == 0x46 ||
1054 CPUID_TO_MODEL(cpu_id) == 0x56 || CPUID_TO_MODEL(cpu_id) == 0x4f ||
1055 CPUID_TO_MODEL(cpu_id) == 0x47 || CPUID_TO_MODEL(cpu_id) == 0x3d) &&
1056 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1058 * Haswell, Broadwell
1062 if (pc->pc_mds_buf == NULL) {
1063 pc->pc_mds_buf = malloc_domainset(1536, M_TEMP,
1064 DOMAINSET_PREF(pc->pc_domain), M_WAITOK);
1065 bzero(pc->pc_mds_buf, 16);
1068 mds_handler = mds_handler_bdw;
1069 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1070 ((CPUID_TO_MODEL(cpu_id) == 0x55 && (cpu_id &
1071 CPUID_STEPPING) <= 5) ||
1072 CPUID_TO_MODEL(cpu_id) == 0x4e || CPUID_TO_MODEL(cpu_id) == 0x5e ||
1073 (CPUID_TO_MODEL(cpu_id) == 0x8e && (cpu_id &
1074 CPUID_STEPPING) <= 0xb) ||
1075 (CPUID_TO_MODEL(cpu_id) == 0x9e && (cpu_id &
1076 CPUID_STEPPING) <= 0xc)) &&
1077 (hw_mds_disable == 2 || hw_mds_disable == 3)) {
1079 * Skylake, KabyLake, CoffeeLake, WhiskeyLake,
1084 if (pc->pc_mds_buf == NULL) {
1085 pc->pc_mds_buf = malloc_domainset(6 * 1024,
1086 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1088 b64 = (vm_offset_t)malloc_domainset(64 + 63,
1089 M_TEMP, DOMAINSET_PREF(pc->pc_domain),
1091 pc->pc_mds_buf64 = (void *)roundup2(b64, 64);
1092 bzero(pc->pc_mds_buf64, 64);
1096 if ((xcr0 & XFEATURE_ENABLED_ZMM_HI256) != 0 &&
1097 (cpu_stdext_feature2 & CPUID_STDEXT_AVX512DQ) != 0)
1098 mds_handler = mds_handler_skl_avx512;
1099 else if ((xcr0 & XFEATURE_ENABLED_AVX) != 0 &&
1100 (cpu_feature2 & CPUID2_AVX) != 0)
1101 mds_handler = mds_handler_skl_avx;
1103 mds_handler = mds_handler_skl_sse;
1104 } else if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1105 ((CPUID_TO_MODEL(cpu_id) == 0x37 ||
1106 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1107 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1108 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1109 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1110 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1111 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1112 CPUID_TO_MODEL(cpu_id) == 0x65 ||
1113 CPUID_TO_MODEL(cpu_id) == 0x75 ||
1114 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1115 CPUID_TO_MODEL(cpu_id) == 0x26 ||
1116 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1117 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1118 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1119 CPUID_TO_MODEL(cpu_id) == 0x7a))) {
1120 /* Silvermont, Airmont */
1123 if (pc->pc_mds_buf == NULL)
1124 pc->pc_mds_buf = malloc(256, M_TEMP, M_WAITOK);
1126 mds_handler = mds_handler_silvermont;
1129 mds_handler = mds_handler_void;
1134 hw_mds_recalculate_boot(void *arg __unused)
1137 hw_mds_recalculate();
1139 SYSINIT(mds_recalc, SI_SUB_SMP, SI_ORDER_ANY, hw_mds_recalculate_boot, NULL);
1142 sysctl_mds_disable_handler(SYSCTL_HANDLER_ARGS)
1146 val = hw_mds_disable;
1147 error = sysctl_handle_int(oidp, &val, 0, req);
1148 if (error != 0 || req->newptr == NULL)
1150 if (val < 0 || val > 3)
1152 hw_mds_disable = val;
1153 hw_mds_recalculate();
1157 SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
1158 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1159 sysctl_mds_disable_handler, "I",
1160 "Microarchitectural Data Sampling Mitigation "
1161 "(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
1165 * Intel Transactional Memory Asynchronous Abort Mitigation
1171 TAA_NONE = 0, /* No mitigation enabled */
1172 TAA_TSX_DISABLE = 1, /* Disable TSX via MSR */
1173 TAA_VERW = 2, /* Use VERW mitigation */
1174 TAA_AUTO = 3, /* Automatically select the mitigation */
1176 /* The states below are not selectable by the operator */
1178 TAA_TAA_UC = 4, /* Mitigation present in microcode */
1179 TAA_NOT_PRESENT = 5 /* TSX is not present */
1183 taa_set(bool enable, bool all)
1186 x86_msr_op(MSR_IA32_TSX_CTRL,
1187 (enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1188 (all ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL),
1189 IA32_TSX_CTRL_RTM_DISABLE | IA32_TSX_CTRL_TSX_CPUID_CLEAR);
1193 x86_taa_recalculate(void)
1195 static int taa_saved_mds_disable = 0;
1196 int taa_need = 0, taa_state = 0;
1197 int mds_disable = 0, need_mds_recalc = 0;
1199 /* Check CPUID.07h.EBX.HLE and RTM for the presence of TSX */
1200 if ((cpu_stdext_feature & CPUID_STDEXT_HLE) == 0 ||
1201 (cpu_stdext_feature & CPUID_STDEXT_RTM) == 0) {
1202 /* TSX is not present */
1203 x86_taa_state = TAA_NOT_PRESENT;
1207 /* Check to see what mitigation options the CPU gives us */
1208 if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TAA_NO) {
1209 /* CPU is not suseptible to TAA */
1210 taa_need = TAA_TAA_UC;
1211 } else if (cpu_ia32_arch_caps & IA32_ARCH_CAP_TSX_CTRL) {
1213 * CPU can turn off TSX. This is the next best option
1214 * if TAA_NO hardware mitigation isn't present
1216 taa_need = TAA_TSX_DISABLE;
1218 /* No TSX/TAA specific remedies are available. */
1219 if (x86_taa_enable == TAA_TSX_DISABLE) {
1221 printf("TSX control not available\n");
1224 taa_need = TAA_VERW;
1227 /* Can we automatically take action, or are we being forced? */
1228 if (x86_taa_enable == TAA_AUTO)
1229 taa_state = taa_need;
1231 taa_state = x86_taa_enable;
1233 /* No state change, nothing to do */
1234 if (taa_state == x86_taa_state) {
1236 printf("No TSX change made\n");
1240 /* Does the MSR need to be turned on or off? */
1241 if (taa_state == TAA_TSX_DISABLE)
1242 taa_set(true, true);
1243 else if (x86_taa_state == TAA_TSX_DISABLE)
1244 taa_set(false, true);
1246 /* Does MDS need to be set to turn on VERW? */
1247 if (taa_state == TAA_VERW) {
1248 taa_saved_mds_disable = hw_mds_disable;
1249 mds_disable = hw_mds_disable = 1;
1250 need_mds_recalc = 1;
1251 } else if (x86_taa_state == TAA_VERW) {
1252 mds_disable = hw_mds_disable = taa_saved_mds_disable;
1253 need_mds_recalc = 1;
1255 if (need_mds_recalc) {
1256 hw_mds_recalculate();
1257 if (mds_disable != hw_mds_disable) {
1259 printf("Cannot change MDS state for TAA\n");
1260 /* Don't update our state */
1265 x86_taa_state = taa_state;
1270 taa_recalculate_boot(void * arg __unused)
1273 x86_taa_recalculate();
1275 SYSINIT(taa_recalc, SI_SUB_SMP, SI_ORDER_ANY, taa_recalculate_boot, NULL);
1277 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, taa, CTLFLAG_RW, 0,
1278 "TSX Asynchronous Abort Mitigation");
1281 sysctl_taa_handler(SYSCTL_HANDLER_ARGS)
1285 val = x86_taa_enable;
1286 error = sysctl_handle_int(oidp, &val, 0, req);
1287 if (error != 0 || req->newptr == NULL)
1289 if (val < TAA_NONE || val > TAA_AUTO)
1291 x86_taa_enable = val;
1292 x86_taa_recalculate();
1296 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, enable, CTLTYPE_INT |
1297 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1298 sysctl_taa_handler, "I",
1299 "TAA Mitigation enablement control "
1300 "(0 - off, 1 - disable TSX, 2 - VERW, 3 - on AUTO");
1303 sysctl_taa_state_handler(SYSCTL_HANDLER_ARGS)
1307 switch (x86_taa_state) {
1311 case TAA_TSX_DISABLE:
1312 state = "TSX disabled";
1318 state = "Mitigated in microcode";
1320 case TAA_NOT_PRESENT:
1321 state = "TSX not present";
1327 return (SYSCTL_OUT(req, state, strlen(state)));
1330 SYSCTL_PROC(_machdep_mitigations_taa, OID_AUTO, state,
1331 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1332 sysctl_taa_state_handler, "A",
1333 "TAA Mitigation state");
1335 int __read_frequently cpu_flush_rsb_ctxsw;
1336 SYSCTL_INT(_machdep_mitigations, OID_AUTO, flush_rsb_ctxsw,
1337 CTLFLAG_RW | CTLFLAG_NOFETCH, &cpu_flush_rsb_ctxsw, 0,
1338 "Flush Return Stack Buffer on context switch");
1340 SYSCTL_NODE(_machdep_mitigations, OID_AUTO, rngds,
1341 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1342 "MCU Optimization, disable RDSEED mitigation");
1344 int x86_rngds_mitg_enable = 1;
1346 x86_rngds_mitg_recalculate(bool all_cpus)
1348 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0)
1350 x86_msr_op(MSR_IA32_MCU_OPT_CTRL,
1351 (x86_rngds_mitg_enable ? MSR_OP_OR : MSR_OP_ANDNOT) |
1352 (all_cpus ? MSR_OP_RENDEZVOUS : MSR_OP_LOCAL),
1353 IA32_RNGDS_MITG_DIS);
1357 sysctl_rngds_mitg_enable_handler(SYSCTL_HANDLER_ARGS)
1361 val = x86_rngds_mitg_enable;
1362 error = sysctl_handle_int(oidp, &val, 0, req);
1363 if (error != 0 || req->newptr == NULL)
1365 x86_rngds_mitg_enable = val;
1366 x86_rngds_mitg_recalculate(true);
1369 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, enable, CTLTYPE_INT |
1370 CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
1371 sysctl_rngds_mitg_enable_handler, "I",
1372 "MCU Optimization, disabling RDSEED mitigation control "
1373 "(0 - mitigation disabled (RDSEED optimized), 1 - mitigation enabled");
1376 sysctl_rngds_state_handler(SYSCTL_HANDLER_ARGS)
1380 if ((cpu_stdext_feature3 & CPUID_STDEXT3_MCUOPT) == 0) {
1381 state = "Not applicable";
1382 } else if (x86_rngds_mitg_enable == 0) {
1383 state = "RDSEED not serialized";
1385 state = "Mitigated";
1387 return (SYSCTL_OUT(req, state, strlen(state)));
1389 SYSCTL_PROC(_machdep_mitigations_rngds, OID_AUTO, state,
1390 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1391 sysctl_rngds_state_handler, "A",
1392 "MCU Optimization state");
1395 * Enable and restore kernel text write permissions.
1396 * Callers must ensure that disable_wp()/restore_wp() are executed
1397 * without rescheduling on the same core.
1405 if ((cr0 & CR0_WP) == 0)
1407 load_cr0(cr0 & ~CR0_WP);
1412 restore_wp(bool old_wp)
1416 load_cr0(rcr0() | CR0_WP);
1420 acpi_get_fadt_bootflags(uint16_t *flagsp)
1423 ACPI_TABLE_FADT *fadt;
1424 vm_paddr_t physaddr;
1426 physaddr = acpi_find_table(ACPI_SIG_FADT);
1429 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT);
1432 *flagsp = fadt->BootFlags;
1433 acpi_unmap_table(fadt);