2 * Mach Operating System
3 * Copyright (c) 1991,1990 Carnegie Mellon University
6 * Permission to use, copy, modify and distribute this software and its
7 * documentation is hereby granted, provided that both the copyright
8 * notice and this permission notice appear in all copies of the
9 * software, derivative works or modified versions, and any portions
10 * thereof, and that both notices appear in supporting documentation.
12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
16 * Carnegie Mellon requests users of this software to return to
18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
19 * School of Computer Science
20 * Carnegie Mellon University
21 * Pittsburgh PA 15213-3890
23 * any improvements or extensions that they make and grant Carnegie the
24 * rights to redistribute these changes.
29 #include <sys/types.h>
34 #include <sys/systm.h>
36 #include <machine/frame.h>
37 #include <machine/kdb.h>
38 #include <machine/md_var.h>
41 #include <ddb/db_sym.h>
45 #define MAXWATCHSIZE 8
47 #define MAXWATCHSIZE 4
51 * Set a watchpoint in the debug register denoted by 'watchnum'.
54 dbreg_set_watchreg(int watchnum, vm_offset_t watchaddr, vm_size_t size,
55 int access, struct dbreg *d)
59 MPASS(watchnum >= 0 && watchnum < NDBREGS);
61 /* size must be 1 for an execution breakpoint */
62 if (access == DBREG_DR7_EXEC)
66 * we can watch a 1, 2, or 4 byte sized location
70 len = DBREG_DR7_LEN_1;
73 len = DBREG_DR7_LEN_2;
76 len = DBREG_DR7_LEN_4;
80 len = DBREG_DR7_LEN_8;
87 /* clear the bits we are about to affect */
88 d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
90 /* set drN register to the address, N=watchnum */
91 DBREG_DRX(d, watchnum) = watchaddr;
93 /* enable the watchpoint */
94 d->dr[7] |= DBREG_DR7_SET(watchnum, len, access,
95 DBREG_DR7_GLOBAL_ENABLE);
99 * Remove a watchpoint from the debug register denoted by 'watchnum'.
102 dbreg_clr_watchreg(int watchnum, struct dbreg *d)
104 MPASS(watchnum >= 0 && watchnum < NDBREGS);
106 d->dr[7] &= ~DBREG_DR7_MASK(watchnum);
107 DBREG_DRX(d, watchnum) = 0;
111 * Sync the debug registers. Other cores will read these values from the PCPU
112 * area when they resume. See amd64_db_resume_dbreg() below.
115 dbreg_sync(struct dbreg *dp)
121 cpu = PCPU_GET(cpuid);
126 memcpy(pc->pc_dbreg, dp, sizeof(*dp));
127 pc->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
133 dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access)
139 d = (struct dbreg *)PCPU_PTR(dbreg);
141 /* debug registers aren't stored in PCPU on i386. */
146 /* Validate the access type */
147 if (access != DBREG_DR7_EXEC && access != DBREG_DR7_WRONLY &&
148 access != DBREG_DR7_RDWR)
151 fill_dbregs(NULL, d);
154 * Check if there are enough available registers to cover the desired
158 for (i = 0; i < NDBREGS; i++) {
159 if (!DBREG_DR7_ENABLED(d->dr[7], i))
163 if (avail * MAXWATCHSIZE < size)
166 for (i = 0; i < NDBREGS && size > 0; i++) {
167 if (!DBREG_DR7_ENABLED(d->dr[7], i)) {
168 if ((size >= 8 || (avail == 1 && size > 4)) &&
175 dbreg_set_watchreg(i, addr, wsize, access, d);
189 dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size)
195 d = (struct dbreg *)PCPU_PTR(dbreg);
197 /* debug registers aren't stored in PCPU on i386. */
201 fill_dbregs(NULL, d);
203 for (i = 0; i < NDBREGS; i++) {
204 if (DBREG_DR7_ENABLED(d->dr[7], i)) {
205 if (DBREG_DRX((d), i) >= addr &&
206 DBREG_DRX((d), i) < addr + size)
207 dbreg_clr_watchreg(i, d);
219 watchtype_str(int type)
226 return ("read/write");
227 case DBREG_DR7_WRONLY:
235 dbreg_list_watchpoints(void)
240 fill_dbregs(NULL, &d);
242 db_printf("\nhardware watchpoints:\n");
243 db_printf(" watch status type len address\n");
244 db_printf(" ----- -------- ---------- --- ----------\n");
245 for (i = 0; i < NDBREGS; i++) {
246 if (DBREG_DR7_ENABLED(d.dr[7], i)) {
247 type = DBREG_DR7_ACCESS(d.dr[7], i);
248 len = DBREG_DR7_LEN(d.dr[7], i);
249 db_printf(" %-5d %-8s %10s %3d ",
250 i, "enabled", watchtype_str(type), len + 1);
251 db_printsym((db_addr_t)DBREG_DRX(&d, i), DB_STGY_ANY);
254 db_printf(" %-5d disabled\n", i);
261 /* Sync debug registers when resuming from debugger. */
263 amd64_db_resume_dbreg(void)
267 switch (PCPU_GET(dbreg_cmd)) {
268 case PC_DBREG_CMD_LOAD:
269 d = (struct dbreg *)PCPU_PTR(dbreg);
271 PCPU_SET(dbreg_cmd, PC_DBREG_CMD_NONE);
278 kdb_cpu_set_watchpoint(vm_offset_t addr, vm_size_t size, int access)
281 /* Convert the KDB access type */
283 case KDB_DBG_ACCESS_W:
284 access = DBREG_DR7_WRONLY;
286 case KDB_DBG_ACCESS_RW:
287 access = DBREG_DR7_RDWR;
289 case KDB_DBG_ACCESS_R:
290 /* FALLTHROUGH: read-only not supported */
295 return (dbreg_set_watchpoint(addr, size, access));
299 kdb_cpu_clr_watchpoint(vm_offset_t addr, vm_size_t size)
302 return (dbreg_clr_watchpoint(addr, size));