sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 122 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %eax */
 123 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %eax */
 124 u_int   cpu_power_edx;          /* 06H: Power management leaf, %eax */
 125 char machine[] = MACHINE;
 126
 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 128     &via_feature_rng, 0,
 129     "VIA RNG feature available in CPU");
 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 131     &via_feature_xcrypt, 0,
 132     "VIA xcrypt feature available in CPU");
 133
 134 #ifdef __amd64__
 135 #ifdef SCTL_MASK32
 136 extern int adaptive_machine_arch;
 137 #endif
 138
 139 static int
 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 141 {
 142 #ifdef SCTL_MASK32
 143         static const char machine32[] = "i386";
 144 #endif
 145         int error;
 146
 147 #ifdef SCTL_MASK32
 148         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 149                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 150         else
 151 #endif
 152                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 153         return (error);
 154
 155 }
 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 157     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 158 #else
 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 160     machine, 0, "Machine class");
 161 #endif
 162
 163 static char cpu_model[128];
 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 165     cpu_model, 0, "Machine model");
 166
 167 static int hw_clockrate;
 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 169     &hw_clockrate, 0, "CPU instruction clock rate");
 170
 171 u_int hv_base;
 172 u_int hv_high;
 173 char hv_vendor[16];
 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 175     0, "Hypervisor vendor");
 176
 177 static eventhandler_tag tsc_post_tag;
 178
 179 static char cpu_brand[48];
 180
 181 #ifdef __i386__
 182 #define MAX_BRAND_INDEX 8
 183
 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 185         NULL,                   /* No brand */
 186         "Intel Celeron",
 187         "Intel Pentium III",
 188         "Intel Pentium III Xeon",
 189         NULL,
 190         NULL,
 191         NULL,
 192         NULL,
 193         "Intel Pentium 4"
 194 };
 195
 196 static struct {
 197         char    *cpu_name;
 198         int     cpu_class;
 199 } cpus[] = {
 200         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 201         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 202         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 203         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 204         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 205         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 206         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 207         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 208         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 209         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 210         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 211         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 212         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 213         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 214         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 215         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 216         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 217 };
 218 #endif
 219
 220 static struct {
 221         char    *vendor;
 222         u_int   vendor_id;
 223 } cpu_vendors[] = {
 224         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 225         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 226         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 227 #ifdef __i386__
 228         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 229         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 230         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 231         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 232         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 233         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 234         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 235 #if 0
 236         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 237         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 238 #endif
 239 #endif
 240 };
 241
 242 void
 243 printcpuinfo(void)
 244 {
 245         u_int regs[4], i;
 246         char *brand;
 247
 248         printf("CPU: ");
 249 #ifdef __i386__
 250         cpu_class = cpus[cpu].cpu_class;
 251         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 252 #else
 253         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 254 #endif
 255
 256         /* Check for extended CPUID information and a processor name. */
 257         if (cpu_exthigh >= 0x80000004) {
 258                 brand = cpu_brand;
 259                 for (i = 0x80000002; i < 0x80000005; i++) {
 260                         do_cpuid(i, regs);
 261                         memcpy(brand, regs, sizeof(regs));
 262                         brand += sizeof(regs);
 263                 }
 264         }
 265
 266         switch (cpu_vendor_id) {
 267         case CPU_VENDOR_INTEL:
 268 #ifdef __i386__
 269                 if ((cpu_id & 0xf00) > 0x300) {
 270                         u_int brand_index;
 271
 272                         cpu_model[0] = '\0';
 273
 274                         switch (cpu_id & 0x3000) {
 275                         case 0x1000:
 276                                 strcpy(cpu_model, "Overdrive ");
 277                                 break;
 278                         case 0x2000:
 279                                 strcpy(cpu_model, "Dual ");
 280                                 break;
 281                         }
 282
 283                         switch (cpu_id & 0xf00) {
 284                         case 0x400:
 285                                 strcat(cpu_model, "i486 ");
 286                                 /* Check the particular flavor of 486 */
 287                                 switch (cpu_id & 0xf0) {
 288                                 case 0x00:
 289                                 case 0x10:
 290                                         strcat(cpu_model, "DX");
 291                                         break;
 292                                 case 0x20:
 293                                         strcat(cpu_model, "SX");
 294                                         break;
 295                                 case 0x30:
 296                                         strcat(cpu_model, "DX2");
 297                                         break;
 298                                 case 0x40:
 299                                         strcat(cpu_model, "SL");
 300                                         break;
 301                                 case 0x50:
 302                                         strcat(cpu_model, "SX2");
 303                                         break;
 304                                 case 0x70:
 305                                         strcat(cpu_model,
 306                                             "DX2 Write-Back Enhanced");
 307                                         break;
 308                                 case 0x80:
 309                                         strcat(cpu_model, "DX4");
 310                                         break;
 311                                 }
 312                                 break;
 313                         case 0x500:
 314                                 /* Check the particular flavor of 586 */
 315                                 strcat(cpu_model, "Pentium");
 316                                 switch (cpu_id & 0xf0) {
 317                                 case 0x00:
 318                                         strcat(cpu_model, " A-step");
 319                                         break;
 320                                 case 0x10:
 321                                         strcat(cpu_model, "/P5");
 322                                         break;
 323                                 case 0x20:
 324                                         strcat(cpu_model, "/P54C");
 325                                         break;
 326                                 case 0x30:
 327                                         strcat(cpu_model, "/P24T");
 328                                         break;
 329                                 case 0x40:
 330                                         strcat(cpu_model, "/P55C");
 331                                         break;
 332                                 case 0x70:
 333                                         strcat(cpu_model, "/P54C");
 334                                         break;
 335                                 case 0x80:
 336                                         strcat(cpu_model, "/P55C (quarter-micron)");
 337                                         break;
 338                                 default:
 339                                         /* nothing */
 340                                         break;
 341                                 }
 342 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 343                                 /*
 344                                  * XXX - If/when Intel fixes the bug, this
 345                                  * should also check the version of the
 346                                  * CPU, not just that it's a Pentium.
 347                                  */
 348                                 has_f00f_bug = 1;
 349 #endif
 350                                 break;
 351                         case 0x600:
 352                                 /* Check the particular flavor of 686 */
 353                                 switch (cpu_id & 0xf0) {
 354                                 case 0x00:
 355                                         strcat(cpu_model, "Pentium Pro A-step");
 356                                         break;
 357                                 case 0x10:
 358                                         strcat(cpu_model, "Pentium Pro");
 359                                         break;
 360                                 case 0x30:
 361                                 case 0x50:
 362                                 case 0x60:
 363                                         strcat(cpu_model,
 364                                 "Pentium II/Pentium II Xeon/Celeron");
 365                                         cpu = CPU_PII;
 366                                         break;
 367                                 case 0x70:
 368                                 case 0x80:
 369                                 case 0xa0:
 370                                 case 0xb0:
 371                                         strcat(cpu_model,
 372                                         "Pentium III/Pentium III Xeon/Celeron");
 373                                         cpu = CPU_PIII;
 374                                         break;
 375                                 default:
 376                                         strcat(cpu_model, "Unknown 80686");
 377                                         break;
 378                                 }
 379                                 break;
 380                         case 0xf00:
 381                                 strcat(cpu_model, "Pentium 4");
 382                                 cpu = CPU_P4;
 383                                 break;
 384                         default:
 385                                 strcat(cpu_model, "unknown");
 386                                 break;
 387                         }
 388
 389                         /*
 390                          * If we didn't get a brand name from the extended
 391                          * CPUID, try to look it up in the brand table.
 392                          */
 393                         if (cpu_high > 0 && *cpu_brand == '\0') {
 394                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 395                                 if (brand_index <= MAX_BRAND_INDEX &&
 396                                     cpu_brandtable[brand_index] != NULL)
 397                                         strcpy(cpu_brand,
 398                                             cpu_brandtable[brand_index]);
 399                         }
 400                 }
 401 #else
 402                 /* Please make up your mind folks! */
 403                 strcat(cpu_model, "EM64T");
 404 #endif
 405                 break;
 406         case CPU_VENDOR_AMD:
 407                 /*
 408                  * Values taken from AMD Processor Recognition
 409                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 410                  * (also describes ``Features'' encodings.
 411                  */
 412                 strcpy(cpu_model, "AMD ");
 413 #ifdef __i386__
 414                 switch (cpu_id & 0xFF0) {
 415                 case 0x410:
 416                         strcat(cpu_model, "Standard Am486DX");
 417                         break;
 418                 case 0x430:
 419                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 420                         break;
 421                 case 0x470:
 422                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 423                         break;
 424                 case 0x480:
 425                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 426                         break;
 427                 case 0x490:
 428                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 429                         break;
 430                 case 0x4E0:
 431                         strcat(cpu_model, "Am5x86 Write-Through");
 432                         break;
 433                 case 0x4F0:
 434                         strcat(cpu_model, "Am5x86 Write-Back");
 435                         break;
 436                 case 0x500:
 437                         strcat(cpu_model, "K5 model 0");
 438                         break;
 439                 case 0x510:
 440                         strcat(cpu_model, "K5 model 1");
 441                         break;
 442                 case 0x520:
 443                         strcat(cpu_model, "K5 PR166 (model 2)");
 444                         break;
 445                 case 0x530:
 446                         strcat(cpu_model, "K5 PR200 (model 3)");
 447                         break;
 448                 case 0x560:
 449                         strcat(cpu_model, "K6");
 450                         break;
 451                 case 0x570:
 452                         strcat(cpu_model, "K6 266 (model 1)");
 453                         break;
 454                 case 0x580:
 455                         strcat(cpu_model, "K6-2");
 456                         break;
 457                 case 0x590:
 458                         strcat(cpu_model, "K6-III");
 459                         break;
 460                 case 0x5a0:
 461                         strcat(cpu_model, "Geode LX");
 462                         break;
 463                 default:
 464                         strcat(cpu_model, "Unknown");
 465                         break;
 466                 }
 467 #else
 468                 if ((cpu_id & 0xf00) == 0xf00)
 469                         strcat(cpu_model, "AMD64 Processor");
 470                 else
 471                         strcat(cpu_model, "Unknown");
 472 #endif
 473                 break;
 474 #ifdef __i386__
 475         case CPU_VENDOR_CYRIX:
 476                 strcpy(cpu_model, "Cyrix ");
 477                 switch (cpu_id & 0xff0) {
 478                 case 0x440:
 479                         strcat(cpu_model, "MediaGX");
 480                         break;
 481                 case 0x520:
 482                         strcat(cpu_model, "6x86");
 483                         break;
 484                 case 0x540:
 485                         cpu_class = CPUCLASS_586;
 486                         strcat(cpu_model, "GXm");
 487                         break;
 488                 case 0x600:
 489                         strcat(cpu_model, "6x86MX");
 490                         break;
 491                 default:
 492                         /*
 493                          * Even though CPU supports the cpuid
 494                          * instruction, it can be disabled.
 495                          * Therefore, this routine supports all Cyrix
 496                          * CPUs.
 497                          */
 498                         switch (cyrix_did & 0xf0) {
 499                         case 0x00:
 500                                 switch (cyrix_did & 0x0f) {
 501                                 case 0x00:
 502                                         strcat(cpu_model, "486SLC");
 503                                         break;
 504                                 case 0x01:
 505                                         strcat(cpu_model, "486DLC");
 506                                         break;
 507                                 case 0x02:
 508                                         strcat(cpu_model, "486SLC2");
 509                                         break;
 510                                 case 0x03:
 511                                         strcat(cpu_model, "486DLC2");
 512                                         break;
 513                                 case 0x04:
 514                                         strcat(cpu_model, "486SRx");
 515                                         break;
 516                                 case 0x05:
 517                                         strcat(cpu_model, "486DRx");
 518                                         break;
 519                                 case 0x06:
 520                                         strcat(cpu_model, "486SRx2");
 521                                         break;
 522                                 case 0x07:
 523                                         strcat(cpu_model, "486DRx2");
 524                                         break;
 525                                 case 0x08:
 526                                         strcat(cpu_model, "486SRu");
 527                                         break;
 528                                 case 0x09:
 529                                         strcat(cpu_model, "486DRu");
 530                                         break;
 531                                 case 0x0a:
 532                                         strcat(cpu_model, "486SRu2");
 533                                         break;
 534                                 case 0x0b:
 535                                         strcat(cpu_model, "486DRu2");
 536                                         break;
 537                                 default:
 538                                         strcat(cpu_model, "Unknown");
 539                                         break;
 540                                 }
 541                                 break;
 542                         case 0x10:
 543                                 switch (cyrix_did & 0x0f) {
 544                                 case 0x00:
 545                                         strcat(cpu_model, "486S");
 546                                         break;
 547                                 case 0x01:
 548                                         strcat(cpu_model, "486S2");
 549                                         break;
 550                                 case 0x02:
 551                                         strcat(cpu_model, "486Se");
 552                                         break;
 553                                 case 0x03:
 554                                         strcat(cpu_model, "486S2e");
 555                                         break;
 556                                 case 0x0a:
 557                                         strcat(cpu_model, "486DX");
 558                                         break;
 559                                 case 0x0b:
 560                                         strcat(cpu_model, "486DX2");
 561                                         break;
 562                                 case 0x0f:
 563                                         strcat(cpu_model, "486DX4");
 564                                         break;
 565                                 default:
 566                                         strcat(cpu_model, "Unknown");
 567                                         break;
 568                                 }
 569                                 break;
 570                         case 0x20:
 571                                 if ((cyrix_did & 0x0f) < 8)
 572                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 573                                 else
 574                                         strcat(cpu_model, "5x86");
 575                                 break;
 576                         case 0x30:
 577                                 strcat(cpu_model, "6x86");
 578                                 break;
 579                         case 0x40:
 580                                 if ((cyrix_did & 0xf000) == 0x3000) {
 581                                         cpu_class = CPUCLASS_586;
 582                                         strcat(cpu_model, "GXm");
 583                                 } else
 584                                         strcat(cpu_model, "MediaGX");
 585                                 break;
 586                         case 0x50:
 587                                 strcat(cpu_model, "6x86MX");
 588                                 break;
 589                         case 0xf0:
 590                                 switch (cyrix_did & 0x0f) {
 591                                 case 0x0d:
 592                                         strcat(cpu_model, "Overdrive CPU");
 593                                         break;
 594                                 case 0x0e:
 595                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 596                                         break;
 597                                 case 0x0f:
 598                                         strcat(cpu_model, "486SLC/DLC");
 599                                         break;
 600                                 default:
 601                                         strcat(cpu_model, "Unknown");
 602                                         break;
 603                                 }
 604                                 break;
 605                         default:
 606                                 strcat(cpu_model, "Unknown");
 607                                 break;
 608                         }
 609                         break;
 610                 }
 611                 break;
 612         case CPU_VENDOR_RISE:
 613                 strcpy(cpu_model, "Rise ");
 614                 switch (cpu_id & 0xff0) {
 615                 case 0x500:     /* 6401 and 6441 (Kirin) */
 616                 case 0x520:     /* 6510 (Lynx) */
 617                         strcat(cpu_model, "mP6");
 618                         break;
 619                 default:
 620                         strcat(cpu_model, "Unknown");
 621                 }
 622                 break;
 623 #endif
 624         case CPU_VENDOR_CENTAUR:
 625 #ifdef __i386__
 626                 switch (cpu_id & 0xff0) {
 627                 case 0x540:
 628                         strcpy(cpu_model, "IDT WinChip C6");
 629                         break;
 630                 case 0x580:
 631                         strcpy(cpu_model, "IDT WinChip 2");
 632                         break;
 633                 case 0x590:
 634                         strcpy(cpu_model, "IDT WinChip 3");
 635                         break;
 636                 case 0x660:
 637                         strcpy(cpu_model, "VIA C3 Samuel");
 638                         break;
 639                 case 0x670:
 640                         if (cpu_id & 0x8)
 641                                 strcpy(cpu_model, "VIA C3 Ezra");
 642                         else
 643                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 644                         break;
 645                 case 0x680:
 646                         strcpy(cpu_model, "VIA C3 Ezra-T");
 647                         break;
 648                 case 0x690:
 649                         strcpy(cpu_model, "VIA C3 Nehemiah");
 650                         break;
 651                 case 0x6a0:
 652                 case 0x6d0:
 653                         strcpy(cpu_model, "VIA C7 Esther");
 654                         break;
 655                 case 0x6f0:
 656                         strcpy(cpu_model, "VIA Nano");
 657                         break;
 658                 default:
 659                         strcpy(cpu_model, "VIA/IDT Unknown");
 660                 }
 661 #else
 662                 strcpy(cpu_model, "VIA ");
 663                 if ((cpu_id & 0xff0) == 0x6f0)
 664                         strcat(cpu_model, "Nano Processor");
 665                 else
 666                         strcat(cpu_model, "Unknown");
 667 #endif
 668                 break;
 669 #ifdef __i386__
 670         case CPU_VENDOR_IBM:
 671                 strcpy(cpu_model, "Blue Lightning CPU");
 672                 break;
 673         case CPU_VENDOR_NSC:
 674                 switch (cpu_id & 0xff0) {
 675                 case 0x540:
 676                         strcpy(cpu_model, "Geode SC1100");
 677                         cpu = CPU_GEODE1100;
 678                         break;
 679                 default:
 680                         strcpy(cpu_model, "Geode/NSC unknown");
 681                         break;
 682                 }
 683                 break;
 684 #endif
 685         default:
 686                 strcat(cpu_model, "Unknown");
 687                 break;
 688         }
 689
 690         /*
 691          * Replace cpu_model with cpu_brand minus leading spaces if
 692          * we have one.
 693          */
 694         brand = cpu_brand;
 695         while (*brand == ' ')
 696                 ++brand;
 697         if (*brand != '\0')
 698                 strcpy(cpu_model, brand);
 699
 700         printf("%s (", cpu_model);
 701         if (tsc_freq != 0) {
 702                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 703                 printf("%jd.%02d-MHz ",
 704                     (intmax_t)(tsc_freq + 4999) / 1000000,
 705                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 706         }
 707 #ifdef __i386__
 708         switch(cpu_class) {
 709         case CPUCLASS_286:
 710                 printf("286");
 711                 break;
 712         case CPUCLASS_386:
 713                 printf("386");
 714                 break;
 715 #if defined(I486_CPU)
 716         case CPUCLASS_486:
 717                 printf("486");
 718                 break;
 719 #endif
 720 #if defined(I586_CPU)
 721         case CPUCLASS_586:
 722                 printf("586");
 723                 break;
 724 #endif
 725 #if defined(I686_CPU)
 726         case CPUCLASS_686:
 727                 printf("686");
 728                 break;
 729 #endif
 730         default:
 731                 printf("Unknown");      /* will panic below... */
 732         }
 733 #else
 734         printf("K8");
 735 #endif
 736         printf("-class CPU)\n");
 737         if (*cpu_vendor)
 738                 printf("  Origin=\"%s\"", cpu_vendor);
 739         if (cpu_id)
 740                 printf("  Id=0x%x", cpu_id);
 741
 742         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 743             cpu_vendor_id == CPU_VENDOR_AMD ||
 744             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 745 #ifdef __i386__
 746             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 747             cpu_vendor_id == CPU_VENDOR_RISE ||
 748             cpu_vendor_id == CPU_VENDOR_NSC ||
 749             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 750 #endif
 751             0) {
 752                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 753                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 754                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 755 #ifdef __i386__
 756                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 757                         printf("\n  DIR=0x%04x", cyrix_did);
 758 #endif
 759
 760                 /*
 761                  * AMD CPUID Specification
 762                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 763                  *
 764                  * Intel Processor Identification and CPUID Instruction
 765                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 766                  */
 767                 if (cpu_high > 0) {
 768
 769                         /*
 770                          * Here we should probably set up flags indicating
 771                          * whether or not various features are available.
 772                          * The interesting ones are probably VME, PSE, PAE,
 773                          * and PGE.  The code already assumes without bothering
 774                          * to check that all CPUs >= Pentium have a TSC and
 775                          * MSRs.
 776                          */
 777                         printf("\n  Features=0x%b", cpu_feature,
 778                         "\020"
 779                         "\001FPU"       /* Integral FPU */
 780                         "\002VME"       /* Extended VM86 mode support */
 781                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 782                         "\004PSE"       /* 4MByte page tables */
 783                         "\005TSC"       /* Timestamp counter */
 784                         "\006MSR"       /* Machine specific registers */
 785                         "\007PAE"       /* Physical address extension */
 786                         "\010MCE"       /* Machine Check support */
 787                         "\011CX8"       /* CMPEXCH8 instruction */
 788                         "\012APIC"      /* SMP local APIC */
 789                         "\013oldMTRR"   /* Previous implementation of MTRR */
 790                         "\014SEP"       /* Fast System Call */
 791                         "\015MTRR"      /* Memory Type Range Registers */
 792                         "\016PGE"       /* PG_G (global bit) support */
 793                         "\017MCA"       /* Machine Check Architecture */
 794                         "\020CMOV"      /* CMOV instruction */
 795                         "\021PAT"       /* Page attributes table */
 796                         "\022PSE36"     /* 36 bit address space support */
 797                         "\023PN"        /* Processor Serial number */
 798                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 799                         "\025<b20>"
 800                         "\026DTS"       /* Debug Trace Store */
 801                         "\027ACPI"      /* ACPI support */
 802                         "\030MMX"       /* MMX instructions */
 803                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 804                         "\032SSE"       /* Streaming SIMD Extensions */
 805                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 806                         "\034SS"        /* Self snoop */
 807                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 808                         "\036TM"        /* Thermal Monitor clock slowdown */
 809                         "\037IA64"      /* CPU can execute IA64 instructions */
 810                         "\040PBE"       /* Pending Break Enable */
 811                         );
 812
 813                         if (cpu_feature2 != 0) {
 814                                 printf("\n  Features2=0x%b", cpu_feature2,
 815                                 "\020"
 816                                 "\001SSE3"      /* SSE3 */
 817                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 818                                 "\003DTES64"    /* 64-bit Debug Trace */
 819                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 820                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 821                                 "\006VMX"       /* Virtual Machine Extensions */
 822                                 "\007SMX"       /* Safer Mode Extensions */
 823                                 "\010EST"       /* Enhanced SpeedStep */
 824                                 "\011TM2"       /* Thermal Monitor 2 */
 825                                 "\012SSSE3"     /* SSSE3 */
 826                                 "\013CNXT-ID"   /* L1 context ID available */
 827                                 "\014SDBG"      /* IA32 silicon debug */
 828                                 "\015FMA"       /* Fused Multiply Add */
 829                                 "\016CX16"      /* CMPXCHG16B Instruction */
 830                                 "\017xTPR"      /* Send Task Priority Messages*/
 831                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 832                                 "\021<b16>"
 833                                 "\022PCID"      /* Process-context Identifiers*/
 834                                 "\023DCA"       /* Direct Cache Access */
 835                                 "\024SSE4.1"    /* SSE 4.1 */
 836                                 "\025SSE4.2"    /* SSE 4.2 */
 837                                 "\026x2APIC"    /* xAPIC Extensions */
 838                                 "\027MOVBE"     /* MOVBE Instruction */
 839                                 "\030POPCNT"    /* POPCNT Instruction */
 840                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 841                                 "\032AESNI"     /* AES Crypto */
 842                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 843                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 844                                 "\035AVX"       /* Advanced Vector Extensions */
 845                                 "\036F16C"      /* Half-precision conversions */
 846                                 "\037RDRAND"    /* RDRAND Instruction */
 847                                 "\040HV"        /* Hypervisor */
 848                                 );
 849                         }
 850
 851                         if (amd_feature != 0) {
 852                                 printf("\n  AMD Features=0x%b", amd_feature,
 853                                 "\020"          /* in hex */
 854                                 "\001<s0>"      /* Same */
 855                                 "\002<s1>"      /* Same */
 856                                 "\003<s2>"      /* Same */
 857                                 "\004<s3>"      /* Same */
 858                                 "\005<s4>"      /* Same */
 859                                 "\006<s5>"      /* Same */
 860                                 "\007<s6>"      /* Same */
 861                                 "\010<s7>"      /* Same */
 862                                 "\011<s8>"      /* Same */
 863                                 "\012<s9>"      /* Same */
 864                                 "\013<b10>"     /* Undefined */
 865                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 866                                 "\015<s12>"     /* Same */
 867                                 "\016<s13>"     /* Same */
 868                                 "\017<s14>"     /* Same */
 869                                 "\020<s15>"     /* Same */
 870                                 "\021<s16>"     /* Same */
 871                                 "\022<s17>"     /* Same */
 872                                 "\023<b18>"     /* Reserved, unknown */
 873                                 "\024MP"        /* Multiprocessor Capable */
 874                                 "\025NX"        /* Has EFER.NXE, NX */
 875                                 "\026<b21>"     /* Undefined */
 876                                 "\027MMX+"      /* AMD MMX Extensions */
 877                                 "\030<s23>"     /* Same */
 878                                 "\031<s24>"     /* Same */
 879                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 880                                 "\033Page1GB"   /* 1-GB large page support */
 881                                 "\034RDTSCP"    /* RDTSCP */
 882                                 "\035<b28>"     /* Undefined */
 883                                 "\036LM"        /* 64 bit long mode */
 884                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 885                                 "\0403DNow!"    /* AMD 3DNow! */
 886                                 );
 887                         }
 888
 889                         if (amd_feature2 != 0) {
 890                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 891                                 "\020"
 892                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 893                                 "\002CMP"       /* CMP legacy */
 894                                 "\003SVM"       /* Secure Virtual Mode */
 895                                 "\004ExtAPIC"   /* Extended APIC register */
 896                                 "\005CR8"       /* CR8 in legacy mode */
 897                                 "\006ABM"       /* LZCNT instruction */
 898                                 "\007SSE4A"     /* SSE4A */
 899                                 "\010MAS"       /* Misaligned SSE mode */
 900                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 901                                 "\012OSVW"      /* OS visible workaround */
 902                                 "\013IBS"       /* Instruction based sampling */
 903                                 "\014XOP"       /* XOP extended instructions */
 904                                 "\015SKINIT"    /* SKINIT/STGI */
 905                                 "\016WDT"       /* Watchdog timer */
 906                                 "\017<b14>"
 907                                 "\020LWP"       /* Lightweight Profiling */
 908                                 "\021FMA4"      /* 4-operand FMA instructions */
 909                                 "\022TCE"       /* Translation Cache Extension */
 910                                 "\023<b18>"
 911                                 "\024NodeId"    /* NodeId MSR support */
 912                                 "\025<b20>"
 913                                 "\026TBM"       /* Trailing Bit Manipulation */
 914                                 "\027Topology"  /* Topology Extensions */
 915                                 "\030PCXC"      /* Core perf count */
 916                                 "\031PNXC"      /* NB perf count */
 917                                 "\032<b25>"
 918                                 "\033DBE"       /* Data Breakpoint extension */
 919                                 "\034PTSC"      /* Performance TSC */
 920                                 "\035PL2I"      /* L2I perf count */
 921                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 922                                 "\037<b30>"
 923                                 "\040<b31>"
 924                                 );
 925                         }
 926
 927                         if (cpu_stdext_feature != 0) {
 928                                 printf("\n  Structured Extended Features=0x%b",
 929                                     cpu_stdext_feature,
 930                                        "\020"
 931                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 932                                        "\001FSGSBASE"
 933                                        "\002TSCADJ"
 934                                        "\003SGX"
 935                                        /* Bit Manipulation Instructions */
 936                                        "\004BMI1"
 937                                        /* Hardware Lock Elision */
 938                                        "\005HLE"
 939                                        /* Advanced Vector Instructions 2 */
 940                                        "\006AVX2"
 941                                        /* FDP_EXCPTN_ONLY */
 942                                        "\007FDPEXC"
 943                                        /* Supervisor Mode Execution Prot. */
 944                                        "\010SMEP"
 945                                        /* Bit Manipulation Instructions */
 946                                        "\011BMI2"
 947                                        "\012ERMS"
 948                                        /* Invalidate Processor Context ID */
 949                                        "\013INVPCID"
 950                                        /* Restricted Transactional Memory */
 951                                        "\014RTM"
 952                                        "\015PQM"
 953                                        "\016NFPUSG"
 954                                        /* Intel Memory Protection Extensions */
 955                                        "\017MPX"
 956                                        "\020PQE"
 957                                        /* AVX512 Foundation */
 958                                        "\021AVX512F"
 959                                        "\022AVX512DQ"
 960                                        /* Enhanced NRBG */
 961                                        "\023RDSEED"
 962                                        /* ADCX + ADOX */
 963                                        "\024ADX"
 964                                        /* Supervisor Mode Access Prevention */
 965                                        "\025SMAP"
 966                                        "\026AVX512IFMA"
 967                                        /* Formerly PCOMMIT */
 968                                        "\027<b22>"
 969                                        "\030CLFLUSHOPT"
 970                                        "\031CLWB"
 971                                        "\032PROCTRACE"
 972                                        "\033AVX512PF"
 973                                        "\034AVX512ER"
 974                                        "\035AVX512CD"
 975                                        "\036SHA"
 976                                        "\037AVX512BW"
 977                                        "\040AVX512VL"
 978                                        );
 979                         }
 980
 981                         if (cpu_stdext_feature2 != 0) {
 982                                 printf("\n  Structured Extended Features2=0x%b",
 983                                     cpu_stdext_feature2,
 984                                        "\020"
 985                                        "\001PREFETCHWT1"
 986                                        "\002AVX512VBMI"
 987                                        "\003UMIP"
 988                                        "\004PKU"
 989                                        "\005OSPKE"
 990                                        "\006WAITPKG"
 991                                        "\007AVX512VBMI2"
 992                                        "\011GFNI"
 993                                        "\012VAES"
 994                                        "\013VPCLMULQDQ"
 995                                        "\014AVX512VNNI"
 996                                        "\015AVX512BITALG"
 997                                        "\016AVX512VPOPCNTDQ"
 998                                        "\027RDPID"
 999                                        "\032CLDEMOTE"
1000                                        "\034MOVDIRI"
1001                                        "\035MOVDIR64B"
1002                                        "\036ENQCMD"
1003                                        "\037SGXLC"
1004                                        );
1005                         }
1006
1007                         if (cpu_stdext_feature3 != 0) {
1008                                 printf("\n  Structured Extended Features3=0x%b",
1009                                     cpu_stdext_feature3,
1010                                        "\020"
1011                                        "\003AVX512_4VNNIW"
1012                                        "\004AVX512_4FMAPS"
1013                                        "\011AVX512VP2INTERSECT"
1014                                        "\013MD_CLEAR"
1015                                        "\016TSXFA"
1016                                        "\023PCONFIG"
1017                                        "\033IBPB"
1018                                        "\034STIBP"
1019                                        "\035L1DFL"
1020                                        "\036ARCH_CAP"
1021                                        "\037CORE_CAP"
1022                                        "\040SSBD"
1023                                        );
1024                         }
1025
1026                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1027                                 cpuid_count(0xd, 0x1, regs);
1028                                 if (regs[0] != 0) {
1029                                         printf("\n  XSAVE Features=0x%b",
1030                                             regs[0],
1031                                             "\020"
1032                                             "\001XSAVEOPT"
1033                                             "\002XSAVEC"
1034                                             "\003XINUSE"
1035                                             "\004XSAVES");
1036                                 }
1037                         }
1038
1039                         if (cpu_ia32_arch_caps != 0) {
1040                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1041                                     (u_int)cpu_ia32_arch_caps,
1042                                        "\020"
1043                                        "\001RDCL_NO"
1044                                        "\002IBRS_ALL"
1045                                        "\003RSBA"
1046                                        "\004SKIP_L1DFL_VME"
1047                                        "\005SSB_NO"
1048                                        "\006MDS_NO"
1049                                        "\010TSX_CTRL"
1050                                        "\011TAA_NO"
1051                                        );
1052                         }
1053
1054                         if (amd_extended_feature_extensions != 0) {
1055                                 u_int amd_fe_masked;
1056
1057                                 amd_fe_masked = amd_extended_feature_extensions;
1058                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1059                                         amd_fe_masked &=
1060                                             ~(AMDFEID_IBRS_ALWAYSON |
1061                                                 AMDFEID_PREFER_IBRS);
1062                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1063                                         amd_fe_masked &=
1064                                             ~AMDFEID_STIBP_ALWAYSON;
1065
1066                                 printf("\n  "
1067                                     "AMD Extended Feature Extensions ID EBX="
1068                                     "0x%b", amd_fe_masked,
1069                                     "\020"
1070                                     "\001CLZERO"
1071                                     "\002IRPerf"
1072                                     "\003XSaveErPtr"
1073                                     "\005RDPRU"
1074                                     "\011MCOMMIT"
1075                                     "\012WBNOINVD"
1076                                     "\015IBPB"
1077                                     "\017IBRS"
1078                                     "\020STIBP"
1079                                     "\021IBRS_ALWAYSON"
1080                                     "\022STIBP_ALWAYSON"
1081                                     "\023PREFER_IBRS"
1082                                     "\031SSBD"
1083                                     "\032VIRT_SSBD"
1084                                     "\033SSB_NO"
1085                                     );
1086                         }
1087
1088                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1089                                 print_via_padlock_info();
1090
1091                         if (cpu_feature2 & CPUID2_VMX)
1092                                 print_vmx_info();
1093
1094                         if (amd_feature2 & AMDID2_SVM)
1095                                 print_svm_info();
1096
1097                         if ((cpu_feature & CPUID_HTT) &&
1098                             cpu_vendor_id == CPU_VENDOR_AMD)
1099                                 cpu_feature &= ~CPUID_HTT;
1100
1101                         /*
1102                          * If this CPU supports P-state invariant TSC then
1103                          * mention the capability.
1104                          */
1105                         if (tsc_is_invariant) {
1106                                 printf("\n  TSC: P-state invariant");
1107                                 if (tsc_perf_stat)
1108                                         printf(", performance statistics");
1109                         }
1110                 }
1111 #ifdef __i386__
1112         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1113                 printf("  DIR=0x%04x", cyrix_did);
1114                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1115                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1116 #ifndef CYRIX_CACHE_REALLY_WORKS
1117                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1118                         printf("\n  CPU cache: write-through mode");
1119 #endif
1120 #endif
1121         }
1122
1123         /* Avoid ugly blank lines: only print newline when we have to. */
1124         if (*cpu_vendor || cpu_id)
1125                 printf("\n");
1126
1127         if (bootverbose) {
1128                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1129                         print_AMD_info();
1130                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1131                         print_INTEL_info();
1132 #ifdef __i386__
1133                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1134                         print_transmeta_info();
1135 #endif
1136         }
1137
1138         print_hypervisor_info();
1139 }
1140
1141 #ifdef __i386__
1142 void
1143 panicifcpuunsupported(void)
1144 {
1145
1146 #if !defined(lint)
1147 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1148 #error This kernel is not configured for one of the supported CPUs
1149 #endif
1150 #else /* lint */
1151 #endif /* lint */
1152         /*
1153          * Now that we have told the user what they have,
1154          * let them know if that machine type isn't configured.
1155          */
1156         switch (cpu_class) {
1157         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1158         case CPUCLASS_386:
1159 #if !defined(I486_CPU)
1160         case CPUCLASS_486:
1161 #endif
1162 #if !defined(I586_CPU)
1163         case CPUCLASS_586:
1164 #endif
1165 #if !defined(I686_CPU)
1166         case CPUCLASS_686:
1167 #endif
1168                 panic("CPU class not configured");
1169         default:
1170                 break;
1171         }
1172 }
1173
1174 static  volatile u_int trap_by_rdmsr;
1175
1176 /*
1177  * Special exception 6 handler.
1178  * The rdmsr instruction generates invalid opcodes fault on 486-class
1179  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1180  * function identblue() when this handler is called.  Stacked eip should
1181  * be advanced.
1182  */
1183 inthand_t       bluetrap6;
1184 #ifdef __GNUCLIKE_ASM
1185 __asm
1186 ("                                                                      \n\
1187         .text                                                           \n\
1188         .p2align 2,0x90                                                 \n\
1189         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1190 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1191         ss                                                              \n\
1192         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1193         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1194         iret                                                            \n\
1195 ");
1196 #endif
1197
1198 /*
1199  * Special exception 13 handler.
1200  * Accessing non-existent MSR generates general protection fault.
1201  */
1202 inthand_t       bluetrap13;
1203 #ifdef __GNUCLIKE_ASM
1204 __asm
1205 ("                                                                      \n\
1206         .text                                                           \n\
1207         .p2align 2,0x90                                                 \n\
1208         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1209 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1210         ss                                                              \n\
1211         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1212         popl    %eax            /* discard error code */                \n\
1213         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1214         iret                                                            \n\
1215 ");
1216 #endif
1217
1218 /*
1219  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1220  * support cpuid instruction.  This function should be called after
1221  * loading interrupt descriptor table register.
1222  *
1223  * I don't like this method that handles fault, but I couldn't get
1224  * information for any other methods.  Does blue giant know?
1225  */
1226 static int
1227 identblue(void)
1228 {
1229
1230         trap_by_rdmsr = 0;
1231
1232         /*
1233          * Cyrix 486-class CPU does not support rdmsr instruction.
1234          * The rdmsr instruction generates invalid opcode fault, and exception
1235          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1236          * bluetrap6() set the magic number to trap_by_rdmsr.
1237          */
1238         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1239             GSEL(GCODE_SEL, SEL_KPL));
1240
1241         /*
1242          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1243          * In this case, rdmsr generates general protection fault, and
1244          * exception will be trapped by bluetrap13().
1245          */
1246         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1247             GSEL(GCODE_SEL, SEL_KPL));
1248
1249         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1250
1251         if (trap_by_rdmsr == 0xa8c1d)
1252                 return IDENTBLUE_CYRIX486;
1253         else if (trap_by_rdmsr == 0xa89c4)
1254                 return IDENTBLUE_CYRIXM2;
1255         return IDENTBLUE_IBMCPU;
1256 }
1257
1258
1259 /*
1260  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1261  *
1262  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1263  * +-------+-------+---------------+
1264  * |  SID  |  RID  |   Device ID   |
1265  * |    (DIR 1)    |    (DIR 0)    |
1266  * +-------+-------+---------------+
1267  */
1268 static void
1269 identifycyrix(void)
1270 {
1271         register_t saveintr;
1272         int     ccr2_test = 0, dir_test = 0;
1273         u_char  ccr2, ccr3;
1274
1275         saveintr = intr_disable();
1276
1277         ccr2 = read_cyrix_reg(CCR2);
1278         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1279         read_cyrix_reg(CCR2);
1280         if (read_cyrix_reg(CCR2) != ccr2)
1281                 ccr2_test = 1;
1282         write_cyrix_reg(CCR2, ccr2);
1283
1284         ccr3 = read_cyrix_reg(CCR3);
1285         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1286         read_cyrix_reg(CCR3);
1287         if (read_cyrix_reg(CCR3) != ccr3)
1288                 dir_test = 1;                                   /* CPU supports DIRs. */
1289         write_cyrix_reg(CCR3, ccr3);
1290
1291         if (dir_test) {
1292                 /* Device ID registers are available. */
1293                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1294                 cyrix_did += read_cyrix_reg(DIR0);
1295         } else if (ccr2_test)
1296                 cyrix_did = 0x0010;             /* 486S A-step */
1297         else
1298                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1299
1300         intr_restore(saveintr);
1301 }
1302 #endif
1303
1304 /* Update TSC freq with the value indicated by the caller. */
1305 static void
1306 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1307 {
1308
1309         /* If there was an error during the transition, don't do anything. */
1310         if (status != 0)
1311                 return;
1312
1313         /* Total setting for this level gives the new frequency in MHz. */
1314         hw_clockrate = level->total_set.freq;
1315 }
1316
1317 static void
1318 hook_tsc_freq(void *arg __unused)
1319 {
1320
1321         if (tsc_is_invariant)
1322                 return;
1323
1324         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1325             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1326 }
1327
1328 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1329
1330 static const struct {
1331         const char *    vm_bname;
1332         int             vm_guest;
1333 } vm_bnames[] = {
1334         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1335         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1336         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1337         { "Xen",        VM_GUEST_XEN },         /* Xen */
1338         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1339         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1340 };
1341
1342 static const struct {
1343         const char *    vm_pname;
1344         int             vm_guest;
1345 } vm_pnames[] = {
1346         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1347         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1348         { "VirtualBox",                 VM_GUEST_VBOX },
1349         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1350         { "KVM",                        VM_GUEST_KVM },
1351 };
1352
1353 static struct {
1354         const char      *vm_cpuid;
1355         int             vm_guest;
1356 } vm_cpuids[] = {
1357         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1358         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1359         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1360         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1361         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1362         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1363 };
1364
1365 static void
1366 identify_hypervisor_cpuid_base(void)
1367 {
1368         u_int leaf, regs[4];
1369         int i;
1370
1371         /*
1372          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1373          * http://lkml.org/lkml/2008/10/1/246
1374          *
1375          * KB1009458: Mechanisms to determine if software is running in
1376          * a VMware virtual machine
1377          * http://kb.vmware.com/kb/1009458
1378          *
1379          * Search for a hypervisor that we recognize. If we cannot find
1380          * a specific hypervisor, return the first information about the
1381          * hypervisor that we found, as others may be able to use.
1382          */
1383         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1384                 do_cpuid(leaf, regs);
1385
1386                 /*
1387                  * KVM from Linux kernels prior to commit
1388                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1389                  * to 0 rather than a valid hv_high value.  Check for
1390                  * the KVM signature bytes and fixup %eax to the
1391                  * highest supported leaf in that case.
1392                  */
1393                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1394                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1395                         regs[0] = leaf + 1;
1396
1397                 if (regs[0] >= leaf) {
1398                         for (i = 0; i < nitems(vm_cpuids); i++)
1399                                 if (strncmp((const char *)&regs[1],
1400                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1401                                         vm_guest = vm_cpuids[i].vm_guest;
1402                                         break;
1403                                 }
1404
1405                         /*
1406                          * If this is the first entry or we found a
1407                          * specific hypervisor, record the base, high value,
1408                          * and vendor identifier.
1409                          */
1410                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1411                                 hv_base = leaf;
1412                                 hv_high = regs[0];
1413                                 ((u_int *)&hv_vendor)[0] = regs[1];
1414                                 ((u_int *)&hv_vendor)[1] = regs[2];
1415                                 ((u_int *)&hv_vendor)[2] = regs[3];
1416                                 hv_vendor[12] = '\0';
1417
1418                                 /*
1419                                  * If we found a specific hypervisor, then
1420                                  * we are finished.
1421                                  */
1422                                 if (vm_guest != VM_GUEST_VM)
1423                                         return;
1424                         }
1425                 }
1426         }
1427 }
1428
1429 void
1430 identify_hypervisor(void)
1431 {
1432         u_int regs[4];
1433         char *p;
1434         int i;
1435
1436         /*
1437          * If CPUID2_HV is set, we are running in a hypervisor environment.
1438          */
1439         if (cpu_feature2 & CPUID2_HV) {
1440                 vm_guest = VM_GUEST_VM;
1441                 identify_hypervisor_cpuid_base();
1442
1443                 /* If we have a definitive vendor, we can return now. */
1444                 if (*hv_vendor != '\0')
1445                         return;
1446         }
1447
1448         /*
1449          * Examine SMBIOS strings for older hypervisors.
1450          */
1451         p = kern_getenv("smbios.system.serial");
1452         if (p != NULL) {
1453                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1454                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1455                         if (regs[1] == VMW_HVMAGIC) {
1456                                 vm_guest = VM_GUEST_VMWARE;
1457                                 freeenv(p);
1458                                 return;
1459                         }
1460                 }
1461                 freeenv(p);
1462         }
1463
1464         /*
1465          * XXX: Some of these entries may not be needed since they were
1466          * added to FreeBSD before the checks above.
1467          */
1468         p = kern_getenv("smbios.bios.vendor");
1469         if (p != NULL) {
1470                 for (i = 0; i < nitems(vm_bnames); i++)
1471                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1472                                 vm_guest = vm_bnames[i].vm_guest;
1473                                 /* If we have a specific match, return */
1474                                 if (vm_guest != VM_GUEST_VM) {
1475                                         freeenv(p);
1476                                         return;
1477                                 }
1478                                 /*
1479                                  * We are done with bnames, but there might be
1480                                  * a more specific match in the pnames
1481                                  */
1482                                 break;
1483                         }
1484                 freeenv(p);
1485         }
1486         p = kern_getenv("smbios.system.product");
1487         if (p != NULL) {
1488                 for (i = 0; i < nitems(vm_pnames); i++)
1489                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1490                                 vm_guest = vm_pnames[i].vm_guest;
1491                                 freeenv(p);
1492                                 return;
1493                         }
1494                 freeenv(p);
1495         }
1496 }
1497
1498 bool
1499 fix_cpuid(void)
1500 {
1501         uint64_t msr;
1502
1503         /*
1504          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1505          * get the largest standard CPUID function number again if it is set
1506          * from BIOS.  It is necessary for probing correct CPU topology later
1507          * and for the correct operation of the AVX-aware userspace.
1508          */
1509         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1510             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1511             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1512             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1513             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1514                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1515                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1516                         msr &= ~IA32_MISC_EN_LIMCPUID;
1517                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1518                         return (true);
1519                 }
1520         }
1521
1522         /*
1523          * Re-enable AMD Topology Extension that could be disabled by BIOS
1524          * on some notebook processors.  Without the extension it's really
1525          * hard to determine the correct CPU cache topology.
1526          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1527          * Models 60h-6Fh Processors, Publication # 50742.
1528          */
1529         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1530             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1531                 msr = rdmsr(MSR_EXTFEATURES);
1532                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1533                         msr |= (uint64_t)1 << 54;
1534                         wrmsr(MSR_EXTFEATURES, msr);
1535                         return (true);
1536                 }
1537         }
1538         return (false);
1539 }
1540
1541 void
1542 identify_cpu1(void)
1543 {
1544         u_int regs[4];
1545
1546         do_cpuid(0, regs);
1547         cpu_high = regs[0];
1548         ((u_int *)&cpu_vendor)[0] = regs[1];
1549         ((u_int *)&cpu_vendor)[1] = regs[3];
1550         ((u_int *)&cpu_vendor)[2] = regs[2];
1551         cpu_vendor[12] = '\0';
1552
1553         do_cpuid(1, regs);
1554         cpu_id = regs[0];
1555         cpu_procinfo = regs[1];
1556         cpu_feature = regs[3];
1557         cpu_feature2 = regs[2];
1558 }
1559
1560 void
1561 identify_cpu2(void)
1562 {
1563         u_int regs[4], cpu_stdext_disable;
1564
1565         if (cpu_high >= 6) {
1566                 cpuid_count(6, 0, regs);
1567                 cpu_power_eax = regs[0];
1568                 cpu_power_ebx = regs[1];
1569                 cpu_power_ecx = regs[2];
1570                 cpu_power_edx = regs[3];
1571         }
1572
1573         if (cpu_high >= 7) {
1574                 cpuid_count(7, 0, regs);
1575                 cpu_stdext_feature = regs[1];
1576
1577                 /*
1578                  * Some hypervisors failed to filter out unsupported
1579                  * extended features.  Allow to disable the
1580                  * extensions, activation of which requires setting a
1581                  * bit in CR4, and which VM monitors do not support.
1582                  */
1583                 cpu_stdext_disable = 0;
1584                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1585                 cpu_stdext_feature &= ~cpu_stdext_disable;
1586
1587                 cpu_stdext_feature2 = regs[2];
1588                 cpu_stdext_feature3 = regs[3];
1589
1590                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1591                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1592         }
1593 }
1594
1595 void
1596 identify_cpu_fixup_bsp(void)
1597 {
1598         u_int regs[4];
1599
1600         cpu_vendor_id = find_cpu_vendor_id();
1601
1602         if (fix_cpuid()) {
1603                 do_cpuid(0, regs);
1604                 cpu_high = regs[0];
1605         }
1606 }
1607
1608 /*
1609  * Final stage of CPU identification.
1610  */
1611 void
1612 finishidentcpu(void)
1613 {
1614         u_int regs[4];
1615 #ifdef __i386__
1616         u_char ccr3;
1617 #endif
1618
1619         identify_cpu_fixup_bsp();
1620
1621         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1622                 do_cpuid(5, regs);
1623                 cpu_mon_mwait_flags = regs[2];
1624                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1625                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1626         }
1627
1628         identify_cpu2();
1629
1630 #ifdef __i386__
1631         if (cpu_high > 0 &&
1632             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1633              cpu_vendor_id == CPU_VENDOR_AMD ||
1634              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1635              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1636              cpu_vendor_id == CPU_VENDOR_NSC)) {
1637                 do_cpuid(0x80000000, regs);
1638                 if (regs[0] >= 0x80000000)
1639                         cpu_exthigh = regs[0];
1640         }
1641 #else
1642         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1643             cpu_vendor_id == CPU_VENDOR_AMD ||
1644             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1645                 do_cpuid(0x80000000, regs);
1646                 cpu_exthigh = regs[0];
1647         }
1648 #endif
1649         if (cpu_exthigh >= 0x80000001) {
1650                 do_cpuid(0x80000001, regs);
1651                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1652                 amd_feature2 = regs[2];
1653         }
1654         if (cpu_exthigh >= 0x80000007) {
1655                 do_cpuid(0x80000007, regs);
1656                 amd_rascap = regs[1];
1657                 amd_pminfo = regs[3];
1658         }
1659         if (cpu_exthigh >= 0x80000008) {
1660                 do_cpuid(0x80000008, regs);
1661                 cpu_maxphyaddr = regs[0] & 0xff;
1662                 amd_extended_feature_extensions = regs[1];
1663                 cpu_procinfo2 = regs[2];
1664         } else {
1665                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1666         }
1667
1668 #ifdef __i386__
1669         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1670                 if (cpu == CPU_486) {
1671                         /*
1672                          * These conditions are equivalent to:
1673                          *     - CPU does not support cpuid instruction.
1674                          *     - Cyrix/IBM CPU is detected.
1675                          */
1676                         if (identblue() == IDENTBLUE_IBMCPU) {
1677                                 strcpy(cpu_vendor, "IBM");
1678                                 cpu_vendor_id = CPU_VENDOR_IBM;
1679                                 cpu = CPU_BLUE;
1680                                 return;
1681                         }
1682                 }
1683                 switch (cpu_id & 0xf00) {
1684                 case 0x600:
1685                         /*
1686                          * Cyrix's datasheet does not describe DIRs.
1687                          * Therefor, I assume it does not have them
1688                          * and use the result of the cpuid instruction.
1689                          * XXX they seem to have it for now at least. -Peter
1690                          */
1691                         identifycyrix();
1692                         cpu = CPU_M2;
1693                         break;
1694                 default:
1695                         identifycyrix();
1696                         /*
1697                          * This routine contains a trick.
1698                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1699                          */
1700                         switch (cyrix_did & 0x00f0) {
1701                         case 0x00:
1702                         case 0xf0:
1703                                 cpu = CPU_486DLC;
1704                                 break;
1705                         case 0x10:
1706                                 cpu = CPU_CY486DX;
1707                                 break;
1708                         case 0x20:
1709                                 if ((cyrix_did & 0x000f) < 8)
1710                                         cpu = CPU_M1;
1711                                 else
1712                                         cpu = CPU_M1SC;
1713                                 break;
1714                         case 0x30:
1715                                 cpu = CPU_M1;
1716                                 break;
1717                         case 0x40:
1718                                 /* MediaGX CPU */
1719                                 cpu = CPU_M1SC;
1720                                 break;
1721                         default:
1722                                 /* M2 and later CPUs are treated as M2. */
1723                                 cpu = CPU_M2;
1724
1725                                 /*
1726                                  * enable cpuid instruction.
1727                                  */
1728                                 ccr3 = read_cyrix_reg(CCR3);
1729                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1730                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1731                                 write_cyrix_reg(CCR3, ccr3);
1732
1733                                 do_cpuid(0, regs);
1734                                 cpu_high = regs[0];     /* eax */
1735                                 do_cpuid(1, regs);
1736                                 cpu_id = regs[0];       /* eax */
1737                                 cpu_feature = regs[3];  /* edx */
1738                                 break;
1739                         }
1740                 }
1741         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1742                 /*
1743                  * There are BlueLightning CPUs that do not change
1744                  * undefined flags by dividing 5 by 2.  In this case,
1745                  * the CPU identification routine in locore.s leaves
1746                  * cpu_vendor null string and puts CPU_486 into the
1747                  * cpu.
1748                  */
1749                 if (identblue() == IDENTBLUE_IBMCPU) {
1750                         strcpy(cpu_vendor, "IBM");
1751                         cpu_vendor_id = CPU_VENDOR_IBM;
1752                         cpu = CPU_BLUE;
1753                         return;
1754                 }
1755         }
1756 #endif
1757 }
1758
1759 int
1760 pti_get_default(void)
1761 {
1762
1763         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1764                 return (0);
1765         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1766                 return (0);
1767         return (1);
1768 }
1769
1770 static u_int
1771 find_cpu_vendor_id(void)
1772 {
1773         int     i;
1774
1775         for (i = 0; i < nitems(cpu_vendors); i++)
1776                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1777                         return (cpu_vendors[i].vendor_id);
1778         return (0);
1779 }
1780
1781 static void
1782 print_AMD_assoc(int i)
1783 {
1784         if (i == 255)
1785                 printf(", fully associative\n");
1786         else
1787                 printf(", %d-way associative\n", i);
1788 }
1789
1790 static void
1791 print_AMD_l2_assoc(int i)
1792 {
1793         switch (i & 0x0f) {
1794         case 0: printf(", disabled/not present\n"); break;
1795         case 1: printf(", direct mapped\n"); break;
1796         case 2: printf(", 2-way associative\n"); break;
1797         case 4: printf(", 4-way associative\n"); break;
1798         case 6: printf(", 8-way associative\n"); break;
1799         case 8: printf(", 16-way associative\n"); break;
1800         case 15: printf(", fully associative\n"); break;
1801         default: printf(", reserved configuration\n"); break;
1802         }
1803 }
1804
1805 static void
1806 print_AMD_info(void)
1807 {
1808 #ifdef __i386__
1809         uint64_t amd_whcr;
1810 #endif
1811         u_int regs[4];
1812
1813         if (cpu_exthigh >= 0x80000005) {
1814                 do_cpuid(0x80000005, regs);
1815                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1816                 print_AMD_assoc(regs[0] >> 24);
1817
1818                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1819                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1820
1821                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1822                 print_AMD_assoc(regs[1] >> 24);
1823
1824                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1825                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1826
1827                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1828                 printf(", %d bytes/line", regs[2] & 0xff);
1829                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1830                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1831
1832                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1833                 printf(", %d bytes/line", regs[3] & 0xff);
1834                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1835                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1836         }
1837
1838         if (cpu_exthigh >= 0x80000006) {
1839                 do_cpuid(0x80000006, regs);
1840                 if ((regs[0] >> 16) != 0) {
1841                         printf("L2 2MB data TLB: %d entries",
1842                             (regs[0] >> 16) & 0xfff);
1843                         print_AMD_l2_assoc(regs[0] >> 28);
1844                         printf("L2 2MB instruction TLB: %d entries",
1845                             regs[0] & 0xfff);
1846                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1847                 } else {
1848                         printf("L2 2MB unified TLB: %d entries",
1849                             regs[0] & 0xfff);
1850                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1851                 }
1852                 if ((regs[1] >> 16) != 0) {
1853                         printf("L2 4KB data TLB: %d entries",
1854                             (regs[1] >> 16) & 0xfff);
1855                         print_AMD_l2_assoc(regs[1] >> 28);
1856
1857                         printf("L2 4KB instruction TLB: %d entries",
1858                             (regs[1] >> 16) & 0xfff);
1859                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1860                 } else {
1861                         printf("L2 4KB unified TLB: %d entries",
1862                             (regs[1] >> 16) & 0xfff);
1863                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1864                 }
1865                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1866                 printf(", %d bytes/line", regs[2] & 0xff);
1867                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1868                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1869         }
1870
1871 #ifdef __i386__
1872         if (((cpu_id & 0xf00) == 0x500)
1873             && (((cpu_id & 0x0f0) > 0x80)
1874                 || (((cpu_id & 0x0f0) == 0x80)
1875                     && (cpu_id & 0x00f) > 0x07))) {
1876                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1877                 amd_whcr = rdmsr(0xc0000082);
1878                 if (!(amd_whcr & (0x3ff << 22))) {
1879                         printf("Write Allocate Disable\n");
1880                 } else {
1881                         printf("Write Allocate Enable Limit: %dM bytes\n",
1882                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1883                         printf("Write Allocate 15-16M bytes: %s\n",
1884                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1885                 }
1886         } else if (((cpu_id & 0xf00) == 0x500)
1887                    && ((cpu_id & 0x0f0) > 0x50)) {
1888                 /* K6, K6-2(old core) */
1889                 amd_whcr = rdmsr(0xc0000082);
1890                 if (!(amd_whcr & (0x7f << 1))) {
1891                         printf("Write Allocate Disable\n");
1892                 } else {
1893                         printf("Write Allocate Enable Limit: %dM bytes\n",
1894                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1895                         printf("Write Allocate 15-16M bytes: %s\n",
1896                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1897                         printf("Hardware Write Allocate Control: %s\n",
1898                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1899                 }
1900         }
1901 #endif
1902         /*
1903          * Opteron Rev E shows a bug as in very rare occasions a read memory
1904          * barrier is not performed as expected if it is followed by a
1905          * non-atomic read-modify-write instruction.
1906          * As long as that bug pops up very rarely (intensive machine usage
1907          * on other operating systems generally generates one unexplainable
1908          * crash any 2 months) and as long as a model specific fix would be
1909          * impractical at this stage, print out a warning string if the broken
1910          * model and family are identified.
1911          */
1912         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1913             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1914                 printf("WARNING: This architecture revision has known SMP "
1915                     "hardware bugs which may cause random instability\n");
1916 }
1917
1918 static void
1919 print_INTEL_info(void)
1920 {
1921         u_int regs[4];
1922         u_int rounds, regnum;
1923         u_int nwaycode, nway;
1924
1925         if (cpu_high >= 2) {
1926                 rounds = 0;
1927                 do {
1928                         do_cpuid(0x2, regs);
1929                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1930                                 break;  /* we have a buggy CPU */
1931
1932                         for (regnum = 0; regnum <= 3; ++regnum) {
1933                                 if (regs[regnum] & (1<<31))
1934                                         continue;
1935                                 if (regnum != 0)
1936                                         print_INTEL_TLB(regs[regnum] & 0xff);
1937                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1938                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1939                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1940                         }
1941                 } while (--rounds > 0);
1942         }
1943
1944         if (cpu_exthigh >= 0x80000006) {
1945                 do_cpuid(0x80000006, regs);
1946                 nwaycode = (regs[2] >> 12) & 0x0f;
1947                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1948                         nway = 1 << (nwaycode / 2);
1949                 else
1950                         nway = 0;
1951                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1952                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1953         }
1954 }
1955
1956 static void
1957 print_INTEL_TLB(u_int data)
1958 {
1959         switch (data) {
1960         case 0x0:
1961         case 0x40:
1962         default:
1963                 break;
1964         case 0x1:
1965                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1966                 break;
1967         case 0x2:
1968                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1969                 break;
1970         case 0x3:
1971                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1972                 break;
1973         case 0x4:
1974                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1975                 break;
1976         case 0x6:
1977                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1978                 break;
1979         case 0x8:
1980                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1981                 break;
1982         case 0x9:
1983                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1984                 break;
1985         case 0xa:
1986                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1987                 break;
1988         case 0xb:
1989                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1990                 break;
1991         case 0xc:
1992                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1993                 break;
1994         case 0xd:
1995                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1996                 break;
1997         case 0xe:
1998                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1999                 break;
2000         case 0x1d:
2001                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2002                 break;
2003         case 0x21:
2004                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2005                 break;
2006         case 0x22:
2007                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2008                 break;
2009         case 0x23:
2010                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2011                 break;
2012         case 0x24:
2013                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2014                 break;
2015         case 0x25:
2016                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2017                 break;
2018         case 0x29:
2019                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2020                 break;
2021         case 0x2c:
2022                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2023                 break;
2024         case 0x30:
2025                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2026                 break;
2027         case 0x39: /* De-listed in SDM rev. 54 */
2028                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2029                 break;
2030         case 0x3b: /* De-listed in SDM rev. 54 */
2031                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2032                 break;
2033         case 0x3c: /* De-listed in SDM rev. 54 */
2034                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2035                 break;
2036         case 0x41:
2037                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2038                 break;
2039         case 0x42:
2040                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2041                 break;
2042         case 0x43:
2043                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2044                 break;
2045         case 0x44:
2046                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2047                 break;
2048         case 0x45:
2049                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2050                 break;
2051         case 0x46:
2052                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2053                 break;
2054         case 0x47:
2055                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2056                 break;
2057         case 0x48:
2058                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2059                 break;
2060         case 0x49:
2061                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2062                     CPUID_TO_MODEL(cpu_id) == 0x6)
2063                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2064                 else
2065                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2066                 break;
2067         case 0x4a:
2068                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2069                 break;
2070         case 0x4b:
2071                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2072                 break;
2073         case 0x4c:
2074                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2075                 break;
2076         case 0x4d:
2077                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2078                 break;
2079         case 0x4e:
2080                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2081                 break;
2082         case 0x4f:
2083                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2084                 break;
2085         case 0x50:
2086                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2087                 break;
2088         case 0x51:
2089                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2090                 break;
2091         case 0x52:
2092                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2093                 break;
2094         case 0x55:
2095                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2096                 break;
2097         case 0x56:
2098                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2099                 break;
2100         case 0x57:
2101                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2102                 break;
2103         case 0x59:
2104                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2105                 break;
2106         case 0x5a:
2107                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2108                 break;
2109         case 0x5b:
2110                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2111                 break;
2112         case 0x5c:
2113                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2114                 break;
2115         case 0x5d:
2116                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2117                 break;
2118         case 0x60:
2119                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2120                 break;
2121         case 0x61:
2122                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2123                 break;
2124         case 0x63:
2125                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2126                 break;
2127         case 0x64:
2128                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2129                 break;
2130         case 0x66:
2131                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2132                 break;
2133         case 0x67:
2134                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2135                 break;
2136         case 0x68:
2137                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2138                 break;
2139         case 0x6a:
2140                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2141                 break;
2142         case 0x6b:
2143                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2144                 break;
2145         case 0x6c:
2146                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2147                 break;
2148         case 0x6d:
2149                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2150                 break;
2151         case 0x70:
2152                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2153                 break;
2154         case 0x71:
2155                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2156                 break;
2157         case 0x72:
2158                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2159                 break;
2160         case 0x76:
2161                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2162                 break;
2163         case 0x78:
2164                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2165                 break;
2166         case 0x79:
2167                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2168                 break;
2169         case 0x7a:
2170                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2171                 break;
2172         case 0x7b:
2173                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2174                 break;
2175         case 0x7c:
2176                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2177                 break;
2178         case 0x7d:
2179                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2180                 break;
2181         case 0x7f:
2182                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2183                 break;
2184         case 0x80:
2185                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2186                 break;
2187         case 0x82:
2188                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2189                 break;
2190         case 0x83:
2191                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2192                 break;
2193         case 0x84:
2194                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2195                 break;
2196         case 0x85:
2197                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2198                 break;
2199         case 0x86:
2200                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2201                 break;
2202         case 0x87:
2203                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2204                 break;
2205         case 0xa0:
2206                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2207                 break;
2208         case 0xb0:
2209                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2210                 break;
2211         case 0xb1:
2212                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2213                 break;
2214         case 0xb2:
2215                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2216                 break;
2217         case 0xb3:
2218                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2219                 break;
2220         case 0xb4:
2221                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2222                 break;
2223         case 0xb5:
2224                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2225                 break;
2226         case 0xb6:
2227                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2228                 break;
2229         case 0xba:
2230                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2231                 break;
2232         case 0xc0:
2233                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2234                 break;
2235         case 0xc1:
2236                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2237                 break;
2238         case 0xc2:
2239                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2240                 break;
2241         case 0xc3:
2242                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2243                 break;
2244         case 0xc4:
2245                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2246                 break;
2247         case 0xca:
2248                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2249                 break;
2250         case 0xd0:
2251                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2252                 break;
2253         case 0xd1:
2254                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2255                 break;
2256         case 0xd2:
2257                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2258                 break;
2259         case 0xd6:
2260                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2261                 break;
2262         case 0xd7:
2263                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2264                 break;
2265         case 0xd8:
2266                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2267                 break;
2268         case 0xdc:
2269                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2270                 break;
2271         case 0xdd:
2272                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2273                 break;
2274         case 0xde:
2275                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2276                 break;
2277         case 0xe2:
2278                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2279                 break;
2280         case 0xe3:
2281                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2282                 break;
2283         case 0xe4:
2284                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2285                 break;
2286         case 0xea:
2287                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2288                 break;
2289         case 0xeb:
2290                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2291                 break;
2292         case 0xec:
2293                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2294                 break;
2295         case 0xf0:
2296                 printf("64-Byte prefetching\n");
2297                 break;
2298         case 0xf1:
2299                 printf("128-Byte prefetching\n");
2300                 break;
2301         }
2302 }
2303
2304 static void
2305 print_svm_info(void)
2306 {
2307         u_int features, regs[4];
2308         uint64_t msr;
2309         int comma;
2310
2311         printf("\n  SVM: ");
2312         do_cpuid(0x8000000A, regs);
2313         features = regs[3];
2314
2315         msr = rdmsr(MSR_VM_CR);
2316         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2317                 printf("(disabled in BIOS) ");
2318
2319         if (!bootverbose) {
2320                 comma = 0;
2321                 if (features & (1 << 0)) {
2322                         printf("%sNP", comma ? "," : "");
2323                         comma = 1;
2324                 }
2325                 if (features & (1 << 3)) {
2326                         printf("%sNRIP", comma ? "," : "");
2327                         comma = 1;
2328                 }
2329                 if (features & (1 << 5)) {
2330                         printf("%sVClean", comma ? "," : "");
2331                         comma = 1;
2332                 }
2333                 if (features & (1 << 6)) {
2334                         printf("%sAFlush", comma ? "," : "");
2335                         comma = 1;
2336                 }
2337                 if (features & (1 << 7)) {
2338                         printf("%sDAssist", comma ? "," : "");
2339                         comma = 1;
2340                 }
2341                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2342                 return;
2343         }
2344
2345         printf("Features=0x%b", features,
2346                "\020"
2347                "\001NP"                 /* Nested paging */
2348                "\002LbrVirt"            /* LBR virtualization */
2349                "\003SVML"               /* SVM lock */
2350                "\004NRIPS"              /* NRIP save */
2351                "\005TscRateMsr"         /* MSR based TSC rate control */
2352                "\006VmcbClean"          /* VMCB clean bits */
2353                "\007FlushByAsid"        /* Flush by ASID */
2354                "\010DecodeAssist"       /* Decode assist */
2355                "\011<b8>"
2356                "\012<b9>"
2357                "\013PauseFilter"        /* PAUSE intercept filter */
2358                "\014EncryptedMcodePatch"
2359                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2360                "\016AVIC"               /* virtual interrupt controller */
2361                "\017<b14>"
2362                "\020V_VMSAVE_VMLOAD"
2363                "\021vGIF"
2364                "\022GMET"               /* Guest Mode Execute Trap */
2365                "\023<b18>"
2366                "\024<b19>"
2367                "\025<b20>"
2368                "\026<b21>"
2369                "\027<b22>"
2370                "\030<b23>"
2371                "\031<b24>"
2372                "\032<b25>"
2373                "\033<b26>"
2374                "\034<b27>"
2375                "\035<b28>"
2376                "\036<b29>"
2377                "\037<b30>"
2378                "\040<b31>"
2379                 );
2380         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2381 }
2382
2383 #ifdef __i386__
2384 static void
2385 print_transmeta_info(void)
2386 {
2387         u_int regs[4], nreg = 0;
2388
2389         do_cpuid(0x80860000, regs);
2390         nreg = regs[0];
2391         if (nreg >= 0x80860001) {
2392                 do_cpuid(0x80860001, regs);
2393                 printf("  Processor revision %u.%u.%u.%u\n",
2394                        (regs[1] >> 24) & 0xff,
2395                        (regs[1] >> 16) & 0xff,
2396                        (regs[1] >> 8) & 0xff,
2397                        regs[1] & 0xff);
2398         }
2399         if (nreg >= 0x80860002) {
2400                 do_cpuid(0x80860002, regs);
2401                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2402                        (regs[1] >> 24) & 0xff,
2403                        (regs[1] >> 16) & 0xff,
2404                        (regs[1] >> 8) & 0xff,
2405                        regs[1] & 0xff,
2406                        regs[2]);
2407         }
2408         if (nreg >= 0x80860006) {
2409                 char info[65];
2410                 do_cpuid(0x80860003, (u_int*) &info[0]);
2411                 do_cpuid(0x80860004, (u_int*) &info[16]);
2412                 do_cpuid(0x80860005, (u_int*) &info[32]);
2413                 do_cpuid(0x80860006, (u_int*) &info[48]);
2414                 info[64] = 0;
2415                 printf("  %s\n", info);
2416         }
2417 }
2418 #endif
2419
2420 static void
2421 print_via_padlock_info(void)
2422 {
2423         u_int regs[4];
2424
2425         do_cpuid(0xc0000001, regs);
2426         printf("\n  VIA Padlock Features=0x%b", regs[3],
2427         "\020"
2428         "\003RNG"               /* RNG */
2429         "\007AES"               /* ACE */
2430         "\011AES-CTR"           /* ACE2 */
2431         "\013SHA1,SHA256"       /* PHE */
2432         "\015RSA"               /* PMM */
2433         );
2434 }
2435
2436 static uint32_t
2437 vmx_settable(uint64_t basic, int msr, int true_msr)
2438 {
2439         uint64_t val;
2440
2441         if (basic & (1ULL << 55))
2442                 val = rdmsr(true_msr);
2443         else
2444                 val = rdmsr(msr);
2445
2446         /* Just report the controls that can be set to 1. */
2447         return (val >> 32);
2448 }
2449
2450 static void
2451 print_vmx_info(void)
2452 {
2453         uint64_t basic, msr;
2454         uint32_t entry, exit, mask, pin, proc, proc2;
2455         int comma;
2456
2457         printf("\n  VT-x: ");
2458         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2459         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2460                 printf("(disabled in BIOS) ");
2461         basic = rdmsr(MSR_VMX_BASIC);
2462         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2463             MSR_VMX_TRUE_PINBASED_CTLS);
2464         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2465             MSR_VMX_TRUE_PROCBASED_CTLS);
2466         if (proc & PROCBASED_SECONDARY_CONTROLS)
2467                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2468                     MSR_VMX_PROCBASED_CTLS2);
2469         else
2470                 proc2 = 0;
2471         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2472         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2473
2474         if (!bootverbose) {
2475                 comma = 0;
2476                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2477                     entry & VM_ENTRY_LOAD_PAT) {
2478                         printf("%sPAT", comma ? "," : "");
2479                         comma = 1;
2480                 }
2481                 if (proc & PROCBASED_HLT_EXITING) {
2482                         printf("%sHLT", comma ? "," : "");
2483                         comma = 1;
2484                 }
2485                 if (proc & PROCBASED_MTF) {
2486                         printf("%sMTF", comma ? "," : "");
2487                         comma = 1;
2488                 }
2489                 if (proc & PROCBASED_PAUSE_EXITING) {
2490                         printf("%sPAUSE", comma ? "," : "");
2491                         comma = 1;
2492                 }
2493                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2494                         printf("%sEPT", comma ? "," : "");
2495                         comma = 1;
2496                 }
2497                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2498                         printf("%sUG", comma ? "," : "");
2499                         comma = 1;
2500                 }
2501                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2502                         printf("%sVPID", comma ? "," : "");
2503                         comma = 1;
2504                 }
2505                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2506                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2507                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2508                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2509                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2510                         printf("%sVID", comma ? "," : "");
2511                         comma = 1;
2512                         if (pin & PINBASED_POSTED_INTERRUPT)
2513                                 printf(",PostIntr");
2514                 }
2515                 return;
2516         }
2517
2518         mask = basic >> 32;
2519         printf("Basic Features=0x%b", mask,
2520         "\020"
2521         "\02132PA"              /* 32-bit physical addresses */
2522         "\022SMM"               /* SMM dual-monitor */
2523         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2524         "\030TRUE"              /* TRUE_CTLS MSRs */
2525         );
2526         printf("\n        Pin-Based Controls=0x%b", pin,
2527         "\020"
2528         "\001ExtINT"            /* External-interrupt exiting */
2529         "\004NMI"               /* NMI exiting */
2530         "\006VNMI"              /* Virtual NMIs */
2531         "\007PreTmr"            /* Activate VMX-preemption timer */
2532         "\010PostIntr"          /* Process posted interrupts */
2533         );
2534         printf("\n        Primary Processor Controls=0x%b", proc,
2535         "\020"
2536         "\003INTWIN"            /* Interrupt-window exiting */
2537         "\004TSCOff"            /* Use TSC offsetting */
2538         "\010HLT"               /* HLT exiting */
2539         "\012INVLPG"            /* INVLPG exiting */
2540         "\013MWAIT"             /* MWAIT exiting */
2541         "\014RDPMC"             /* RDPMC exiting */
2542         "\015RDTSC"             /* RDTSC exiting */
2543         "\020CR3-LD"            /* CR3-load exiting */
2544         "\021CR3-ST"            /* CR3-store exiting */
2545         "\024CR8-LD"            /* CR8-load exiting */
2546         "\025CR8-ST"            /* CR8-store exiting */
2547         "\026TPR"               /* Use TPR shadow */
2548         "\027NMIWIN"            /* NMI-window exiting */
2549         "\030MOV-DR"            /* MOV-DR exiting */
2550         "\031IO"                /* Unconditional I/O exiting */
2551         "\032IOmap"             /* Use I/O bitmaps */
2552         "\034MTF"               /* Monitor trap flag */
2553         "\035MSRmap"            /* Use MSR bitmaps */
2554         "\036MONITOR"           /* MONITOR exiting */
2555         "\037PAUSE"             /* PAUSE exiting */
2556         );
2557         if (proc & PROCBASED_SECONDARY_CONTROLS)
2558                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2559                 "\020"
2560                 "\001APIC"              /* Virtualize APIC accesses */
2561                 "\002EPT"               /* Enable EPT */
2562                 "\003DT"                /* Descriptor-table exiting */
2563                 "\004RDTSCP"            /* Enable RDTSCP */
2564                 "\005x2APIC"            /* Virtualize x2APIC mode */
2565                 "\006VPID"              /* Enable VPID */
2566                 "\007WBINVD"            /* WBINVD exiting */
2567                 "\010UG"                /* Unrestricted guest */
2568                 "\011APIC-reg"          /* APIC-register virtualization */
2569                 "\012VID"               /* Virtual-interrupt delivery */
2570                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2571                 "\014RDRAND"            /* RDRAND exiting */
2572                 "\015INVPCID"           /* Enable INVPCID */
2573                 "\016VMFUNC"            /* Enable VM functions */
2574                 "\017VMCS"              /* VMCS shadowing */
2575                 "\020EPT#VE"            /* EPT-violation #VE */
2576                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2577                 );
2578         printf("\n        Exit Controls=0x%b", mask,
2579         "\020"
2580         "\003DR"                /* Save debug controls */
2581                                 /* Ignore Host address-space size */
2582         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2583         "\020AckInt"            /* Acknowledge interrupt on exit */
2584         "\023PAT-SV"            /* Save MSR_PAT */
2585         "\024PAT-LD"            /* Load MSR_PAT */
2586         "\025EFER-SV"           /* Save MSR_EFER */
2587         "\026EFER-LD"           /* Load MSR_EFER */
2588         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2589         );
2590         printf("\n        Entry Controls=0x%b", mask,
2591         "\020"
2592         "\003DR"                /* Save debug controls */
2593                                 /* Ignore IA-32e mode guest */
2594                                 /* Ignore Entry to SMM */
2595                                 /* Ignore Deactivate dual-monitor treatment */
2596         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2597         "\017PAT"               /* Load MSR_PAT */
2598         "\020EFER"              /* Load MSR_EFER */
2599         );
2600         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2601             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2602                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2603                 mask = msr;
2604                 printf("\n        EPT Features=0x%b", mask,
2605                 "\020"
2606                 "\001XO"                /* Execute-only translations */
2607                 "\007PW4"               /* Page-walk length of 4 */
2608                 "\011UC"                /* EPT paging-structure mem can be UC */
2609                 "\017WB"                /* EPT paging-structure mem can be WB */
2610                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2611                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2612                 "\025INVEPT"            /* INVEPT is supported */
2613                 "\026AD"                /* Accessed and dirty flags for EPT */
2614                 "\032single"            /* INVEPT single-context type */
2615                 "\033all"               /* INVEPT all-context type */
2616                 );
2617                 mask = msr >> 32;
2618                 printf("\n        VPID Features=0x%b", mask,
2619                 "\020"
2620                 "\001INVVPID"           /* INVVPID is supported */
2621                 "\011individual"        /* INVVPID individual-address type */
2622                 "\012single"            /* INVVPID single-context type */
2623                 "\013all"               /* INVVPID all-context type */
2624                  /* INVVPID single-context-retaining-globals type */
2625                 "\014single-globals"
2626                 );
2627         }
2628 }
2629
2630 static void
2631 print_hypervisor_info(void)
2632 {
2633
2634         if (*hv_vendor != '\0')
2635                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2636 }
2637
2638 /*
2639  * Returns the maximum physical address that can be used with the
2640  * current system.
2641  */
2642 vm_paddr_t
2643 cpu_getmaxphyaddr(void)
2644 {
2645
2646 #if defined(__i386__)
2647         if (!pae_mode)
2648                 return (0xffffffff);
2649 #endif
2650         return ((1ULL << cpu_maxphyaddr) - 1);
2651 }