sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 122 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %ebx */
 123 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %ecx */
 124 u_int   cpu_power_edx;          /* 06H: Power management leaf, %edx */
 125 char machine[] = MACHINE;
 126
 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 128     &via_feature_rng, 0,
 129     "VIA RNG feature available in CPU");
 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 131     &via_feature_xcrypt, 0,
 132     "VIA xcrypt feature available in CPU");
 133
 134 #ifdef __amd64__
 135 #ifdef SCTL_MASK32
 136 extern int adaptive_machine_arch;
 137 #endif
 138
 139 static int
 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 141 {
 142 #ifdef SCTL_MASK32
 143         static const char machine32[] = "i386";
 144 #endif
 145         int error;
 146
 147 #ifdef SCTL_MASK32
 148         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 149                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 150         else
 151 #endif
 152                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 153         return (error);
 154
 155 }
 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 157     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 158 #else
 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 160     machine, 0, "Machine class");
 161 #endif
 162
 163 static char cpu_model[128];
 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 165     cpu_model, 0, "Machine model");
 166
 167 static int hw_clockrate;
 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 169     &hw_clockrate, 0, "CPU instruction clock rate");
 170
 171 u_int hv_base;
 172 u_int hv_high;
 173 char hv_vendor[16];
 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 175     0, "Hypervisor vendor");
 176
 177 static eventhandler_tag tsc_post_tag;
 178
 179 static char cpu_brand[48];
 180
 181 #ifdef __i386__
 182 #define MAX_BRAND_INDEX 8
 183
 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 185         NULL,                   /* No brand */
 186         "Intel Celeron",
 187         "Intel Pentium III",
 188         "Intel Pentium III Xeon",
 189         NULL,
 190         NULL,
 191         NULL,
 192         NULL,
 193         "Intel Pentium 4"
 194 };
 195
 196 static struct {
 197         char    *cpu_name;
 198         int     cpu_class;
 199 } cpus[] = {
 200         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 201         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 202         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 203         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 204         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 205         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 206         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 207         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 208         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 209         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 210         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 211         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 212         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 213         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 214         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 215         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 216         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 217 };
 218 #endif
 219
 220 static struct {
 221         char    *vendor;
 222         u_int   vendor_id;
 223 } cpu_vendors[] = {
 224         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 225         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 226         { HYGON_VENDOR_ID,      CPU_VENDOR_HYGON },     /* HygonGenuine */
 227         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 228 #ifdef __i386__
 229         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 230         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 231         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 232         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 233         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 234         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 235         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 236 #if 0
 237         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 238         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 239 #endif
 240 #endif
 241 };
 242
 243 void
 244 printcpuinfo(void)
 245 {
 246         u_int regs[4], i;
 247         char *brand;
 248
 249         printf("CPU: ");
 250 #ifdef __i386__
 251         cpu_class = cpus[cpu].cpu_class;
 252         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 253 #else
 254         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 255 #endif
 256
 257         /* Check for extended CPUID information and a processor name. */
 258         if (cpu_exthigh >= 0x80000004) {
 259                 brand = cpu_brand;
 260                 for (i = 0x80000002; i < 0x80000005; i++) {
 261                         do_cpuid(i, regs);
 262                         memcpy(brand, regs, sizeof(regs));
 263                         brand += sizeof(regs);
 264                 }
 265         }
 266
 267         switch (cpu_vendor_id) {
 268         case CPU_VENDOR_INTEL:
 269 #ifdef __i386__
 270                 if ((cpu_id & 0xf00) > 0x300) {
 271                         u_int brand_index;
 272
 273                         cpu_model[0] = '\0';
 274
 275                         switch (cpu_id & 0x3000) {
 276                         case 0x1000:
 277                                 strcpy(cpu_model, "Overdrive ");
 278                                 break;
 279                         case 0x2000:
 280                                 strcpy(cpu_model, "Dual ");
 281                                 break;
 282                         }
 283
 284                         switch (cpu_id & 0xf00) {
 285                         case 0x400:
 286                                 strcat(cpu_model, "i486 ");
 287                                 /* Check the particular flavor of 486 */
 288                                 switch (cpu_id & 0xf0) {
 289                                 case 0x00:
 290                                 case 0x10:
 291                                         strcat(cpu_model, "DX");
 292                                         break;
 293                                 case 0x20:
 294                                         strcat(cpu_model, "SX");
 295                                         break;
 296                                 case 0x30:
 297                                         strcat(cpu_model, "DX2");
 298                                         break;
 299                                 case 0x40:
 300                                         strcat(cpu_model, "SL");
 301                                         break;
 302                                 case 0x50:
 303                                         strcat(cpu_model, "SX2");
 304                                         break;
 305                                 case 0x70:
 306                                         strcat(cpu_model,
 307                                             "DX2 Write-Back Enhanced");
 308                                         break;
 309                                 case 0x80:
 310                                         strcat(cpu_model, "DX4");
 311                                         break;
 312                                 }
 313                                 break;
 314                         case 0x500:
 315                                 /* Check the particular flavor of 586 */
 316                                 strcat(cpu_model, "Pentium");
 317                                 switch (cpu_id & 0xf0) {
 318                                 case 0x00:
 319                                         strcat(cpu_model, " A-step");
 320                                         break;
 321                                 case 0x10:
 322                                         strcat(cpu_model, "/P5");
 323                                         break;
 324                                 case 0x20:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x30:
 328                                         strcat(cpu_model, "/P24T");
 329                                         break;
 330                                 case 0x40:
 331                                         strcat(cpu_model, "/P55C");
 332                                         break;
 333                                 case 0x70:
 334                                         strcat(cpu_model, "/P54C");
 335                                         break;
 336                                 case 0x80:
 337                                         strcat(cpu_model, "/P55C (quarter-micron)");
 338                                         break;
 339                                 default:
 340                                         /* nothing */
 341                                         break;
 342                                 }
 343 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 344                                 /*
 345                                  * XXX - If/when Intel fixes the bug, this
 346                                  * should also check the version of the
 347                                  * CPU, not just that it's a Pentium.
 348                                  */
 349                                 has_f00f_bug = 1;
 350 #endif
 351                                 break;
 352                         case 0x600:
 353                                 /* Check the particular flavor of 686 */
 354                                 switch (cpu_id & 0xf0) {
 355                                 case 0x00:
 356                                         strcat(cpu_model, "Pentium Pro A-step");
 357                                         break;
 358                                 case 0x10:
 359                                         strcat(cpu_model, "Pentium Pro");
 360                                         break;
 361                                 case 0x30:
 362                                 case 0x50:
 363                                 case 0x60:
 364                                         strcat(cpu_model,
 365                                 "Pentium II/Pentium II Xeon/Celeron");
 366                                         cpu = CPU_PII;
 367                                         break;
 368                                 case 0x70:
 369                                 case 0x80:
 370                                 case 0xa0:
 371                                 case 0xb0:
 372                                         strcat(cpu_model,
 373                                         "Pentium III/Pentium III Xeon/Celeron");
 374                                         cpu = CPU_PIII;
 375                                         break;
 376                                 default:
 377                                         strcat(cpu_model, "Unknown 80686");
 378                                         break;
 379                                 }
 380                                 break;
 381                         case 0xf00:
 382                                 strcat(cpu_model, "Pentium 4");
 383                                 cpu = CPU_P4;
 384                                 break;
 385                         default:
 386                                 strcat(cpu_model, "unknown");
 387                                 break;
 388                         }
 389
 390                         /*
 391                          * If we didn't get a brand name from the extended
 392                          * CPUID, try to look it up in the brand table.
 393                          */
 394                         if (cpu_high > 0 && *cpu_brand == '\0') {
 395                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 396                                 if (brand_index <= MAX_BRAND_INDEX &&
 397                                     cpu_brandtable[brand_index] != NULL)
 398                                         strcpy(cpu_brand,
 399                                             cpu_brandtable[brand_index]);
 400                         }
 401                 }
 402 #else
 403                 /* Please make up your mind folks! */
 404                 strcat(cpu_model, "EM64T");
 405 #endif
 406                 break;
 407         case CPU_VENDOR_AMD:
 408                 /*
 409                  * Values taken from AMD Processor Recognition
 410                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 411                  * (also describes ``Features'' encodings.
 412                  */
 413                 strcpy(cpu_model, "AMD ");
 414 #ifdef __i386__
 415                 switch (cpu_id & 0xFF0) {
 416                 case 0x410:
 417                         strcat(cpu_model, "Standard Am486DX");
 418                         break;
 419                 case 0x430:
 420                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 421                         break;
 422                 case 0x470:
 423                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 424                         break;
 425                 case 0x480:
 426                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 427                         break;
 428                 case 0x490:
 429                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 430                         break;
 431                 case 0x4E0:
 432                         strcat(cpu_model, "Am5x86 Write-Through");
 433                         break;
 434                 case 0x4F0:
 435                         strcat(cpu_model, "Am5x86 Write-Back");
 436                         break;
 437                 case 0x500:
 438                         strcat(cpu_model, "K5 model 0");
 439                         break;
 440                 case 0x510:
 441                         strcat(cpu_model, "K5 model 1");
 442                         break;
 443                 case 0x520:
 444                         strcat(cpu_model, "K5 PR166 (model 2)");
 445                         break;
 446                 case 0x530:
 447                         strcat(cpu_model, "K5 PR200 (model 3)");
 448                         break;
 449                 case 0x560:
 450                         strcat(cpu_model, "K6");
 451                         break;
 452                 case 0x570:
 453                         strcat(cpu_model, "K6 266 (model 1)");
 454                         break;
 455                 case 0x580:
 456                         strcat(cpu_model, "K6-2");
 457                         break;
 458                 case 0x590:
 459                         strcat(cpu_model, "K6-III");
 460                         break;
 461                 case 0x5a0:
 462                         strcat(cpu_model, "Geode LX");
 463                         break;
 464                 default:
 465                         strcat(cpu_model, "Unknown");
 466                         break;
 467                 }
 468 #else
 469                 if ((cpu_id & 0xf00) == 0xf00)
 470                         strcat(cpu_model, "AMD64 Processor");
 471                 else
 472                         strcat(cpu_model, "Unknown");
 473 #endif
 474                 break;
 475 #ifdef __i386__
 476         case CPU_VENDOR_CYRIX:
 477                 strcpy(cpu_model, "Cyrix ");
 478                 switch (cpu_id & 0xff0) {
 479                 case 0x440:
 480                         strcat(cpu_model, "MediaGX");
 481                         break;
 482                 case 0x520:
 483                         strcat(cpu_model, "6x86");
 484                         break;
 485                 case 0x540:
 486                         cpu_class = CPUCLASS_586;
 487                         strcat(cpu_model, "GXm");
 488                         break;
 489                 case 0x600:
 490                         strcat(cpu_model, "6x86MX");
 491                         break;
 492                 default:
 493                         /*
 494                          * Even though CPU supports the cpuid
 495                          * instruction, it can be disabled.
 496                          * Therefore, this routine supports all Cyrix
 497                          * CPUs.
 498                          */
 499                         switch (cyrix_did & 0xf0) {
 500                         case 0x00:
 501                                 switch (cyrix_did & 0x0f) {
 502                                 case 0x00:
 503                                         strcat(cpu_model, "486SLC");
 504                                         break;
 505                                 case 0x01:
 506                                         strcat(cpu_model, "486DLC");
 507                                         break;
 508                                 case 0x02:
 509                                         strcat(cpu_model, "486SLC2");
 510                                         break;
 511                                 case 0x03:
 512                                         strcat(cpu_model, "486DLC2");
 513                                         break;
 514                                 case 0x04:
 515                                         strcat(cpu_model, "486SRx");
 516                                         break;
 517                                 case 0x05:
 518                                         strcat(cpu_model, "486DRx");
 519                                         break;
 520                                 case 0x06:
 521                                         strcat(cpu_model, "486SRx2");
 522                                         break;
 523                                 case 0x07:
 524                                         strcat(cpu_model, "486DRx2");
 525                                         break;
 526                                 case 0x08:
 527                                         strcat(cpu_model, "486SRu");
 528                                         break;
 529                                 case 0x09:
 530                                         strcat(cpu_model, "486DRu");
 531                                         break;
 532                                 case 0x0a:
 533                                         strcat(cpu_model, "486SRu2");
 534                                         break;
 535                                 case 0x0b:
 536                                         strcat(cpu_model, "486DRu2");
 537                                         break;
 538                                 default:
 539                                         strcat(cpu_model, "Unknown");
 540                                         break;
 541                                 }
 542                                 break;
 543                         case 0x10:
 544                                 switch (cyrix_did & 0x0f) {
 545                                 case 0x00:
 546                                         strcat(cpu_model, "486S");
 547                                         break;
 548                                 case 0x01:
 549                                         strcat(cpu_model, "486S2");
 550                                         break;
 551                                 case 0x02:
 552                                         strcat(cpu_model, "486Se");
 553                                         break;
 554                                 case 0x03:
 555                                         strcat(cpu_model, "486S2e");
 556                                         break;
 557                                 case 0x0a:
 558                                         strcat(cpu_model, "486DX");
 559                                         break;
 560                                 case 0x0b:
 561                                         strcat(cpu_model, "486DX2");
 562                                         break;
 563                                 case 0x0f:
 564                                         strcat(cpu_model, "486DX4");
 565                                         break;
 566                                 default:
 567                                         strcat(cpu_model, "Unknown");
 568                                         break;
 569                                 }
 570                                 break;
 571                         case 0x20:
 572                                 if ((cyrix_did & 0x0f) < 8)
 573                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 574                                 else
 575                                         strcat(cpu_model, "5x86");
 576                                 break;
 577                         case 0x30:
 578                                 strcat(cpu_model, "6x86");
 579                                 break;
 580                         case 0x40:
 581                                 if ((cyrix_did & 0xf000) == 0x3000) {
 582                                         cpu_class = CPUCLASS_586;
 583                                         strcat(cpu_model, "GXm");
 584                                 } else
 585                                         strcat(cpu_model, "MediaGX");
 586                                 break;
 587                         case 0x50:
 588                                 strcat(cpu_model, "6x86MX");
 589                                 break;
 590                         case 0xf0:
 591                                 switch (cyrix_did & 0x0f) {
 592                                 case 0x0d:
 593                                         strcat(cpu_model, "Overdrive CPU");
 594                                         break;
 595                                 case 0x0e:
 596                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 597                                         break;
 598                                 case 0x0f:
 599                                         strcat(cpu_model, "486SLC/DLC");
 600                                         break;
 601                                 default:
 602                                         strcat(cpu_model, "Unknown");
 603                                         break;
 604                                 }
 605                                 break;
 606                         default:
 607                                 strcat(cpu_model, "Unknown");
 608                                 break;
 609                         }
 610                         break;
 611                 }
 612                 break;
 613         case CPU_VENDOR_RISE:
 614                 strcpy(cpu_model, "Rise ");
 615                 switch (cpu_id & 0xff0) {
 616                 case 0x500:     /* 6401 and 6441 (Kirin) */
 617                 case 0x520:     /* 6510 (Lynx) */
 618                         strcat(cpu_model, "mP6");
 619                         break;
 620                 default:
 621                         strcat(cpu_model, "Unknown");
 622                 }
 623                 break;
 624 #endif
 625         case CPU_VENDOR_CENTAUR:
 626 #ifdef __i386__
 627                 switch (cpu_id & 0xff0) {
 628                 case 0x540:
 629                         strcpy(cpu_model, "IDT WinChip C6");
 630                         break;
 631                 case 0x580:
 632                         strcpy(cpu_model, "IDT WinChip 2");
 633                         break;
 634                 case 0x590:
 635                         strcpy(cpu_model, "IDT WinChip 3");
 636                         break;
 637                 case 0x660:
 638                         strcpy(cpu_model, "VIA C3 Samuel");
 639                         break;
 640                 case 0x670:
 641                         if (cpu_id & 0x8)
 642                                 strcpy(cpu_model, "VIA C3 Ezra");
 643                         else
 644                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 645                         break;
 646                 case 0x680:
 647                         strcpy(cpu_model, "VIA C3 Ezra-T");
 648                         break;
 649                 case 0x690:
 650                         strcpy(cpu_model, "VIA C3 Nehemiah");
 651                         break;
 652                 case 0x6a0:
 653                 case 0x6d0:
 654                         strcpy(cpu_model, "VIA C7 Esther");
 655                         break;
 656                 case 0x6f0:
 657                         strcpy(cpu_model, "VIA Nano");
 658                         break;
 659                 default:
 660                         strcpy(cpu_model, "VIA/IDT Unknown");
 661                 }
 662 #else
 663                 strcpy(cpu_model, "VIA ");
 664                 if ((cpu_id & 0xff0) == 0x6f0)
 665                         strcat(cpu_model, "Nano Processor");
 666                 else
 667                         strcat(cpu_model, "Unknown");
 668 #endif
 669                 break;
 670 #ifdef __i386__
 671         case CPU_VENDOR_IBM:
 672                 strcpy(cpu_model, "Blue Lightning CPU");
 673                 break;
 674         case CPU_VENDOR_NSC:
 675                 switch (cpu_id & 0xff0) {
 676                 case 0x540:
 677                         strcpy(cpu_model, "Geode SC1100");
 678                         cpu = CPU_GEODE1100;
 679                         break;
 680                 default:
 681                         strcpy(cpu_model, "Geode/NSC unknown");
 682                         break;
 683                 }
 684                 break;
 685 #endif
 686         case CPU_VENDOR_HYGON:
 687                 strcpy(cpu_model, "Hygon ");
 688 #ifdef __i386__
 689                 strcat(cpu_model, "Unknown");
 690 #else
 691                 if ((cpu_id & 0xf00) == 0xf00)
 692                         strcat(cpu_model, "AMD64 Processor");
 693                 else
 694                         strcat(cpu_model, "Unknown");
 695 #endif
 696                 break;
 697
 698         default:
 699                 strcat(cpu_model, "Unknown");
 700                 break;
 701         }
 702
 703         /*
 704          * Replace cpu_model with cpu_brand minus leading spaces if
 705          * we have one.
 706          */
 707         brand = cpu_brand;
 708         while (*brand == ' ')
 709                 ++brand;
 710         if (*brand != '\0')
 711                 strcpy(cpu_model, brand);
 712
 713         printf("%s (", cpu_model);
 714         if (tsc_freq != 0) {
 715                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 716                 printf("%jd.%02d-MHz ",
 717                     (intmax_t)(tsc_freq + 4999) / 1000000,
 718                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 719         }
 720 #ifdef __i386__
 721         switch(cpu_class) {
 722         case CPUCLASS_286:
 723                 printf("286");
 724                 break;
 725         case CPUCLASS_386:
 726                 printf("386");
 727                 break;
 728 #if defined(I486_CPU)
 729         case CPUCLASS_486:
 730                 printf("486");
 731                 break;
 732 #endif
 733 #if defined(I586_CPU)
 734         case CPUCLASS_586:
 735                 printf("586");
 736                 break;
 737 #endif
 738 #if defined(I686_CPU)
 739         case CPUCLASS_686:
 740                 printf("686");
 741                 break;
 742 #endif
 743         default:
 744                 printf("Unknown");      /* will panic below... */
 745         }
 746 #else
 747         printf("K8");
 748 #endif
 749         printf("-class CPU)\n");
 750         if (*cpu_vendor)
 751                 printf("  Origin=\"%s\"", cpu_vendor);
 752         if (cpu_id)
 753                 printf("  Id=0x%x", cpu_id);
 754
 755         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 756             cpu_vendor_id == CPU_VENDOR_AMD ||
 757             cpu_vendor_id == CPU_VENDOR_HYGON ||
 758             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 759 #ifdef __i386__
 760             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 761             cpu_vendor_id == CPU_VENDOR_RISE ||
 762             cpu_vendor_id == CPU_VENDOR_NSC ||
 763             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 764 #endif
 765             0) {
 766                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 767                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 768                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 769 #ifdef __i386__
 770                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 771                         printf("\n  DIR=0x%04x", cyrix_did);
 772 #endif
 773
 774                 /*
 775                  * AMD CPUID Specification
 776                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 777                  *
 778                  * Intel Processor Identification and CPUID Instruction
 779                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 780                  */
 781                 if (cpu_high > 0) {
 782                         /*
 783                          * Here we should probably set up flags indicating
 784                          * whether or not various features are available.
 785                          * The interesting ones are probably VME, PSE, PAE,
 786                          * and PGE.  The code already assumes without bothering
 787                          * to check that all CPUs >= Pentium have a TSC and
 788                          * MSRs.
 789                          */
 790                         printf("\n  Features=0x%b", cpu_feature,
 791                         "\020"
 792                         "\001FPU"       /* Integral FPU */
 793                         "\002VME"       /* Extended VM86 mode support */
 794                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 795                         "\004PSE"       /* 4MByte page tables */
 796                         "\005TSC"       /* Timestamp counter */
 797                         "\006MSR"       /* Machine specific registers */
 798                         "\007PAE"       /* Physical address extension */
 799                         "\010MCE"       /* Machine Check support */
 800                         "\011CX8"       /* CMPEXCH8 instruction */
 801                         "\012APIC"      /* SMP local APIC */
 802                         "\013oldMTRR"   /* Previous implementation of MTRR */
 803                         "\014SEP"       /* Fast System Call */
 804                         "\015MTRR"      /* Memory Type Range Registers */
 805                         "\016PGE"       /* PG_G (global bit) support */
 806                         "\017MCA"       /* Machine Check Architecture */
 807                         "\020CMOV"      /* CMOV instruction */
 808                         "\021PAT"       /* Page attributes table */
 809                         "\022PSE36"     /* 36 bit address space support */
 810                         "\023PN"        /* Processor Serial number */
 811                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 812                         "\025<b20>"
 813                         "\026DTS"       /* Debug Trace Store */
 814                         "\027ACPI"      /* ACPI support */
 815                         "\030MMX"       /* MMX instructions */
 816                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 817                         "\032SSE"       /* Streaming SIMD Extensions */
 818                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 819                         "\034SS"        /* Self snoop */
 820                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 821                         "\036TM"        /* Thermal Monitor clock slowdown */
 822                         "\037IA64"      /* CPU can execute IA64 instructions */
 823                         "\040PBE"       /* Pending Break Enable */
 824                         );
 825
 826                         if (cpu_feature2 != 0) {
 827                                 printf("\n  Features2=0x%b", cpu_feature2,
 828                                 "\020"
 829                                 "\001SSE3"      /* SSE3 */
 830                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 831                                 "\003DTES64"    /* 64-bit Debug Trace */
 832                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 833                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 834                                 "\006VMX"       /* Virtual Machine Extensions */
 835                                 "\007SMX"       /* Safer Mode Extensions */
 836                                 "\010EST"       /* Enhanced SpeedStep */
 837                                 "\011TM2"       /* Thermal Monitor 2 */
 838                                 "\012SSSE3"     /* SSSE3 */
 839                                 "\013CNXT-ID"   /* L1 context ID available */
 840                                 "\014SDBG"      /* IA32 silicon debug */
 841                                 "\015FMA"       /* Fused Multiply Add */
 842                                 "\016CX16"      /* CMPXCHG16B Instruction */
 843                                 "\017xTPR"      /* Send Task Priority Messages*/
 844                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 845                                 "\021<b16>"
 846                                 "\022PCID"      /* Process-context Identifiers*/
 847                                 "\023DCA"       /* Direct Cache Access */
 848                                 "\024SSE4.1"    /* SSE 4.1 */
 849                                 "\025SSE4.2"    /* SSE 4.2 */
 850                                 "\026x2APIC"    /* xAPIC Extensions */
 851                                 "\027MOVBE"     /* MOVBE Instruction */
 852                                 "\030POPCNT"    /* POPCNT Instruction */
 853                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 854                                 "\032AESNI"     /* AES Crypto */
 855                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 856                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 857                                 "\035AVX"       /* Advanced Vector Extensions */
 858                                 "\036F16C"      /* Half-precision conversions */
 859                                 "\037RDRAND"    /* RDRAND Instruction */
 860                                 "\040HV"        /* Hypervisor */
 861                                 );
 862                         }
 863
 864                         if (amd_feature != 0) {
 865                                 printf("\n  AMD Features=0x%b", amd_feature,
 866                                 "\020"          /* in hex */
 867                                 "\001<s0>"      /* Same */
 868                                 "\002<s1>"      /* Same */
 869                                 "\003<s2>"      /* Same */
 870                                 "\004<s3>"      /* Same */
 871                                 "\005<s4>"      /* Same */
 872                                 "\006<s5>"      /* Same */
 873                                 "\007<s6>"      /* Same */
 874                                 "\010<s7>"      /* Same */
 875                                 "\011<s8>"      /* Same */
 876                                 "\012<s9>"      /* Same */
 877                                 "\013<b10>"     /* Undefined */
 878                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 879                                 "\015<s12>"     /* Same */
 880                                 "\016<s13>"     /* Same */
 881                                 "\017<s14>"     /* Same */
 882                                 "\020<s15>"     /* Same */
 883                                 "\021<s16>"     /* Same */
 884                                 "\022<s17>"     /* Same */
 885                                 "\023<b18>"     /* Reserved, unknown */
 886                                 "\024MP"        /* Multiprocessor Capable */
 887                                 "\025NX"        /* Has EFER.NXE, NX */
 888                                 "\026<b21>"     /* Undefined */
 889                                 "\027MMX+"      /* AMD MMX Extensions */
 890                                 "\030<s23>"     /* Same */
 891                                 "\031<s24>"     /* Same */
 892                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 893                                 "\033Page1GB"   /* 1-GB large page support */
 894                                 "\034RDTSCP"    /* RDTSCP */
 895                                 "\035<b28>"     /* Undefined */
 896                                 "\036LM"        /* 64 bit long mode */
 897                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 898                                 "\0403DNow!"    /* AMD 3DNow! */
 899                                 );
 900                         }
 901
 902                         if (amd_feature2 != 0) {
 903                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 904                                 "\020"
 905                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 906                                 "\002CMP"       /* CMP legacy */
 907                                 "\003SVM"       /* Secure Virtual Mode */
 908                                 "\004ExtAPIC"   /* Extended APIC register */
 909                                 "\005CR8"       /* CR8 in legacy mode */
 910                                 "\006ABM"       /* LZCNT instruction */
 911                                 "\007SSE4A"     /* SSE4A */
 912                                 "\010MAS"       /* Misaligned SSE mode */
 913                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 914                                 "\012OSVW"      /* OS visible workaround */
 915                                 "\013IBS"       /* Instruction based sampling */
 916                                 "\014XOP"       /* XOP extended instructions */
 917                                 "\015SKINIT"    /* SKINIT/STGI */
 918                                 "\016WDT"       /* Watchdog timer */
 919                                 "\017<b14>"
 920                                 "\020LWP"       /* Lightweight Profiling */
 921                                 "\021FMA4"      /* 4-operand FMA instructions */
 922                                 "\022TCE"       /* Translation Cache Extension */
 923                                 "\023<b18>"
 924                                 "\024NodeId"    /* NodeId MSR support */
 925                                 "\025<b20>"
 926                                 "\026TBM"       /* Trailing Bit Manipulation */
 927                                 "\027Topology"  /* Topology Extensions */
 928                                 "\030PCXC"      /* Core perf count */
 929                                 "\031PNXC"      /* NB perf count */
 930                                 "\032<b25>"
 931                                 "\033DBE"       /* Data Breakpoint extension */
 932                                 "\034PTSC"      /* Performance TSC */
 933                                 "\035PL2I"      /* L2I perf count */
 934                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 935                                 "\037ADMSKX"    /* Address mask extension */
 936                                 "\040<b31>"
 937                                 );
 938                         }
 939
 940                         if (cpu_stdext_feature != 0) {
 941                                 printf("\n  Structured Extended Features=0x%b",
 942                                     cpu_stdext_feature,
 943                                        "\020"
 944                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 945                                        "\001FSGSBASE"
 946                                        "\002TSCADJ"
 947                                        "\003SGX"
 948                                        /* Bit Manipulation Instructions */
 949                                        "\004BMI1"
 950                                        /* Hardware Lock Elision */
 951                                        "\005HLE"
 952                                        /* Advanced Vector Instructions 2 */
 953                                        "\006AVX2"
 954                                        /* FDP_EXCPTN_ONLY */
 955                                        "\007FDPEXC"
 956                                        /* Supervisor Mode Execution Prot. */
 957                                        "\010SMEP"
 958                                        /* Bit Manipulation Instructions */
 959                                        "\011BMI2"
 960                                        "\012ERMS"
 961                                        /* Invalidate Processor Context ID */
 962                                        "\013INVPCID"
 963                                        /* Restricted Transactional Memory */
 964                                        "\014RTM"
 965                                        "\015PQM"
 966                                        "\016NFPUSG"
 967                                        /* Intel Memory Protection Extensions */
 968                                        "\017MPX"
 969                                        "\020PQE"
 970                                        /* AVX512 Foundation */
 971                                        "\021AVX512F"
 972                                        "\022AVX512DQ"
 973                                        /* Enhanced NRBG */
 974                                        "\023RDSEED"
 975                                        /* ADCX + ADOX */
 976                                        "\024ADX"
 977                                        /* Supervisor Mode Access Prevention */
 978                                        "\025SMAP"
 979                                        "\026AVX512IFMA"
 980                                        /* Formerly PCOMMIT */
 981                                        "\027<b22>"
 982                                        "\030CLFLUSHOPT"
 983                                        "\031CLWB"
 984                                        "\032PROCTRACE"
 985                                        "\033AVX512PF"
 986                                        "\034AVX512ER"
 987                                        "\035AVX512CD"
 988                                        "\036SHA"
 989                                        "\037AVX512BW"
 990                                        "\040AVX512VL"
 991                                        );
 992                         }
 993
 994                         if (cpu_stdext_feature2 != 0) {
 995                                 printf("\n  Structured Extended Features2=0x%b",
 996                                     cpu_stdext_feature2,
 997                                        "\020"
 998                                        "\001PREFETCHWT1"
 999                                        "\002AVX512VBMI"
1000                                        "\003UMIP"
1001                                        "\004PKU"
1002                                        "\005OSPKE"
1003                                        "\006WAITPKG"
1004                                        "\007AVX512VBMI2"
1005                                        "\011GFNI"
1006                                        "\012VAES"
1007                                        "\013VPCLMULQDQ"
1008                                        "\014AVX512VNNI"
1009                                        "\015AVX512BITALG"
1010                                        "\016TME"
1011                                        "\017AVX512VPOPCNTDQ"
1012                                        "\021LA57"
1013                                        "\027RDPID"
1014                                        "\032CLDEMOTE"
1015                                        "\034MOVDIRI"
1016                                        "\035MOVDIR64B"
1017                                        "\036ENQCMD"
1018                                        "\037SGXLC"
1019                                        );
1020                         }
1021
1022                         if (cpu_stdext_feature3 != 0) {
1023                                 printf("\n  Structured Extended Features3=0x%b",
1024                                     cpu_stdext_feature3,
1025                                        "\020"
1026                                        "\003AVX512_4VNNIW"
1027                                        "\004AVX512_4FMAPS"
1028                                        "\005FSRM"
1029                                        "\011AVX512VP2INTERSECT"
1030                                        "\012MCUOPT"
1031                                        "\013MD_CLEAR"
1032                                        "\016TSXFA"
1033                                        "\023PCONFIG"
1034                                        "\025IBT"
1035                                        "\033IBPB"
1036                                        "\034STIBP"
1037                                        "\035L1DFL"
1038                                        "\036ARCH_CAP"
1039                                        "\037CORE_CAP"
1040                                        "\040SSBD"
1041                                        );
1042                         }
1043
1044                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1045                                 cpuid_count(0xd, 0x1, regs);
1046                                 if (regs[0] != 0) {
1047                                         printf("\n  XSAVE Features=0x%b",
1048                                             regs[0],
1049                                             "\020"
1050                                             "\001XSAVEOPT"
1051                                             "\002XSAVEC"
1052                                             "\003XINUSE"
1053                                             "\004XSAVES");
1054                                 }
1055                         }
1056
1057                         if (cpu_ia32_arch_caps != 0) {
1058                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1059                                     (u_int)cpu_ia32_arch_caps,
1060                                        "\020"
1061                                        "\001RDCL_NO"
1062                                        "\002IBRS_ALL"
1063                                        "\003RSBA"
1064                                        "\004SKIP_L1DFL_VME"
1065                                        "\005SSB_NO"
1066                                        "\006MDS_NO"
1067                                        "\010TSX_CTRL"
1068                                        "\011TAA_NO"
1069                                        );
1070                         }
1071
1072                         if (amd_extended_feature_extensions != 0) {
1073                                 u_int amd_fe_masked;
1074
1075                                 amd_fe_masked = amd_extended_feature_extensions;
1076                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1077                                         amd_fe_masked &=
1078                                             ~(AMDFEID_IBRS_ALWAYSON |
1079                                                 AMDFEID_PREFER_IBRS);
1080                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1081                                         amd_fe_masked &=
1082                                             ~AMDFEID_STIBP_ALWAYSON;
1083
1084                                 printf("\n  "
1085                                     "AMD Extended Feature Extensions ID EBX="
1086                                     "0x%b", amd_fe_masked,
1087                                     "\020"
1088                                     "\001CLZERO"
1089                                     "\002IRPerf"
1090                                     "\003XSaveErPtr"
1091                                     "\005RDPRU"
1092                                     "\011MCOMMIT"
1093                                     "\012WBNOINVD"
1094                                     "\015IBPB"
1095                                     "\017IBRS"
1096                                     "\020STIBP"
1097                                     "\021IBRS_ALWAYSON"
1098                                     "\022STIBP_ALWAYSON"
1099                                     "\023PREFER_IBRS"
1100                                     "\030PPIN"
1101                                     "\031SSBD"
1102                                     "\032VIRT_SSBD"
1103                                     "\033SSB_NO"
1104                                     );
1105                         }
1106
1107                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1108                                 print_via_padlock_info();
1109
1110                         if (cpu_feature2 & CPUID2_VMX)
1111                                 print_vmx_info();
1112
1113                         if (amd_feature2 & AMDID2_SVM)
1114                                 print_svm_info();
1115
1116                         if ((cpu_feature & CPUID_HTT) &&
1117                             (cpu_vendor_id == CPU_VENDOR_AMD ||
1118                              cpu_vendor_id == CPU_VENDOR_HYGON))
1119                                 cpu_feature &= ~CPUID_HTT;
1120
1121                         /*
1122                          * If this CPU supports P-state invariant TSC then
1123                          * mention the capability.
1124                          */
1125                         if (tsc_is_invariant) {
1126                                 printf("\n  TSC: P-state invariant");
1127                                 if (tsc_perf_stat)
1128                                         printf(", performance statistics");
1129                         }
1130                 }
1131 #ifdef __i386__
1132         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1133                 printf("  DIR=0x%04x", cyrix_did);
1134                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1135                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1136 #ifndef CYRIX_CACHE_REALLY_WORKS
1137                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1138                         printf("\n  CPU cache: write-through mode");
1139 #endif
1140 #endif
1141         }
1142
1143         /* Avoid ugly blank lines: only print newline when we have to. */
1144         if (*cpu_vendor || cpu_id)
1145                 printf("\n");
1146
1147         if (bootverbose) {
1148                 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1149                     cpu_vendor_id == CPU_VENDOR_HYGON)
1150                         print_AMD_info();
1151                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1152                         print_INTEL_info();
1153 #ifdef __i386__
1154                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1155                         print_transmeta_info();
1156 #endif
1157         }
1158
1159         print_hypervisor_info();
1160 }
1161
1162 #ifdef __i386__
1163 void
1164 panicifcpuunsupported(void)
1165 {
1166
1167 #if !defined(lint)
1168 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1169 #error This kernel is not configured for one of the supported CPUs
1170 #endif
1171 #else /* lint */
1172 #endif /* lint */
1173         /*
1174          * Now that we have told the user what they have,
1175          * let them know if that machine type isn't configured.
1176          */
1177         switch (cpu_class) {
1178         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1179         case CPUCLASS_386:
1180 #if !defined(I486_CPU)
1181         case CPUCLASS_486:
1182 #endif
1183 #if !defined(I586_CPU)
1184         case CPUCLASS_586:
1185 #endif
1186 #if !defined(I686_CPU)
1187         case CPUCLASS_686:
1188 #endif
1189                 panic("CPU class not configured");
1190         default:
1191                 break;
1192         }
1193 }
1194
1195 static  volatile u_int trap_by_rdmsr;
1196
1197 /*
1198  * Special exception 6 handler.
1199  * The rdmsr instruction generates invalid opcodes fault on 486-class
1200  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1201  * function identblue() when this handler is called.  Stacked eip should
1202  * be advanced.
1203  */
1204 inthand_t       bluetrap6;
1205 __asm
1206 ("                                                                      \n\
1207         .text                                                           \n\
1208         .p2align 2,0x90                                                 \n\
1209         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1210 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1211         ss                                                              \n\
1212         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1213         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1214         iret                                                            \n\
1215 ");
1216
1217 /*
1218  * Special exception 13 handler.
1219  * Accessing non-existent MSR generates general protection fault.
1220  */
1221 inthand_t       bluetrap13;
1222 __asm
1223 ("                                                                      \n\
1224         .text                                                           \n\
1225         .p2align 2,0x90                                                 \n\
1226         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1227 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1228         ss                                                              \n\
1229         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1230         popl    %eax            /* discard error code */                \n\
1231         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1232         iret                                                            \n\
1233 ");
1234
1235 /*
1236  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1237  * support cpuid instruction.  This function should be called after
1238  * loading interrupt descriptor table register.
1239  *
1240  * I don't like this method that handles fault, but I couldn't get
1241  * information for any other methods.  Does blue giant know?
1242  */
1243 static int
1244 identblue(void)
1245 {
1246
1247         trap_by_rdmsr = 0;
1248
1249         /*
1250          * Cyrix 486-class CPU does not support rdmsr instruction.
1251          * The rdmsr instruction generates invalid opcode fault, and exception
1252          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1253          * bluetrap6() set the magic number to trap_by_rdmsr.
1254          */
1255         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1256             GSEL(GCODE_SEL, SEL_KPL));
1257
1258         /*
1259          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1260          * In this case, rdmsr generates general protection fault, and
1261          * exception will be trapped by bluetrap13().
1262          */
1263         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1264             GSEL(GCODE_SEL, SEL_KPL));
1265
1266         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1267
1268         if (trap_by_rdmsr == 0xa8c1d)
1269                 return IDENTBLUE_CYRIX486;
1270         else if (trap_by_rdmsr == 0xa89c4)
1271                 return IDENTBLUE_CYRIXM2;
1272         return IDENTBLUE_IBMCPU;
1273 }
1274
1275 /*
1276  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1277  *
1278  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1279  * +-------+-------+---------------+
1280  * |  SID  |  RID  |   Device ID   |
1281  * |    (DIR 1)    |    (DIR 0)    |
1282  * +-------+-------+---------------+
1283  */
1284 static void
1285 identifycyrix(void)
1286 {
1287         register_t saveintr;
1288         int     ccr2_test = 0, dir_test = 0;
1289         u_char  ccr2, ccr3;
1290
1291         saveintr = intr_disable();
1292
1293         ccr2 = read_cyrix_reg(CCR2);
1294         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1295         read_cyrix_reg(CCR2);
1296         if (read_cyrix_reg(CCR2) != ccr2)
1297                 ccr2_test = 1;
1298         write_cyrix_reg(CCR2, ccr2);
1299
1300         ccr3 = read_cyrix_reg(CCR3);
1301         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1302         read_cyrix_reg(CCR3);
1303         if (read_cyrix_reg(CCR3) != ccr3)
1304                 dir_test = 1;                                   /* CPU supports DIRs. */
1305         write_cyrix_reg(CCR3, ccr3);
1306
1307         if (dir_test) {
1308                 /* Device ID registers are available. */
1309                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1310                 cyrix_did += read_cyrix_reg(DIR0);
1311         } else if (ccr2_test)
1312                 cyrix_did = 0x0010;             /* 486S A-step */
1313         else
1314                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1315
1316         intr_restore(saveintr);
1317 }
1318 #endif
1319
1320 /* Update TSC freq with the value indicated by the caller. */
1321 static void
1322 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1323 {
1324
1325         /* If there was an error during the transition, don't do anything. */
1326         if (status != 0)
1327                 return;
1328
1329         /* Total setting for this level gives the new frequency in MHz. */
1330         hw_clockrate = level->total_set.freq;
1331 }
1332
1333 static void
1334 hook_tsc_freq(void *arg __unused)
1335 {
1336
1337         if (tsc_is_invariant)
1338                 return;
1339
1340         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1341             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1342 }
1343
1344 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1345
1346 static const struct {
1347         const char *    vm_bname;
1348         int             vm_guest;
1349 } vm_bnames[] = {
1350         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1351         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1352         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1353         { "Xen",        VM_GUEST_XEN },         /* Xen */
1354         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1355         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1356 };
1357
1358 static const struct {
1359         const char *    vm_pname;
1360         int             vm_guest;
1361 } vm_pnames[] = {
1362         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1363         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1364         { "VirtualBox",                 VM_GUEST_VBOX },
1365         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1366         { "KVM",                        VM_GUEST_KVM },
1367 };
1368
1369 static struct {
1370         const char      *vm_cpuid;
1371         int             vm_guest;
1372 } vm_cpuids[] = {
1373         { "XenVMMXenVMM",       VM_GUEST_XEN },         /* XEN */
1374         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1375         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1376         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1377         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1378         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1379 };
1380
1381 static void
1382 identify_hypervisor_cpuid_base(void)
1383 {
1384         u_int leaf, regs[4];
1385         int i;
1386
1387         /*
1388          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1389          * http://lkml.org/lkml/2008/10/1/246
1390          *
1391          * KB1009458: Mechanisms to determine if software is running in
1392          * a VMware virtual machine
1393          * http://kb.vmware.com/kb/1009458
1394          *
1395          * Search for a hypervisor that we recognize. If we cannot find
1396          * a specific hypervisor, return the first information about the
1397          * hypervisor that we found, as others may be able to use.
1398          */
1399         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1400                 do_cpuid(leaf, regs);
1401
1402                 /*
1403                  * KVM from Linux kernels prior to commit
1404                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1405                  * to 0 rather than a valid hv_high value.  Check for
1406                  * the KVM signature bytes and fixup %eax to the
1407                  * highest supported leaf in that case.
1408                  */
1409                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1410                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1411                         regs[0] = leaf + 1;
1412
1413                 if (regs[0] >= leaf) {
1414                         for (i = 0; i < nitems(vm_cpuids); i++)
1415                                 if (strncmp((const char *)&regs[1],
1416                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1417                                         vm_guest = vm_cpuids[i].vm_guest;
1418                                         break;
1419                                 }
1420
1421                         /*
1422                          * If this is the first entry or we found a
1423                          * specific hypervisor, record the base, high value,
1424                          * and vendor identifier.
1425                          */
1426                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1427                                 hv_base = leaf;
1428                                 hv_high = regs[0];
1429                                 ((u_int *)&hv_vendor)[0] = regs[1];
1430                                 ((u_int *)&hv_vendor)[1] = regs[2];
1431                                 ((u_int *)&hv_vendor)[2] = regs[3];
1432                                 hv_vendor[12] = '\0';
1433
1434                                 /*
1435                                  * If we found a specific hypervisor, then
1436                                  * we are finished.
1437                                  */
1438                                 if (vm_guest != VM_GUEST_VM)
1439                                         return;
1440                         }
1441                 }
1442         }
1443 }
1444
1445 void
1446 identify_hypervisor(void)
1447 {
1448         u_int regs[4];
1449         char *p;
1450         int i;
1451
1452         /*
1453          * If CPUID2_HV is set, we are running in a hypervisor environment.
1454          */
1455         if (cpu_feature2 & CPUID2_HV) {
1456                 vm_guest = VM_GUEST_VM;
1457                 identify_hypervisor_cpuid_base();
1458
1459                 /* If we have a definitive vendor, we can return now. */
1460                 if (*hv_vendor != '\0')
1461                         return;
1462         }
1463
1464         /*
1465          * Examine SMBIOS strings for older hypervisors.
1466          */
1467         p = kern_getenv("smbios.system.serial");
1468         if (p != NULL) {
1469                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1470                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1471                         if (regs[1] == VMW_HVMAGIC) {
1472                                 vm_guest = VM_GUEST_VMWARE;
1473                                 freeenv(p);
1474                                 return;
1475                         }
1476                 }
1477                 freeenv(p);
1478         }
1479
1480         /*
1481          * XXX: Some of these entries may not be needed since they were
1482          * added to FreeBSD before the checks above.
1483          */
1484         p = kern_getenv("smbios.bios.vendor");
1485         if (p != NULL) {
1486                 for (i = 0; i < nitems(vm_bnames); i++)
1487                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1488                                 vm_guest = vm_bnames[i].vm_guest;
1489                                 /* If we have a specific match, return */
1490                                 if (vm_guest != VM_GUEST_VM) {
1491                                         freeenv(p);
1492                                         return;
1493                                 }
1494                                 /*
1495                                  * We are done with bnames, but there might be
1496                                  * a more specific match in the pnames
1497                                  */
1498                                 break;
1499                         }
1500                 freeenv(p);
1501         }
1502         p = kern_getenv("smbios.system.product");
1503         if (p != NULL) {
1504                 for (i = 0; i < nitems(vm_pnames); i++)
1505                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1506                                 vm_guest = vm_pnames[i].vm_guest;
1507                                 freeenv(p);
1508                                 return;
1509                         }
1510                 freeenv(p);
1511         }
1512 }
1513
1514 bool
1515 fix_cpuid(void)
1516 {
1517         uint64_t msr;
1518
1519         /*
1520          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1521          * get the largest standard CPUID function number again if it is set
1522          * from BIOS.  It is necessary for probing correct CPU topology later
1523          * and for the correct operation of the AVX-aware userspace.
1524          */
1525         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1526             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1527             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1528             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1529             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1530                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1531                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1532                         msr &= ~IA32_MISC_EN_LIMCPUID;
1533                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1534                         return (true);
1535                 }
1536         }
1537
1538         /*
1539          * Re-enable AMD Topology Extension that could be disabled by BIOS
1540          * on some notebook processors.  Without the extension it's really
1541          * hard to determine the correct CPU cache topology.
1542          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1543          * Models 60h-6Fh Processors, Publication # 50742.
1544          */
1545         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1546             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1547                 msr = rdmsr(MSR_EXTFEATURES);
1548                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1549                         msr |= (uint64_t)1 << 54;
1550                         wrmsr(MSR_EXTFEATURES, msr);
1551                         return (true);
1552                 }
1553         }
1554         return (false);
1555 }
1556
1557 void
1558 identify_cpu1(void)
1559 {
1560         u_int regs[4];
1561
1562         do_cpuid(0, regs);
1563         cpu_high = regs[0];
1564         ((u_int *)&cpu_vendor)[0] = regs[1];
1565         ((u_int *)&cpu_vendor)[1] = regs[3];
1566         ((u_int *)&cpu_vendor)[2] = regs[2];
1567         cpu_vendor[12] = '\0';
1568
1569         do_cpuid(1, regs);
1570         cpu_id = regs[0];
1571         cpu_procinfo = regs[1];
1572         cpu_feature = regs[3];
1573         cpu_feature2 = regs[2];
1574 }
1575
1576 void
1577 identify_cpu2(void)
1578 {
1579         u_int regs[4], cpu_stdext_disable;
1580
1581         if (cpu_high >= 6) {
1582                 cpuid_count(6, 0, regs);
1583                 cpu_power_eax = regs[0];
1584                 cpu_power_ebx = regs[1];
1585                 cpu_power_ecx = regs[2];
1586                 cpu_power_edx = regs[3];
1587         }
1588
1589         if (cpu_high >= 7) {
1590                 cpuid_count(7, 0, regs);
1591                 cpu_stdext_feature = regs[1];
1592
1593                 /*
1594                  * Some hypervisors failed to filter out unsupported
1595                  * extended features.  Allow to disable the
1596                  * extensions, activation of which requires setting a
1597                  * bit in CR4, and which VM monitors do not support.
1598                  */
1599                 cpu_stdext_disable = 0;
1600                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1601                 cpu_stdext_feature &= ~cpu_stdext_disable;
1602
1603                 cpu_stdext_feature2 = regs[2];
1604                 cpu_stdext_feature3 = regs[3];
1605
1606                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1607                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1608         }
1609 }
1610
1611 void
1612 identify_cpu_fixup_bsp(void)
1613 {
1614         u_int regs[4];
1615
1616         cpu_vendor_id = find_cpu_vendor_id();
1617
1618         if (fix_cpuid()) {
1619                 do_cpuid(0, regs);
1620                 cpu_high = regs[0];
1621         }
1622 }
1623
1624 /*
1625  * Final stage of CPU identification.
1626  */
1627 void
1628 finishidentcpu(void)
1629 {
1630         u_int regs[4];
1631 #ifdef __i386__
1632         u_char ccr3;
1633 #endif
1634
1635         identify_cpu_fixup_bsp();
1636
1637         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1638                 do_cpuid(5, regs);
1639                 cpu_mon_mwait_flags = regs[2];
1640                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1641                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1642         }
1643
1644         identify_cpu2();
1645
1646 #ifdef __i386__
1647         if (cpu_high > 0 &&
1648             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1649              cpu_vendor_id == CPU_VENDOR_AMD ||
1650              cpu_vendor_id == CPU_VENDOR_HYGON ||
1651              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1652              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1653              cpu_vendor_id == CPU_VENDOR_NSC)) {
1654                 do_cpuid(0x80000000, regs);
1655                 if (regs[0] >= 0x80000000)
1656                         cpu_exthigh = regs[0];
1657         }
1658 #else
1659         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1660             cpu_vendor_id == CPU_VENDOR_AMD ||
1661             cpu_vendor_id == CPU_VENDOR_HYGON ||
1662             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1663                 do_cpuid(0x80000000, regs);
1664                 cpu_exthigh = regs[0];
1665         }
1666 #endif
1667         if (cpu_exthigh >= 0x80000001) {
1668                 do_cpuid(0x80000001, regs);
1669                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1670                 amd_feature2 = regs[2];
1671         }
1672         if (cpu_exthigh >= 0x80000007) {
1673                 do_cpuid(0x80000007, regs);
1674                 amd_rascap = regs[1];
1675                 amd_pminfo = regs[3];
1676         }
1677         if (cpu_exthigh >= 0x80000008) {
1678                 do_cpuid(0x80000008, regs);
1679                 cpu_maxphyaddr = regs[0] & 0xff;
1680                 amd_extended_feature_extensions = regs[1];
1681                 cpu_procinfo2 = regs[2];
1682         } else {
1683                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1684         }
1685
1686 #ifdef __i386__
1687         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1688                 if (cpu == CPU_486) {
1689                         /*
1690                          * These conditions are equivalent to:
1691                          *     - CPU does not support cpuid instruction.
1692                          *     - Cyrix/IBM CPU is detected.
1693                          */
1694                         if (identblue() == IDENTBLUE_IBMCPU) {
1695                                 strcpy(cpu_vendor, "IBM");
1696                                 cpu_vendor_id = CPU_VENDOR_IBM;
1697                                 cpu = CPU_BLUE;
1698                                 return;
1699                         }
1700                 }
1701                 switch (cpu_id & 0xf00) {
1702                 case 0x600:
1703                         /*
1704                          * Cyrix's datasheet does not describe DIRs.
1705                          * Therefor, I assume it does not have them
1706                          * and use the result of the cpuid instruction.
1707                          * XXX they seem to have it for now at least. -Peter
1708                          */
1709                         identifycyrix();
1710                         cpu = CPU_M2;
1711                         break;
1712                 default:
1713                         identifycyrix();
1714                         /*
1715                          * This routine contains a trick.
1716                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1717                          */
1718                         switch (cyrix_did & 0x00f0) {
1719                         case 0x00:
1720                         case 0xf0:
1721                                 cpu = CPU_486DLC;
1722                                 break;
1723                         case 0x10:
1724                                 cpu = CPU_CY486DX;
1725                                 break;
1726                         case 0x20:
1727                                 if ((cyrix_did & 0x000f) < 8)
1728                                         cpu = CPU_M1;
1729                                 else
1730                                         cpu = CPU_M1SC;
1731                                 break;
1732                         case 0x30:
1733                                 cpu = CPU_M1;
1734                                 break;
1735                         case 0x40:
1736                                 /* MediaGX CPU */
1737                                 cpu = CPU_M1SC;
1738                                 break;
1739                         default:
1740                                 /* M2 and later CPUs are treated as M2. */
1741                                 cpu = CPU_M2;
1742
1743                                 /*
1744                                  * enable cpuid instruction.
1745                                  */
1746                                 ccr3 = read_cyrix_reg(CCR3);
1747                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1748                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1749                                 write_cyrix_reg(CCR3, ccr3);
1750
1751                                 do_cpuid(0, regs);
1752                                 cpu_high = regs[0];     /* eax */
1753                                 do_cpuid(1, regs);
1754                                 cpu_id = regs[0];       /* eax */
1755                                 cpu_feature = regs[3];  /* edx */
1756                                 break;
1757                         }
1758                 }
1759         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1760                 /*
1761                  * There are BlueLightning CPUs that do not change
1762                  * undefined flags by dividing 5 by 2.  In this case,
1763                  * the CPU identification routine in locore.s leaves
1764                  * cpu_vendor null string and puts CPU_486 into the
1765                  * cpu.
1766                  */
1767                 if (identblue() == IDENTBLUE_IBMCPU) {
1768                         strcpy(cpu_vendor, "IBM");
1769                         cpu_vendor_id = CPU_VENDOR_IBM;
1770                         cpu = CPU_BLUE;
1771                         return;
1772                 }
1773         }
1774 #endif
1775 }
1776
1777 int
1778 pti_get_default(void)
1779 {
1780
1781         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1782             strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1783                 return (0);
1784         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1785                 return (0);
1786         return (1);
1787 }
1788
1789 static u_int
1790 find_cpu_vendor_id(void)
1791 {
1792         int     i;
1793
1794         for (i = 0; i < nitems(cpu_vendors); i++)
1795                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1796                         return (cpu_vendors[i].vendor_id);
1797         return (0);
1798 }
1799
1800 static void
1801 print_AMD_assoc(int i)
1802 {
1803         if (i == 255)
1804                 printf(", fully associative\n");
1805         else
1806                 printf(", %d-way associative\n", i);
1807 }
1808
1809 static void
1810 print_AMD_l2_assoc(int i)
1811 {
1812         switch (i & 0x0f) {
1813         case 0: printf(", disabled/not present\n"); break;
1814         case 1: printf(", direct mapped\n"); break;
1815         case 2: printf(", 2-way associative\n"); break;
1816         case 4: printf(", 4-way associative\n"); break;
1817         case 6: printf(", 8-way associative\n"); break;
1818         case 8: printf(", 16-way associative\n"); break;
1819         case 15: printf(", fully associative\n"); break;
1820         default: printf(", reserved configuration\n"); break;
1821         }
1822 }
1823
1824 static void
1825 print_AMD_info(void)
1826 {
1827 #ifdef __i386__
1828         uint64_t amd_whcr;
1829 #endif
1830         u_int regs[4];
1831
1832         if (cpu_exthigh >= 0x80000005) {
1833                 do_cpuid(0x80000005, regs);
1834                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1835                 print_AMD_assoc(regs[0] >> 24);
1836
1837                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1838                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1839
1840                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1841                 print_AMD_assoc(regs[1] >> 24);
1842
1843                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1844                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1845
1846                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1847                 printf(", %d bytes/line", regs[2] & 0xff);
1848                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1849                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1850
1851                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1852                 printf(", %d bytes/line", regs[3] & 0xff);
1853                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1854                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1855         }
1856
1857         if (cpu_exthigh >= 0x80000006) {
1858                 do_cpuid(0x80000006, regs);
1859                 if ((regs[0] >> 16) != 0) {
1860                         printf("L2 2MB data TLB: %d entries",
1861                             (regs[0] >> 16) & 0xfff);
1862                         print_AMD_l2_assoc(regs[0] >> 28);
1863                         printf("L2 2MB instruction TLB: %d entries",
1864                             regs[0] & 0xfff);
1865                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1866                 } else {
1867                         printf("L2 2MB unified TLB: %d entries",
1868                             regs[0] & 0xfff);
1869                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1870                 }
1871                 if ((regs[1] >> 16) != 0) {
1872                         printf("L2 4KB data TLB: %d entries",
1873                             (regs[1] >> 16) & 0xfff);
1874                         print_AMD_l2_assoc(regs[1] >> 28);
1875
1876                         printf("L2 4KB instruction TLB: %d entries",
1877                             (regs[1] >> 16) & 0xfff);
1878                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1879                 } else {
1880                         printf("L2 4KB unified TLB: %d entries",
1881                             (regs[1] >> 16) & 0xfff);
1882                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1883                 }
1884                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1885                 printf(", %d bytes/line", regs[2] & 0xff);
1886                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1887                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1888         }
1889
1890 #ifdef __i386__
1891         if (((cpu_id & 0xf00) == 0x500)
1892             && (((cpu_id & 0x0f0) > 0x80)
1893                 || (((cpu_id & 0x0f0) == 0x80)
1894                     && (cpu_id & 0x00f) > 0x07))) {
1895                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1896                 amd_whcr = rdmsr(0xc0000082);
1897                 if (!(amd_whcr & (0x3ff << 22))) {
1898                         printf("Write Allocate Disable\n");
1899                 } else {
1900                         printf("Write Allocate Enable Limit: %dM bytes\n",
1901                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1902                         printf("Write Allocate 15-16M bytes: %s\n",
1903                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1904                 }
1905         } else if (((cpu_id & 0xf00) == 0x500)
1906                    && ((cpu_id & 0x0f0) > 0x50)) {
1907                 /* K6, K6-2(old core) */
1908                 amd_whcr = rdmsr(0xc0000082);
1909                 if (!(amd_whcr & (0x7f << 1))) {
1910                         printf("Write Allocate Disable\n");
1911                 } else {
1912                         printf("Write Allocate Enable Limit: %dM bytes\n",
1913                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1914                         printf("Write Allocate 15-16M bytes: %s\n",
1915                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1916                         printf("Hardware Write Allocate Control: %s\n",
1917                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1918                 }
1919         }
1920 #endif
1921         /*
1922          * Opteron Rev E shows a bug as in very rare occasions a read memory
1923          * barrier is not performed as expected if it is followed by a
1924          * non-atomic read-modify-write instruction.
1925          * As long as that bug pops up very rarely (intensive machine usage
1926          * on other operating systems generally generates one unexplainable
1927          * crash any 2 months) and as long as a model specific fix would be
1928          * impractical at this stage, print out a warning string if the broken
1929          * model and family are identified.
1930          */
1931         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1932             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1933                 printf("WARNING: This architecture revision has known SMP "
1934                     "hardware bugs which may cause random instability\n");
1935 }
1936
1937 static void
1938 print_INTEL_info(void)
1939 {
1940         u_int regs[4];
1941         u_int rounds, regnum;
1942         u_int nwaycode, nway;
1943
1944         if (cpu_high >= 2) {
1945                 rounds = 0;
1946                 do {
1947                         do_cpuid(0x2, regs);
1948                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1949                                 break;  /* we have a buggy CPU */
1950
1951                         for (regnum = 0; regnum <= 3; ++regnum) {
1952                                 if (regs[regnum] & (1<<31))
1953                                         continue;
1954                                 if (regnum != 0)
1955                                         print_INTEL_TLB(regs[regnum] & 0xff);
1956                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1957                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1958                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1959                         }
1960                 } while (--rounds > 0);
1961         }
1962
1963         if (cpu_exthigh >= 0x80000006) {
1964                 do_cpuid(0x80000006, regs);
1965                 nwaycode = (regs[2] >> 12) & 0x0f;
1966                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1967                         nway = 1 << (nwaycode / 2);
1968                 else
1969                         nway = 0;
1970                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1971                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1972         }
1973 }
1974
1975 static void
1976 print_INTEL_TLB(u_int data)
1977 {
1978         switch (data) {
1979         case 0x0:
1980         case 0x40:
1981         default:
1982                 break;
1983         case 0x1:
1984                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1985                 break;
1986         case 0x2:
1987                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1988                 break;
1989         case 0x3:
1990                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1991                 break;
1992         case 0x4:
1993                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1994                 break;
1995         case 0x6:
1996                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1997                 break;
1998         case 0x8:
1999                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2000                 break;
2001         case 0x9:
2002                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2003                 break;
2004         case 0xa:
2005                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2006                 break;
2007         case 0xb:
2008                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2009                 break;
2010         case 0xc:
2011                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2012                 break;
2013         case 0xd:
2014                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2015                 break;
2016         case 0xe:
2017                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2018                 break;
2019         case 0x1d:
2020                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2021                 break;
2022         case 0x21:
2023                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2024                 break;
2025         case 0x22:
2026                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2027                 break;
2028         case 0x23:
2029                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2030                 break;
2031         case 0x24:
2032                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2033                 break;
2034         case 0x25:
2035                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2036                 break;
2037         case 0x29:
2038                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2039                 break;
2040         case 0x2c:
2041                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2042                 break;
2043         case 0x30:
2044                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2045                 break;
2046         case 0x39: /* De-listed in SDM rev. 54 */
2047                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2048                 break;
2049         case 0x3b: /* De-listed in SDM rev. 54 */
2050                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2051                 break;
2052         case 0x3c: /* De-listed in SDM rev. 54 */
2053                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2054                 break;
2055         case 0x41:
2056                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2057                 break;
2058         case 0x42:
2059                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2060                 break;
2061         case 0x43:
2062                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2063                 break;
2064         case 0x44:
2065                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2066                 break;
2067         case 0x45:
2068                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2069                 break;
2070         case 0x46:
2071                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2072                 break;
2073         case 0x47:
2074                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2075                 break;
2076         case 0x48:
2077                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2078                 break;
2079         case 0x49:
2080                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2081                     CPUID_TO_MODEL(cpu_id) == 0x6)
2082                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2083                 else
2084                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2085                 break;
2086         case 0x4a:
2087                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2088                 break;
2089         case 0x4b:
2090                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2091                 break;
2092         case 0x4c:
2093                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2094                 break;
2095         case 0x4d:
2096                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2097                 break;
2098         case 0x4e:
2099                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2100                 break;
2101         case 0x4f:
2102                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2103                 break;
2104         case 0x50:
2105                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2106                 break;
2107         case 0x51:
2108                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2109                 break;
2110         case 0x52:
2111                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2112                 break;
2113         case 0x55:
2114                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2115                 break;
2116         case 0x56:
2117                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2118                 break;
2119         case 0x57:
2120                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2121                 break;
2122         case 0x59:
2123                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2124                 break;
2125         case 0x5a:
2126                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2127                 break;
2128         case 0x5b:
2129                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2130                 break;
2131         case 0x5c:
2132                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2133                 break;
2134         case 0x5d:
2135                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2136                 break;
2137         case 0x60:
2138                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2139                 break;
2140         case 0x61:
2141                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2142                 break;
2143         case 0x63:
2144                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2145                 break;
2146         case 0x64:
2147                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2148                 break;
2149         case 0x66:
2150                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2151                 break;
2152         case 0x67:
2153                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2154                 break;
2155         case 0x68:
2156                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2157                 break;
2158         case 0x6a:
2159                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2160                 break;
2161         case 0x6b:
2162                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2163                 break;
2164         case 0x6c:
2165                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2166                 break;
2167         case 0x6d:
2168                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2169                 break;
2170         case 0x70:
2171                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2172                 break;
2173         case 0x71:
2174                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2175                 break;
2176         case 0x72:
2177                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2178                 break;
2179         case 0x76:
2180                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2181                 break;
2182         case 0x78:
2183                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2184                 break;
2185         case 0x79:
2186                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2187                 break;
2188         case 0x7a:
2189                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2190                 break;
2191         case 0x7b:
2192                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2193                 break;
2194         case 0x7c:
2195                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2196                 break;
2197         case 0x7d:
2198                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2199                 break;
2200         case 0x7f:
2201                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2202                 break;
2203         case 0x80:
2204                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2205                 break;
2206         case 0x82:
2207                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2208                 break;
2209         case 0x83:
2210                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2211                 break;
2212         case 0x84:
2213                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2214                 break;
2215         case 0x85:
2216                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2217                 break;
2218         case 0x86:
2219                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2220                 break;
2221         case 0x87:
2222                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2223                 break;
2224         case 0xa0:
2225                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2226                 break;
2227         case 0xb0:
2228                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2229                 break;
2230         case 0xb1:
2231                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2232                 break;
2233         case 0xb2:
2234                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2235                 break;
2236         case 0xb3:
2237                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2238                 break;
2239         case 0xb4:
2240                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2241                 break;
2242         case 0xb5:
2243                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2244                 break;
2245         case 0xb6:
2246                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2247                 break;
2248         case 0xba:
2249                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2250                 break;
2251         case 0xc0:
2252                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2253                 break;
2254         case 0xc1:
2255                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2256                 break;
2257         case 0xc2:
2258                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2259                 break;
2260         case 0xc3:
2261                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2262                 break;
2263         case 0xc4:
2264                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2265                 break;
2266         case 0xca:
2267                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2268                 break;
2269         case 0xd0:
2270                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2271                 break;
2272         case 0xd1:
2273                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2274                 break;
2275         case 0xd2:
2276                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2277                 break;
2278         case 0xd6:
2279                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2280                 break;
2281         case 0xd7:
2282                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2283                 break;
2284         case 0xd8:
2285                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2286                 break;
2287         case 0xdc:
2288                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2289                 break;
2290         case 0xdd:
2291                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2292                 break;
2293         case 0xde:
2294                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2295                 break;
2296         case 0xe2:
2297                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2298                 break;
2299         case 0xe3:
2300                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2301                 break;
2302         case 0xe4:
2303                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2304                 break;
2305         case 0xea:
2306                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2307                 break;
2308         case 0xeb:
2309                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2310                 break;
2311         case 0xec:
2312                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2313                 break;
2314         case 0xf0:
2315                 printf("64-Byte prefetching\n");
2316                 break;
2317         case 0xf1:
2318                 printf("128-Byte prefetching\n");
2319                 break;
2320         }
2321 }
2322
2323 static void
2324 print_svm_info(void)
2325 {
2326         u_int features, regs[4];
2327         uint64_t msr;
2328         int comma;
2329
2330         printf("\n  SVM: ");
2331         do_cpuid(0x8000000A, regs);
2332         features = regs[3];
2333
2334         msr = rdmsr(MSR_VM_CR);
2335         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2336                 printf("(disabled in BIOS) ");
2337
2338         if (!bootverbose) {
2339                 comma = 0;
2340                 if (features & (1 << 0)) {
2341                         printf("%sNP", comma ? "," : "");
2342                         comma = 1;
2343                 }
2344                 if (features & (1 << 3)) {
2345                         printf("%sNRIP", comma ? "," : "");
2346                         comma = 1;
2347                 }
2348                 if (features & (1 << 5)) {
2349                         printf("%sVClean", comma ? "," : "");
2350                         comma = 1;
2351                 }
2352                 if (features & (1 << 6)) {
2353                         printf("%sAFlush", comma ? "," : "");
2354                         comma = 1;
2355                 }
2356                 if (features & (1 << 7)) {
2357                         printf("%sDAssist", comma ? "," : "");
2358                         comma = 1;
2359                 }
2360                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2361                 return;
2362         }
2363
2364         printf("Features=0x%b", features,
2365                "\020"
2366                "\001NP"                 /* Nested paging */
2367                "\002LbrVirt"            /* LBR virtualization */
2368                "\003SVML"               /* SVM lock */
2369                "\004NRIPS"              /* NRIP save */
2370                "\005TscRateMsr"         /* MSR based TSC rate control */
2371                "\006VmcbClean"          /* VMCB clean bits */
2372                "\007FlushByAsid"        /* Flush by ASID */
2373                "\010DecodeAssist"       /* Decode assist */
2374                "\011<b8>"
2375                "\012<b9>"
2376                "\013PauseFilter"        /* PAUSE intercept filter */
2377                "\014EncryptedMcodePatch"
2378                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2379                "\016AVIC"               /* virtual interrupt controller */
2380                "\017<b14>"
2381                "\020V_VMSAVE_VMLOAD"
2382                "\021vGIF"
2383                "\022GMET"               /* Guest Mode Execute Trap */
2384                "\023<b18>"
2385                "\024<b19>"
2386                "\025GuesSpecCtl"        /* Guest Spec_ctl */
2387                "\026<b21>"
2388                "\027<b22>"
2389                "\030<b23>"
2390                "\031<b24>"
2391                "\032<b25>"
2392                "\033<b26>"
2393                "\034<b27>"
2394                "\035<b28>"
2395                "\036<b29>"
2396                "\037<b30>"
2397                "\040<b31>"
2398                );
2399         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2400 }
2401
2402 #ifdef __i386__
2403 static void
2404 print_transmeta_info(void)
2405 {
2406         u_int regs[4], nreg = 0;
2407
2408         do_cpuid(0x80860000, regs);
2409         nreg = regs[0];
2410         if (nreg >= 0x80860001) {
2411                 do_cpuid(0x80860001, regs);
2412                 printf("  Processor revision %u.%u.%u.%u\n",
2413                        (regs[1] >> 24) & 0xff,
2414                        (regs[1] >> 16) & 0xff,
2415                        (regs[1] >> 8) & 0xff,
2416                        regs[1] & 0xff);
2417         }
2418         if (nreg >= 0x80860002) {
2419                 do_cpuid(0x80860002, regs);
2420                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2421                        (regs[1] >> 24) & 0xff,
2422                        (regs[1] >> 16) & 0xff,
2423                        (regs[1] >> 8) & 0xff,
2424                        regs[1] & 0xff,
2425                        regs[2]);
2426         }
2427         if (nreg >= 0x80860006) {
2428                 char info[65];
2429                 do_cpuid(0x80860003, (u_int*) &info[0]);
2430                 do_cpuid(0x80860004, (u_int*) &info[16]);
2431                 do_cpuid(0x80860005, (u_int*) &info[32]);
2432                 do_cpuid(0x80860006, (u_int*) &info[48]);
2433                 info[64] = 0;
2434                 printf("  %s\n", info);
2435         }
2436 }
2437 #endif
2438
2439 static void
2440 print_via_padlock_info(void)
2441 {
2442         u_int regs[4];
2443
2444         do_cpuid(0xc0000001, regs);
2445         printf("\n  VIA Padlock Features=0x%b", regs[3],
2446         "\020"
2447         "\003RNG"               /* RNG */
2448         "\007AES"               /* ACE */
2449         "\011AES-CTR"           /* ACE2 */
2450         "\013SHA1,SHA256"       /* PHE */
2451         "\015RSA"               /* PMM */
2452         );
2453 }
2454
2455 static uint32_t
2456 vmx_settable(uint64_t basic, int msr, int true_msr)
2457 {
2458         uint64_t val;
2459
2460         if (basic & (1ULL << 55))
2461                 val = rdmsr(true_msr);
2462         else
2463                 val = rdmsr(msr);
2464
2465         /* Just report the controls that can be set to 1. */
2466         return (val >> 32);
2467 }
2468
2469 static void
2470 print_vmx_info(void)
2471 {
2472         uint64_t basic, msr;
2473         uint32_t entry, exit, mask, pin, proc, proc2;
2474         int comma;
2475
2476         printf("\n  VT-x: ");
2477         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2478         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2479                 printf("(disabled in BIOS) ");
2480         basic = rdmsr(MSR_VMX_BASIC);
2481         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2482             MSR_VMX_TRUE_PINBASED_CTLS);
2483         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2484             MSR_VMX_TRUE_PROCBASED_CTLS);
2485         if (proc & PROCBASED_SECONDARY_CONTROLS)
2486                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2487                     MSR_VMX_PROCBASED_CTLS2);
2488         else
2489                 proc2 = 0;
2490         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2491         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2492
2493         if (!bootverbose) {
2494                 comma = 0;
2495                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2496                     entry & VM_ENTRY_LOAD_PAT) {
2497                         printf("%sPAT", comma ? "," : "");
2498                         comma = 1;
2499                 }
2500                 if (proc & PROCBASED_HLT_EXITING) {
2501                         printf("%sHLT", comma ? "," : "");
2502                         comma = 1;
2503                 }
2504                 if (proc & PROCBASED_MTF) {
2505                         printf("%sMTF", comma ? "," : "");
2506                         comma = 1;
2507                 }
2508                 if (proc & PROCBASED_PAUSE_EXITING) {
2509                         printf("%sPAUSE", comma ? "," : "");
2510                         comma = 1;
2511                 }
2512                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2513                         printf("%sEPT", comma ? "," : "");
2514                         comma = 1;
2515                 }
2516                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2517                         printf("%sUG", comma ? "," : "");
2518                         comma = 1;
2519                 }
2520                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2521                         printf("%sVPID", comma ? "," : "");
2522                         comma = 1;
2523                 }
2524                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2525                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2526                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2527                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2528                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2529                         printf("%sVID", comma ? "," : "");
2530                         comma = 1;
2531                         if (pin & PINBASED_POSTED_INTERRUPT)
2532                                 printf(",PostIntr");
2533                 }
2534                 return;
2535         }
2536
2537         mask = basic >> 32;
2538         printf("Basic Features=0x%b", mask,
2539         "\020"
2540         "\02132PA"              /* 32-bit physical addresses */
2541         "\022SMM"               /* SMM dual-monitor */
2542         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2543         "\030TRUE"              /* TRUE_CTLS MSRs */
2544         );
2545         printf("\n        Pin-Based Controls=0x%b", pin,
2546         "\020"
2547         "\001ExtINT"            /* External-interrupt exiting */
2548         "\004NMI"               /* NMI exiting */
2549         "\006VNMI"              /* Virtual NMIs */
2550         "\007PreTmr"            /* Activate VMX-preemption timer */
2551         "\010PostIntr"          /* Process posted interrupts */
2552         );
2553         printf("\n        Primary Processor Controls=0x%b", proc,
2554         "\020"
2555         "\003INTWIN"            /* Interrupt-window exiting */
2556         "\004TSCOff"            /* Use TSC offsetting */
2557         "\010HLT"               /* HLT exiting */
2558         "\012INVLPG"            /* INVLPG exiting */
2559         "\013MWAIT"             /* MWAIT exiting */
2560         "\014RDPMC"             /* RDPMC exiting */
2561         "\015RDTSC"             /* RDTSC exiting */
2562         "\020CR3-LD"            /* CR3-load exiting */
2563         "\021CR3-ST"            /* CR3-store exiting */
2564         "\024CR8-LD"            /* CR8-load exiting */
2565         "\025CR8-ST"            /* CR8-store exiting */
2566         "\026TPR"               /* Use TPR shadow */
2567         "\027NMIWIN"            /* NMI-window exiting */
2568         "\030MOV-DR"            /* MOV-DR exiting */
2569         "\031IO"                /* Unconditional I/O exiting */
2570         "\032IOmap"             /* Use I/O bitmaps */
2571         "\034MTF"               /* Monitor trap flag */
2572         "\035MSRmap"            /* Use MSR bitmaps */
2573         "\036MONITOR"           /* MONITOR exiting */
2574         "\037PAUSE"             /* PAUSE exiting */
2575         );
2576         if (proc & PROCBASED_SECONDARY_CONTROLS)
2577                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2578                 "\020"
2579                 "\001APIC"              /* Virtualize APIC accesses */
2580                 "\002EPT"               /* Enable EPT */
2581                 "\003DT"                /* Descriptor-table exiting */
2582                 "\004RDTSCP"            /* Enable RDTSCP */
2583                 "\005x2APIC"            /* Virtualize x2APIC mode */
2584                 "\006VPID"              /* Enable VPID */
2585                 "\007WBINVD"            /* WBINVD exiting */
2586                 "\010UG"                /* Unrestricted guest */
2587                 "\011APIC-reg"          /* APIC-register virtualization */
2588                 "\012VID"               /* Virtual-interrupt delivery */
2589                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2590                 "\014RDRAND"            /* RDRAND exiting */
2591                 "\015INVPCID"           /* Enable INVPCID */
2592                 "\016VMFUNC"            /* Enable VM functions */
2593                 "\017VMCS"              /* VMCS shadowing */
2594                 "\020EPT#VE"            /* EPT-violation #VE */
2595                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2596                 );
2597         printf("\n        Exit Controls=0x%b", mask,
2598         "\020"
2599         "\003DR"                /* Save debug controls */
2600                                 /* Ignore Host address-space size */
2601         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2602         "\020AckInt"            /* Acknowledge interrupt on exit */
2603         "\023PAT-SV"            /* Save MSR_PAT */
2604         "\024PAT-LD"            /* Load MSR_PAT */
2605         "\025EFER-SV"           /* Save MSR_EFER */
2606         "\026EFER-LD"           /* Load MSR_EFER */
2607         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2608         );
2609         printf("\n        Entry Controls=0x%b", mask,
2610         "\020"
2611         "\003DR"                /* Save debug controls */
2612                                 /* Ignore IA-32e mode guest */
2613                                 /* Ignore Entry to SMM */
2614                                 /* Ignore Deactivate dual-monitor treatment */
2615         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2616         "\017PAT"               /* Load MSR_PAT */
2617         "\020EFER"              /* Load MSR_EFER */
2618         );
2619         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2620             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2621                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2622                 mask = msr;
2623                 printf("\n        EPT Features=0x%b", mask,
2624                 "\020"
2625                 "\001XO"                /* Execute-only translations */
2626                 "\007PW4"               /* Page-walk length of 4 */
2627                 "\011UC"                /* EPT paging-structure mem can be UC */
2628                 "\017WB"                /* EPT paging-structure mem can be WB */
2629                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2630                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2631                 "\025INVEPT"            /* INVEPT is supported */
2632                 "\026AD"                /* Accessed and dirty flags for EPT */
2633                 "\032single"            /* INVEPT single-context type */
2634                 "\033all"               /* INVEPT all-context type */
2635                 );
2636                 mask = msr >> 32;
2637                 printf("\n        VPID Features=0x%b", mask,
2638                 "\020"
2639                 "\001INVVPID"           /* INVVPID is supported */
2640                 "\011individual"        /* INVVPID individual-address type */
2641                 "\012single"            /* INVVPID single-context type */
2642                 "\013all"               /* INVVPID all-context type */
2643                  /* INVVPID single-context-retaining-globals type */
2644                 "\014single-globals"
2645                 );
2646         }
2647 }
2648
2649 static void
2650 print_hypervisor_info(void)
2651 {
2652
2653         if (*hv_vendor != '\0')
2654                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2655 }
2656
2657 /*
2658  * Returns the maximum physical address that can be used with the
2659  * current system.
2660  */
2661 vm_paddr_t
2662 cpu_getmaxphyaddr(void)
2663 {
2664
2665 #if defined(__i386__)
2666         if (!pae_mode)
2667                 return (0xffffffff);
2668 #endif
2669         return ((1ULL << cpu_maxphyaddr) - 1);
2670 }