sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   amd_extended_feature_extensions;
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 u_int   cpu_fxsr;               /* SSE enabled */
 107 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 108 u_int   cpu_clflush_line_size = 32;
 109 u_int   cpu_stdext_feature;     /* %ebx */
 110 u_int   cpu_stdext_feature2;    /* %ecx */
 111 u_int   cpu_stdext_feature3;    /* %edx */
 112 uint64_t cpu_ia32_arch_caps;
 113 u_int   cpu_max_ext_state_size;
 114 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 115 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 116 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 117 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 118 char machine[] = MACHINE;
 119
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 121     &via_feature_rng, 0,
 122     "VIA RNG feature available in CPU");
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 124     &via_feature_xcrypt, 0,
 125     "VIA xcrypt feature available in CPU");
 126
 127 #ifdef __amd64__
 128 #ifdef SCTL_MASK32
 129 extern int adaptive_machine_arch;
 130 #endif
 131
 132 static int
 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 134 {
 135 #ifdef SCTL_MASK32
 136         static const char machine32[] = "i386";
 137 #endif
 138         int error;
 139
 140 #ifdef SCTL_MASK32
 141         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 142                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 143         else
 144 #endif
 145                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 146         return (error);
 147
 148 }
 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 150     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 151 #else
 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 153     machine, 0, "Machine class");
 154 #endif
 155
 156 static char cpu_model[128];
 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 158     cpu_model, 0, "Machine model");
 159
 160 static int hw_clockrate;
 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 162     &hw_clockrate, 0, "CPU instruction clock rate");
 163
 164 u_int hv_high;
 165 char hv_vendor[16];
 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 167     0, "Hypervisor vendor");
 168
 169 static eventhandler_tag tsc_post_tag;
 170
 171 static char cpu_brand[48];
 172
 173 #ifdef __i386__
 174 #define MAX_BRAND_INDEX 8
 175
 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 177         NULL,                   /* No brand */
 178         "Intel Celeron",
 179         "Intel Pentium III",
 180         "Intel Pentium III Xeon",
 181         NULL,
 182         NULL,
 183         NULL,
 184         NULL,
 185         "Intel Pentium 4"
 186 };
 187
 188 static struct {
 189         char    *cpu_name;
 190         int     cpu_class;
 191 } cpus[] = {
 192         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 193         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 194         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 195         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 196         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 197         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 198         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 199         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 200         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 201         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 202         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 203         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 204         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 205         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 206         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 207         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 208         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 209 };
 210 #endif
 211
 212 static struct {
 213         char    *vendor;
 214         u_int   vendor_id;
 215 } cpu_vendors[] = {
 216         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 217         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 218         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 219 #ifdef __i386__
 220         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 221         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 222         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 223         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 224         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 225         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 226         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 227 #if 0
 228         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 229         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 230 #endif
 231 #endif
 232 };
 233
 234 void
 235 printcpuinfo(void)
 236 {
 237         u_int regs[4], i;
 238         char *brand;
 239
 240         printf("CPU: ");
 241 #ifdef __i386__
 242         cpu_class = cpus[cpu].cpu_class;
 243         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 244 #else
 245         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 246 #endif
 247
 248         /* Check for extended CPUID information and a processor name. */
 249         if (cpu_exthigh >= 0x80000004) {
 250                 brand = cpu_brand;
 251                 for (i = 0x80000002; i < 0x80000005; i++) {
 252                         do_cpuid(i, regs);
 253                         memcpy(brand, regs, sizeof(regs));
 254                         brand += sizeof(regs);
 255                 }
 256         }
 257
 258         switch (cpu_vendor_id) {
 259         case CPU_VENDOR_INTEL:
 260 #ifdef __i386__
 261                 if ((cpu_id & 0xf00) > 0x300) {
 262                         u_int brand_index;
 263
 264                         cpu_model[0] = '\0';
 265
 266                         switch (cpu_id & 0x3000) {
 267                         case 0x1000:
 268                                 strcpy(cpu_model, "Overdrive ");
 269                                 break;
 270                         case 0x2000:
 271                                 strcpy(cpu_model, "Dual ");
 272                                 break;
 273                         }
 274
 275                         switch (cpu_id & 0xf00) {
 276                         case 0x400:
 277                                 strcat(cpu_model, "i486 ");
 278                                 /* Check the particular flavor of 486 */
 279                                 switch (cpu_id & 0xf0) {
 280                                 case 0x00:
 281                                 case 0x10:
 282                                         strcat(cpu_model, "DX");
 283                                         break;
 284                                 case 0x20:
 285                                         strcat(cpu_model, "SX");
 286                                         break;
 287                                 case 0x30:
 288                                         strcat(cpu_model, "DX2");
 289                                         break;
 290                                 case 0x40:
 291                                         strcat(cpu_model, "SL");
 292                                         break;
 293                                 case 0x50:
 294                                         strcat(cpu_model, "SX2");
 295                                         break;
 296                                 case 0x70:
 297                                         strcat(cpu_model,
 298                                             "DX2 Write-Back Enhanced");
 299                                         break;
 300                                 case 0x80:
 301                                         strcat(cpu_model, "DX4");
 302                                         break;
 303                                 }
 304                                 break;
 305                         case 0x500:
 306                                 /* Check the particular flavor of 586 */
 307                                 strcat(cpu_model, "Pentium");
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, " A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "/P5");
 314                                         break;
 315                                 case 0x20:
 316                                         strcat(cpu_model, "/P54C");
 317                                         break;
 318                                 case 0x30:
 319                                         strcat(cpu_model, "/P24T");
 320                                         break;
 321                                 case 0x40:
 322                                         strcat(cpu_model, "/P55C");
 323                                         break;
 324                                 case 0x70:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x80:
 328                                         strcat(cpu_model, "/P55C (quarter-micron)");
 329                                         break;
 330                                 default:
 331                                         /* nothing */
 332                                         break;
 333                                 }
 334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 335                                 /*
 336                                  * XXX - If/when Intel fixes the bug, this
 337                                  * should also check the version of the
 338                                  * CPU, not just that it's a Pentium.
 339                                  */
 340                                 has_f00f_bug = 1;
 341 #endif
 342                                 break;
 343                         case 0x600:
 344                                 /* Check the particular flavor of 686 */
 345                                 switch (cpu_id & 0xf0) {
 346                                 case 0x00:
 347                                         strcat(cpu_model, "Pentium Pro A-step");
 348                                         break;
 349                                 case 0x10:
 350                                         strcat(cpu_model, "Pentium Pro");
 351                                         break;
 352                                 case 0x30:
 353                                 case 0x50:
 354                                 case 0x60:
 355                                         strcat(cpu_model,
 356                                 "Pentium II/Pentium II Xeon/Celeron");
 357                                         cpu = CPU_PII;
 358                                         break;
 359                                 case 0x70:
 360                                 case 0x80:
 361                                 case 0xa0:
 362                                 case 0xb0:
 363                                         strcat(cpu_model,
 364                                         "Pentium III/Pentium III Xeon/Celeron");
 365                                         cpu = CPU_PIII;
 366                                         break;
 367                                 default:
 368                                         strcat(cpu_model, "Unknown 80686");
 369                                         break;
 370                                 }
 371                                 break;
 372                         case 0xf00:
 373                                 strcat(cpu_model, "Pentium 4");
 374                                 cpu = CPU_P4;
 375                                 break;
 376                         default:
 377                                 strcat(cpu_model, "unknown");
 378                                 break;
 379                         }
 380
 381                         /*
 382                          * If we didn't get a brand name from the extended
 383                          * CPUID, try to look it up in the brand table.
 384                          */
 385                         if (cpu_high > 0 && *cpu_brand == '\0') {
 386                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 387                                 if (brand_index <= MAX_BRAND_INDEX &&
 388                                     cpu_brandtable[brand_index] != NULL)
 389                                         strcpy(cpu_brand,
 390                                             cpu_brandtable[brand_index]);
 391                         }
 392                 }
 393 #else
 394                 /* Please make up your mind folks! */
 395                 strcat(cpu_model, "EM64T");
 396 #endif
 397                 break;
 398         case CPU_VENDOR_AMD:
 399                 /*
 400                  * Values taken from AMD Processor Recognition
 401                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 402                  * (also describes ``Features'' encodings.
 403                  */
 404                 strcpy(cpu_model, "AMD ");
 405 #ifdef __i386__
 406                 switch (cpu_id & 0xFF0) {
 407                 case 0x410:
 408                         strcat(cpu_model, "Standard Am486DX");
 409                         break;
 410                 case 0x430:
 411                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 412                         break;
 413                 case 0x470:
 414                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 415                         break;
 416                 case 0x480:
 417                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 418                         break;
 419                 case 0x490:
 420                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 421                         break;
 422                 case 0x4E0:
 423                         strcat(cpu_model, "Am5x86 Write-Through");
 424                         break;
 425                 case 0x4F0:
 426                         strcat(cpu_model, "Am5x86 Write-Back");
 427                         break;
 428                 case 0x500:
 429                         strcat(cpu_model, "K5 model 0");
 430                         break;
 431                 case 0x510:
 432                         strcat(cpu_model, "K5 model 1");
 433                         break;
 434                 case 0x520:
 435                         strcat(cpu_model, "K5 PR166 (model 2)");
 436                         break;
 437                 case 0x530:
 438                         strcat(cpu_model, "K5 PR200 (model 3)");
 439                         break;
 440                 case 0x560:
 441                         strcat(cpu_model, "K6");
 442                         break;
 443                 case 0x570:
 444                         strcat(cpu_model, "K6 266 (model 1)");
 445                         break;
 446                 case 0x580:
 447                         strcat(cpu_model, "K6-2");
 448                         break;
 449                 case 0x590:
 450                         strcat(cpu_model, "K6-III");
 451                         break;
 452                 case 0x5a0:
 453                         strcat(cpu_model, "Geode LX");
 454                         break;
 455                 default:
 456                         strcat(cpu_model, "Unknown");
 457                         break;
 458                 }
 459 #else
 460                 if ((cpu_id & 0xf00) == 0xf00)
 461                         strcat(cpu_model, "AMD64 Processor");
 462                 else
 463                         strcat(cpu_model, "Unknown");
 464 #endif
 465                 break;
 466 #ifdef __i386__
 467         case CPU_VENDOR_CYRIX:
 468                 strcpy(cpu_model, "Cyrix ");
 469                 switch (cpu_id & 0xff0) {
 470                 case 0x440:
 471                         strcat(cpu_model, "MediaGX");
 472                         break;
 473                 case 0x520:
 474                         strcat(cpu_model, "6x86");
 475                         break;
 476                 case 0x540:
 477                         cpu_class = CPUCLASS_586;
 478                         strcat(cpu_model, "GXm");
 479                         break;
 480                 case 0x600:
 481                         strcat(cpu_model, "6x86MX");
 482                         break;
 483                 default:
 484                         /*
 485                          * Even though CPU supports the cpuid
 486                          * instruction, it can be disabled.
 487                          * Therefore, this routine supports all Cyrix
 488                          * CPUs.
 489                          */
 490                         switch (cyrix_did & 0xf0) {
 491                         case 0x00:
 492                                 switch (cyrix_did & 0x0f) {
 493                                 case 0x00:
 494                                         strcat(cpu_model, "486SLC");
 495                                         break;
 496                                 case 0x01:
 497                                         strcat(cpu_model, "486DLC");
 498                                         break;
 499                                 case 0x02:
 500                                         strcat(cpu_model, "486SLC2");
 501                                         break;
 502                                 case 0x03:
 503                                         strcat(cpu_model, "486DLC2");
 504                                         break;
 505                                 case 0x04:
 506                                         strcat(cpu_model, "486SRx");
 507                                         break;
 508                                 case 0x05:
 509                                         strcat(cpu_model, "486DRx");
 510                                         break;
 511                                 case 0x06:
 512                                         strcat(cpu_model, "486SRx2");
 513                                         break;
 514                                 case 0x07:
 515                                         strcat(cpu_model, "486DRx2");
 516                                         break;
 517                                 case 0x08:
 518                                         strcat(cpu_model, "486SRu");
 519                                         break;
 520                                 case 0x09:
 521                                         strcat(cpu_model, "486DRu");
 522                                         break;
 523                                 case 0x0a:
 524                                         strcat(cpu_model, "486SRu2");
 525                                         break;
 526                                 case 0x0b:
 527                                         strcat(cpu_model, "486DRu2");
 528                                         break;
 529                                 default:
 530                                         strcat(cpu_model, "Unknown");
 531                                         break;
 532                                 }
 533                                 break;
 534                         case 0x10:
 535                                 switch (cyrix_did & 0x0f) {
 536                                 case 0x00:
 537                                         strcat(cpu_model, "486S");
 538                                         break;
 539                                 case 0x01:
 540                                         strcat(cpu_model, "486S2");
 541                                         break;
 542                                 case 0x02:
 543                                         strcat(cpu_model, "486Se");
 544                                         break;
 545                                 case 0x03:
 546                                         strcat(cpu_model, "486S2e");
 547                                         break;
 548                                 case 0x0a:
 549                                         strcat(cpu_model, "486DX");
 550                                         break;
 551                                 case 0x0b:
 552                                         strcat(cpu_model, "486DX2");
 553                                         break;
 554                                 case 0x0f:
 555                                         strcat(cpu_model, "486DX4");
 556                                         break;
 557                                 default:
 558                                         strcat(cpu_model, "Unknown");
 559                                         break;
 560                                 }
 561                                 break;
 562                         case 0x20:
 563                                 if ((cyrix_did & 0x0f) < 8)
 564                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 565                                 else
 566                                         strcat(cpu_model, "5x86");
 567                                 break;
 568                         case 0x30:
 569                                 strcat(cpu_model, "6x86");
 570                                 break;
 571                         case 0x40:
 572                                 if ((cyrix_did & 0xf000) == 0x3000) {
 573                                         cpu_class = CPUCLASS_586;
 574                                         strcat(cpu_model, "GXm");
 575                                 } else
 576                                         strcat(cpu_model, "MediaGX");
 577                                 break;
 578                         case 0x50:
 579                                 strcat(cpu_model, "6x86MX");
 580                                 break;
 581                         case 0xf0:
 582                                 switch (cyrix_did & 0x0f) {
 583                                 case 0x0d:
 584                                         strcat(cpu_model, "Overdrive CPU");
 585                                         break;
 586                                 case 0x0e:
 587                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 588                                         break;
 589                                 case 0x0f:
 590                                         strcat(cpu_model, "486SLC/DLC");
 591                                         break;
 592                                 default:
 593                                         strcat(cpu_model, "Unknown");
 594                                         break;
 595                                 }
 596                                 break;
 597                         default:
 598                                 strcat(cpu_model, "Unknown");
 599                                 break;
 600                         }
 601                         break;
 602                 }
 603                 break;
 604         case CPU_VENDOR_RISE:
 605                 strcpy(cpu_model, "Rise ");
 606                 switch (cpu_id & 0xff0) {
 607                 case 0x500:     /* 6401 and 6441 (Kirin) */
 608                 case 0x520:     /* 6510 (Lynx) */
 609                         strcat(cpu_model, "mP6");
 610                         break;
 611                 default:
 612                         strcat(cpu_model, "Unknown");
 613                 }
 614                 break;
 615 #endif
 616         case CPU_VENDOR_CENTAUR:
 617 #ifdef __i386__
 618                 switch (cpu_id & 0xff0) {
 619                 case 0x540:
 620                         strcpy(cpu_model, "IDT WinChip C6");
 621                         break;
 622                 case 0x580:
 623                         strcpy(cpu_model, "IDT WinChip 2");
 624                         break;
 625                 case 0x590:
 626                         strcpy(cpu_model, "IDT WinChip 3");
 627                         break;
 628                 case 0x660:
 629                         strcpy(cpu_model, "VIA C3 Samuel");
 630                         break;
 631                 case 0x670:
 632                         if (cpu_id & 0x8)
 633                                 strcpy(cpu_model, "VIA C3 Ezra");
 634                         else
 635                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 636                         break;
 637                 case 0x680:
 638                         strcpy(cpu_model, "VIA C3 Ezra-T");
 639                         break;
 640                 case 0x690:
 641                         strcpy(cpu_model, "VIA C3 Nehemiah");
 642                         break;
 643                 case 0x6a0:
 644                 case 0x6d0:
 645                         strcpy(cpu_model, "VIA C7 Esther");
 646                         break;
 647                 case 0x6f0:
 648                         strcpy(cpu_model, "VIA Nano");
 649                         break;
 650                 default:
 651                         strcpy(cpu_model, "VIA/IDT Unknown");
 652                 }
 653 #else
 654                 strcpy(cpu_model, "VIA ");
 655                 if ((cpu_id & 0xff0) == 0x6f0)
 656                         strcat(cpu_model, "Nano Processor");
 657                 else
 658                         strcat(cpu_model, "Unknown");
 659 #endif
 660                 break;
 661 #ifdef __i386__
 662         case CPU_VENDOR_IBM:
 663                 strcpy(cpu_model, "Blue Lightning CPU");
 664                 break;
 665         case CPU_VENDOR_NSC:
 666                 switch (cpu_id & 0xff0) {
 667                 case 0x540:
 668                         strcpy(cpu_model, "Geode SC1100");
 669                         cpu = CPU_GEODE1100;
 670                         break;
 671                 default:
 672                         strcpy(cpu_model, "Geode/NSC unknown");
 673                         break;
 674                 }
 675                 break;
 676 #endif
 677         default:
 678                 strcat(cpu_model, "Unknown");
 679                 break;
 680         }
 681
 682         /*
 683          * Replace cpu_model with cpu_brand minus leading spaces if
 684          * we have one.
 685          */
 686         brand = cpu_brand;
 687         while (*brand == ' ')
 688                 ++brand;
 689         if (*brand != '\0')
 690                 strcpy(cpu_model, brand);
 691
 692         printf("%s (", cpu_model);
 693         if (tsc_freq != 0) {
 694                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 695                 printf("%jd.%02d-MHz ",
 696                     (intmax_t)(tsc_freq + 4999) / 1000000,
 697                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 698         }
 699 #ifdef __i386__
 700         switch(cpu_class) {
 701         case CPUCLASS_286:
 702                 printf("286");
 703                 break;
 704         case CPUCLASS_386:
 705                 printf("386");
 706                 break;
 707 #if defined(I486_CPU)
 708         case CPUCLASS_486:
 709                 printf("486");
 710                 break;
 711 #endif
 712 #if defined(I586_CPU)
 713         case CPUCLASS_586:
 714                 printf("586");
 715                 break;
 716 #endif
 717 #if defined(I686_CPU)
 718         case CPUCLASS_686:
 719                 printf("686");
 720                 break;
 721 #endif
 722         default:
 723                 printf("Unknown");      /* will panic below... */
 724         }
 725 #else
 726         printf("K8");
 727 #endif
 728         printf("-class CPU)\n");
 729         if (*cpu_vendor)
 730                 printf("  Origin=\"%s\"", cpu_vendor);
 731         if (cpu_id)
 732                 printf("  Id=0x%x", cpu_id);
 733
 734         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 735             cpu_vendor_id == CPU_VENDOR_AMD ||
 736             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 737 #ifdef __i386__
 738             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 739             cpu_vendor_id == CPU_VENDOR_RISE ||
 740             cpu_vendor_id == CPU_VENDOR_NSC ||
 741             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 742 #endif
 743             0) {
 744                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 745                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 746                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 747 #ifdef __i386__
 748                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 749                         printf("\n  DIR=0x%04x", cyrix_did);
 750 #endif
 751
 752                 /*
 753                  * AMD CPUID Specification
 754                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 755                  *
 756                  * Intel Processor Identification and CPUID Instruction
 757                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 758                  */
 759                 if (cpu_high > 0) {
 760
 761                         /*
 762                          * Here we should probably set up flags indicating
 763                          * whether or not various features are available.
 764                          * The interesting ones are probably VME, PSE, PAE,
 765                          * and PGE.  The code already assumes without bothering
 766                          * to check that all CPUs >= Pentium have a TSC and
 767                          * MSRs.
 768                          */
 769                         printf("\n  Features=0x%b", cpu_feature,
 770                         "\020"
 771                         "\001FPU"       /* Integral FPU */
 772                         "\002VME"       /* Extended VM86 mode support */
 773                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 774                         "\004PSE"       /* 4MByte page tables */
 775                         "\005TSC"       /* Timestamp counter */
 776                         "\006MSR"       /* Machine specific registers */
 777                         "\007PAE"       /* Physical address extension */
 778                         "\010MCE"       /* Machine Check support */
 779                         "\011CX8"       /* CMPEXCH8 instruction */
 780                         "\012APIC"      /* SMP local APIC */
 781                         "\013oldMTRR"   /* Previous implementation of MTRR */
 782                         "\014SEP"       /* Fast System Call */
 783                         "\015MTRR"      /* Memory Type Range Registers */
 784                         "\016PGE"       /* PG_G (global bit) support */
 785                         "\017MCA"       /* Machine Check Architecture */
 786                         "\020CMOV"      /* CMOV instruction */
 787                         "\021PAT"       /* Page attributes table */
 788                         "\022PSE36"     /* 36 bit address space support */
 789                         "\023PN"        /* Processor Serial number */
 790                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 791                         "\025<b20>"
 792                         "\026DTS"       /* Debug Trace Store */
 793                         "\027ACPI"      /* ACPI support */
 794                         "\030MMX"       /* MMX instructions */
 795                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 796                         "\032SSE"       /* Streaming SIMD Extensions */
 797                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 798                         "\034SS"        /* Self snoop */
 799                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 800                         "\036TM"        /* Thermal Monitor clock slowdown */
 801                         "\037IA64"      /* CPU can execute IA64 instructions */
 802                         "\040PBE"       /* Pending Break Enable */
 803                         );
 804
 805                         if (cpu_feature2 != 0) {
 806                                 printf("\n  Features2=0x%b", cpu_feature2,
 807                                 "\020"
 808                                 "\001SSE3"      /* SSE3 */
 809                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 810                                 "\003DTES64"    /* 64-bit Debug Trace */
 811                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 812                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 813                                 "\006VMX"       /* Virtual Machine Extensions */
 814                                 "\007SMX"       /* Safer Mode Extensions */
 815                                 "\010EST"       /* Enhanced SpeedStep */
 816                                 "\011TM2"       /* Thermal Monitor 2 */
 817                                 "\012SSSE3"     /* SSSE3 */
 818                                 "\013CNXT-ID"   /* L1 context ID available */
 819                                 "\014SDBG"      /* IA32 silicon debug */
 820                                 "\015FMA"       /* Fused Multiply Add */
 821                                 "\016CX16"      /* CMPXCHG16B Instruction */
 822                                 "\017xTPR"      /* Send Task Priority Messages*/
 823                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 824                                 "\021<b16>"
 825                                 "\022PCID"      /* Process-context Identifiers*/
 826                                 "\023DCA"       /* Direct Cache Access */
 827                                 "\024SSE4.1"    /* SSE 4.1 */
 828                                 "\025SSE4.2"    /* SSE 4.2 */
 829                                 "\026x2APIC"    /* xAPIC Extensions */
 830                                 "\027MOVBE"     /* MOVBE Instruction */
 831                                 "\030POPCNT"    /* POPCNT Instruction */
 832                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 833                                 "\032AESNI"     /* AES Crypto */
 834                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 835                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 836                                 "\035AVX"       /* Advanced Vector Extensions */
 837                                 "\036F16C"      /* Half-precision conversions */
 838                                 "\037RDRAND"    /* RDRAND Instruction */
 839                                 "\040HV"        /* Hypervisor */
 840                                 );
 841                         }
 842
 843                         if (amd_feature != 0) {
 844                                 printf("\n  AMD Features=0x%b", amd_feature,
 845                                 "\020"          /* in hex */
 846                                 "\001<s0>"      /* Same */
 847                                 "\002<s1>"      /* Same */
 848                                 "\003<s2>"      /* Same */
 849                                 "\004<s3>"      /* Same */
 850                                 "\005<s4>"      /* Same */
 851                                 "\006<s5>"      /* Same */
 852                                 "\007<s6>"      /* Same */
 853                                 "\010<s7>"      /* Same */
 854                                 "\011<s8>"      /* Same */
 855                                 "\012<s9>"      /* Same */
 856                                 "\013<b10>"     /* Undefined */
 857                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 858                                 "\015<s12>"     /* Same */
 859                                 "\016<s13>"     /* Same */
 860                                 "\017<s14>"     /* Same */
 861                                 "\020<s15>"     /* Same */
 862                                 "\021<s16>"     /* Same */
 863                                 "\022<s17>"     /* Same */
 864                                 "\023<b18>"     /* Reserved, unknown */
 865                                 "\024MP"        /* Multiprocessor Capable */
 866                                 "\025NX"        /* Has EFER.NXE, NX */
 867                                 "\026<b21>"     /* Undefined */
 868                                 "\027MMX+"      /* AMD MMX Extensions */
 869                                 "\030<s23>"     /* Same */
 870                                 "\031<s24>"     /* Same */
 871                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 872                                 "\033Page1GB"   /* 1-GB large page support */
 873                                 "\034RDTSCP"    /* RDTSCP */
 874                                 "\035<b28>"     /* Undefined */
 875                                 "\036LM"        /* 64 bit long mode */
 876                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 877                                 "\0403DNow!"    /* AMD 3DNow! */
 878                                 );
 879                         }
 880
 881                         if (amd_feature2 != 0) {
 882                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 883                                 "\020"
 884                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 885                                 "\002CMP"       /* CMP legacy */
 886                                 "\003SVM"       /* Secure Virtual Mode */
 887                                 "\004ExtAPIC"   /* Extended APIC register */
 888                                 "\005CR8"       /* CR8 in legacy mode */
 889                                 "\006ABM"       /* LZCNT instruction */
 890                                 "\007SSE4A"     /* SSE4A */
 891                                 "\010MAS"       /* Misaligned SSE mode */
 892                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 893                                 "\012OSVW"      /* OS visible workaround */
 894                                 "\013IBS"       /* Instruction based sampling */
 895                                 "\014XOP"       /* XOP extended instructions */
 896                                 "\015SKINIT"    /* SKINIT/STGI */
 897                                 "\016WDT"       /* Watchdog timer */
 898                                 "\017<b14>"
 899                                 "\020LWP"       /* Lightweight Profiling */
 900                                 "\021FMA4"      /* 4-operand FMA instructions */
 901                                 "\022TCE"       /* Translation Cache Extension */
 902                                 "\023<b18>"
 903                                 "\024NodeId"    /* NodeId MSR support */
 904                                 "\025<b20>"
 905                                 "\026TBM"       /* Trailing Bit Manipulation */
 906                                 "\027Topology"  /* Topology Extensions */
 907                                 "\030PCXC"      /* Core perf count */
 908                                 "\031PNXC"      /* NB perf count */
 909                                 "\032<b25>"
 910                                 "\033DBE"       /* Data Breakpoint extension */
 911                                 "\034PTSC"      /* Performance TSC */
 912                                 "\035PL2I"      /* L2I perf count */
 913                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 914                                 "\037<b30>"
 915                                 "\040<b31>"
 916                                 );
 917                         }
 918
 919                         if (cpu_stdext_feature != 0) {
 920                                 printf("\n  Structured Extended Features=0x%b",
 921                                     cpu_stdext_feature,
 922                                        "\020"
 923                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 924                                        "\001FSGSBASE"
 925                                        "\002TSCADJ"
 926                                        "\003SGX"
 927                                        /* Bit Manipulation Instructions */
 928                                        "\004BMI1"
 929                                        /* Hardware Lock Elision */
 930                                        "\005HLE"
 931                                        /* Advanced Vector Instructions 2 */
 932                                        "\006AVX2"
 933                                        /* FDP_EXCPTN_ONLY */
 934                                        "\007FDPEXC"
 935                                        /* Supervisor Mode Execution Prot. */
 936                                        "\010SMEP"
 937                                        /* Bit Manipulation Instructions */
 938                                        "\011BMI2"
 939                                        "\012ERMS"
 940                                        /* Invalidate Processor Context ID */
 941                                        "\013INVPCID"
 942                                        /* Restricted Transactional Memory */
 943                                        "\014RTM"
 944                                        "\015PQM"
 945                                        "\016NFPUSG"
 946                                        /* Intel Memory Protection Extensions */
 947                                        "\017MPX"
 948                                        "\020PQE"
 949                                        /* AVX512 Foundation */
 950                                        "\021AVX512F"
 951                                        "\022AVX512DQ"
 952                                        /* Enhanced NRBG */
 953                                        "\023RDSEED"
 954                                        /* ADCX + ADOX */
 955                                        "\024ADX"
 956                                        /* Supervisor Mode Access Prevention */
 957                                        "\025SMAP"
 958                                        "\026AVX512IFMA"
 959                                        "\027PCOMMIT"
 960                                        "\030CLFLUSHOPT"
 961                                        "\031CLWB"
 962                                        "\032PROCTRACE"
 963                                        "\033AVX512PF"
 964                                        "\034AVX512ER"
 965                                        "\035AVX512CD"
 966                                        "\036SHA"
 967                                        "\037AVX512BW"
 968                                        "\040AVX512VL"
 969                                        );
 970                         }
 971
 972                         if (cpu_stdext_feature2 != 0) {
 973                                 printf("\n  Structured Extended Features2=0x%b",
 974                                     cpu_stdext_feature2,
 975                                        "\020"
 976                                        "\001PREFETCHWT1"
 977                                        "\002AVX512VBMI"
 978                                        "\003UMIP"
 979                                        "\004PKU"
 980                                        "\005OSPKE"
 981                                        "\027RDPID"
 982                                        "\037SGXLC"
 983                                        );
 984                         }
 985
 986                         if (cpu_stdext_feature3 != 0) {
 987                                 printf("\n  Structured Extended Features3=0x%b",
 988                                     cpu_stdext_feature3,
 989                                        "\020"
 990                                        "\033IBPB"
 991                                        "\034STIBP"
 992                                        "\035L1DFL"
 993                                        "\036ARCH_CAP"
 994                                        "\040SSBD"
 995                                        );
 996                         }
 997
 998                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 999                                 cpuid_count(0xd, 0x1, regs);
1000                                 if (regs[0] != 0) {
1001                                         printf("\n  XSAVE Features=0x%b",
1002                                             regs[0],
1003                                             "\020"
1004                                             "\001XSAVEOPT"
1005                                             "\002XSAVEC"
1006                                             "\003XINUSE"
1007                                             "\004XSAVES");
1008                                 }
1009                         }
1010
1011                         if (cpu_ia32_arch_caps != 0) {
1012                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1013                                     (u_int)cpu_ia32_arch_caps,
1014                                        "\020"
1015                                        "\001RDCL_NO"
1016                                        "\002IBRS_ALL"
1017                                        );
1018                         }
1019
1020                         if (amd_extended_feature_extensions != 0) {
1021                                 printf("\n  "
1022                                     "AMD Extended Feature Extensions ID EBX="
1023                                     "0x%b", amd_extended_feature_extensions,
1024                                     "\020"
1025                                     "\001CLZERO"
1026                                     "\002IRPerf"
1027                                     "\003XSaveErPtr");
1028                         }
1029
1030                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1031                                 print_via_padlock_info();
1032
1033                         if (cpu_feature2 & CPUID2_VMX)
1034                                 print_vmx_info();
1035
1036                         if (amd_feature2 & AMDID2_SVM)
1037                                 print_svm_info();
1038
1039                         if ((cpu_feature & CPUID_HTT) &&
1040                             cpu_vendor_id == CPU_VENDOR_AMD)
1041                                 cpu_feature &= ~CPUID_HTT;
1042
1043                         /*
1044                          * If this CPU supports P-state invariant TSC then
1045                          * mention the capability.
1046                          */
1047                         if (tsc_is_invariant) {
1048                                 printf("\n  TSC: P-state invariant");
1049                                 if (tsc_perf_stat)
1050                                         printf(", performance statistics");
1051                         }
1052                 }
1053 #ifdef __i386__
1054         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1055                 printf("  DIR=0x%04x", cyrix_did);
1056                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1057                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1058 #ifndef CYRIX_CACHE_REALLY_WORKS
1059                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1060                         printf("\n  CPU cache: write-through mode");
1061 #endif
1062 #endif
1063         }
1064
1065         /* Avoid ugly blank lines: only print newline when we have to. */
1066         if (*cpu_vendor || cpu_id)
1067                 printf("\n");
1068
1069         if (bootverbose) {
1070                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1071                         print_AMD_info();
1072                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1073                         print_INTEL_info();
1074 #ifdef __i386__
1075                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1076                         print_transmeta_info();
1077 #endif
1078         }
1079
1080         print_hypervisor_info();
1081 }
1082
1083 #ifdef __i386__
1084 void
1085 panicifcpuunsupported(void)
1086 {
1087
1088 #if !defined(lint)
1089 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1090 #error This kernel is not configured for one of the supported CPUs
1091 #endif
1092 #else /* lint */
1093 #endif /* lint */
1094         /*
1095          * Now that we have told the user what they have,
1096          * let them know if that machine type isn't configured.
1097          */
1098         switch (cpu_class) {
1099         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1100         case CPUCLASS_386:
1101 #if !defined(I486_CPU)
1102         case CPUCLASS_486:
1103 #endif
1104 #if !defined(I586_CPU)
1105         case CPUCLASS_586:
1106 #endif
1107 #if !defined(I686_CPU)
1108         case CPUCLASS_686:
1109 #endif
1110                 panic("CPU class not configured");
1111         default:
1112                 break;
1113         }
1114 }
1115
1116 static  volatile u_int trap_by_rdmsr;
1117
1118 /*
1119  * Special exception 6 handler.
1120  * The rdmsr instruction generates invalid opcodes fault on 486-class
1121  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1122  * function identblue() when this handler is called.  Stacked eip should
1123  * be advanced.
1124  */
1125 inthand_t       bluetrap6;
1126 #ifdef __GNUCLIKE_ASM
1127 __asm
1128 ("                                                                      \n\
1129         .text                                                           \n\
1130         .p2align 2,0x90                                                 \n\
1131         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1132 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1133         ss                                                              \n\
1134         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1135         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1136         iret                                                            \n\
1137 ");
1138 #endif
1139
1140 /*
1141  * Special exception 13 handler.
1142  * Accessing non-existent MSR generates general protection fault.
1143  */
1144 inthand_t       bluetrap13;
1145 #ifdef __GNUCLIKE_ASM
1146 __asm
1147 ("                                                                      \n\
1148         .text                                                           \n\
1149         .p2align 2,0x90                                                 \n\
1150         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1151 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1152         ss                                                              \n\
1153         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1154         popl    %eax            /* discard error code */                \n\
1155         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1156         iret                                                            \n\
1157 ");
1158 #endif
1159
1160 /*
1161  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1162  * support cpuid instruction.  This function should be called after
1163  * loading interrupt descriptor table register.
1164  *
1165  * I don't like this method that handles fault, but I couldn't get
1166  * information for any other methods.  Does blue giant know?
1167  */
1168 static int
1169 identblue(void)
1170 {
1171
1172         trap_by_rdmsr = 0;
1173
1174         /*
1175          * Cyrix 486-class CPU does not support rdmsr instruction.
1176          * The rdmsr instruction generates invalid opcode fault, and exception
1177          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1178          * bluetrap6() set the magic number to trap_by_rdmsr.
1179          */
1180         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1181             GSEL(GCODE_SEL, SEL_KPL));
1182
1183         /*
1184          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1185          * In this case, rdmsr generates general protection fault, and
1186          * exception will be trapped by bluetrap13().
1187          */
1188         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1189             GSEL(GCODE_SEL, SEL_KPL));
1190
1191         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1192
1193         if (trap_by_rdmsr == 0xa8c1d)
1194                 return IDENTBLUE_CYRIX486;
1195         else if (trap_by_rdmsr == 0xa89c4)
1196                 return IDENTBLUE_CYRIXM2;
1197         return IDENTBLUE_IBMCPU;
1198 }
1199
1200
1201 /*
1202  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1203  *
1204  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1205  * +-------+-------+---------------+
1206  * |  SID  |  RID  |   Device ID   |
1207  * |    (DIR 1)    |    (DIR 0)    |
1208  * +-------+-------+---------------+
1209  */
1210 static void
1211 identifycyrix(void)
1212 {
1213         register_t saveintr;
1214         int     ccr2_test = 0, dir_test = 0;
1215         u_char  ccr2, ccr3;
1216
1217         saveintr = intr_disable();
1218
1219         ccr2 = read_cyrix_reg(CCR2);
1220         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1221         read_cyrix_reg(CCR2);
1222         if (read_cyrix_reg(CCR2) != ccr2)
1223                 ccr2_test = 1;
1224         write_cyrix_reg(CCR2, ccr2);
1225
1226         ccr3 = read_cyrix_reg(CCR3);
1227         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1228         read_cyrix_reg(CCR3);
1229         if (read_cyrix_reg(CCR3) != ccr3)
1230                 dir_test = 1;                                   /* CPU supports DIRs. */
1231         write_cyrix_reg(CCR3, ccr3);
1232
1233         if (dir_test) {
1234                 /* Device ID registers are available. */
1235                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1236                 cyrix_did += read_cyrix_reg(DIR0);
1237         } else if (ccr2_test)
1238                 cyrix_did = 0x0010;             /* 486S A-step */
1239         else
1240                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1241
1242         intr_restore(saveintr);
1243 }
1244 #endif
1245
1246 /* Update TSC freq with the value indicated by the caller. */
1247 static void
1248 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1249 {
1250
1251         /* If there was an error during the transition, don't do anything. */
1252         if (status != 0)
1253                 return;
1254
1255         /* Total setting for this level gives the new frequency in MHz. */
1256         hw_clockrate = level->total_set.freq;
1257 }
1258
1259 static void
1260 hook_tsc_freq(void *arg __unused)
1261 {
1262
1263         if (tsc_is_invariant)
1264                 return;
1265
1266         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1267             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1268 }
1269
1270 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1271
1272 static const char *const vm_bnames[] = {
1273         "QEMU",                         /* QEMU */
1274         "Plex86",                       /* Plex86 */
1275         "Bochs",                        /* Bochs */
1276         "Xen",                          /* Xen */
1277         "BHYVE",                        /* bhyve */
1278         "Seabios",                      /* KVM */
1279         NULL
1280 };
1281
1282 static const char *const vm_pnames[] = {
1283         "VMware Virtual Platform",      /* VMWare VM */
1284         "Virtual Machine",              /* Microsoft VirtualPC */
1285         "VirtualBox",                   /* Sun xVM VirtualBox */
1286         "Parallels Virtual Platform",   /* Parallels VM */
1287         "KVM",                          /* KVM */
1288         NULL
1289 };
1290
1291 void
1292 identify_hypervisor(void)
1293 {
1294         u_int regs[4];
1295         char *p;
1296         int i;
1297
1298         /*
1299          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1300          * http://lkml.org/lkml/2008/10/1/246
1301          *
1302          * KB1009458: Mechanisms to determine if software is running in
1303          * a VMware virtual machine
1304          * http://kb.vmware.com/kb/1009458
1305          */
1306         if (cpu_feature2 & CPUID2_HV) {
1307                 vm_guest = VM_GUEST_VM;
1308                 do_cpuid(0x40000000, regs);
1309
1310                 /*
1311                  * KVM from Linux kernels prior to commit
1312                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1313                  * to 0 rather than a valid hv_high value.  Check for
1314                  * the KVM signature bytes and fixup %eax to the
1315                  * highest supported leaf in that case.
1316                  */
1317                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1318                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1319                         regs[0] = 0x40000001;
1320
1321                 if (regs[0] >= 0x40000000) {
1322                         hv_high = regs[0];
1323                         ((u_int *)&hv_vendor)[0] = regs[1];
1324                         ((u_int *)&hv_vendor)[1] = regs[2];
1325                         ((u_int *)&hv_vendor)[2] = regs[3];
1326                         hv_vendor[12] = '\0';
1327                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1328                                 vm_guest = VM_GUEST_VMWARE;
1329                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1330                                 vm_guest = VM_GUEST_HV;
1331                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1332                                 vm_guest = VM_GUEST_KVM;
1333                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1334                                 vm_guest = VM_GUEST_BHYVE;
1335                 }
1336                 return;
1337         }
1338
1339         /*
1340          * Examine SMBIOS strings for older hypervisors.
1341          */
1342         p = kern_getenv("smbios.system.serial");
1343         if (p != NULL) {
1344                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1345                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1346                         if (regs[1] == VMW_HVMAGIC) {
1347                                 vm_guest = VM_GUEST_VMWARE;
1348                                 freeenv(p);
1349                                 return;
1350                         }
1351                 }
1352                 freeenv(p);
1353         }
1354
1355         /*
1356          * XXX: Some of these entries may not be needed since they were
1357          * added to FreeBSD before the checks above.
1358          */
1359         p = kern_getenv("smbios.bios.vendor");
1360         if (p != NULL) {
1361                 for (i = 0; vm_bnames[i] != NULL; i++)
1362                         if (strcmp(p, vm_bnames[i]) == 0) {
1363                                 vm_guest = VM_GUEST_VM;
1364                                 freeenv(p);
1365                                 return;
1366                         }
1367                 freeenv(p);
1368         }
1369         p = kern_getenv("smbios.system.product");
1370         if (p != NULL) {
1371                 for (i = 0; vm_pnames[i] != NULL; i++)
1372                         if (strcmp(p, vm_pnames[i]) == 0) {
1373                                 vm_guest = VM_GUEST_VM;
1374                                 freeenv(p);
1375                                 return;
1376                         }
1377                 freeenv(p);
1378         }
1379 }
1380
1381 bool
1382 fix_cpuid(void)
1383 {
1384         uint64_t msr;
1385
1386         /*
1387          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1388          * get the largest standard CPUID function number again if it is set
1389          * from BIOS.  It is necessary for probing correct CPU topology later
1390          * and for the correct operation of the AVX-aware userspace.
1391          */
1392         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1393             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1394             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1395             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1396             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1397                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1398                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1399                         msr &= ~IA32_MISC_EN_LIMCPUID;
1400                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1401                         return (true);
1402                 }
1403         }
1404
1405         /*
1406          * Re-enable AMD Topology Extension that could be disabled by BIOS
1407          * on some notebook processors.  Without the extension it's really
1408          * hard to determine the correct CPU cache topology.
1409          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1410          * Models 60h-6Fh Processors, Publication # 50742.
1411          */
1412         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1413             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1414                 msr = rdmsr(MSR_EXTFEATURES);
1415                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1416                         msr |= (uint64_t)1 << 54;
1417                         wrmsr(MSR_EXTFEATURES, msr);
1418                         return (true);
1419                 }
1420         }
1421         return (false);
1422 }
1423
1424 void
1425 identify_cpu1(void)
1426 {
1427         u_int regs[4];
1428
1429         do_cpuid(0, regs);
1430         cpu_high = regs[0];
1431         ((u_int *)&cpu_vendor)[0] = regs[1];
1432         ((u_int *)&cpu_vendor)[1] = regs[3];
1433         ((u_int *)&cpu_vendor)[2] = regs[2];
1434         cpu_vendor[12] = '\0';
1435
1436         do_cpuid(1, regs);
1437         cpu_id = regs[0];
1438         cpu_procinfo = regs[1];
1439         cpu_feature = regs[3];
1440         cpu_feature2 = regs[2];
1441 }
1442
1443 void
1444 identify_cpu2(void)
1445 {
1446         u_int regs[4], cpu_stdext_disable;
1447
1448         if (cpu_high >= 7) {
1449                 cpuid_count(7, 0, regs);
1450                 cpu_stdext_feature = regs[1];
1451
1452                 /*
1453                  * Some hypervisors failed to filter out unsupported
1454                  * extended features.  Allow to disable the
1455                  * extensions, activation of which requires setting a
1456                  * bit in CR4, and which VM monitors do not support.
1457                  */
1458                 cpu_stdext_disable = 0;
1459                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1460                 cpu_stdext_feature &= ~cpu_stdext_disable;
1461
1462                 cpu_stdext_feature2 = regs[2];
1463                 cpu_stdext_feature3 = regs[3];
1464
1465                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1466                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1467         }
1468 }
1469
1470 /*
1471  * Final stage of CPU identification.
1472  */
1473 void
1474 finishidentcpu(void)
1475 {
1476         u_int regs[4];
1477 #ifdef __i386__
1478         u_char ccr3;
1479 #endif
1480
1481         cpu_vendor_id = find_cpu_vendor_id();
1482
1483         if (fix_cpuid()) {
1484                 do_cpuid(0, regs);
1485                 cpu_high = regs[0];
1486         }
1487
1488         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1489                 do_cpuid(5, regs);
1490                 cpu_mon_mwait_flags = regs[2];
1491                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1492                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1493         }
1494
1495         identify_cpu2();
1496
1497 #ifdef __i386__
1498         if (cpu_high > 0 &&
1499             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1500              cpu_vendor_id == CPU_VENDOR_AMD ||
1501              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1502              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1503              cpu_vendor_id == CPU_VENDOR_NSC)) {
1504                 do_cpuid(0x80000000, regs);
1505                 if (regs[0] >= 0x80000000)
1506                         cpu_exthigh = regs[0];
1507         }
1508 #else
1509         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1510             cpu_vendor_id == CPU_VENDOR_AMD ||
1511             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1512                 do_cpuid(0x80000000, regs);
1513                 cpu_exthigh = regs[0];
1514         }
1515 #endif
1516         if (cpu_exthigh >= 0x80000001) {
1517                 do_cpuid(0x80000001, regs);
1518                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1519                 amd_feature2 = regs[2];
1520         }
1521         if (cpu_exthigh >= 0x80000007) {
1522                 do_cpuid(0x80000007, regs);
1523                 amd_rascap = regs[1];
1524                 amd_pminfo = regs[3];
1525         }
1526         if (cpu_exthigh >= 0x80000008) {
1527                 do_cpuid(0x80000008, regs);
1528                 cpu_maxphyaddr = regs[0] & 0xff;
1529                 amd_extended_feature_extensions = regs[1];
1530                 cpu_procinfo2 = regs[2];
1531         } else {
1532                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1533         }
1534
1535 #ifdef __i386__
1536         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1537                 if (cpu == CPU_486) {
1538                         /*
1539                          * These conditions are equivalent to:
1540                          *     - CPU does not support cpuid instruction.
1541                          *     - Cyrix/IBM CPU is detected.
1542                          */
1543                         if (identblue() == IDENTBLUE_IBMCPU) {
1544                                 strcpy(cpu_vendor, "IBM");
1545                                 cpu_vendor_id = CPU_VENDOR_IBM;
1546                                 cpu = CPU_BLUE;
1547                                 return;
1548                         }
1549                 }
1550                 switch (cpu_id & 0xf00) {
1551                 case 0x600:
1552                         /*
1553                          * Cyrix's datasheet does not describe DIRs.
1554                          * Therefor, I assume it does not have them
1555                          * and use the result of the cpuid instruction.
1556                          * XXX they seem to have it for now at least. -Peter
1557                          */
1558                         identifycyrix();
1559                         cpu = CPU_M2;
1560                         break;
1561                 default:
1562                         identifycyrix();
1563                         /*
1564                          * This routine contains a trick.
1565                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1566                          */
1567                         switch (cyrix_did & 0x00f0) {
1568                         case 0x00:
1569                         case 0xf0:
1570                                 cpu = CPU_486DLC;
1571                                 break;
1572                         case 0x10:
1573                                 cpu = CPU_CY486DX;
1574                                 break;
1575                         case 0x20:
1576                                 if ((cyrix_did & 0x000f) < 8)
1577                                         cpu = CPU_M1;
1578                                 else
1579                                         cpu = CPU_M1SC;
1580                                 break;
1581                         case 0x30:
1582                                 cpu = CPU_M1;
1583                                 break;
1584                         case 0x40:
1585                                 /* MediaGX CPU */
1586                                 cpu = CPU_M1SC;
1587                                 break;
1588                         default:
1589                                 /* M2 and later CPUs are treated as M2. */
1590                                 cpu = CPU_M2;
1591
1592                                 /*
1593                                  * enable cpuid instruction.
1594                                  */
1595                                 ccr3 = read_cyrix_reg(CCR3);
1596                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1597                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1598                                 write_cyrix_reg(CCR3, ccr3);
1599
1600                                 do_cpuid(0, regs);
1601                                 cpu_high = regs[0];     /* eax */
1602                                 do_cpuid(1, regs);
1603                                 cpu_id = regs[0];       /* eax */
1604                                 cpu_feature = regs[3];  /* edx */
1605                                 break;
1606                         }
1607                 }
1608         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1609                 /*
1610                  * There are BlueLightning CPUs that do not change
1611                  * undefined flags by dividing 5 by 2.  In this case,
1612                  * the CPU identification routine in locore.s leaves
1613                  * cpu_vendor null string and puts CPU_486 into the
1614                  * cpu.
1615                  */
1616                 if (identblue() == IDENTBLUE_IBMCPU) {
1617                         strcpy(cpu_vendor, "IBM");
1618                         cpu_vendor_id = CPU_VENDOR_IBM;
1619                         cpu = CPU_BLUE;
1620                         return;
1621                 }
1622         }
1623 #endif
1624 }
1625
1626 int
1627 pti_get_default(void)
1628 {
1629
1630         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1631                 return (0);
1632         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1633                 return (0);
1634         return (1);
1635 }
1636
1637 static u_int
1638 find_cpu_vendor_id(void)
1639 {
1640         int     i;
1641
1642         for (i = 0; i < nitems(cpu_vendors); i++)
1643                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1644                         return (cpu_vendors[i].vendor_id);
1645         return (0);
1646 }
1647
1648 static void
1649 print_AMD_assoc(int i)
1650 {
1651         if (i == 255)
1652                 printf(", fully associative\n");
1653         else
1654                 printf(", %d-way associative\n", i);
1655 }
1656
1657 static void
1658 print_AMD_l2_assoc(int i)
1659 {
1660         switch (i & 0x0f) {
1661         case 0: printf(", disabled/not present\n"); break;
1662         case 1: printf(", direct mapped\n"); break;
1663         case 2: printf(", 2-way associative\n"); break;
1664         case 4: printf(", 4-way associative\n"); break;
1665         case 6: printf(", 8-way associative\n"); break;
1666         case 8: printf(", 16-way associative\n"); break;
1667         case 15: printf(", fully associative\n"); break;
1668         default: printf(", reserved configuration\n"); break;
1669         }
1670 }
1671
1672 static void
1673 print_AMD_info(void)
1674 {
1675 #ifdef __i386__
1676         uint64_t amd_whcr;
1677 #endif
1678         u_int regs[4];
1679
1680         if (cpu_exthigh >= 0x80000005) {
1681                 do_cpuid(0x80000005, regs);
1682                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1683                 print_AMD_assoc(regs[0] >> 24);
1684
1685                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1686                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1687
1688                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1689                 print_AMD_assoc(regs[1] >> 24);
1690
1691                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1692                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1693
1694                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1695                 printf(", %d bytes/line", regs[2] & 0xff);
1696                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1697                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1698
1699                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1700                 printf(", %d bytes/line", regs[3] & 0xff);
1701                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1702                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1703         }
1704
1705         if (cpu_exthigh >= 0x80000006) {
1706                 do_cpuid(0x80000006, regs);
1707                 if ((regs[0] >> 16) != 0) {
1708                         printf("L2 2MB data TLB: %d entries",
1709                             (regs[0] >> 16) & 0xfff);
1710                         print_AMD_l2_assoc(regs[0] >> 28);
1711                         printf("L2 2MB instruction TLB: %d entries",
1712                             regs[0] & 0xfff);
1713                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1714                 } else {
1715                         printf("L2 2MB unified TLB: %d entries",
1716                             regs[0] & 0xfff);
1717                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1718                 }
1719                 if ((regs[1] >> 16) != 0) {
1720                         printf("L2 4KB data TLB: %d entries",
1721                             (regs[1] >> 16) & 0xfff);
1722                         print_AMD_l2_assoc(regs[1] >> 28);
1723
1724                         printf("L2 4KB instruction TLB: %d entries",
1725                             (regs[1] >> 16) & 0xfff);
1726                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1727                 } else {
1728                         printf("L2 4KB unified TLB: %d entries",
1729                             (regs[1] >> 16) & 0xfff);
1730                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1731                 }
1732                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1733                 printf(", %d bytes/line", regs[2] & 0xff);
1734                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1735                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1736         }
1737
1738 #ifdef __i386__
1739         if (((cpu_id & 0xf00) == 0x500)
1740             && (((cpu_id & 0x0f0) > 0x80)
1741                 || (((cpu_id & 0x0f0) == 0x80)
1742                     && (cpu_id & 0x00f) > 0x07))) {
1743                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1744                 amd_whcr = rdmsr(0xc0000082);
1745                 if (!(amd_whcr & (0x3ff << 22))) {
1746                         printf("Write Allocate Disable\n");
1747                 } else {
1748                         printf("Write Allocate Enable Limit: %dM bytes\n",
1749                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1750                         printf("Write Allocate 15-16M bytes: %s\n",
1751                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1752                 }
1753         } else if (((cpu_id & 0xf00) == 0x500)
1754                    && ((cpu_id & 0x0f0) > 0x50)) {
1755                 /* K6, K6-2(old core) */
1756                 amd_whcr = rdmsr(0xc0000082);
1757                 if (!(amd_whcr & (0x7f << 1))) {
1758                         printf("Write Allocate Disable\n");
1759                 } else {
1760                         printf("Write Allocate Enable Limit: %dM bytes\n",
1761                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1762                         printf("Write Allocate 15-16M bytes: %s\n",
1763                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1764                         printf("Hardware Write Allocate Control: %s\n",
1765                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1766                 }
1767         }
1768 #endif
1769         /*
1770          * Opteron Rev E shows a bug as in very rare occasions a read memory
1771          * barrier is not performed as expected if it is followed by a
1772          * non-atomic read-modify-write instruction.
1773          * As long as that bug pops up very rarely (intensive machine usage
1774          * on other operating systems generally generates one unexplainable
1775          * crash any 2 months) and as long as a model specific fix would be
1776          * impractical at this stage, print out a warning string if the broken
1777          * model and family are identified.
1778          */
1779         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1780             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1781                 printf("WARNING: This architecture revision has known SMP "
1782                     "hardware bugs which may cause random instability\n");
1783 }
1784
1785 static void
1786 print_INTEL_info(void)
1787 {
1788         u_int regs[4];
1789         u_int rounds, regnum;
1790         u_int nwaycode, nway;
1791
1792         if (cpu_high >= 2) {
1793                 rounds = 0;
1794                 do {
1795                         do_cpuid(0x2, regs);
1796                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1797                                 break;  /* we have a buggy CPU */
1798
1799                         for (regnum = 0; regnum <= 3; ++regnum) {
1800                                 if (regs[regnum] & (1<<31))
1801                                         continue;
1802                                 if (regnum != 0)
1803                                         print_INTEL_TLB(regs[regnum] & 0xff);
1804                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1805                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1806                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1807                         }
1808                 } while (--rounds > 0);
1809         }
1810
1811         if (cpu_exthigh >= 0x80000006) {
1812                 do_cpuid(0x80000006, regs);
1813                 nwaycode = (regs[2] >> 12) & 0x0f;
1814                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1815                         nway = 1 << (nwaycode / 2);
1816                 else
1817                         nway = 0;
1818                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1819                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1820         }
1821 }
1822
1823 static void
1824 print_INTEL_TLB(u_int data)
1825 {
1826         switch (data) {
1827         case 0x0:
1828         case 0x40:
1829         default:
1830                 break;
1831         case 0x1:
1832                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1833                 break;
1834         case 0x2:
1835                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1836                 break;
1837         case 0x3:
1838                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1839                 break;
1840         case 0x4:
1841                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1842                 break;
1843         case 0x6:
1844                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1845                 break;
1846         case 0x8:
1847                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1848                 break;
1849         case 0x9:
1850                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1851                 break;
1852         case 0xa:
1853                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1854                 break;
1855         case 0xb:
1856                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1857                 break;
1858         case 0xc:
1859                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1860                 break;
1861         case 0xd:
1862                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1863                 break;
1864         case 0xe:
1865                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1866                 break;
1867         case 0x1d:
1868                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1869                 break;
1870         case 0x21:
1871                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1872                 break;
1873         case 0x22:
1874                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1875                 break;
1876         case 0x23:
1877                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1878                 break;
1879         case 0x24:
1880                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1881                 break;
1882         case 0x25:
1883                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1884                 break;
1885         case 0x29:
1886                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1887                 break;
1888         case 0x2c:
1889                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1890                 break;
1891         case 0x30:
1892                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1893                 break;
1894         case 0x39: /* De-listed in SDM rev. 54 */
1895                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1896                 break;
1897         case 0x3b: /* De-listed in SDM rev. 54 */
1898                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1899                 break;
1900         case 0x3c: /* De-listed in SDM rev. 54 */
1901                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1902                 break;
1903         case 0x41:
1904                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1905                 break;
1906         case 0x42:
1907                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1908                 break;
1909         case 0x43:
1910                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1911                 break;
1912         case 0x44:
1913                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1914                 break;
1915         case 0x45:
1916                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1917                 break;
1918         case 0x46:
1919                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1920                 break;
1921         case 0x47:
1922                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1923                 break;
1924         case 0x48:
1925                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1926                 break;
1927         case 0x49:
1928                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1929                     CPUID_TO_MODEL(cpu_id) == 0x6)
1930                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1931                 else
1932                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1933                 break;
1934         case 0x4a:
1935                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1936                 break;
1937         case 0x4b:
1938                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1939                 break;
1940         case 0x4c:
1941                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1942                 break;
1943         case 0x4d:
1944                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1945                 break;
1946         case 0x4e:
1947                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1948                 break;
1949         case 0x4f:
1950                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1951                 break;
1952         case 0x50:
1953                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1954                 break;
1955         case 0x51:
1956                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1957                 break;
1958         case 0x52:
1959                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1960                 break;
1961         case 0x55:
1962                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1963                 break;
1964         case 0x56:
1965                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1966                 break;
1967         case 0x57:
1968                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1969                 break;
1970         case 0x59:
1971                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1972                 break;
1973         case 0x5a:
1974                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1975                 break;
1976         case 0x5b:
1977                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1978                 break;
1979         case 0x5c:
1980                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1981                 break;
1982         case 0x5d:
1983                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1984                 break;
1985         case 0x60:
1986                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1987                 break;
1988         case 0x61:
1989                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1990                 break;
1991         case 0x63:
1992                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1993                 break;
1994         case 0x64:
1995                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1996                 break;
1997         case 0x66:
1998                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1999                 break;
2000         case 0x67:
2001                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2002                 break;
2003         case 0x68:
2004                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2005                 break;
2006         case 0x6a:
2007                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2008                 break;
2009         case 0x6b:
2010                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2011                 break;
2012         case 0x6c:
2013                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2014                 break;
2015         case 0x6d:
2016                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2017                 break;
2018         case 0x70:
2019                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2020                 break;
2021         case 0x71:
2022                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2023                 break;
2024         case 0x72:
2025                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2026                 break;
2027         case 0x76:
2028                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2029                 break;
2030         case 0x78:
2031                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2032                 break;
2033         case 0x79:
2034                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2035                 break;
2036         case 0x7a:
2037                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2038                 break;
2039         case 0x7b:
2040                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2041                 break;
2042         case 0x7c:
2043                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2044                 break;
2045         case 0x7d:
2046                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2047                 break;
2048         case 0x7f:
2049                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2050                 break;
2051         case 0x80:
2052                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2053                 break;
2054         case 0x82:
2055                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2056                 break;
2057         case 0x83:
2058                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2059                 break;
2060         case 0x84:
2061                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2062                 break;
2063         case 0x85:
2064                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2065                 break;
2066         case 0x86:
2067                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2068                 break;
2069         case 0x87:
2070                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2071                 break;
2072         case 0xa0:
2073                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2074                 break;
2075         case 0xb0:
2076                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2077                 break;
2078         case 0xb1:
2079                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2080                 break;
2081         case 0xb2:
2082                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2083                 break;
2084         case 0xb3:
2085                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2086                 break;
2087         case 0xb4:
2088                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2089                 break;
2090         case 0xb5:
2091                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2092                 break;
2093         case 0xb6:
2094                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2095                 break;
2096         case 0xba:
2097                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2098                 break;
2099         case 0xc0:
2100                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2101                 break;
2102         case 0xc1:
2103                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2104                 break;
2105         case 0xc2:
2106                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2107                 break;
2108         case 0xc3:
2109                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2110                 break;
2111         case 0xc4:
2112                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2113                 break;
2114         case 0xca:
2115                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2116                 break;
2117         case 0xd0:
2118                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2119                 break;
2120         case 0xd1:
2121                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2122                 break;
2123         case 0xd2:
2124                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2125                 break;
2126         case 0xd6:
2127                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2128                 break;
2129         case 0xd7:
2130                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2131                 break;
2132         case 0xd8:
2133                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2134                 break;
2135         case 0xdc:
2136                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2137                 break;
2138         case 0xdd:
2139                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2140                 break;
2141         case 0xde:
2142                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2143                 break;
2144         case 0xe2:
2145                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2146                 break;
2147         case 0xe3:
2148                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2149                 break;
2150         case 0xe4:
2151                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2152                 break;
2153         case 0xea:
2154                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2155                 break;
2156         case 0xeb:
2157                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2158                 break;
2159         case 0xec:
2160                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2161                 break;
2162         case 0xf0:
2163                 printf("64-Byte prefetching\n");
2164                 break;
2165         case 0xf1:
2166                 printf("128-Byte prefetching\n");
2167                 break;
2168         }
2169 }
2170
2171 static void
2172 print_svm_info(void)
2173 {
2174         u_int features, regs[4];
2175         uint64_t msr;
2176         int comma;
2177
2178         printf("\n  SVM: ");
2179         do_cpuid(0x8000000A, regs);
2180         features = regs[3];
2181
2182         msr = rdmsr(MSR_VM_CR);
2183         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2184                 printf("(disabled in BIOS) ");
2185
2186         if (!bootverbose) {
2187                 comma = 0;
2188                 if (features & (1 << 0)) {
2189                         printf("%sNP", comma ? "," : "");
2190                         comma = 1;
2191                 }
2192                 if (features & (1 << 3)) {
2193                         printf("%sNRIP", comma ? "," : "");
2194                         comma = 1;
2195                 }
2196                 if (features & (1 << 5)) {
2197                         printf("%sVClean", comma ? "," : "");
2198                         comma = 1;
2199                 }
2200                 if (features & (1 << 6)) {
2201                         printf("%sAFlush", comma ? "," : "");
2202                         comma = 1;
2203                 }
2204                 if (features & (1 << 7)) {
2205                         printf("%sDAssist", comma ? "," : "");
2206                         comma = 1;
2207                 }
2208                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2209                 return;
2210         }
2211
2212         printf("Features=0x%b", features,
2213                "\020"
2214                "\001NP"                 /* Nested paging */
2215                "\002LbrVirt"            /* LBR virtualization */
2216                "\003SVML"               /* SVM lock */
2217                "\004NRIPS"              /* NRIP save */
2218                "\005TscRateMsr"         /* MSR based TSC rate control */
2219                "\006VmcbClean"          /* VMCB clean bits */
2220                "\007FlushByAsid"        /* Flush by ASID */
2221                "\010DecodeAssist"       /* Decode assist */
2222                "\011<b8>"
2223                "\012<b9>"
2224                "\013PauseFilter"        /* PAUSE intercept filter */
2225                "\014EncryptedMcodePatch"
2226                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2227                "\016AVIC"               /* virtual interrupt controller */
2228                "\017<b14>"
2229                "\020V_VMSAVE_VMLOAD"
2230                "\021vGIF"
2231                "\022<b17>"
2232                "\023<b18>"
2233                "\024<b19>"
2234                "\025<b20>"
2235                "\026<b21>"
2236                "\027<b22>"
2237                "\030<b23>"
2238                "\031<b24>"
2239                "\032<b25>"
2240                "\033<b26>"
2241                "\034<b27>"
2242                "\035<b28>"
2243                "\036<b29>"
2244                "\037<b30>"
2245                "\040<b31>"
2246                 );
2247         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2248 }
2249
2250 #ifdef __i386__
2251 static void
2252 print_transmeta_info(void)
2253 {
2254         u_int regs[4], nreg = 0;
2255
2256         do_cpuid(0x80860000, regs);
2257         nreg = regs[0];
2258         if (nreg >= 0x80860001) {
2259                 do_cpuid(0x80860001, regs);
2260                 printf("  Processor revision %u.%u.%u.%u\n",
2261                        (regs[1] >> 24) & 0xff,
2262                        (regs[1] >> 16) & 0xff,
2263                        (regs[1] >> 8) & 0xff,
2264                        regs[1] & 0xff);
2265         }
2266         if (nreg >= 0x80860002) {
2267                 do_cpuid(0x80860002, regs);
2268                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2269                        (regs[1] >> 24) & 0xff,
2270                        (regs[1] >> 16) & 0xff,
2271                        (regs[1] >> 8) & 0xff,
2272                        regs[1] & 0xff,
2273                        regs[2]);
2274         }
2275         if (nreg >= 0x80860006) {
2276                 char info[65];
2277                 do_cpuid(0x80860003, (u_int*) &info[0]);
2278                 do_cpuid(0x80860004, (u_int*) &info[16]);
2279                 do_cpuid(0x80860005, (u_int*) &info[32]);
2280                 do_cpuid(0x80860006, (u_int*) &info[48]);
2281                 info[64] = 0;
2282                 printf("  %s\n", info);
2283         }
2284 }
2285 #endif
2286
2287 static void
2288 print_via_padlock_info(void)
2289 {
2290         u_int regs[4];
2291
2292         do_cpuid(0xc0000001, regs);
2293         printf("\n  VIA Padlock Features=0x%b", regs[3],
2294         "\020"
2295         "\003RNG"               /* RNG */
2296         "\007AES"               /* ACE */
2297         "\011AES-CTR"           /* ACE2 */
2298         "\013SHA1,SHA256"       /* PHE */
2299         "\015RSA"               /* PMM */
2300         );
2301 }
2302
2303 static uint32_t
2304 vmx_settable(uint64_t basic, int msr, int true_msr)
2305 {
2306         uint64_t val;
2307
2308         if (basic & (1ULL << 55))
2309                 val = rdmsr(true_msr);
2310         else
2311                 val = rdmsr(msr);
2312
2313         /* Just report the controls that can be set to 1. */
2314         return (val >> 32);
2315 }
2316
2317 static void
2318 print_vmx_info(void)
2319 {
2320         uint64_t basic, msr;
2321         uint32_t entry, exit, mask, pin, proc, proc2;
2322         int comma;
2323
2324         printf("\n  VT-x: ");
2325         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2326         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2327                 printf("(disabled in BIOS) ");
2328         basic = rdmsr(MSR_VMX_BASIC);
2329         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2330             MSR_VMX_TRUE_PINBASED_CTLS);
2331         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2332             MSR_VMX_TRUE_PROCBASED_CTLS);
2333         if (proc & PROCBASED_SECONDARY_CONTROLS)
2334                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2335                     MSR_VMX_PROCBASED_CTLS2);
2336         else
2337                 proc2 = 0;
2338         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2339         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2340
2341         if (!bootverbose) {
2342                 comma = 0;
2343                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2344                     entry & VM_ENTRY_LOAD_PAT) {
2345                         printf("%sPAT", comma ? "," : "");
2346                         comma = 1;
2347                 }
2348                 if (proc & PROCBASED_HLT_EXITING) {
2349                         printf("%sHLT", comma ? "," : "");
2350                         comma = 1;
2351                 }
2352                 if (proc & PROCBASED_MTF) {
2353                         printf("%sMTF", comma ? "," : "");
2354                         comma = 1;
2355                 }
2356                 if (proc & PROCBASED_PAUSE_EXITING) {
2357                         printf("%sPAUSE", comma ? "," : "");
2358                         comma = 1;
2359                 }
2360                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2361                         printf("%sEPT", comma ? "," : "");
2362                         comma = 1;
2363                 }
2364                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2365                         printf("%sUG", comma ? "," : "");
2366                         comma = 1;
2367                 }
2368                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2369                         printf("%sVPID", comma ? "," : "");
2370                         comma = 1;
2371                 }
2372                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2373                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2374                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2375                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2376                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2377                         printf("%sVID", comma ? "," : "");
2378                         comma = 1;
2379                         if (pin & PINBASED_POSTED_INTERRUPT)
2380                                 printf(",PostIntr");
2381                 }
2382                 return;
2383         }
2384
2385         mask = basic >> 32;
2386         printf("Basic Features=0x%b", mask,
2387         "\020"
2388         "\02132PA"              /* 32-bit physical addresses */
2389         "\022SMM"               /* SMM dual-monitor */
2390         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2391         "\030TRUE"              /* TRUE_CTLS MSRs */
2392         );
2393         printf("\n        Pin-Based Controls=0x%b", pin,
2394         "\020"
2395         "\001ExtINT"            /* External-interrupt exiting */
2396         "\004NMI"               /* NMI exiting */
2397         "\006VNMI"              /* Virtual NMIs */
2398         "\007PreTmr"            /* Activate VMX-preemption timer */
2399         "\010PostIntr"          /* Process posted interrupts */
2400         );
2401         printf("\n        Primary Processor Controls=0x%b", proc,
2402         "\020"
2403         "\003INTWIN"            /* Interrupt-window exiting */
2404         "\004TSCOff"            /* Use TSC offsetting */
2405         "\010HLT"               /* HLT exiting */
2406         "\012INVLPG"            /* INVLPG exiting */
2407         "\013MWAIT"             /* MWAIT exiting */
2408         "\014RDPMC"             /* RDPMC exiting */
2409         "\015RDTSC"             /* RDTSC exiting */
2410         "\020CR3-LD"            /* CR3-load exiting */
2411         "\021CR3-ST"            /* CR3-store exiting */
2412         "\024CR8-LD"            /* CR8-load exiting */
2413         "\025CR8-ST"            /* CR8-store exiting */
2414         "\026TPR"               /* Use TPR shadow */
2415         "\027NMIWIN"            /* NMI-window exiting */
2416         "\030MOV-DR"            /* MOV-DR exiting */
2417         "\031IO"                /* Unconditional I/O exiting */
2418         "\032IOmap"             /* Use I/O bitmaps */
2419         "\034MTF"               /* Monitor trap flag */
2420         "\035MSRmap"            /* Use MSR bitmaps */
2421         "\036MONITOR"           /* MONITOR exiting */
2422         "\037PAUSE"             /* PAUSE exiting */
2423         );
2424         if (proc & PROCBASED_SECONDARY_CONTROLS)
2425                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2426                 "\020"
2427                 "\001APIC"              /* Virtualize APIC accesses */
2428                 "\002EPT"               /* Enable EPT */
2429                 "\003DT"                /* Descriptor-table exiting */
2430                 "\004RDTSCP"            /* Enable RDTSCP */
2431                 "\005x2APIC"            /* Virtualize x2APIC mode */
2432                 "\006VPID"              /* Enable VPID */
2433                 "\007WBINVD"            /* WBINVD exiting */
2434                 "\010UG"                /* Unrestricted guest */
2435                 "\011APIC-reg"          /* APIC-register virtualization */
2436                 "\012VID"               /* Virtual-interrupt delivery */
2437                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2438                 "\014RDRAND"            /* RDRAND exiting */
2439                 "\015INVPCID"           /* Enable INVPCID */
2440                 "\016VMFUNC"            /* Enable VM functions */
2441                 "\017VMCS"              /* VMCS shadowing */
2442                 "\020EPT#VE"            /* EPT-violation #VE */
2443                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2444                 );
2445         printf("\n        Exit Controls=0x%b", mask,
2446         "\020"
2447         "\003DR"                /* Save debug controls */
2448                                 /* Ignore Host address-space size */
2449         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2450         "\020AckInt"            /* Acknowledge interrupt on exit */
2451         "\023PAT-SV"            /* Save MSR_PAT */
2452         "\024PAT-LD"            /* Load MSR_PAT */
2453         "\025EFER-SV"           /* Save MSR_EFER */
2454         "\026EFER-LD"           /* Load MSR_EFER */
2455         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2456         );
2457         printf("\n        Entry Controls=0x%b", mask,
2458         "\020"
2459         "\003DR"                /* Save debug controls */
2460                                 /* Ignore IA-32e mode guest */
2461                                 /* Ignore Entry to SMM */
2462                                 /* Ignore Deactivate dual-monitor treatment */
2463         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2464         "\017PAT"               /* Load MSR_PAT */
2465         "\020EFER"              /* Load MSR_EFER */
2466         );
2467         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2468             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2469                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2470                 mask = msr;
2471                 printf("\n        EPT Features=0x%b", mask,
2472                 "\020"
2473                 "\001XO"                /* Execute-only translations */
2474                 "\007PW4"               /* Page-walk length of 4 */
2475                 "\011UC"                /* EPT paging-structure mem can be UC */
2476                 "\017WB"                /* EPT paging-structure mem can be WB */
2477                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2478                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2479                 "\025INVEPT"            /* INVEPT is supported */
2480                 "\026AD"                /* Accessed and dirty flags for EPT */
2481                 "\032single"            /* INVEPT single-context type */
2482                 "\033all"               /* INVEPT all-context type */
2483                 );
2484                 mask = msr >> 32;
2485                 printf("\n        VPID Features=0x%b", mask,
2486                 "\020"
2487                 "\001INVVPID"           /* INVVPID is supported */
2488                 "\011individual"        /* INVVPID individual-address type */
2489                 "\012single"            /* INVVPID single-context type */
2490                 "\013all"               /* INVVPID all-context type */
2491                  /* INVVPID single-context-retaining-globals type */
2492                 "\014single-globals"
2493                 );
2494         }
2495 }
2496
2497 static void
2498 print_hypervisor_info(void)
2499 {
2500
2501         if (*hv_vendor)
2502                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2503 }