sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 #include "opt_cpu.h"
  43
  44 #include <sys/param.h>
  45 #include <sys/bus.h>
  46 #include <sys/cpu.h>
  47 #include <sys/eventhandler.h>
  48 #include <sys/limits.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/sysctl.h>
  52 #include <sys/power.h>
  53
  54 #include <vm/vm.h>
  55 #include <vm/pmap.h>
  56
  57 #include <machine/asmacros.h>
  58 #include <machine/clock.h>
  59 #include <machine/cputypes.h>
  60 #include <machine/frame.h>
  61 #include <machine/intr_machdep.h>
  62 #include <machine/md_var.h>
  63 #include <machine/segments.h>
  64 #include <machine/specialreg.h>
  65
  66 #include <amd64/vmm/intel/vmx_controls.h>
  67 #include <x86/isa/icu.h>
  68 #include <x86/vmware.h>
  69
  70 #ifdef XENHVM
  71 #include <xen/xen-os.h>
  72 #endif
  73
  74 #ifdef __i386__
  75 #define IDENTBLUE_CYRIX486      0
  76 #define IDENTBLUE_IBMCPU        1
  77 #define IDENTBLUE_CYRIXM2       2
  78
  79 static void identifycyrix(void);
  80 static void print_transmeta_info(void);
  81 #endif
  82 static u_int find_cpu_vendor_id(void);
  83 static void print_AMD_info(void);
  84 static void print_INTEL_info(void);
  85 static void print_INTEL_TLB(u_int data);
  86 static void print_hypervisor_info(void);
  87 static void print_svm_info(void);
  88 static void print_via_padlock_info(void);
  89 static void print_vmx_info(void);
  90
  91 #ifdef __i386__
  92 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  93 int     cpu_class;
  94 #endif
  95 u_int   cpu_feature;            /* Feature flags */
  96 u_int   cpu_feature2;           /* Feature flags */
  97 u_int   amd_feature;            /* AMD feature flags */
  98 u_int   amd_feature2;           /* AMD feature flags */
  99 u_int   amd_rascap;             /* AMD RAS capabilities */
 100 u_int   amd_pminfo;             /* AMD advanced power management info */
 101 u_int   amd_extended_feature_extensions;
 102 u_int   via_feature_rng;        /* VIA RNG features */
 103 u_int   via_feature_xcrypt;     /* VIA ACE features */
 104 u_int   cpu_high;               /* Highest arg to CPUID */
 105 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 106 u_int   cpu_id;                 /* Stepping ID */
 107 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 108 u_int   cpu_procinfo2;          /* Multicore info */
 109 char    cpu_vendor[20];         /* CPU Origin code */
 110 u_int   cpu_vendor_id;          /* CPU vendor ID */
 111 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 112 u_int   cpu_clflush_line_size = 32;
 113 u_int   cpu_stdext_feature;     /* %ebx */
 114 u_int   cpu_stdext_feature2;    /* %ecx */
 115 u_int   cpu_stdext_feature3;    /* %edx */
 116 uint64_t cpu_ia32_arch_caps;
 117 u_int   cpu_max_ext_state_size;
 118 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 119 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 121 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 122 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 123 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %ebx */
 124 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %ecx */
 125 u_int   cpu_power_edx;          /* 06H: Power management leaf, %edx */
 126 char machine[] = MACHINE;
 127
 128 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 129     &via_feature_rng, 0,
 130     "VIA RNG feature available in CPU");
 131 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 132     &via_feature_xcrypt, 0,
 133     "VIA xcrypt feature available in CPU");
 134
 135 #ifdef __amd64__
 136 #ifdef SCTL_MASK32
 137 extern int adaptive_machine_arch;
 138 #endif
 139
 140 static int
 141 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 142 {
 143 #ifdef SCTL_MASK32
 144         static const char machine32[] = "i386";
 145 #endif
 146         int error;
 147
 148 #ifdef SCTL_MASK32
 149         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 150                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 151         else
 152 #endif
 153                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 154         return (error);
 155
 156 }
 157 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 158     CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 159 #else
 160 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
 161     machine, 0, "Machine class");
 162 #endif
 163
 164 char cpu_model[128];
 165 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
 166     cpu_model, 0, "Machine model");
 167
 168 static int hw_clockrate;
 169 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 170     &hw_clockrate, 0, "CPU instruction clock rate");
 171
 172 u_int hv_base;
 173 u_int hv_high;
 174 char hv_vendor[16];
 175 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
 176     0, "Hypervisor vendor");
 177
 178 static eventhandler_tag tsc_post_tag;
 179
 180 static char cpu_brand[48];
 181
 182 #ifdef __i386__
 183 #define MAX_BRAND_INDEX 8
 184
 185 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 186         NULL,                   /* No brand */
 187         "Intel Celeron",
 188         "Intel Pentium III",
 189         "Intel Pentium III Xeon",
 190         NULL,
 191         NULL,
 192         NULL,
 193         NULL,
 194         "Intel Pentium 4"
 195 };
 196
 197 static struct {
 198         char    *cpu_name;
 199         int     cpu_class;
 200 } cpus[] = {
 201         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 202         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 203         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 204         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 205         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 206         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 207         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 208         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 209         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 210         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 211         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 212         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 213         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 214         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 215         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 216         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 217         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 218 };
 219 #endif
 220
 221 static struct {
 222         char    *vendor;
 223         u_int   vendor_id;
 224 } cpu_vendors[] = {
 225         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 226         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 227         { HYGON_VENDOR_ID,      CPU_VENDOR_HYGON },     /* HygonGenuine */
 228         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 229 #ifdef __i386__
 230         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 231         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 232         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 233         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 234         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 235         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 236         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 237 #if 0
 238         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 239         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 240 #endif
 241 #endif
 242 };
 243
 244 void
 245 printcpuinfo(void)
 246 {
 247         u_int regs[4], i;
 248         char *brand;
 249
 250         printf("CPU: ");
 251 #ifdef __i386__
 252         cpu_class = cpus[cpu].cpu_class;
 253         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 254 #else
 255         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 256 #endif
 257
 258         /* Check for extended CPUID information and a processor name. */
 259         if (cpu_exthigh >= 0x80000004) {
 260                 brand = cpu_brand;
 261                 for (i = 0x80000002; i < 0x80000005; i++) {
 262                         do_cpuid(i, regs);
 263                         memcpy(brand, regs, sizeof(regs));
 264                         brand += sizeof(regs);
 265                 }
 266         }
 267
 268         switch (cpu_vendor_id) {
 269         case CPU_VENDOR_INTEL:
 270 #ifdef __i386__
 271                 if ((cpu_id & 0xf00) > 0x300) {
 272                         u_int brand_index;
 273
 274                         cpu_model[0] = '\0';
 275
 276                         switch (cpu_id & 0x3000) {
 277                         case 0x1000:
 278                                 strcpy(cpu_model, "Overdrive ");
 279                                 break;
 280                         case 0x2000:
 281                                 strcpy(cpu_model, "Dual ");
 282                                 break;
 283                         }
 284
 285                         switch (cpu_id & 0xf00) {
 286                         case 0x400:
 287                                 strcat(cpu_model, "i486 ");
 288                                 /* Check the particular flavor of 486 */
 289                                 switch (cpu_id & 0xf0) {
 290                                 case 0x00:
 291                                 case 0x10:
 292                                         strcat(cpu_model, "DX");
 293                                         break;
 294                                 case 0x20:
 295                                         strcat(cpu_model, "SX");
 296                                         break;
 297                                 case 0x30:
 298                                         strcat(cpu_model, "DX2");
 299                                         break;
 300                                 case 0x40:
 301                                         strcat(cpu_model, "SL");
 302                                         break;
 303                                 case 0x50:
 304                                         strcat(cpu_model, "SX2");
 305                                         break;
 306                                 case 0x70:
 307                                         strcat(cpu_model,
 308                                             "DX2 Write-Back Enhanced");
 309                                         break;
 310                                 case 0x80:
 311                                         strcat(cpu_model, "DX4");
 312                                         break;
 313                                 }
 314                                 break;
 315                         case 0x500:
 316                                 /* Check the particular flavor of 586 */
 317                                 strcat(cpu_model, "Pentium");
 318                                 switch (cpu_id & 0xf0) {
 319                                 case 0x00:
 320                                         strcat(cpu_model, " A-step");
 321                                         break;
 322                                 case 0x10:
 323                                         strcat(cpu_model, "/P5");
 324                                         break;
 325                                 case 0x20:
 326                                         strcat(cpu_model, "/P54C");
 327                                         break;
 328                                 case 0x30:
 329                                         strcat(cpu_model, "/P24T");
 330                                         break;
 331                                 case 0x40:
 332                                         strcat(cpu_model, "/P55C");
 333                                         break;
 334                                 case 0x70:
 335                                         strcat(cpu_model, "/P54C");
 336                                         break;
 337                                 case 0x80:
 338                                         strcat(cpu_model, "/P55C (quarter-micron)");
 339                                         break;
 340                                 default:
 341                                         /* nothing */
 342                                         break;
 343                                 }
 344 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 345                                 /*
 346                                  * XXX - If/when Intel fixes the bug, this
 347                                  * should also check the version of the
 348                                  * CPU, not just that it's a Pentium.
 349                                  */
 350                                 has_f00f_bug = 1;
 351 #endif
 352                                 break;
 353                         case 0x600:
 354                                 /* Check the particular flavor of 686 */
 355                                 switch (cpu_id & 0xf0) {
 356                                 case 0x00:
 357                                         strcat(cpu_model, "Pentium Pro A-step");
 358                                         break;
 359                                 case 0x10:
 360                                         strcat(cpu_model, "Pentium Pro");
 361                                         break;
 362                                 case 0x30:
 363                                 case 0x50:
 364                                 case 0x60:
 365                                         strcat(cpu_model,
 366                                 "Pentium II/Pentium II Xeon/Celeron");
 367                                         cpu = CPU_PII;
 368                                         break;
 369                                 case 0x70:
 370                                 case 0x80:
 371                                 case 0xa0:
 372                                 case 0xb0:
 373                                         strcat(cpu_model,
 374                                         "Pentium III/Pentium III Xeon/Celeron");
 375                                         cpu = CPU_PIII;
 376                                         break;
 377                                 default:
 378                                         strcat(cpu_model, "Unknown 80686");
 379                                         break;
 380                                 }
 381                                 break;
 382                         case 0xf00:
 383                                 strcat(cpu_model, "Pentium 4");
 384                                 cpu = CPU_P4;
 385                                 break;
 386                         default:
 387                                 strcat(cpu_model, "unknown");
 388                                 break;
 389                         }
 390
 391                         /*
 392                          * If we didn't get a brand name from the extended
 393                          * CPUID, try to look it up in the brand table.
 394                          */
 395                         if (cpu_high > 0 && *cpu_brand == '\0') {
 396                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 397                                 if (brand_index <= MAX_BRAND_INDEX &&
 398                                     cpu_brandtable[brand_index] != NULL)
 399                                         strcpy(cpu_brand,
 400                                             cpu_brandtable[brand_index]);
 401                         }
 402                 }
 403 #else
 404                 /* Please make up your mind folks! */
 405                 strcat(cpu_model, "EM64T");
 406 #endif
 407                 break;
 408         case CPU_VENDOR_AMD:
 409                 /*
 410                  * Values taken from AMD Processor Recognition
 411                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 412                  * (also describes ``Features'' encodings.
 413                  */
 414                 strcpy(cpu_model, "AMD ");
 415 #ifdef __i386__
 416                 switch (cpu_id & 0xFF0) {
 417                 case 0x410:
 418                         strcat(cpu_model, "Standard Am486DX");
 419                         break;
 420                 case 0x430:
 421                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 422                         break;
 423                 case 0x470:
 424                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 425                         break;
 426                 case 0x480:
 427                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 428                         break;
 429                 case 0x490:
 430                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 431                         break;
 432                 case 0x4E0:
 433                         strcat(cpu_model, "Am5x86 Write-Through");
 434                         break;
 435                 case 0x4F0:
 436                         strcat(cpu_model, "Am5x86 Write-Back");
 437                         break;
 438                 case 0x500:
 439                         strcat(cpu_model, "K5 model 0");
 440                         break;
 441                 case 0x510:
 442                         strcat(cpu_model, "K5 model 1");
 443                         break;
 444                 case 0x520:
 445                         strcat(cpu_model, "K5 PR166 (model 2)");
 446                         break;
 447                 case 0x530:
 448                         strcat(cpu_model, "K5 PR200 (model 3)");
 449                         break;
 450                 case 0x560:
 451                         strcat(cpu_model, "K6");
 452                         break;
 453                 case 0x570:
 454                         strcat(cpu_model, "K6 266 (model 1)");
 455                         break;
 456                 case 0x580:
 457                         strcat(cpu_model, "K6-2");
 458                         break;
 459                 case 0x590:
 460                         strcat(cpu_model, "K6-III");
 461                         break;
 462                 case 0x5a0:
 463                         strcat(cpu_model, "Geode LX");
 464                         break;
 465                 default:
 466                         strcat(cpu_model, "Unknown");
 467                         break;
 468                 }
 469 #else
 470                 if ((cpu_id & 0xf00) == 0xf00)
 471                         strcat(cpu_model, "AMD64 Processor");
 472                 else
 473                         strcat(cpu_model, "Unknown");
 474 #endif
 475                 break;
 476 #ifdef __i386__
 477         case CPU_VENDOR_CYRIX:
 478                 strcpy(cpu_model, "Cyrix ");
 479                 switch (cpu_id & 0xff0) {
 480                 case 0x440:
 481                         strcat(cpu_model, "MediaGX");
 482                         break;
 483                 case 0x520:
 484                         strcat(cpu_model, "6x86");
 485                         break;
 486                 case 0x540:
 487                         cpu_class = CPUCLASS_586;
 488                         strcat(cpu_model, "GXm");
 489                         break;
 490                 case 0x600:
 491                         strcat(cpu_model, "6x86MX");
 492                         break;
 493                 default:
 494                         /*
 495                          * Even though CPU supports the cpuid
 496                          * instruction, it can be disabled.
 497                          * Therefore, this routine supports all Cyrix
 498                          * CPUs.
 499                          */
 500                         switch (cyrix_did & 0xf0) {
 501                         case 0x00:
 502                                 switch (cyrix_did & 0x0f) {
 503                                 case 0x00:
 504                                         strcat(cpu_model, "486SLC");
 505                                         break;
 506                                 case 0x01:
 507                                         strcat(cpu_model, "486DLC");
 508                                         break;
 509                                 case 0x02:
 510                                         strcat(cpu_model, "486SLC2");
 511                                         break;
 512                                 case 0x03:
 513                                         strcat(cpu_model, "486DLC2");
 514                                         break;
 515                                 case 0x04:
 516                                         strcat(cpu_model, "486SRx");
 517                                         break;
 518                                 case 0x05:
 519                                         strcat(cpu_model, "486DRx");
 520                                         break;
 521                                 case 0x06:
 522                                         strcat(cpu_model, "486SRx2");
 523                                         break;
 524                                 case 0x07:
 525                                         strcat(cpu_model, "486DRx2");
 526                                         break;
 527                                 case 0x08:
 528                                         strcat(cpu_model, "486SRu");
 529                                         break;
 530                                 case 0x09:
 531                                         strcat(cpu_model, "486DRu");
 532                                         break;
 533                                 case 0x0a:
 534                                         strcat(cpu_model, "486SRu2");
 535                                         break;
 536                                 case 0x0b:
 537                                         strcat(cpu_model, "486DRu2");
 538                                         break;
 539                                 default:
 540                                         strcat(cpu_model, "Unknown");
 541                                         break;
 542                                 }
 543                                 break;
 544                         case 0x10:
 545                                 switch (cyrix_did & 0x0f) {
 546                                 case 0x00:
 547                                         strcat(cpu_model, "486S");
 548                                         break;
 549                                 case 0x01:
 550                                         strcat(cpu_model, "486S2");
 551                                         break;
 552                                 case 0x02:
 553                                         strcat(cpu_model, "486Se");
 554                                         break;
 555                                 case 0x03:
 556                                         strcat(cpu_model, "486S2e");
 557                                         break;
 558                                 case 0x0a:
 559                                         strcat(cpu_model, "486DX");
 560                                         break;
 561                                 case 0x0b:
 562                                         strcat(cpu_model, "486DX2");
 563                                         break;
 564                                 case 0x0f:
 565                                         strcat(cpu_model, "486DX4");
 566                                         break;
 567                                 default:
 568                                         strcat(cpu_model, "Unknown");
 569                                         break;
 570                                 }
 571                                 break;
 572                         case 0x20:
 573                                 if ((cyrix_did & 0x0f) < 8)
 574                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 575                                 else
 576                                         strcat(cpu_model, "5x86");
 577                                 break;
 578                         case 0x30:
 579                                 strcat(cpu_model, "6x86");
 580                                 break;
 581                         case 0x40:
 582                                 if ((cyrix_did & 0xf000) == 0x3000) {
 583                                         cpu_class = CPUCLASS_586;
 584                                         strcat(cpu_model, "GXm");
 585                                 } else
 586                                         strcat(cpu_model, "MediaGX");
 587                                 break;
 588                         case 0x50:
 589                                 strcat(cpu_model, "6x86MX");
 590                                 break;
 591                         case 0xf0:
 592                                 switch (cyrix_did & 0x0f) {
 593                                 case 0x0d:
 594                                         strcat(cpu_model, "Overdrive CPU");
 595                                         break;
 596                                 case 0x0e:
 597                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 598                                         break;
 599                                 case 0x0f:
 600                                         strcat(cpu_model, "486SLC/DLC");
 601                                         break;
 602                                 default:
 603                                         strcat(cpu_model, "Unknown");
 604                                         break;
 605                                 }
 606                                 break;
 607                         default:
 608                                 strcat(cpu_model, "Unknown");
 609                                 break;
 610                         }
 611                         break;
 612                 }
 613                 break;
 614         case CPU_VENDOR_RISE:
 615                 strcpy(cpu_model, "Rise ");
 616                 switch (cpu_id & 0xff0) {
 617                 case 0x500:     /* 6401 and 6441 (Kirin) */
 618                 case 0x520:     /* 6510 (Lynx) */
 619                         strcat(cpu_model, "mP6");
 620                         break;
 621                 default:
 622                         strcat(cpu_model, "Unknown");
 623                 }
 624                 break;
 625 #endif
 626         case CPU_VENDOR_CENTAUR:
 627 #ifdef __i386__
 628                 switch (cpu_id & 0xff0) {
 629                 case 0x540:
 630                         strcpy(cpu_model, "IDT WinChip C6");
 631                         break;
 632                 case 0x580:
 633                         strcpy(cpu_model, "IDT WinChip 2");
 634                         break;
 635                 case 0x590:
 636                         strcpy(cpu_model, "IDT WinChip 3");
 637                         break;
 638                 case 0x660:
 639                         strcpy(cpu_model, "VIA C3 Samuel");
 640                         break;
 641                 case 0x670:
 642                         if (cpu_id & 0x8)
 643                                 strcpy(cpu_model, "VIA C3 Ezra");
 644                         else
 645                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 646                         break;
 647                 case 0x680:
 648                         strcpy(cpu_model, "VIA C3 Ezra-T");
 649                         break;
 650                 case 0x690:
 651                         strcpy(cpu_model, "VIA C3 Nehemiah");
 652                         break;
 653                 case 0x6a0:
 654                 case 0x6d0:
 655                         strcpy(cpu_model, "VIA C7 Esther");
 656                         break;
 657                 case 0x6f0:
 658                         strcpy(cpu_model, "VIA Nano");
 659                         break;
 660                 default:
 661                         strcpy(cpu_model, "VIA/IDT Unknown");
 662                 }
 663 #else
 664                 strcpy(cpu_model, "VIA ");
 665                 if ((cpu_id & 0xff0) == 0x6f0)
 666                         strcat(cpu_model, "Nano Processor");
 667                 else
 668                         strcat(cpu_model, "Unknown");
 669 #endif
 670                 break;
 671 #ifdef __i386__
 672         case CPU_VENDOR_IBM:
 673                 strcpy(cpu_model, "Blue Lightning CPU");
 674                 break;
 675         case CPU_VENDOR_NSC:
 676                 switch (cpu_id & 0xff0) {
 677                 case 0x540:
 678                         strcpy(cpu_model, "Geode SC1100");
 679                         cpu = CPU_GEODE1100;
 680                         break;
 681                 default:
 682                         strcpy(cpu_model, "Geode/NSC unknown");
 683                         break;
 684                 }
 685                 break;
 686 #endif
 687         case CPU_VENDOR_HYGON:
 688                 strcpy(cpu_model, "Hygon ");
 689 #ifdef __i386__
 690                 strcat(cpu_model, "Unknown");
 691 #else
 692                 if ((cpu_id & 0xf00) == 0xf00)
 693                         strcat(cpu_model, "AMD64 Processor");
 694                 else
 695                         strcat(cpu_model, "Unknown");
 696 #endif
 697                 break;
 698
 699         default:
 700                 strcat(cpu_model, "Unknown");
 701                 break;
 702         }
 703
 704         /*
 705          * Replace cpu_model with cpu_brand minus leading spaces if
 706          * we have one.
 707          */
 708         brand = cpu_brand;
 709         while (*brand == ' ')
 710                 ++brand;
 711         if (*brand != '\0')
 712                 strcpy(cpu_model, brand);
 713
 714         printf("%s (", cpu_model);
 715         if (tsc_freq != 0) {
 716                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 717                 printf("%jd.%02d-MHz ",
 718                     (intmax_t)(tsc_freq + 4999) / 1000000,
 719                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 720         }
 721 #ifdef __i386__
 722         switch(cpu_class) {
 723         case CPUCLASS_286:
 724                 printf("286");
 725                 break;
 726         case CPUCLASS_386:
 727                 printf("386");
 728                 break;
 729 #if defined(I486_CPU)
 730         case CPUCLASS_486:
 731                 printf("486");
 732                 break;
 733 #endif
 734 #if defined(I586_CPU)
 735         case CPUCLASS_586:
 736                 printf("586");
 737                 break;
 738 #endif
 739 #if defined(I686_CPU)
 740         case CPUCLASS_686:
 741                 printf("686");
 742                 break;
 743 #endif
 744         default:
 745                 printf("Unknown");      /* will panic below... */
 746         }
 747 #else
 748         printf("K8");
 749 #endif
 750         printf("-class CPU)\n");
 751         if (*cpu_vendor)
 752                 printf("  Origin=\"%s\"", cpu_vendor);
 753         if (cpu_id)
 754                 printf("  Id=0x%x", cpu_id);
 755
 756         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 757             cpu_vendor_id == CPU_VENDOR_AMD ||
 758             cpu_vendor_id == CPU_VENDOR_HYGON ||
 759             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 760 #ifdef __i386__
 761             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 762             cpu_vendor_id == CPU_VENDOR_RISE ||
 763             cpu_vendor_id == CPU_VENDOR_NSC ||
 764             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 765 #endif
 766             0) {
 767                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 768                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 769                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 770 #ifdef __i386__
 771                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 772                         printf("\n  DIR=0x%04x", cyrix_did);
 773 #endif
 774
 775                 /*
 776                  * AMD CPUID Specification
 777                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 778                  *
 779                  * Intel Processor Identification and CPUID Instruction
 780                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 781                  */
 782                 if (cpu_high > 0) {
 783                         /*
 784                          * Here we should probably set up flags indicating
 785                          * whether or not various features are available.
 786                          * The interesting ones are probably VME, PSE, PAE,
 787                          * and PGE.  The code already assumes without bothering
 788                          * to check that all CPUs >= Pentium have a TSC and
 789                          * MSRs.
 790                          */
 791                         printf("\n  Features=0x%b", cpu_feature,
 792                         "\020"
 793                         "\001FPU"       /* Integral FPU */
 794                         "\002VME"       /* Extended VM86 mode support */
 795                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 796                         "\004PSE"       /* 4MByte page tables */
 797                         "\005TSC"       /* Timestamp counter */
 798                         "\006MSR"       /* Machine specific registers */
 799                         "\007PAE"       /* Physical address extension */
 800                         "\010MCE"       /* Machine Check support */
 801                         "\011CX8"       /* CMPEXCH8 instruction */
 802                         "\012APIC"      /* SMP local APIC */
 803                         "\013oldMTRR"   /* Previous implementation of MTRR */
 804                         "\014SEP"       /* Fast System Call */
 805                         "\015MTRR"      /* Memory Type Range Registers */
 806                         "\016PGE"       /* PG_G (global bit) support */
 807                         "\017MCA"       /* Machine Check Architecture */
 808                         "\020CMOV"      /* CMOV instruction */
 809                         "\021PAT"       /* Page attributes table */
 810                         "\022PSE36"     /* 36 bit address space support */
 811                         "\023PN"        /* Processor Serial number */
 812                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 813                         "\025<b20>"
 814                         "\026DTS"       /* Debug Trace Store */
 815                         "\027ACPI"      /* ACPI support */
 816                         "\030MMX"       /* MMX instructions */
 817                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 818                         "\032SSE"       /* Streaming SIMD Extensions */
 819                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 820                         "\034SS"        /* Self snoop */
 821                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 822                         "\036TM"        /* Thermal Monitor clock slowdown */
 823                         "\037IA64"      /* CPU can execute IA64 instructions */
 824                         "\040PBE"       /* Pending Break Enable */
 825                         );
 826
 827                         if (cpu_feature2 != 0) {
 828                                 printf("\n  Features2=0x%b", cpu_feature2,
 829                                 "\020"
 830                                 "\001SSE3"      /* SSE3 */
 831                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 832                                 "\003DTES64"    /* 64-bit Debug Trace */
 833                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 834                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 835                                 "\006VMX"       /* Virtual Machine Extensions */
 836                                 "\007SMX"       /* Safer Mode Extensions */
 837                                 "\010EST"       /* Enhanced SpeedStep */
 838                                 "\011TM2"       /* Thermal Monitor 2 */
 839                                 "\012SSSE3"     /* SSSE3 */
 840                                 "\013CNXT-ID"   /* L1 context ID available */
 841                                 "\014SDBG"      /* IA32 silicon debug */
 842                                 "\015FMA"       /* Fused Multiply Add */
 843                                 "\016CX16"      /* CMPXCHG16B Instruction */
 844                                 "\017xTPR"      /* Send Task Priority Messages*/
 845                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 846                                 "\021<b16>"
 847                                 "\022PCID"      /* Process-context Identifiers*/
 848                                 "\023DCA"       /* Direct Cache Access */
 849                                 "\024SSE4.1"    /* SSE 4.1 */
 850                                 "\025SSE4.2"    /* SSE 4.2 */
 851                                 "\026x2APIC"    /* xAPIC Extensions */
 852                                 "\027MOVBE"     /* MOVBE Instruction */
 853                                 "\030POPCNT"    /* POPCNT Instruction */
 854                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 855                                 "\032AESNI"     /* AES Crypto */
 856                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 857                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 858                                 "\035AVX"       /* Advanced Vector Extensions */
 859                                 "\036F16C"      /* Half-precision conversions */
 860                                 "\037RDRAND"    /* RDRAND Instruction */
 861                                 "\040HV"        /* Hypervisor */
 862                                 );
 863                         }
 864
 865                         if (amd_feature != 0) {
 866                                 printf("\n  AMD Features=0x%b", amd_feature,
 867                                 "\020"          /* in hex */
 868                                 "\001<s0>"      /* Same */
 869                                 "\002<s1>"      /* Same */
 870                                 "\003<s2>"      /* Same */
 871                                 "\004<s3>"      /* Same */
 872                                 "\005<s4>"      /* Same */
 873                                 "\006<s5>"      /* Same */
 874                                 "\007<s6>"      /* Same */
 875                                 "\010<s7>"      /* Same */
 876                                 "\011<s8>"      /* Same */
 877                                 "\012<s9>"      /* Same */
 878                                 "\013<b10>"     /* Undefined */
 879                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 880                                 "\015<s12>"     /* Same */
 881                                 "\016<s13>"     /* Same */
 882                                 "\017<s14>"     /* Same */
 883                                 "\020<s15>"     /* Same */
 884                                 "\021<s16>"     /* Same */
 885                                 "\022<s17>"     /* Same */
 886                                 "\023<b18>"     /* Reserved, unknown */
 887                                 "\024MP"        /* Multiprocessor Capable */
 888                                 "\025NX"        /* Has EFER.NXE, NX */
 889                                 "\026<b21>"     /* Undefined */
 890                                 "\027MMX+"      /* AMD MMX Extensions */
 891                                 "\030<s23>"     /* Same */
 892                                 "\031<s24>"     /* Same */
 893                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 894                                 "\033Page1GB"   /* 1-GB large page support */
 895                                 "\034RDTSCP"    /* RDTSCP */
 896                                 "\035<b28>"     /* Undefined */
 897                                 "\036LM"        /* 64 bit long mode */
 898                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 899                                 "\0403DNow!"    /* AMD 3DNow! */
 900                                 );
 901                         }
 902
 903                         if (amd_feature2 != 0) {
 904                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 905                                 "\020"
 906                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 907                                 "\002CMP"       /* CMP legacy */
 908                                 "\003SVM"       /* Secure Virtual Mode */
 909                                 "\004ExtAPIC"   /* Extended APIC register */
 910                                 "\005CR8"       /* CR8 in legacy mode */
 911                                 "\006ABM"       /* LZCNT instruction */
 912                                 "\007SSE4A"     /* SSE4A */
 913                                 "\010MAS"       /* Misaligned SSE mode */
 914                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 915                                 "\012OSVW"      /* OS visible workaround */
 916                                 "\013IBS"       /* Instruction based sampling */
 917                                 "\014XOP"       /* XOP extended instructions */
 918                                 "\015SKINIT"    /* SKINIT/STGI */
 919                                 "\016WDT"       /* Watchdog timer */
 920                                 "\017<b14>"
 921                                 "\020LWP"       /* Lightweight Profiling */
 922                                 "\021FMA4"      /* 4-operand FMA instructions */
 923                                 "\022TCE"       /* Translation Cache Extension */
 924                                 "\023<b18>"
 925                                 "\024NodeId"    /* NodeId MSR support */
 926                                 "\025<b20>"
 927                                 "\026TBM"       /* Trailing Bit Manipulation */
 928                                 "\027Topology"  /* Topology Extensions */
 929                                 "\030PCXC"      /* Core perf count */
 930                                 "\031PNXC"      /* NB perf count */
 931                                 "\032<b25>"
 932                                 "\033DBE"       /* Data Breakpoint extension */
 933                                 "\034PTSC"      /* Performance TSC */
 934                                 "\035PL2I"      /* L2I perf count */
 935                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 936                                 "\037ADMSKX"    /* Address mask extension */
 937                                 "\040<b31>"
 938                                 );
 939                         }
 940
 941                         if (cpu_stdext_feature != 0) {
 942                                 printf("\n  Structured Extended Features=0x%b",
 943                                     cpu_stdext_feature,
 944                                        "\020"
 945                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 946                                        "\001FSGSBASE"
 947                                        "\002TSCADJ"
 948                                        "\003SGX"
 949                                        /* Bit Manipulation Instructions */
 950                                        "\004BMI1"
 951                                        /* Hardware Lock Elision */
 952                                        "\005HLE"
 953                                        /* Advanced Vector Instructions 2 */
 954                                        "\006AVX2"
 955                                        /* FDP_EXCPTN_ONLY */
 956                                        "\007FDPEXC"
 957                                        /* Supervisor Mode Execution Prot. */
 958                                        "\010SMEP"
 959                                        /* Bit Manipulation Instructions */
 960                                        "\011BMI2"
 961                                        "\012ERMS"
 962                                        /* Invalidate Processor Context ID */
 963                                        "\013INVPCID"
 964                                        /* Restricted Transactional Memory */
 965                                        "\014RTM"
 966                                        "\015PQM"
 967                                        "\016NFPUSG"
 968                                        /* Intel Memory Protection Extensions */
 969                                        "\017MPX"
 970                                        "\020PQE"
 971                                        /* AVX512 Foundation */
 972                                        "\021AVX512F"
 973                                        "\022AVX512DQ"
 974                                        /* Enhanced NRBG */
 975                                        "\023RDSEED"
 976                                        /* ADCX + ADOX */
 977                                        "\024ADX"
 978                                        /* Supervisor Mode Access Prevention */
 979                                        "\025SMAP"
 980                                        "\026AVX512IFMA"
 981                                        /* Formerly PCOMMIT */
 982                                        "\027<b22>"
 983                                        "\030CLFLUSHOPT"
 984                                        "\031CLWB"
 985                                        "\032PROCTRACE"
 986                                        "\033AVX512PF"
 987                                        "\034AVX512ER"
 988                                        "\035AVX512CD"
 989                                        "\036SHA"
 990                                        "\037AVX512BW"
 991                                        "\040AVX512VL"
 992                                        );
 993                         }
 994
 995                         if (cpu_stdext_feature2 != 0) {
 996                                 printf("\n  Structured Extended Features2=0x%b",
 997                                     cpu_stdext_feature2,
 998                                        "\020"
 999                                        "\001PREFETCHWT1"
1000                                        "\002AVX512VBMI"
1001                                        "\003UMIP"
1002                                        "\004PKU"
1003                                        "\005OSPKE"
1004                                        "\006WAITPKG"
1005                                        "\007AVX512VBMI2"
1006                                        "\011GFNI"
1007                                        "\012VAES"
1008                                        "\013VPCLMULQDQ"
1009                                        "\014AVX512VNNI"
1010                                        "\015AVX512BITALG"
1011                                        "\016TME"
1012                                        "\017AVX512VPOPCNTDQ"
1013                                        "\021LA57"
1014                                        "\027RDPID"
1015                                        "\032CLDEMOTE"
1016                                        "\034MOVDIRI"
1017                                        "\035MOVDIR64B"
1018                                        "\036ENQCMD"
1019                                        "\037SGXLC"
1020                                        );
1021                         }
1022
1023                         if (cpu_stdext_feature3 != 0) {
1024                                 printf("\n  Structured Extended Features3=0x%b",
1025                                     cpu_stdext_feature3,
1026                                        "\020"
1027                                        "\003AVX512_4VNNIW"
1028                                        "\004AVX512_4FMAPS"
1029                                        "\005FSRM"
1030                                        "\011AVX512VP2INTERSECT"
1031                                        "\012MCUOPT"
1032                                        "\013MD_CLEAR"
1033                                        "\016TSXFA"
1034                                        "\023PCONFIG"
1035                                        "\025IBT"
1036                                        "\033IBPB"
1037                                        "\034STIBP"
1038                                        "\035L1DFL"
1039                                        "\036ARCH_CAP"
1040                                        "\037CORE_CAP"
1041                                        "\040SSBD"
1042                                        );
1043                         }
1044
1045                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1046                                 cpuid_count(0xd, 0x1, regs);
1047                                 if (regs[0] != 0) {
1048                                         printf("\n  XSAVE Features=0x%b",
1049                                             regs[0],
1050                                             "\020"
1051                                             "\001XSAVEOPT"
1052                                             "\002XSAVEC"
1053                                             "\003XINUSE"
1054                                             "\004XSAVES");
1055                                 }
1056                         }
1057
1058                         if (cpu_ia32_arch_caps != 0) {
1059                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1060                                     (u_int)cpu_ia32_arch_caps,
1061                                        "\020"
1062                                        "\001RDCL_NO"
1063                                        "\002IBRS_ALL"
1064                                        "\003RSBA"
1065                                        "\004SKIP_L1DFL_VME"
1066                                        "\005SSB_NO"
1067                                        "\006MDS_NO"
1068                                        "\010TSX_CTRL"
1069                                        "\011TAA_NO"
1070                                        );
1071                         }
1072
1073                         if (amd_extended_feature_extensions != 0) {
1074                                 u_int amd_fe_masked;
1075
1076                                 amd_fe_masked = amd_extended_feature_extensions;
1077                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1078                                         amd_fe_masked &=
1079                                             ~(AMDFEID_IBRS_ALWAYSON |
1080                                                 AMDFEID_PREFER_IBRS);
1081                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1082                                         amd_fe_masked &=
1083                                             ~AMDFEID_STIBP_ALWAYSON;
1084
1085                                 printf("\n  "
1086                                     "AMD Extended Feature Extensions ID EBX="
1087                                     "0x%b", amd_fe_masked,
1088                                     "\020"
1089                                     "\001CLZERO"
1090                                     "\002IRPerf"
1091                                     "\003XSaveErPtr"
1092                                     "\005RDPRU"
1093                                     "\011MCOMMIT"
1094                                     "\012WBNOINVD"
1095                                     "\015IBPB"
1096                                     "\017IBRS"
1097                                     "\020STIBP"
1098                                     "\021IBRS_ALWAYSON"
1099                                     "\022STIBP_ALWAYSON"
1100                                     "\023PREFER_IBRS"
1101                                     "\030PPIN"
1102                                     "\031SSBD"
1103                                     "\032VIRT_SSBD"
1104                                     "\033SSB_NO"
1105                                     );
1106                         }
1107
1108                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1109                                 print_via_padlock_info();
1110
1111                         if (cpu_feature2 & CPUID2_VMX)
1112                                 print_vmx_info();
1113
1114                         if (amd_feature2 & AMDID2_SVM)
1115                                 print_svm_info();
1116
1117                         if ((cpu_feature & CPUID_HTT) &&
1118                             (cpu_vendor_id == CPU_VENDOR_AMD ||
1119                              cpu_vendor_id == CPU_VENDOR_HYGON))
1120                                 cpu_feature &= ~CPUID_HTT;
1121
1122                         /*
1123                          * If this CPU supports P-state invariant TSC then
1124                          * mention the capability.
1125                          */
1126                         if (tsc_is_invariant) {
1127                                 printf("\n  TSC: P-state invariant");
1128                                 if (tsc_perf_stat)
1129                                         printf(", performance statistics");
1130                         }
1131                 }
1132 #ifdef __i386__
1133         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1134                 printf("  DIR=0x%04x", cyrix_did);
1135                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1136                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1137 #ifndef CYRIX_CACHE_REALLY_WORKS
1138                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1139                         printf("\n  CPU cache: write-through mode");
1140 #endif
1141 #endif
1142         }
1143
1144         /* Avoid ugly blank lines: only print newline when we have to. */
1145         if (*cpu_vendor || cpu_id)
1146                 printf("\n");
1147
1148         if (bootverbose) {
1149                 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1150                     cpu_vendor_id == CPU_VENDOR_HYGON)
1151                         print_AMD_info();
1152                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1153                         print_INTEL_info();
1154 #ifdef __i386__
1155                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1156                         print_transmeta_info();
1157 #endif
1158         }
1159
1160         print_hypervisor_info();
1161 }
1162
1163 #ifdef __i386__
1164 void
1165 panicifcpuunsupported(void)
1166 {
1167
1168 #if !defined(lint)
1169 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1170 #error This kernel is not configured for one of the supported CPUs
1171 #endif
1172 #else /* lint */
1173 #endif /* lint */
1174         /*
1175          * Now that we have told the user what they have,
1176          * let them know if that machine type isn't configured.
1177          */
1178         switch (cpu_class) {
1179         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1180         case CPUCLASS_386:
1181 #if !defined(I486_CPU)
1182         case CPUCLASS_486:
1183 #endif
1184 #if !defined(I586_CPU)
1185         case CPUCLASS_586:
1186 #endif
1187 #if !defined(I686_CPU)
1188         case CPUCLASS_686:
1189 #endif
1190                 panic("CPU class not configured");
1191         default:
1192                 break;
1193         }
1194 }
1195
1196 static  volatile u_int trap_by_rdmsr;
1197
1198 /*
1199  * Special exception 6 handler.
1200  * The rdmsr instruction generates invalid opcodes fault on 486-class
1201  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1202  * function identblue() when this handler is called.  Stacked eip should
1203  * be advanced.
1204  */
1205 inthand_t       bluetrap6;
1206 __asm
1207 ("                                                                      \n\
1208         .text                                                           \n\
1209         .p2align 2,0x90                                                 \n\
1210         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1211 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1212         ss                                                              \n\
1213         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1214         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1215         iret                                                            \n\
1216 ");
1217
1218 /*
1219  * Special exception 13 handler.
1220  * Accessing non-existent MSR generates general protection fault.
1221  */
1222 inthand_t       bluetrap13;
1223 __asm
1224 ("                                                                      \n\
1225         .text                                                           \n\
1226         .p2align 2,0x90                                                 \n\
1227         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1228 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1229         ss                                                              \n\
1230         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1231         popl    %eax            /* discard error code */                \n\
1232         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1233         iret                                                            \n\
1234 ");
1235
1236 /*
1237  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1238  * support cpuid instruction.  This function should be called after
1239  * loading interrupt descriptor table register.
1240  *
1241  * I don't like this method that handles fault, but I couldn't get
1242  * information for any other methods.  Does blue giant know?
1243  */
1244 static int
1245 identblue(void)
1246 {
1247
1248         trap_by_rdmsr = 0;
1249
1250         /*
1251          * Cyrix 486-class CPU does not support rdmsr instruction.
1252          * The rdmsr instruction generates invalid opcode fault, and exception
1253          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1254          * bluetrap6() set the magic number to trap_by_rdmsr.
1255          */
1256         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1257             GSEL(GCODE_SEL, SEL_KPL));
1258
1259         /*
1260          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1261          * In this case, rdmsr generates general protection fault, and
1262          * exception will be trapped by bluetrap13().
1263          */
1264         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1265             GSEL(GCODE_SEL, SEL_KPL));
1266
1267         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1268
1269         if (trap_by_rdmsr == 0xa8c1d)
1270                 return IDENTBLUE_CYRIX486;
1271         else if (trap_by_rdmsr == 0xa89c4)
1272                 return IDENTBLUE_CYRIXM2;
1273         return IDENTBLUE_IBMCPU;
1274 }
1275
1276 /*
1277  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1278  *
1279  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1280  * +-------+-------+---------------+
1281  * |  SID  |  RID  |   Device ID   |
1282  * |    (DIR 1)    |    (DIR 0)    |
1283  * +-------+-------+---------------+
1284  */
1285 static void
1286 identifycyrix(void)
1287 {
1288         register_t saveintr;
1289         int     ccr2_test = 0, dir_test = 0;
1290         u_char  ccr2, ccr3;
1291
1292         saveintr = intr_disable();
1293
1294         ccr2 = read_cyrix_reg(CCR2);
1295         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1296         read_cyrix_reg(CCR2);
1297         if (read_cyrix_reg(CCR2) != ccr2)
1298                 ccr2_test = 1;
1299         write_cyrix_reg(CCR2, ccr2);
1300
1301         ccr3 = read_cyrix_reg(CCR3);
1302         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1303         read_cyrix_reg(CCR3);
1304         if (read_cyrix_reg(CCR3) != ccr3)
1305                 dir_test = 1;                                   /* CPU supports DIRs. */
1306         write_cyrix_reg(CCR3, ccr3);
1307
1308         if (dir_test) {
1309                 /* Device ID registers are available. */
1310                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1311                 cyrix_did += read_cyrix_reg(DIR0);
1312         } else if (ccr2_test)
1313                 cyrix_did = 0x0010;             /* 486S A-step */
1314         else
1315                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1316
1317         intr_restore(saveintr);
1318 }
1319 #endif
1320
1321 /* Update TSC freq with the value indicated by the caller. */
1322 static void
1323 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1324 {
1325
1326         /* If there was an error during the transition, don't do anything. */
1327         if (status != 0)
1328                 return;
1329
1330         /* Total setting for this level gives the new frequency in MHz. */
1331         hw_clockrate = level->total_set.freq;
1332 }
1333
1334 static void
1335 hook_tsc_freq(void *arg __unused)
1336 {
1337
1338         if (tsc_is_invariant)
1339                 return;
1340
1341         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1342             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1343 }
1344
1345 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1346
1347 static struct {
1348         const char      *vm_cpuid;
1349         int             vm_guest;
1350         void            (*init)(void);
1351 } vm_cpuids[] = {
1352         { "XenVMMXenVMM",       VM_GUEST_XEN,
1353 #ifdef XENHVM
1354           &xen_early_init,
1355 #endif
1356         },                                              /* XEN */
1357         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1358         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1359         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1360         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1361         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1362 };
1363
1364 static void
1365 identify_hypervisor_cpuid_base(void)
1366 {
1367         void (*init_fn)(void) = NULL;
1368         u_int leaf, regs[4];
1369         int i;
1370
1371         /*
1372          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1373          * http://lkml.org/lkml/2008/10/1/246
1374          *
1375          * KB1009458: Mechanisms to determine if software is running in
1376          * a VMware virtual machine
1377          * http://kb.vmware.com/kb/1009458
1378          *
1379          * Search for a hypervisor that we recognize. If we cannot find
1380          * a specific hypervisor, return the first information about the
1381          * hypervisor that we found, as others may be able to use.
1382          */
1383         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1384                 do_cpuid(leaf, regs);
1385
1386                 /*
1387                  * KVM from Linux kernels prior to commit
1388                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1389                  * to 0 rather than a valid hv_high value.  Check for
1390                  * the KVM signature bytes and fixup %eax to the
1391                  * highest supported leaf in that case.
1392                  */
1393                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1394                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1395                         regs[0] = leaf + 1;
1396
1397                 if (regs[0] >= leaf) {
1398                         enum VM_GUEST prev_vm_guest = vm_guest;
1399
1400                         for (i = 0; i < nitems(vm_cpuids); i++)
1401                                 if (strncmp((const char *)&regs[1],
1402                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1403                                         vm_guest = vm_cpuids[i].vm_guest;
1404                                         init_fn = vm_cpuids[i].init;
1405                                         break;
1406                                 }
1407
1408                         /*
1409                          * If this is the first entry or we found a
1410                          * specific hypervisor, record the base, high value,
1411                          * and vendor identifier.
1412                          */
1413                         if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1414                                 hv_base = leaf;
1415                                 hv_high = regs[0];
1416                                 ((u_int *)&hv_vendor)[0] = regs[1];
1417                                 ((u_int *)&hv_vendor)[1] = regs[2];
1418                                 ((u_int *)&hv_vendor)[2] = regs[3];
1419                                 hv_vendor[12] = '\0';
1420
1421                                 /*
1422                                  * If we found a specific hypervisor, then
1423                                  * we are finished.
1424                                  */
1425                                 if (vm_guest != VM_GUEST_VM &&
1426                                     /*
1427                                      * Xen and other hypervisors can expose the
1428                                      * HyperV signature in addition to the
1429                                      * native one in order to support Viridian
1430                                      * extensions for Windows guests.
1431                                      *
1432                                      * Do the full cpuid scan if HyperV is
1433                                      * detected, as the native hypervisor is
1434                                      * preferred.
1435                                      */
1436                                     vm_guest != VM_GUEST_HV)
1437                                         break;
1438                         }
1439                 }
1440         }
1441
1442         if (init_fn != NULL)
1443                 init_fn();
1444 }
1445
1446 void
1447 identify_hypervisor(void)
1448 {
1449         u_int regs[4];
1450         char *p;
1451
1452         TSENTER();
1453         /*
1454          * If CPUID2_HV is set, we are running in a hypervisor environment.
1455          */
1456         if (cpu_feature2 & CPUID2_HV) {
1457                 vm_guest = VM_GUEST_VM;
1458                 identify_hypervisor_cpuid_base();
1459
1460                 /* If we have a definitive vendor, we can return now. */
1461                 if (*hv_vendor != '\0') {
1462                         TSEXIT();
1463                         return;
1464                 }
1465         }
1466
1467         /*
1468          * Examine SMBIOS strings for older hypervisors.
1469          */
1470         p = kern_getenv("smbios.system.serial");
1471         if (p != NULL) {
1472                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1473                         vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1474                             VMW_HVCMD_DEFAULT_PARAM, regs);
1475                         if (regs[1] == VMW_HVMAGIC) {
1476                                 vm_guest = VM_GUEST_VMWARE;
1477                                 freeenv(p);
1478                                 TSEXIT();
1479                                 return;
1480                         }
1481                 }
1482                 freeenv(p);
1483         }
1484         TSEXIT();
1485 }
1486
1487 bool
1488 fix_cpuid(void)
1489 {
1490         uint64_t msr;
1491
1492         /*
1493          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1494          * get the largest standard CPUID function number again if it is set
1495          * from BIOS.  It is necessary for probing correct CPU topology later
1496          * and for the correct operation of the AVX-aware userspace.
1497          */
1498         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1499             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1500             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1501             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1502             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1503                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1504                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1505                         msr &= ~IA32_MISC_EN_LIMCPUID;
1506                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1507                         return (true);
1508                 }
1509         }
1510
1511         /*
1512          * Re-enable AMD Topology Extension that could be disabled by BIOS
1513          * on some notebook processors.  Without the extension it's really
1514          * hard to determine the correct CPU cache topology.
1515          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1516          * Models 60h-6Fh Processors, Publication # 50742.
1517          */
1518         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1519             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1520                 msr = rdmsr(MSR_EXTFEATURES);
1521                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1522                         msr |= (uint64_t)1 << 54;
1523                         wrmsr(MSR_EXTFEATURES, msr);
1524                         return (true);
1525                 }
1526         }
1527         return (false);
1528 }
1529
1530 void
1531 identify_cpu1(void)
1532 {
1533         u_int regs[4];
1534
1535         do_cpuid(0, regs);
1536         cpu_high = regs[0];
1537         ((u_int *)&cpu_vendor)[0] = regs[1];
1538         ((u_int *)&cpu_vendor)[1] = regs[3];
1539         ((u_int *)&cpu_vendor)[2] = regs[2];
1540         cpu_vendor[12] = '\0';
1541
1542         do_cpuid(1, regs);
1543         cpu_id = regs[0];
1544         cpu_procinfo = regs[1];
1545         cpu_feature = regs[3];
1546         cpu_feature2 = regs[2];
1547 }
1548
1549 void
1550 identify_cpu2(void)
1551 {
1552         u_int regs[4], cpu_stdext_disable;
1553
1554         if (cpu_high >= 6) {
1555                 cpuid_count(6, 0, regs);
1556                 cpu_power_eax = regs[0];
1557                 cpu_power_ebx = regs[1];
1558                 cpu_power_ecx = regs[2];
1559                 cpu_power_edx = regs[3];
1560         }
1561
1562         if (cpu_high >= 7) {
1563                 cpuid_count(7, 0, regs);
1564                 cpu_stdext_feature = regs[1];
1565
1566                 /*
1567                  * Some hypervisors failed to filter out unsupported
1568                  * extended features.  Allow to disable the
1569                  * extensions, activation of which requires setting a
1570                  * bit in CR4, and which VM monitors do not support.
1571                  */
1572                 cpu_stdext_disable = 0;
1573                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1574                 cpu_stdext_feature &= ~cpu_stdext_disable;
1575
1576                 cpu_stdext_feature2 = regs[2];
1577                 cpu_stdext_feature3 = regs[3];
1578
1579                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1580                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1581         }
1582 }
1583
1584 void
1585 identify_cpu_ext_features(void)
1586 {
1587         u_int regs[4];
1588
1589         if (cpu_high >= 7) {
1590                 cpuid_count(7, 0, regs);
1591                 cpu_stdext_feature2 = regs[2];
1592                 cpu_stdext_feature3 = regs[3];
1593         }
1594 }
1595
1596 void
1597 identify_cpu_fixup_bsp(void)
1598 {
1599         u_int regs[4];
1600
1601         cpu_vendor_id = find_cpu_vendor_id();
1602
1603         if (fix_cpuid()) {
1604                 do_cpuid(0, regs);
1605                 cpu_high = regs[0];
1606         }
1607 }
1608
1609 /*
1610  * Final stage of CPU identification.
1611  */
1612 void
1613 finishidentcpu(void)
1614 {
1615         u_int regs[4];
1616 #ifdef __i386__
1617         u_char ccr3;
1618 #endif
1619
1620         identify_cpu_fixup_bsp();
1621
1622         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1623                 do_cpuid(5, regs);
1624                 cpu_mon_mwait_flags = regs[2];
1625                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1626                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1627         }
1628
1629         identify_cpu2();
1630
1631 #ifdef __i386__
1632         if (cpu_high > 0 &&
1633             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1634              cpu_vendor_id == CPU_VENDOR_AMD ||
1635              cpu_vendor_id == CPU_VENDOR_HYGON ||
1636              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1637              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1638              cpu_vendor_id == CPU_VENDOR_NSC)) {
1639                 do_cpuid(0x80000000, regs);
1640                 if (regs[0] >= 0x80000000)
1641                         cpu_exthigh = regs[0];
1642         }
1643 #else
1644         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1645             cpu_vendor_id == CPU_VENDOR_AMD ||
1646             cpu_vendor_id == CPU_VENDOR_HYGON ||
1647             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1648                 do_cpuid(0x80000000, regs);
1649                 cpu_exthigh = regs[0];
1650         }
1651 #endif
1652         if (cpu_exthigh >= 0x80000001) {
1653                 do_cpuid(0x80000001, regs);
1654                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1655                 amd_feature2 = regs[2];
1656         }
1657         if (cpu_exthigh >= 0x80000007) {
1658                 do_cpuid(0x80000007, regs);
1659                 amd_rascap = regs[1];
1660                 amd_pminfo = regs[3];
1661         }
1662         if (cpu_exthigh >= 0x80000008) {
1663                 do_cpuid(0x80000008, regs);
1664                 cpu_maxphyaddr = regs[0] & 0xff;
1665                 amd_extended_feature_extensions = regs[1];
1666                 cpu_procinfo2 = regs[2];
1667         } else {
1668                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1669         }
1670
1671 #ifdef __i386__
1672         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1673                 if (cpu == CPU_486) {
1674                         /*
1675                          * These conditions are equivalent to:
1676                          *     - CPU does not support cpuid instruction.
1677                          *     - Cyrix/IBM CPU is detected.
1678                          */
1679                         if (identblue() == IDENTBLUE_IBMCPU) {
1680                                 strcpy(cpu_vendor, "IBM");
1681                                 cpu_vendor_id = CPU_VENDOR_IBM;
1682                                 cpu = CPU_BLUE;
1683                                 return;
1684                         }
1685                 }
1686                 switch (cpu_id & 0xf00) {
1687                 case 0x600:
1688                         /*
1689                          * Cyrix's datasheet does not describe DIRs.
1690                          * Therefor, I assume it does not have them
1691                          * and use the result of the cpuid instruction.
1692                          * XXX they seem to have it for now at least. -Peter
1693                          */
1694                         identifycyrix();
1695                         cpu = CPU_M2;
1696                         break;
1697                 default:
1698                         identifycyrix();
1699                         /*
1700                          * This routine contains a trick.
1701                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1702                          */
1703                         switch (cyrix_did & 0x00f0) {
1704                         case 0x00:
1705                         case 0xf0:
1706                                 cpu = CPU_486DLC;
1707                                 break;
1708                         case 0x10:
1709                                 cpu = CPU_CY486DX;
1710                                 break;
1711                         case 0x20:
1712                                 if ((cyrix_did & 0x000f) < 8)
1713                                         cpu = CPU_M1;
1714                                 else
1715                                         cpu = CPU_M1SC;
1716                                 break;
1717                         case 0x30:
1718                                 cpu = CPU_M1;
1719                                 break;
1720                         case 0x40:
1721                                 /* MediaGX CPU */
1722                                 cpu = CPU_M1SC;
1723                                 break;
1724                         default:
1725                                 /* M2 and later CPUs are treated as M2. */
1726                                 cpu = CPU_M2;
1727
1728                                 /*
1729                                  * enable cpuid instruction.
1730                                  */
1731                                 ccr3 = read_cyrix_reg(CCR3);
1732                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1733                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1734                                 write_cyrix_reg(CCR3, ccr3);
1735
1736                                 do_cpuid(0, regs);
1737                                 cpu_high = regs[0];     /* eax */
1738                                 do_cpuid(1, regs);
1739                                 cpu_id = regs[0];       /* eax */
1740                                 cpu_feature = regs[3];  /* edx */
1741                                 break;
1742                         }
1743                 }
1744         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1745                 /*
1746                  * There are BlueLightning CPUs that do not change
1747                  * undefined flags by dividing 5 by 2.  In this case,
1748                  * the CPU identification routine in locore.s leaves
1749                  * cpu_vendor null string and puts CPU_486 into the
1750                  * cpu.
1751                  */
1752                 if (identblue() == IDENTBLUE_IBMCPU) {
1753                         strcpy(cpu_vendor, "IBM");
1754                         cpu_vendor_id = CPU_VENDOR_IBM;
1755                         cpu = CPU_BLUE;
1756                         return;
1757                 }
1758         }
1759 #endif
1760 }
1761
1762 int
1763 pti_get_default(void)
1764 {
1765
1766         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1767             strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1768                 return (0);
1769         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1770                 return (0);
1771         return (1);
1772 }
1773
1774 static u_int
1775 find_cpu_vendor_id(void)
1776 {
1777         int     i;
1778
1779         for (i = 0; i < nitems(cpu_vendors); i++)
1780                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1781                         return (cpu_vendors[i].vendor_id);
1782         return (0);
1783 }
1784
1785 static void
1786 print_AMD_assoc(int i)
1787 {
1788         if (i == 255)
1789                 printf(", fully associative\n");
1790         else
1791                 printf(", %d-way associative\n", i);
1792 }
1793
1794 static void
1795 print_AMD_l2_assoc(int i)
1796 {
1797         switch (i & 0x0f) {
1798         case 0: printf(", disabled/not present\n"); break;
1799         case 1: printf(", direct mapped\n"); break;
1800         case 2: printf(", 2-way associative\n"); break;
1801         case 4: printf(", 4-way associative\n"); break;
1802         case 6: printf(", 8-way associative\n"); break;
1803         case 8: printf(", 16-way associative\n"); break;
1804         case 15: printf(", fully associative\n"); break;
1805         default: printf(", reserved configuration\n"); break;
1806         }
1807 }
1808
1809 static void
1810 print_AMD_info(void)
1811 {
1812 #ifdef __i386__
1813         uint64_t amd_whcr;
1814 #endif
1815         u_int regs[4];
1816
1817         if (cpu_exthigh >= 0x80000005) {
1818                 do_cpuid(0x80000005, regs);
1819                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1820                 print_AMD_assoc(regs[0] >> 24);
1821
1822                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1823                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1824
1825                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1826                 print_AMD_assoc(regs[1] >> 24);
1827
1828                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1829                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1830
1831                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1832                 printf(", %d bytes/line", regs[2] & 0xff);
1833                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1834                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1835
1836                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1837                 printf(", %d bytes/line", regs[3] & 0xff);
1838                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1839                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1840         }
1841
1842         if (cpu_exthigh >= 0x80000006) {
1843                 do_cpuid(0x80000006, regs);
1844                 if ((regs[0] >> 16) != 0) {
1845                         printf("L2 2MB data TLB: %d entries",
1846                             (regs[0] >> 16) & 0xfff);
1847                         print_AMD_l2_assoc(regs[0] >> 28);
1848                         printf("L2 2MB instruction TLB: %d entries",
1849                             regs[0] & 0xfff);
1850                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1851                 } else {
1852                         printf("L2 2MB unified TLB: %d entries",
1853                             regs[0] & 0xfff);
1854                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1855                 }
1856                 if ((regs[1] >> 16) != 0) {
1857                         printf("L2 4KB data TLB: %d entries",
1858                             (regs[1] >> 16) & 0xfff);
1859                         print_AMD_l2_assoc(regs[1] >> 28);
1860
1861                         printf("L2 4KB instruction TLB: %d entries",
1862                             (regs[1] >> 16) & 0xfff);
1863                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1864                 } else {
1865                         printf("L2 4KB unified TLB: %d entries",
1866                             (regs[1] >> 16) & 0xfff);
1867                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1868                 }
1869                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1870                 printf(", %d bytes/line", regs[2] & 0xff);
1871                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1872                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1873         }
1874
1875 #ifdef __i386__
1876         if (((cpu_id & 0xf00) == 0x500)
1877             && (((cpu_id & 0x0f0) > 0x80)
1878                 || (((cpu_id & 0x0f0) == 0x80)
1879                     && (cpu_id & 0x00f) > 0x07))) {
1880                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1881                 amd_whcr = rdmsr(0xc0000082);
1882                 if (!(amd_whcr & (0x3ff << 22))) {
1883                         printf("Write Allocate Disable\n");
1884                 } else {
1885                         printf("Write Allocate Enable Limit: %dM bytes\n",
1886                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1887                         printf("Write Allocate 15-16M bytes: %s\n",
1888                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1889                 }
1890         } else if (((cpu_id & 0xf00) == 0x500)
1891                    && ((cpu_id & 0x0f0) > 0x50)) {
1892                 /* K6, K6-2(old core) */
1893                 amd_whcr = rdmsr(0xc0000082);
1894                 if (!(amd_whcr & (0x7f << 1))) {
1895                         printf("Write Allocate Disable\n");
1896                 } else {
1897                         printf("Write Allocate Enable Limit: %dM bytes\n",
1898                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1899                         printf("Write Allocate 15-16M bytes: %s\n",
1900                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1901                         printf("Hardware Write Allocate Control: %s\n",
1902                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1903                 }
1904         }
1905 #endif
1906         /*
1907          * Opteron Rev E shows a bug as in very rare occasions a read memory
1908          * barrier is not performed as expected if it is followed by a
1909          * non-atomic read-modify-write instruction.
1910          * As long as that bug pops up very rarely (intensive machine usage
1911          * on other operating systems generally generates one unexplainable
1912          * crash any 2 months) and as long as a model specific fix would be
1913          * impractical at this stage, print out a warning string if the broken
1914          * model and family are identified.
1915          */
1916         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1917             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1918                 printf("WARNING: This architecture revision has known SMP "
1919                     "hardware bugs which may cause random instability\n");
1920 }
1921
1922 static void
1923 print_INTEL_info(void)
1924 {
1925         u_int regs[4];
1926         u_int rounds, regnum;
1927         u_int nwaycode, nway;
1928
1929         if (cpu_high >= 2) {
1930                 rounds = 0;
1931                 do {
1932                         do_cpuid(0x2, regs);
1933                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1934                                 break;  /* we have a buggy CPU */
1935
1936                         for (regnum = 0; regnum <= 3; ++regnum) {
1937                                 if (regs[regnum] & (1<<31))
1938                                         continue;
1939                                 if (regnum != 0)
1940                                         print_INTEL_TLB(regs[regnum] & 0xff);
1941                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1942                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1943                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1944                         }
1945                 } while (--rounds > 0);
1946         }
1947
1948         if (cpu_exthigh >= 0x80000006) {
1949                 do_cpuid(0x80000006, regs);
1950                 nwaycode = (regs[2] >> 12) & 0x0f;
1951                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1952                         nway = 1 << (nwaycode / 2);
1953                 else
1954                         nway = 0;
1955                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1956                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1957         }
1958 }
1959
1960 static void
1961 print_INTEL_TLB(u_int data)
1962 {
1963         switch (data) {
1964         case 0x0:
1965         case 0x40:
1966         default:
1967                 break;
1968         case 0x1:
1969                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1970                 break;
1971         case 0x2:
1972                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1973                 break;
1974         case 0x3:
1975                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1976                 break;
1977         case 0x4:
1978                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1979                 break;
1980         case 0x6:
1981                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1982                 break;
1983         case 0x8:
1984                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1985                 break;
1986         case 0x9:
1987                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1988                 break;
1989         case 0xa:
1990                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1991                 break;
1992         case 0xb:
1993                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1994                 break;
1995         case 0xc:
1996                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1997                 break;
1998         case 0xd:
1999                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2000                 break;
2001         case 0xe:
2002                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2003                 break;
2004         case 0x1d:
2005                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2006                 break;
2007         case 0x21:
2008                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2009                 break;
2010         case 0x22:
2011                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2012                 break;
2013         case 0x23:
2014                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2015                 break;
2016         case 0x24:
2017                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2018                 break;
2019         case 0x25:
2020                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2021                 break;
2022         case 0x29:
2023                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2024                 break;
2025         case 0x2c:
2026                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2027                 break;
2028         case 0x30:
2029                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2030                 break;
2031         case 0x39: /* De-listed in SDM rev. 54 */
2032                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2033                 break;
2034         case 0x3b: /* De-listed in SDM rev. 54 */
2035                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2036                 break;
2037         case 0x3c: /* De-listed in SDM rev. 54 */
2038                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2039                 break;
2040         case 0x41:
2041                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2042                 break;
2043         case 0x42:
2044                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2045                 break;
2046         case 0x43:
2047                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2048                 break;
2049         case 0x44:
2050                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2051                 break;
2052         case 0x45:
2053                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2054                 break;
2055         case 0x46:
2056                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2057                 break;
2058         case 0x47:
2059                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2060                 break;
2061         case 0x48:
2062                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2063                 break;
2064         case 0x49:
2065                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2066                     CPUID_TO_MODEL(cpu_id) == 0x6)
2067                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2068                 else
2069                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2070                 break;
2071         case 0x4a:
2072                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2073                 break;
2074         case 0x4b:
2075                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2076                 break;
2077         case 0x4c:
2078                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2079                 break;
2080         case 0x4d:
2081                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2082                 break;
2083         case 0x4e:
2084                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2085                 break;
2086         case 0x4f:
2087                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2088                 break;
2089         case 0x50:
2090                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2091                 break;
2092         case 0x51:
2093                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2094                 break;
2095         case 0x52:
2096                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2097                 break;
2098         case 0x55:
2099                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2100                 break;
2101         case 0x56:
2102                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2103                 break;
2104         case 0x57:
2105                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2106                 break;
2107         case 0x59:
2108                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2109                 break;
2110         case 0x5a:
2111                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2112                 break;
2113         case 0x5b:
2114                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2115                 break;
2116         case 0x5c:
2117                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2118                 break;
2119         case 0x5d:
2120                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2121                 break;
2122         case 0x60:
2123                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2124                 break;
2125         case 0x61:
2126                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2127                 break;
2128         case 0x63:
2129                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2130                 break;
2131         case 0x64:
2132                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2133                 break;
2134         case 0x66:
2135                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2136                 break;
2137         case 0x67:
2138                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2139                 break;
2140         case 0x68:
2141                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2142                 break;
2143         case 0x6a:
2144                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2145                 break;
2146         case 0x6b:
2147                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2148                 break;
2149         case 0x6c:
2150                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2151                 break;
2152         case 0x6d:
2153                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2154                 break;
2155         case 0x70:
2156                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2157                 break;
2158         case 0x71:
2159                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2160                 break;
2161         case 0x72:
2162                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2163                 break;
2164         case 0x76:
2165                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2166                 break;
2167         case 0x78:
2168                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2169                 break;
2170         case 0x79:
2171                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2172                 break;
2173         case 0x7a:
2174                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2175                 break;
2176         case 0x7b:
2177                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2178                 break;
2179         case 0x7c:
2180                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2181                 break;
2182         case 0x7d:
2183                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2184                 break;
2185         case 0x7f:
2186                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2187                 break;
2188         case 0x80:
2189                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2190                 break;
2191         case 0x82:
2192                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2193                 break;
2194         case 0x83:
2195                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2196                 break;
2197         case 0x84:
2198                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2199                 break;
2200         case 0x85:
2201                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2202                 break;
2203         case 0x86:
2204                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2205                 break;
2206         case 0x87:
2207                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2208                 break;
2209         case 0xa0:
2210                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2211                 break;
2212         case 0xb0:
2213                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2214                 break;
2215         case 0xb1:
2216                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2217                 break;
2218         case 0xb2:
2219                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2220                 break;
2221         case 0xb3:
2222                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2223                 break;
2224         case 0xb4:
2225                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2226                 break;
2227         case 0xb5:
2228                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2229                 break;
2230         case 0xb6:
2231                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2232                 break;
2233         case 0xba:
2234                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2235                 break;
2236         case 0xc0:
2237                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2238                 break;
2239         case 0xc1:
2240                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2241                 break;
2242         case 0xc2:
2243                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2244                 break;
2245         case 0xc3:
2246                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2247                 break;
2248         case 0xc4:
2249                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2250                 break;
2251         case 0xca:
2252                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2253                 break;
2254         case 0xd0:
2255                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2256                 break;
2257         case 0xd1:
2258                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2259                 break;
2260         case 0xd2:
2261                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2262                 break;
2263         case 0xd6:
2264                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2265                 break;
2266         case 0xd7:
2267                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2268                 break;
2269         case 0xd8:
2270                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2271                 break;
2272         case 0xdc:
2273                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2274                 break;
2275         case 0xdd:
2276                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2277                 break;
2278         case 0xde:
2279                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2280                 break;
2281         case 0xe2:
2282                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2283                 break;
2284         case 0xe3:
2285                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2286                 break;
2287         case 0xe4:
2288                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2289                 break;
2290         case 0xea:
2291                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2292                 break;
2293         case 0xeb:
2294                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2295                 break;
2296         case 0xec:
2297                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2298                 break;
2299         case 0xf0:
2300                 printf("64-Byte prefetching\n");
2301                 break;
2302         case 0xf1:
2303                 printf("128-Byte prefetching\n");
2304                 break;
2305         }
2306 }
2307
2308 static void
2309 print_svm_info(void)
2310 {
2311         u_int features, regs[4];
2312         uint64_t msr;
2313         int comma;
2314
2315         printf("\n  SVM: ");
2316         do_cpuid(0x8000000A, regs);
2317         features = regs[3];
2318
2319         msr = rdmsr(MSR_VM_CR);
2320         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2321                 printf("(disabled in BIOS) ");
2322
2323         if (!bootverbose) {
2324                 comma = 0;
2325                 if (features & (1 << 0)) {
2326                         printf("%sNP", comma ? "," : "");
2327                         comma = 1;
2328                 }
2329                 if (features & (1 << 3)) {
2330                         printf("%sNRIP", comma ? "," : "");
2331                         comma = 1;
2332                 }
2333                 if (features & (1 << 5)) {
2334                         printf("%sVClean", comma ? "," : "");
2335                         comma = 1;
2336                 }
2337                 if (features & (1 << 6)) {
2338                         printf("%sAFlush", comma ? "," : "");
2339                         comma = 1;
2340                 }
2341                 if (features & (1 << 7)) {
2342                         printf("%sDAssist", comma ? "," : "");
2343                         comma = 1;
2344                 }
2345                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2346                 return;
2347         }
2348
2349         printf("Features=0x%b", features,
2350                "\020"
2351                "\001NP"                 /* Nested paging */
2352                "\002LbrVirt"            /* LBR virtualization */
2353                "\003SVML"               /* SVM lock */
2354                "\004NRIPS"              /* NRIP save */
2355                "\005TscRateMsr"         /* MSR based TSC rate control */
2356                "\006VmcbClean"          /* VMCB clean bits */
2357                "\007FlushByAsid"        /* Flush by ASID */
2358                "\010DecodeAssist"       /* Decode assist */
2359                "\011<b8>"
2360                "\012<b9>"
2361                "\013PauseFilter"        /* PAUSE intercept filter */
2362                "\014EncryptedMcodePatch"
2363                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2364                "\016AVIC"               /* virtual interrupt controller */
2365                "\017<b14>"
2366                "\020V_VMSAVE_VMLOAD"
2367                "\021vGIF"
2368                "\022GMET"               /* Guest Mode Execute Trap */
2369                "\023<b18>"
2370                "\024<b19>"
2371                "\025GuesSpecCtl"        /* Guest Spec_ctl */
2372                "\026<b21>"
2373                "\027<b22>"
2374                "\030<b23>"
2375                "\031<b24>"
2376                "\032<b25>"
2377                "\033<b26>"
2378                "\034<b27>"
2379                "\035<b28>"
2380                "\036<b29>"
2381                "\037<b30>"
2382                "\040<b31>"
2383                );
2384         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2385 }
2386
2387 #ifdef __i386__
2388 static void
2389 print_transmeta_info(void)
2390 {
2391         u_int regs[4], nreg = 0;
2392
2393         do_cpuid(0x80860000, regs);
2394         nreg = regs[0];
2395         if (nreg >= 0x80860001) {
2396                 do_cpuid(0x80860001, regs);
2397                 printf("  Processor revision %u.%u.%u.%u\n",
2398                        (regs[1] >> 24) & 0xff,
2399                        (regs[1] >> 16) & 0xff,
2400                        (regs[1] >> 8) & 0xff,
2401                        regs[1] & 0xff);
2402         }
2403         if (nreg >= 0x80860002) {
2404                 do_cpuid(0x80860002, regs);
2405                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2406                        (regs[1] >> 24) & 0xff,
2407                        (regs[1] >> 16) & 0xff,
2408                        (regs[1] >> 8) & 0xff,
2409                        regs[1] & 0xff,
2410                        regs[2]);
2411         }
2412         if (nreg >= 0x80860006) {
2413                 char info[65];
2414                 do_cpuid(0x80860003, (u_int*) &info[0]);
2415                 do_cpuid(0x80860004, (u_int*) &info[16]);
2416                 do_cpuid(0x80860005, (u_int*) &info[32]);
2417                 do_cpuid(0x80860006, (u_int*) &info[48]);
2418                 info[64] = 0;
2419                 printf("  %s\n", info);
2420         }
2421 }
2422 #endif
2423
2424 static void
2425 print_via_padlock_info(void)
2426 {
2427         u_int regs[4];
2428
2429         do_cpuid(0xc0000001, regs);
2430         printf("\n  VIA Padlock Features=0x%b", regs[3],
2431         "\020"
2432         "\003RNG"               /* RNG */
2433         "\007AES"               /* ACE */
2434         "\011AES-CTR"           /* ACE2 */
2435         "\013SHA1,SHA256"       /* PHE */
2436         "\015RSA"               /* PMM */
2437         );
2438 }
2439
2440 static uint32_t
2441 vmx_settable(uint64_t basic, int msr, int true_msr)
2442 {
2443         uint64_t val;
2444
2445         if (basic & (1ULL << 55))
2446                 val = rdmsr(true_msr);
2447         else
2448                 val = rdmsr(msr);
2449
2450         /* Just report the controls that can be set to 1. */
2451         return (val >> 32);
2452 }
2453
2454 static void
2455 print_vmx_info(void)
2456 {
2457         uint64_t basic, msr;
2458         uint32_t entry, exit, mask, pin, proc, proc2;
2459         int comma;
2460
2461         printf("\n  VT-x: ");
2462         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2463         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2464                 printf("(disabled in BIOS) ");
2465         basic = rdmsr(MSR_VMX_BASIC);
2466         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2467             MSR_VMX_TRUE_PINBASED_CTLS);
2468         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2469             MSR_VMX_TRUE_PROCBASED_CTLS);
2470         if (proc & PROCBASED_SECONDARY_CONTROLS)
2471                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2472                     MSR_VMX_PROCBASED_CTLS2);
2473         else
2474                 proc2 = 0;
2475         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2476         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2477
2478         if (!bootverbose) {
2479                 comma = 0;
2480                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2481                     entry & VM_ENTRY_LOAD_PAT) {
2482                         printf("%sPAT", comma ? "," : "");
2483                         comma = 1;
2484                 }
2485                 if (proc & PROCBASED_HLT_EXITING) {
2486                         printf("%sHLT", comma ? "," : "");
2487                         comma = 1;
2488                 }
2489                 if (proc & PROCBASED_MTF) {
2490                         printf("%sMTF", comma ? "," : "");
2491                         comma = 1;
2492                 }
2493                 if (proc & PROCBASED_PAUSE_EXITING) {
2494                         printf("%sPAUSE", comma ? "," : "");
2495                         comma = 1;
2496                 }
2497                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2498                         printf("%sEPT", comma ? "," : "");
2499                         comma = 1;
2500                 }
2501                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2502                         printf("%sUG", comma ? "," : "");
2503                         comma = 1;
2504                 }
2505                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2506                         printf("%sVPID", comma ? "," : "");
2507                         comma = 1;
2508                 }
2509                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2510                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2511                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2512                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2513                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2514                         printf("%sVID", comma ? "," : "");
2515                         comma = 1;
2516                         if (pin & PINBASED_POSTED_INTERRUPT)
2517                                 printf(",PostIntr");
2518                 }
2519                 return;
2520         }
2521
2522         mask = basic >> 32;
2523         printf("Basic Features=0x%b", mask,
2524         "\020"
2525         "\02132PA"              /* 32-bit physical addresses */
2526         "\022SMM"               /* SMM dual-monitor */
2527         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2528         "\030TRUE"              /* TRUE_CTLS MSRs */
2529         );
2530         printf("\n        Pin-Based Controls=0x%b", pin,
2531         "\020"
2532         "\001ExtINT"            /* External-interrupt exiting */
2533         "\004NMI"               /* NMI exiting */
2534         "\006VNMI"              /* Virtual NMIs */
2535         "\007PreTmr"            /* Activate VMX-preemption timer */
2536         "\010PostIntr"          /* Process posted interrupts */
2537         );
2538         printf("\n        Primary Processor Controls=0x%b", proc,
2539         "\020"
2540         "\003INTWIN"            /* Interrupt-window exiting */
2541         "\004TSCOff"            /* Use TSC offsetting */
2542         "\010HLT"               /* HLT exiting */
2543         "\012INVLPG"            /* INVLPG exiting */
2544         "\013MWAIT"             /* MWAIT exiting */
2545         "\014RDPMC"             /* RDPMC exiting */
2546         "\015RDTSC"             /* RDTSC exiting */
2547         "\020CR3-LD"            /* CR3-load exiting */
2548         "\021CR3-ST"            /* CR3-store exiting */
2549         "\024CR8-LD"            /* CR8-load exiting */
2550         "\025CR8-ST"            /* CR8-store exiting */
2551         "\026TPR"               /* Use TPR shadow */
2552         "\027NMIWIN"            /* NMI-window exiting */
2553         "\030MOV-DR"            /* MOV-DR exiting */
2554         "\031IO"                /* Unconditional I/O exiting */
2555         "\032IOmap"             /* Use I/O bitmaps */
2556         "\034MTF"               /* Monitor trap flag */
2557         "\035MSRmap"            /* Use MSR bitmaps */
2558         "\036MONITOR"           /* MONITOR exiting */
2559         "\037PAUSE"             /* PAUSE exiting */
2560         );
2561         if (proc & PROCBASED_SECONDARY_CONTROLS)
2562                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2563                 "\020"
2564                 "\001APIC"              /* Virtualize APIC accesses */
2565                 "\002EPT"               /* Enable EPT */
2566                 "\003DT"                /* Descriptor-table exiting */
2567                 "\004RDTSCP"            /* Enable RDTSCP */
2568                 "\005x2APIC"            /* Virtualize x2APIC mode */
2569                 "\006VPID"              /* Enable VPID */
2570                 "\007WBINVD"            /* WBINVD exiting */
2571                 "\010UG"                /* Unrestricted guest */
2572                 "\011APIC-reg"          /* APIC-register virtualization */
2573                 "\012VID"               /* Virtual-interrupt delivery */
2574                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2575                 "\014RDRAND"            /* RDRAND exiting */
2576                 "\015INVPCID"           /* Enable INVPCID */
2577                 "\016VMFUNC"            /* Enable VM functions */
2578                 "\017VMCS"              /* VMCS shadowing */
2579                 "\020EPT#VE"            /* EPT-violation #VE */
2580                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2581                 );
2582         printf("\n        Exit Controls=0x%b", mask,
2583         "\020"
2584         "\003DR"                /* Save debug controls */
2585                                 /* Ignore Host address-space size */
2586         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2587         "\020AckInt"            /* Acknowledge interrupt on exit */
2588         "\023PAT-SV"            /* Save MSR_PAT */
2589         "\024PAT-LD"            /* Load MSR_PAT */
2590         "\025EFER-SV"           /* Save MSR_EFER */
2591         "\026EFER-LD"           /* Load MSR_EFER */
2592         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2593         );
2594         printf("\n        Entry Controls=0x%b", mask,
2595         "\020"
2596         "\003DR"                /* Save debug controls */
2597                                 /* Ignore IA-32e mode guest */
2598                                 /* Ignore Entry to SMM */
2599                                 /* Ignore Deactivate dual-monitor treatment */
2600         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2601         "\017PAT"               /* Load MSR_PAT */
2602         "\020EFER"              /* Load MSR_EFER */
2603         );
2604         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2605             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2606                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2607                 mask = msr;
2608                 printf("\n        EPT Features=0x%b", mask,
2609                 "\020"
2610                 "\001XO"                /* Execute-only translations */
2611                 "\007PW4"               /* Page-walk length of 4 */
2612                 "\011UC"                /* EPT paging-structure mem can be UC */
2613                 "\017WB"                /* EPT paging-structure mem can be WB */
2614                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2615                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2616                 "\025INVEPT"            /* INVEPT is supported */
2617                 "\026AD"                /* Accessed and dirty flags for EPT */
2618                 "\032single"            /* INVEPT single-context type */
2619                 "\033all"               /* INVEPT all-context type */
2620                 );
2621                 mask = msr >> 32;
2622                 printf("\n        VPID Features=0x%b", mask,
2623                 "\020"
2624                 "\001INVVPID"           /* INVVPID is supported */
2625                 "\011individual"        /* INVVPID individual-address type */
2626                 "\012single"            /* INVVPID single-context type */
2627                 "\013all"               /* INVVPID all-context type */
2628                  /* INVVPID single-context-retaining-globals type */
2629                 "\014single-globals"
2630                 );
2631         }
2632 }
2633
2634 static void
2635 print_hypervisor_info(void)
2636 {
2637
2638         if (*hv_vendor != '\0')
2639                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2640 }
2641
2642 /*
2643  * Returns the maximum physical address that can be used with the
2644  * current system.
2645  */
2646 vm_paddr_t
2647 cpu_getmaxphyaddr(void)
2648 {
2649
2650 #if defined(__i386__)
2651         if (!pae_mode)
2652                 return (0xffffffff);
2653 #endif
2654         return ((1ULL << cpu_maxphyaddr) - 1);
2655 }