sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   amd_extended_feature_extensions;
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 u_int   cpu_fxsr;               /* SSE enabled */
 107 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 108 u_int   cpu_clflush_line_size = 32;
 109 u_int   cpu_stdext_feature;     /* %ebx */
 110 u_int   cpu_stdext_feature2;    /* %ecx */
 111 u_int   cpu_stdext_feature3;    /* %edx */
 112 uint64_t cpu_ia32_arch_caps;
 113 u_int   cpu_max_ext_state_size;
 114 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 115 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 116 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 117 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 118 char machine[] = MACHINE;
 119
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 121     &via_feature_rng, 0,
 122     "VIA RNG feature available in CPU");
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 124     &via_feature_xcrypt, 0,
 125     "VIA xcrypt feature available in CPU");
 126
 127 #ifdef __amd64__
 128 #ifdef SCTL_MASK32
 129 extern int adaptive_machine_arch;
 130 #endif
 131
 132 static int
 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 134 {
 135 #ifdef SCTL_MASK32
 136         static const char machine32[] = "i386";
 137 #endif
 138         int error;
 139
 140 #ifdef SCTL_MASK32
 141         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 142                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 143         else
 144 #endif
 145                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 146         return (error);
 147
 148 }
 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 150     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 151 #else
 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 153     machine, 0, "Machine class");
 154 #endif
 155
 156 static char cpu_model[128];
 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 158     cpu_model, 0, "Machine model");
 159
 160 static int hw_clockrate;
 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 162     &hw_clockrate, 0, "CPU instruction clock rate");
 163
 164 u_int hv_high;
 165 char hv_vendor[16];
 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 167     0, "Hypervisor vendor");
 168
 169 static eventhandler_tag tsc_post_tag;
 170
 171 static char cpu_brand[48];
 172
 173 #ifdef __i386__
 174 #define MAX_BRAND_INDEX 8
 175
 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 177         NULL,                   /* No brand */
 178         "Intel Celeron",
 179         "Intel Pentium III",
 180         "Intel Pentium III Xeon",
 181         NULL,
 182         NULL,
 183         NULL,
 184         NULL,
 185         "Intel Pentium 4"
 186 };
 187
 188 static struct {
 189         char    *cpu_name;
 190         int     cpu_class;
 191 } cpus[] = {
 192         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 193         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 194         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 195         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 196         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 197         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 198         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 199         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 200         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 201         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 202         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 203         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 204         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 205         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 206         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 207         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 208         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 209 };
 210 #endif
 211
 212 static struct {
 213         char    *vendor;
 214         u_int   vendor_id;
 215 } cpu_vendors[] = {
 216         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 217         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 218         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 219 #ifdef __i386__
 220         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 221         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 222         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 223         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 224         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 225         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 226         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 227 #if 0
 228         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 229         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 230 #endif
 231 #endif
 232 };
 233
 234 void
 235 printcpuinfo(void)
 236 {
 237         u_int regs[4], i;
 238         char *brand;
 239
 240         printf("CPU: ");
 241 #ifdef __i386__
 242         cpu_class = cpus[cpu].cpu_class;
 243         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 244 #else
 245         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 246 #endif
 247
 248         /* Check for extended CPUID information and a processor name. */
 249         if (cpu_exthigh >= 0x80000004) {
 250                 brand = cpu_brand;
 251                 for (i = 0x80000002; i < 0x80000005; i++) {
 252                         do_cpuid(i, regs);
 253                         memcpy(brand, regs, sizeof(regs));
 254                         brand += sizeof(regs);
 255                 }
 256         }
 257
 258         switch (cpu_vendor_id) {
 259         case CPU_VENDOR_INTEL:
 260 #ifdef __i386__
 261                 if ((cpu_id & 0xf00) > 0x300) {
 262                         u_int brand_index;
 263
 264                         cpu_model[0] = '\0';
 265
 266                         switch (cpu_id & 0x3000) {
 267                         case 0x1000:
 268                                 strcpy(cpu_model, "Overdrive ");
 269                                 break;
 270                         case 0x2000:
 271                                 strcpy(cpu_model, "Dual ");
 272                                 break;
 273                         }
 274
 275                         switch (cpu_id & 0xf00) {
 276                         case 0x400:
 277                                 strcat(cpu_model, "i486 ");
 278                                 /* Check the particular flavor of 486 */
 279                                 switch (cpu_id & 0xf0) {
 280                                 case 0x00:
 281                                 case 0x10:
 282                                         strcat(cpu_model, "DX");
 283                                         break;
 284                                 case 0x20:
 285                                         strcat(cpu_model, "SX");
 286                                         break;
 287                                 case 0x30:
 288                                         strcat(cpu_model, "DX2");
 289                                         break;
 290                                 case 0x40:
 291                                         strcat(cpu_model, "SL");
 292                                         break;
 293                                 case 0x50:
 294                                         strcat(cpu_model, "SX2");
 295                                         break;
 296                                 case 0x70:
 297                                         strcat(cpu_model,
 298                                             "DX2 Write-Back Enhanced");
 299                                         break;
 300                                 case 0x80:
 301                                         strcat(cpu_model, "DX4");
 302                                         break;
 303                                 }
 304                                 break;
 305                         case 0x500:
 306                                 /* Check the particular flavor of 586 */
 307                                 strcat(cpu_model, "Pentium");
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, " A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "/P5");
 314                                         break;
 315                                 case 0x20:
 316                                         strcat(cpu_model, "/P54C");
 317                                         break;
 318                                 case 0x30:
 319                                         strcat(cpu_model, "/P24T");
 320                                         break;
 321                                 case 0x40:
 322                                         strcat(cpu_model, "/P55C");
 323                                         break;
 324                                 case 0x70:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x80:
 328                                         strcat(cpu_model, "/P55C (quarter-micron)");
 329                                         break;
 330                                 default:
 331                                         /* nothing */
 332                                         break;
 333                                 }
 334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 335                                 /*
 336                                  * XXX - If/when Intel fixes the bug, this
 337                                  * should also check the version of the
 338                                  * CPU, not just that it's a Pentium.
 339                                  */
 340                                 has_f00f_bug = 1;
 341 #endif
 342                                 break;
 343                         case 0x600:
 344                                 /* Check the particular flavor of 686 */
 345                                 switch (cpu_id & 0xf0) {
 346                                 case 0x00:
 347                                         strcat(cpu_model, "Pentium Pro A-step");
 348                                         break;
 349                                 case 0x10:
 350                                         strcat(cpu_model, "Pentium Pro");
 351                                         break;
 352                                 case 0x30:
 353                                 case 0x50:
 354                                 case 0x60:
 355                                         strcat(cpu_model,
 356                                 "Pentium II/Pentium II Xeon/Celeron");
 357                                         cpu = CPU_PII;
 358                                         break;
 359                                 case 0x70:
 360                                 case 0x80:
 361                                 case 0xa0:
 362                                 case 0xb0:
 363                                         strcat(cpu_model,
 364                                         "Pentium III/Pentium III Xeon/Celeron");
 365                                         cpu = CPU_PIII;
 366                                         break;
 367                                 default:
 368                                         strcat(cpu_model, "Unknown 80686");
 369                                         break;
 370                                 }
 371                                 break;
 372                         case 0xf00:
 373                                 strcat(cpu_model, "Pentium 4");
 374                                 cpu = CPU_P4;
 375                                 break;
 376                         default:
 377                                 strcat(cpu_model, "unknown");
 378                                 break;
 379                         }
 380
 381                         /*
 382                          * If we didn't get a brand name from the extended
 383                          * CPUID, try to look it up in the brand table.
 384                          */
 385                         if (cpu_high > 0 && *cpu_brand == '\0') {
 386                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 387                                 if (brand_index <= MAX_BRAND_INDEX &&
 388                                     cpu_brandtable[brand_index] != NULL)
 389                                         strcpy(cpu_brand,
 390                                             cpu_brandtable[brand_index]);
 391                         }
 392                 }
 393 #else
 394                 /* Please make up your mind folks! */
 395                 strcat(cpu_model, "EM64T");
 396 #endif
 397                 break;
 398         case CPU_VENDOR_AMD:
 399                 /*
 400                  * Values taken from AMD Processor Recognition
 401                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 402                  * (also describes ``Features'' encodings.
 403                  */
 404                 strcpy(cpu_model, "AMD ");
 405 #ifdef __i386__
 406                 switch (cpu_id & 0xFF0) {
 407                 case 0x410:
 408                         strcat(cpu_model, "Standard Am486DX");
 409                         break;
 410                 case 0x430:
 411                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 412                         break;
 413                 case 0x470:
 414                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 415                         break;
 416                 case 0x480:
 417                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 418                         break;
 419                 case 0x490:
 420                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 421                         break;
 422                 case 0x4E0:
 423                         strcat(cpu_model, "Am5x86 Write-Through");
 424                         break;
 425                 case 0x4F0:
 426                         strcat(cpu_model, "Am5x86 Write-Back");
 427                         break;
 428                 case 0x500:
 429                         strcat(cpu_model, "K5 model 0");
 430                         break;
 431                 case 0x510:
 432                         strcat(cpu_model, "K5 model 1");
 433                         break;
 434                 case 0x520:
 435                         strcat(cpu_model, "K5 PR166 (model 2)");
 436                         break;
 437                 case 0x530:
 438                         strcat(cpu_model, "K5 PR200 (model 3)");
 439                         break;
 440                 case 0x560:
 441                         strcat(cpu_model, "K6");
 442                         break;
 443                 case 0x570:
 444                         strcat(cpu_model, "K6 266 (model 1)");
 445                         break;
 446                 case 0x580:
 447                         strcat(cpu_model, "K6-2");
 448                         break;
 449                 case 0x590:
 450                         strcat(cpu_model, "K6-III");
 451                         break;
 452                 case 0x5a0:
 453                         strcat(cpu_model, "Geode LX");
 454                         break;
 455                 default:
 456                         strcat(cpu_model, "Unknown");
 457                         break;
 458                 }
 459 #else
 460                 if ((cpu_id & 0xf00) == 0xf00)
 461                         strcat(cpu_model, "AMD64 Processor");
 462                 else
 463                         strcat(cpu_model, "Unknown");
 464 #endif
 465                 break;
 466 #ifdef __i386__
 467         case CPU_VENDOR_CYRIX:
 468                 strcpy(cpu_model, "Cyrix ");
 469                 switch (cpu_id & 0xff0) {
 470                 case 0x440:
 471                         strcat(cpu_model, "MediaGX");
 472                         break;
 473                 case 0x520:
 474                         strcat(cpu_model, "6x86");
 475                         break;
 476                 case 0x540:
 477                         cpu_class = CPUCLASS_586;
 478                         strcat(cpu_model, "GXm");
 479                         break;
 480                 case 0x600:
 481                         strcat(cpu_model, "6x86MX");
 482                         break;
 483                 default:
 484                         /*
 485                          * Even though CPU supports the cpuid
 486                          * instruction, it can be disabled.
 487                          * Therefore, this routine supports all Cyrix
 488                          * CPUs.
 489                          */
 490                         switch (cyrix_did & 0xf0) {
 491                         case 0x00:
 492                                 switch (cyrix_did & 0x0f) {
 493                                 case 0x00:
 494                                         strcat(cpu_model, "486SLC");
 495                                         break;
 496                                 case 0x01:
 497                                         strcat(cpu_model, "486DLC");
 498                                         break;
 499                                 case 0x02:
 500                                         strcat(cpu_model, "486SLC2");
 501                                         break;
 502                                 case 0x03:
 503                                         strcat(cpu_model, "486DLC2");
 504                                         break;
 505                                 case 0x04:
 506                                         strcat(cpu_model, "486SRx");
 507                                         break;
 508                                 case 0x05:
 509                                         strcat(cpu_model, "486DRx");
 510                                         break;
 511                                 case 0x06:
 512                                         strcat(cpu_model, "486SRx2");
 513                                         break;
 514                                 case 0x07:
 515                                         strcat(cpu_model, "486DRx2");
 516                                         break;
 517                                 case 0x08:
 518                                         strcat(cpu_model, "486SRu");
 519                                         break;
 520                                 case 0x09:
 521                                         strcat(cpu_model, "486DRu");
 522                                         break;
 523                                 case 0x0a:
 524                                         strcat(cpu_model, "486SRu2");
 525                                         break;
 526                                 case 0x0b:
 527                                         strcat(cpu_model, "486DRu2");
 528                                         break;
 529                                 default:
 530                                         strcat(cpu_model, "Unknown");
 531                                         break;
 532                                 }
 533                                 break;
 534                         case 0x10:
 535                                 switch (cyrix_did & 0x0f) {
 536                                 case 0x00:
 537                                         strcat(cpu_model, "486S");
 538                                         break;
 539                                 case 0x01:
 540                                         strcat(cpu_model, "486S2");
 541                                         break;
 542                                 case 0x02:
 543                                         strcat(cpu_model, "486Se");
 544                                         break;
 545                                 case 0x03:
 546                                         strcat(cpu_model, "486S2e");
 547                                         break;
 548                                 case 0x0a:
 549                                         strcat(cpu_model, "486DX");
 550                                         break;
 551                                 case 0x0b:
 552                                         strcat(cpu_model, "486DX2");
 553                                         break;
 554                                 case 0x0f:
 555                                         strcat(cpu_model, "486DX4");
 556                                         break;
 557                                 default:
 558                                         strcat(cpu_model, "Unknown");
 559                                         break;
 560                                 }
 561                                 break;
 562                         case 0x20:
 563                                 if ((cyrix_did & 0x0f) < 8)
 564                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 565                                 else
 566                                         strcat(cpu_model, "5x86");
 567                                 break;
 568                         case 0x30:
 569                                 strcat(cpu_model, "6x86");
 570                                 break;
 571                         case 0x40:
 572                                 if ((cyrix_did & 0xf000) == 0x3000) {
 573                                         cpu_class = CPUCLASS_586;
 574                                         strcat(cpu_model, "GXm");
 575                                 } else
 576                                         strcat(cpu_model, "MediaGX");
 577                                 break;
 578                         case 0x50:
 579                                 strcat(cpu_model, "6x86MX");
 580                                 break;
 581                         case 0xf0:
 582                                 switch (cyrix_did & 0x0f) {
 583                                 case 0x0d:
 584                                         strcat(cpu_model, "Overdrive CPU");
 585                                         break;
 586                                 case 0x0e:
 587                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 588                                         break;
 589                                 case 0x0f:
 590                                         strcat(cpu_model, "486SLC/DLC");
 591                                         break;
 592                                 default:
 593                                         strcat(cpu_model, "Unknown");
 594                                         break;
 595                                 }
 596                                 break;
 597                         default:
 598                                 strcat(cpu_model, "Unknown");
 599                                 break;
 600                         }
 601                         break;
 602                 }
 603                 break;
 604         case CPU_VENDOR_RISE:
 605                 strcpy(cpu_model, "Rise ");
 606                 switch (cpu_id & 0xff0) {
 607                 case 0x500:     /* 6401 and 6441 (Kirin) */
 608                 case 0x520:     /* 6510 (Lynx) */
 609                         strcat(cpu_model, "mP6");
 610                         break;
 611                 default:
 612                         strcat(cpu_model, "Unknown");
 613                 }
 614                 break;
 615 #endif
 616         case CPU_VENDOR_CENTAUR:
 617 #ifdef __i386__
 618                 switch (cpu_id & 0xff0) {
 619                 case 0x540:
 620                         strcpy(cpu_model, "IDT WinChip C6");
 621                         break;
 622                 case 0x580:
 623                         strcpy(cpu_model, "IDT WinChip 2");
 624                         break;
 625                 case 0x590:
 626                         strcpy(cpu_model, "IDT WinChip 3");
 627                         break;
 628                 case 0x660:
 629                         strcpy(cpu_model, "VIA C3 Samuel");
 630                         break;
 631                 case 0x670:
 632                         if (cpu_id & 0x8)
 633                                 strcpy(cpu_model, "VIA C3 Ezra");
 634                         else
 635                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 636                         break;
 637                 case 0x680:
 638                         strcpy(cpu_model, "VIA C3 Ezra-T");
 639                         break;
 640                 case 0x690:
 641                         strcpy(cpu_model, "VIA C3 Nehemiah");
 642                         break;
 643                 case 0x6a0:
 644                 case 0x6d0:
 645                         strcpy(cpu_model, "VIA C7 Esther");
 646                         break;
 647                 case 0x6f0:
 648                         strcpy(cpu_model, "VIA Nano");
 649                         break;
 650                 default:
 651                         strcpy(cpu_model, "VIA/IDT Unknown");
 652                 }
 653 #else
 654                 strcpy(cpu_model, "VIA ");
 655                 if ((cpu_id & 0xff0) == 0x6f0)
 656                         strcat(cpu_model, "Nano Processor");
 657                 else
 658                         strcat(cpu_model, "Unknown");
 659 #endif
 660                 break;
 661 #ifdef __i386__
 662         case CPU_VENDOR_IBM:
 663                 strcpy(cpu_model, "Blue Lightning CPU");
 664                 break;
 665         case CPU_VENDOR_NSC:
 666                 switch (cpu_id & 0xff0) {
 667                 case 0x540:
 668                         strcpy(cpu_model, "Geode SC1100");
 669                         cpu = CPU_GEODE1100;
 670                         break;
 671                 default:
 672                         strcpy(cpu_model, "Geode/NSC unknown");
 673                         break;
 674                 }
 675                 break;
 676 #endif
 677         default:
 678                 strcat(cpu_model, "Unknown");
 679                 break;
 680         }
 681
 682         /*
 683          * Replace cpu_model with cpu_brand minus leading spaces if
 684          * we have one.
 685          */
 686         brand = cpu_brand;
 687         while (*brand == ' ')
 688                 ++brand;
 689         if (*brand != '\0')
 690                 strcpy(cpu_model, brand);
 691
 692         printf("%s (", cpu_model);
 693         if (tsc_freq != 0) {
 694                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 695                 printf("%jd.%02d-MHz ",
 696                     (intmax_t)(tsc_freq + 4999) / 1000000,
 697                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 698         }
 699 #ifdef __i386__
 700         switch(cpu_class) {
 701         case CPUCLASS_286:
 702                 printf("286");
 703                 break;
 704         case CPUCLASS_386:
 705                 printf("386");
 706                 break;
 707 #if defined(I486_CPU)
 708         case CPUCLASS_486:
 709                 printf("486");
 710                 break;
 711 #endif
 712 #if defined(I586_CPU)
 713         case CPUCLASS_586:
 714                 printf("586");
 715                 break;
 716 #endif
 717 #if defined(I686_CPU)
 718         case CPUCLASS_686:
 719                 printf("686");
 720                 break;
 721 #endif
 722         default:
 723                 printf("Unknown");      /* will panic below... */
 724         }
 725 #else
 726         printf("K8");
 727 #endif
 728         printf("-class CPU)\n");
 729         if (*cpu_vendor)
 730                 printf("  Origin=\"%s\"", cpu_vendor);
 731         if (cpu_id)
 732                 printf("  Id=0x%x", cpu_id);
 733
 734         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 735             cpu_vendor_id == CPU_VENDOR_AMD ||
 736             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 737 #ifdef __i386__
 738             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 739             cpu_vendor_id == CPU_VENDOR_RISE ||
 740             cpu_vendor_id == CPU_VENDOR_NSC ||
 741             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 742 #endif
 743             0) {
 744                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 745                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 746                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 747 #ifdef __i386__
 748                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 749                         printf("\n  DIR=0x%04x", cyrix_did);
 750 #endif
 751
 752                 /*
 753                  * AMD CPUID Specification
 754                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 755                  *
 756                  * Intel Processor Identification and CPUID Instruction
 757                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 758                  */
 759                 if (cpu_high > 0) {
 760
 761                         /*
 762                          * Here we should probably set up flags indicating
 763                          * whether or not various features are available.
 764                          * The interesting ones are probably VME, PSE, PAE,
 765                          * and PGE.  The code already assumes without bothering
 766                          * to check that all CPUs >= Pentium have a TSC and
 767                          * MSRs.
 768                          */
 769                         printf("\n  Features=0x%b", cpu_feature,
 770                         "\020"
 771                         "\001FPU"       /* Integral FPU */
 772                         "\002VME"       /* Extended VM86 mode support */
 773                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 774                         "\004PSE"       /* 4MByte page tables */
 775                         "\005TSC"       /* Timestamp counter */
 776                         "\006MSR"       /* Machine specific registers */
 777                         "\007PAE"       /* Physical address extension */
 778                         "\010MCE"       /* Machine Check support */
 779                         "\011CX8"       /* CMPEXCH8 instruction */
 780                         "\012APIC"      /* SMP local APIC */
 781                         "\013oldMTRR"   /* Previous implementation of MTRR */
 782                         "\014SEP"       /* Fast System Call */
 783                         "\015MTRR"      /* Memory Type Range Registers */
 784                         "\016PGE"       /* PG_G (global bit) support */
 785                         "\017MCA"       /* Machine Check Architecture */
 786                         "\020CMOV"      /* CMOV instruction */
 787                         "\021PAT"       /* Page attributes table */
 788                         "\022PSE36"     /* 36 bit address space support */
 789                         "\023PN"        /* Processor Serial number */
 790                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 791                         "\025<b20>"
 792                         "\026DTS"       /* Debug Trace Store */
 793                         "\027ACPI"      /* ACPI support */
 794                         "\030MMX"       /* MMX instructions */
 795                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 796                         "\032SSE"       /* Streaming SIMD Extensions */
 797                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 798                         "\034SS"        /* Self snoop */
 799                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 800                         "\036TM"        /* Thermal Monitor clock slowdown */
 801                         "\037IA64"      /* CPU can execute IA64 instructions */
 802                         "\040PBE"       /* Pending Break Enable */
 803                         );
 804
 805                         if (cpu_feature2 != 0) {
 806                                 printf("\n  Features2=0x%b", cpu_feature2,
 807                                 "\020"
 808                                 "\001SSE3"      /* SSE3 */
 809                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 810                                 "\003DTES64"    /* 64-bit Debug Trace */
 811                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 812                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 813                                 "\006VMX"       /* Virtual Machine Extensions */
 814                                 "\007SMX"       /* Safer Mode Extensions */
 815                                 "\010EST"       /* Enhanced SpeedStep */
 816                                 "\011TM2"       /* Thermal Monitor 2 */
 817                                 "\012SSSE3"     /* SSSE3 */
 818                                 "\013CNXT-ID"   /* L1 context ID available */
 819                                 "\014SDBG"      /* IA32 silicon debug */
 820                                 "\015FMA"       /* Fused Multiply Add */
 821                                 "\016CX16"      /* CMPXCHG16B Instruction */
 822                                 "\017xTPR"      /* Send Task Priority Messages*/
 823                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 824                                 "\021<b16>"
 825                                 "\022PCID"      /* Process-context Identifiers*/
 826                                 "\023DCA"       /* Direct Cache Access */
 827                                 "\024SSE4.1"    /* SSE 4.1 */
 828                                 "\025SSE4.2"    /* SSE 4.2 */
 829                                 "\026x2APIC"    /* xAPIC Extensions */
 830                                 "\027MOVBE"     /* MOVBE Instruction */
 831                                 "\030POPCNT"    /* POPCNT Instruction */
 832                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 833                                 "\032AESNI"     /* AES Crypto */
 834                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 835                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 836                                 "\035AVX"       /* Advanced Vector Extensions */
 837                                 "\036F16C"      /* Half-precision conversions */
 838                                 "\037RDRAND"    /* RDRAND Instruction */
 839                                 "\040HV"        /* Hypervisor */
 840                                 );
 841                         }
 842
 843                         if (amd_feature != 0) {
 844                                 printf("\n  AMD Features=0x%b", amd_feature,
 845                                 "\020"          /* in hex */
 846                                 "\001<s0>"      /* Same */
 847                                 "\002<s1>"      /* Same */
 848                                 "\003<s2>"      /* Same */
 849                                 "\004<s3>"      /* Same */
 850                                 "\005<s4>"      /* Same */
 851                                 "\006<s5>"      /* Same */
 852                                 "\007<s6>"      /* Same */
 853                                 "\010<s7>"      /* Same */
 854                                 "\011<s8>"      /* Same */
 855                                 "\012<s9>"      /* Same */
 856                                 "\013<b10>"     /* Undefined */
 857                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 858                                 "\015<s12>"     /* Same */
 859                                 "\016<s13>"     /* Same */
 860                                 "\017<s14>"     /* Same */
 861                                 "\020<s15>"     /* Same */
 862                                 "\021<s16>"     /* Same */
 863                                 "\022<s17>"     /* Same */
 864                                 "\023<b18>"     /* Reserved, unknown */
 865                                 "\024MP"        /* Multiprocessor Capable */
 866                                 "\025NX"        /* Has EFER.NXE, NX */
 867                                 "\026<b21>"     /* Undefined */
 868                                 "\027MMX+"      /* AMD MMX Extensions */
 869                                 "\030<s23>"     /* Same */
 870                                 "\031<s24>"     /* Same */
 871                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 872                                 "\033Page1GB"   /* 1-GB large page support */
 873                                 "\034RDTSCP"    /* RDTSCP */
 874                                 "\035<b28>"     /* Undefined */
 875                                 "\036LM"        /* 64 bit long mode */
 876                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 877                                 "\0403DNow!"    /* AMD 3DNow! */
 878                                 );
 879                         }
 880
 881                         if (amd_feature2 != 0) {
 882                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 883                                 "\020"
 884                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 885                                 "\002CMP"       /* CMP legacy */
 886                                 "\003SVM"       /* Secure Virtual Mode */
 887                                 "\004ExtAPIC"   /* Extended APIC register */
 888                                 "\005CR8"       /* CR8 in legacy mode */
 889                                 "\006ABM"       /* LZCNT instruction */
 890                                 "\007SSE4A"     /* SSE4A */
 891                                 "\010MAS"       /* Misaligned SSE mode */
 892                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 893                                 "\012OSVW"      /* OS visible workaround */
 894                                 "\013IBS"       /* Instruction based sampling */
 895                                 "\014XOP"       /* XOP extended instructions */
 896                                 "\015SKINIT"    /* SKINIT/STGI */
 897                                 "\016WDT"       /* Watchdog timer */
 898                                 "\017<b14>"
 899                                 "\020LWP"       /* Lightweight Profiling */
 900                                 "\021FMA4"      /* 4-operand FMA instructions */
 901                                 "\022TCE"       /* Translation Cache Extension */
 902                                 "\023<b18>"
 903                                 "\024NodeId"    /* NodeId MSR support */
 904                                 "\025<b20>"
 905                                 "\026TBM"       /* Trailing Bit Manipulation */
 906                                 "\027Topology"  /* Topology Extensions */
 907                                 "\030PCXC"      /* Core perf count */
 908                                 "\031PNXC"      /* NB perf count */
 909                                 "\032<b25>"
 910                                 "\033DBE"       /* Data Breakpoint extension */
 911                                 "\034PTSC"      /* Performance TSC */
 912                                 "\035PL2I"      /* L2I perf count */
 913                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 914                                 "\037<b30>"
 915                                 "\040<b31>"
 916                                 );
 917                         }
 918
 919                         if (cpu_stdext_feature != 0) {
 920                                 printf("\n  Structured Extended Features=0x%b",
 921                                     cpu_stdext_feature,
 922                                        "\020"
 923                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 924                                        "\001FSGSBASE"
 925                                        "\002TSCADJ"
 926                                        "\003SGX"
 927                                        /* Bit Manipulation Instructions */
 928                                        "\004BMI1"
 929                                        /* Hardware Lock Elision */
 930                                        "\005HLE"
 931                                        /* Advanced Vector Instructions 2 */
 932                                        "\006AVX2"
 933                                        /* FDP_EXCPTN_ONLY */
 934                                        "\007FDPEXC"
 935                                        /* Supervisor Mode Execution Prot. */
 936                                        "\010SMEP"
 937                                        /* Bit Manipulation Instructions */
 938                                        "\011BMI2"
 939                                        "\012ERMS"
 940                                        /* Invalidate Processor Context ID */
 941                                        "\013INVPCID"
 942                                        /* Restricted Transactional Memory */
 943                                        "\014RTM"
 944                                        "\015PQM"
 945                                        "\016NFPUSG"
 946                                        /* Intel Memory Protection Extensions */
 947                                        "\017MPX"
 948                                        "\020PQE"
 949                                        /* AVX512 Foundation */
 950                                        "\021AVX512F"
 951                                        "\022AVX512DQ"
 952                                        /* Enhanced NRBG */
 953                                        "\023RDSEED"
 954                                        /* ADCX + ADOX */
 955                                        "\024ADX"
 956                                        /* Supervisor Mode Access Prevention */
 957                                        "\025SMAP"
 958                                        "\026AVX512IFMA"
 959                                        "\027PCOMMIT"
 960                                        "\030CLFLUSHOPT"
 961                                        "\031CLWB"
 962                                        "\032PROCTRACE"
 963                                        "\033AVX512PF"
 964                                        "\034AVX512ER"
 965                                        "\035AVX512CD"
 966                                        "\036SHA"
 967                                        "\037AVX512BW"
 968                                        "\040AVX512VL"
 969                                        );
 970                         }
 971
 972                         if (cpu_stdext_feature2 != 0) {
 973                                 printf("\n  Structured Extended Features2=0x%b",
 974                                     cpu_stdext_feature2,
 975                                        "\020"
 976                                        "\001PREFETCHWT1"
 977                                        "\002AVX512VBMI"
 978                                        "\003UMIP"
 979                                        "\004PKU"
 980                                        "\005OSPKE"
 981                                        "\027RDPID"
 982                                        "\037SGXLC"
 983                                        );
 984                         }
 985
 986                         if (cpu_stdext_feature3 != 0) {
 987                                 printf("\n  Structured Extended Features3=0x%b",
 988                                     cpu_stdext_feature3,
 989                                        "\020"
 990                                        "\033IBPB"
 991                                        "\034STIBP"
 992                                        "\035L1DFL"
 993                                        "\036ARCH_CAP"
 994                                        "\040SSBD"
 995                                        );
 996                         }
 997
 998                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 999                                 cpuid_count(0xd, 0x1, regs);
1000                                 if (regs[0] != 0) {
1001                                         printf("\n  XSAVE Features=0x%b",
1002                                             regs[0],
1003                                             "\020"
1004                                             "\001XSAVEOPT"
1005                                             "\002XSAVEC"
1006                                             "\003XINUSE"
1007                                             "\004XSAVES");
1008                                 }
1009                         }
1010
1011                         if (cpu_ia32_arch_caps != 0) {
1012                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1013                                     (u_int)cpu_ia32_arch_caps,
1014                                        "\020"
1015                                        "\001RDCL_NO"
1016                                        "\002IBRS_ALL"
1017                                        "\003RSBA"
1018                                        "\004SKIP_L1DFL_VME"
1019                                        "\005SSB_NO"
1020                                        );
1021                         }
1022
1023                         if (amd_extended_feature_extensions != 0) {
1024                                 u_int amd_fe_masked;
1025
1026                                 amd_fe_masked = amd_extended_feature_extensions;
1027                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1028                                         amd_fe_masked &=
1029                                             ~(AMDFEID_IBRS_ALWAYSON |
1030                                                 AMDFEID_PREFER_IBRS);
1031                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1032                                         amd_fe_masked &=
1033                                             ~AMDFEID_STIBP_ALWAYSON;
1034
1035                                 printf("\n  "
1036                                     "AMD Extended Feature Extensions ID EBX="
1037                                     "0x%b", amd_fe_masked,
1038                                     "\020"
1039                                     "\001CLZERO"
1040                                     "\002IRPerf"
1041                                     "\003XSaveErPtr"
1042                                     "\015IBPB"
1043                                     "\017IBRS"
1044                                     "\020STIBP"
1045                                     "\021IBRS_ALWAYSON"
1046                                     "\022STIBP_ALWAYSON"
1047                                     "\023PREFER_IBRS"
1048                                     "\031SSBD"
1049                                     "\032VIRT_SSBD"
1050                                     "\033SSB_NO"
1051                                     );
1052                         }
1053
1054                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1055                                 print_via_padlock_info();
1056
1057                         if (cpu_feature2 & CPUID2_VMX)
1058                                 print_vmx_info();
1059
1060                         if (amd_feature2 & AMDID2_SVM)
1061                                 print_svm_info();
1062
1063                         if ((cpu_feature & CPUID_HTT) &&
1064                             cpu_vendor_id == CPU_VENDOR_AMD)
1065                                 cpu_feature &= ~CPUID_HTT;
1066
1067                         /*
1068                          * If this CPU supports P-state invariant TSC then
1069                          * mention the capability.
1070                          */
1071                         if (tsc_is_invariant) {
1072                                 printf("\n  TSC: P-state invariant");
1073                                 if (tsc_perf_stat)
1074                                         printf(", performance statistics");
1075                         }
1076                 }
1077 #ifdef __i386__
1078         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1079                 printf("  DIR=0x%04x", cyrix_did);
1080                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1081                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1082 #ifndef CYRIX_CACHE_REALLY_WORKS
1083                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1084                         printf("\n  CPU cache: write-through mode");
1085 #endif
1086 #endif
1087         }
1088
1089         /* Avoid ugly blank lines: only print newline when we have to. */
1090         if (*cpu_vendor || cpu_id)
1091                 printf("\n");
1092
1093         if (bootverbose) {
1094                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1095                         print_AMD_info();
1096                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1097                         print_INTEL_info();
1098 #ifdef __i386__
1099                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1100                         print_transmeta_info();
1101 #endif
1102         }
1103
1104         print_hypervisor_info();
1105 }
1106
1107 #ifdef __i386__
1108 void
1109 panicifcpuunsupported(void)
1110 {
1111
1112 #if !defined(lint)
1113 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1114 #error This kernel is not configured for one of the supported CPUs
1115 #endif
1116 #else /* lint */
1117 #endif /* lint */
1118         /*
1119          * Now that we have told the user what they have,
1120          * let them know if that machine type isn't configured.
1121          */
1122         switch (cpu_class) {
1123         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1124         case CPUCLASS_386:
1125 #if !defined(I486_CPU)
1126         case CPUCLASS_486:
1127 #endif
1128 #if !defined(I586_CPU)
1129         case CPUCLASS_586:
1130 #endif
1131 #if !defined(I686_CPU)
1132         case CPUCLASS_686:
1133 #endif
1134                 panic("CPU class not configured");
1135         default:
1136                 break;
1137         }
1138 }
1139
1140 static  volatile u_int trap_by_rdmsr;
1141
1142 /*
1143  * Special exception 6 handler.
1144  * The rdmsr instruction generates invalid opcodes fault on 486-class
1145  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1146  * function identblue() when this handler is called.  Stacked eip should
1147  * be advanced.
1148  */
1149 inthand_t       bluetrap6;
1150 #ifdef __GNUCLIKE_ASM
1151 __asm
1152 ("                                                                      \n\
1153         .text                                                           \n\
1154         .p2align 2,0x90                                                 \n\
1155         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1156 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1157         ss                                                              \n\
1158         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1159         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1160         iret                                                            \n\
1161 ");
1162 #endif
1163
1164 /*
1165  * Special exception 13 handler.
1166  * Accessing non-existent MSR generates general protection fault.
1167  */
1168 inthand_t       bluetrap13;
1169 #ifdef __GNUCLIKE_ASM
1170 __asm
1171 ("                                                                      \n\
1172         .text                                                           \n\
1173         .p2align 2,0x90                                                 \n\
1174         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1175 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1176         ss                                                              \n\
1177         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1178         popl    %eax            /* discard error code */                \n\
1179         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1180         iret                                                            \n\
1181 ");
1182 #endif
1183
1184 /*
1185  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1186  * support cpuid instruction.  This function should be called after
1187  * loading interrupt descriptor table register.
1188  *
1189  * I don't like this method that handles fault, but I couldn't get
1190  * information for any other methods.  Does blue giant know?
1191  */
1192 static int
1193 identblue(void)
1194 {
1195
1196         trap_by_rdmsr = 0;
1197
1198         /*
1199          * Cyrix 486-class CPU does not support rdmsr instruction.
1200          * The rdmsr instruction generates invalid opcode fault, and exception
1201          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1202          * bluetrap6() set the magic number to trap_by_rdmsr.
1203          */
1204         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1205             GSEL(GCODE_SEL, SEL_KPL));
1206
1207         /*
1208          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1209          * In this case, rdmsr generates general protection fault, and
1210          * exception will be trapped by bluetrap13().
1211          */
1212         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1213             GSEL(GCODE_SEL, SEL_KPL));
1214
1215         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1216
1217         if (trap_by_rdmsr == 0xa8c1d)
1218                 return IDENTBLUE_CYRIX486;
1219         else if (trap_by_rdmsr == 0xa89c4)
1220                 return IDENTBLUE_CYRIXM2;
1221         return IDENTBLUE_IBMCPU;
1222 }
1223
1224
1225 /*
1226  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1227  *
1228  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1229  * +-------+-------+---------------+
1230  * |  SID  |  RID  |   Device ID   |
1231  * |    (DIR 1)    |    (DIR 0)    |
1232  * +-------+-------+---------------+
1233  */
1234 static void
1235 identifycyrix(void)
1236 {
1237         register_t saveintr;
1238         int     ccr2_test = 0, dir_test = 0;
1239         u_char  ccr2, ccr3;
1240
1241         saveintr = intr_disable();
1242
1243         ccr2 = read_cyrix_reg(CCR2);
1244         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1245         read_cyrix_reg(CCR2);
1246         if (read_cyrix_reg(CCR2) != ccr2)
1247                 ccr2_test = 1;
1248         write_cyrix_reg(CCR2, ccr2);
1249
1250         ccr3 = read_cyrix_reg(CCR3);
1251         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1252         read_cyrix_reg(CCR3);
1253         if (read_cyrix_reg(CCR3) != ccr3)
1254                 dir_test = 1;                                   /* CPU supports DIRs. */
1255         write_cyrix_reg(CCR3, ccr3);
1256
1257         if (dir_test) {
1258                 /* Device ID registers are available. */
1259                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1260                 cyrix_did += read_cyrix_reg(DIR0);
1261         } else if (ccr2_test)
1262                 cyrix_did = 0x0010;             /* 486S A-step */
1263         else
1264                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1265
1266         intr_restore(saveintr);
1267 }
1268 #endif
1269
1270 /* Update TSC freq with the value indicated by the caller. */
1271 static void
1272 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1273 {
1274
1275         /* If there was an error during the transition, don't do anything. */
1276         if (status != 0)
1277                 return;
1278
1279         /* Total setting for this level gives the new frequency in MHz. */
1280         hw_clockrate = level->total_set.freq;
1281 }
1282
1283 static void
1284 hook_tsc_freq(void *arg __unused)
1285 {
1286
1287         if (tsc_is_invariant)
1288                 return;
1289
1290         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1291             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1292 }
1293
1294 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1295
1296 static const char *const vm_bnames[] = {
1297         "QEMU",                         /* QEMU */
1298         "Plex86",                       /* Plex86 */
1299         "Bochs",                        /* Bochs */
1300         "Xen",                          /* Xen */
1301         "BHYVE",                        /* bhyve */
1302         "Seabios",                      /* KVM */
1303         NULL
1304 };
1305
1306 static const char *const vm_pnames[] = {
1307         "VMware Virtual Platform",      /* VMWare VM */
1308         "Virtual Machine",              /* Microsoft VirtualPC */
1309         "VirtualBox",                   /* Sun xVM VirtualBox */
1310         "Parallels Virtual Platform",   /* Parallels VM */
1311         "KVM",                          /* KVM */
1312         NULL
1313 };
1314
1315 void
1316 identify_hypervisor(void)
1317 {
1318         u_int regs[4];
1319         char *p;
1320         int i;
1321
1322         /*
1323          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1324          * http://lkml.org/lkml/2008/10/1/246
1325          *
1326          * KB1009458: Mechanisms to determine if software is running in
1327          * a VMware virtual machine
1328          * http://kb.vmware.com/kb/1009458
1329          */
1330         if (cpu_feature2 & CPUID2_HV) {
1331                 vm_guest = VM_GUEST_VM;
1332                 do_cpuid(0x40000000, regs);
1333
1334                 /*
1335                  * KVM from Linux kernels prior to commit
1336                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1337                  * to 0 rather than a valid hv_high value.  Check for
1338                  * the KVM signature bytes and fixup %eax to the
1339                  * highest supported leaf in that case.
1340                  */
1341                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1342                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1343                         regs[0] = 0x40000001;
1344
1345                 if (regs[0] >= 0x40000000) {
1346                         hv_high = regs[0];
1347                         ((u_int *)&hv_vendor)[0] = regs[1];
1348                         ((u_int *)&hv_vendor)[1] = regs[2];
1349                         ((u_int *)&hv_vendor)[2] = regs[3];
1350                         hv_vendor[12] = '\0';
1351                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1352                                 vm_guest = VM_GUEST_VMWARE;
1353                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1354                                 vm_guest = VM_GUEST_HV;
1355                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1356                                 vm_guest = VM_GUEST_KVM;
1357                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1358                                 vm_guest = VM_GUEST_BHYVE;
1359                 }
1360                 return;
1361         }
1362
1363         /*
1364          * Examine SMBIOS strings for older hypervisors.
1365          */
1366         p = kern_getenv("smbios.system.serial");
1367         if (p != NULL) {
1368                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1369                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1370                         if (regs[1] == VMW_HVMAGIC) {
1371                                 vm_guest = VM_GUEST_VMWARE;
1372                                 freeenv(p);
1373                                 return;
1374                         }
1375                 }
1376                 freeenv(p);
1377         }
1378
1379         /*
1380          * XXX: Some of these entries may not be needed since they were
1381          * added to FreeBSD before the checks above.
1382          */
1383         p = kern_getenv("smbios.bios.vendor");
1384         if (p != NULL) {
1385                 for (i = 0; vm_bnames[i] != NULL; i++)
1386                         if (strcmp(p, vm_bnames[i]) == 0) {
1387                                 vm_guest = VM_GUEST_VM;
1388                                 freeenv(p);
1389                                 return;
1390                         }
1391                 freeenv(p);
1392         }
1393         p = kern_getenv("smbios.system.product");
1394         if (p != NULL) {
1395                 for (i = 0; vm_pnames[i] != NULL; i++)
1396                         if (strcmp(p, vm_pnames[i]) == 0) {
1397                                 vm_guest = VM_GUEST_VM;
1398                                 freeenv(p);
1399                                 return;
1400                         }
1401                 freeenv(p);
1402         }
1403 }
1404
1405 bool
1406 fix_cpuid(void)
1407 {
1408         uint64_t msr;
1409
1410         /*
1411          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1412          * get the largest standard CPUID function number again if it is set
1413          * from BIOS.  It is necessary for probing correct CPU topology later
1414          * and for the correct operation of the AVX-aware userspace.
1415          */
1416         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1417             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1418             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1419             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1420             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1421                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1422                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1423                         msr &= ~IA32_MISC_EN_LIMCPUID;
1424                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1425                         return (true);
1426                 }
1427         }
1428
1429         /*
1430          * Re-enable AMD Topology Extension that could be disabled by BIOS
1431          * on some notebook processors.  Without the extension it's really
1432          * hard to determine the correct CPU cache topology.
1433          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1434          * Models 60h-6Fh Processors, Publication # 50742.
1435          */
1436         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1437             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1438                 msr = rdmsr(MSR_EXTFEATURES);
1439                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1440                         msr |= (uint64_t)1 << 54;
1441                         wrmsr(MSR_EXTFEATURES, msr);
1442                         return (true);
1443                 }
1444         }
1445         return (false);
1446 }
1447
1448 void
1449 identify_cpu1(void)
1450 {
1451         u_int regs[4];
1452
1453         do_cpuid(0, regs);
1454         cpu_high = regs[0];
1455         ((u_int *)&cpu_vendor)[0] = regs[1];
1456         ((u_int *)&cpu_vendor)[1] = regs[3];
1457         ((u_int *)&cpu_vendor)[2] = regs[2];
1458         cpu_vendor[12] = '\0';
1459
1460         do_cpuid(1, regs);
1461         cpu_id = regs[0];
1462         cpu_procinfo = regs[1];
1463         cpu_feature = regs[3];
1464         cpu_feature2 = regs[2];
1465 }
1466
1467 void
1468 identify_cpu2(void)
1469 {
1470         u_int regs[4], cpu_stdext_disable;
1471
1472         if (cpu_high >= 7) {
1473                 cpuid_count(7, 0, regs);
1474                 cpu_stdext_feature = regs[1];
1475
1476                 /*
1477                  * Some hypervisors failed to filter out unsupported
1478                  * extended features.  Allow to disable the
1479                  * extensions, activation of which requires setting a
1480                  * bit in CR4, and which VM monitors do not support.
1481                  */
1482                 cpu_stdext_disable = 0;
1483                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1484                 cpu_stdext_feature &= ~cpu_stdext_disable;
1485
1486                 cpu_stdext_feature2 = regs[2];
1487                 cpu_stdext_feature3 = regs[3];
1488
1489                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1490                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1491         }
1492 }
1493
1494 void
1495 identify_cpu_fixup_bsp(void)
1496 {
1497         u_int regs[4];
1498
1499         cpu_vendor_id = find_cpu_vendor_id();
1500
1501         if (fix_cpuid()) {
1502                 do_cpuid(0, regs);
1503                 cpu_high = regs[0];
1504         }
1505 }
1506
1507 /*
1508  * Final stage of CPU identification.
1509  */
1510 void
1511 finishidentcpu(void)
1512 {
1513         u_int regs[4];
1514 #ifdef __i386__
1515         u_char ccr3;
1516 #endif
1517
1518         identify_cpu_fixup_bsp();
1519
1520         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1521                 do_cpuid(5, regs);
1522                 cpu_mon_mwait_flags = regs[2];
1523                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1524                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1525         }
1526
1527         identify_cpu2();
1528
1529 #ifdef __i386__
1530         if (cpu_high > 0 &&
1531             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1532              cpu_vendor_id == CPU_VENDOR_AMD ||
1533              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1534              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1535              cpu_vendor_id == CPU_VENDOR_NSC)) {
1536                 do_cpuid(0x80000000, regs);
1537                 if (regs[0] >= 0x80000000)
1538                         cpu_exthigh = regs[0];
1539         }
1540 #else
1541         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1542             cpu_vendor_id == CPU_VENDOR_AMD ||
1543             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1544                 do_cpuid(0x80000000, regs);
1545                 cpu_exthigh = regs[0];
1546         }
1547 #endif
1548         if (cpu_exthigh >= 0x80000001) {
1549                 do_cpuid(0x80000001, regs);
1550                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1551                 amd_feature2 = regs[2];
1552         }
1553         if (cpu_exthigh >= 0x80000007) {
1554                 do_cpuid(0x80000007, regs);
1555                 amd_rascap = regs[1];
1556                 amd_pminfo = regs[3];
1557         }
1558         if (cpu_exthigh >= 0x80000008) {
1559                 do_cpuid(0x80000008, regs);
1560                 cpu_maxphyaddr = regs[0] & 0xff;
1561                 amd_extended_feature_extensions = regs[1];
1562                 cpu_procinfo2 = regs[2];
1563         } else {
1564                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1565         }
1566
1567 #ifdef __i386__
1568         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1569                 if (cpu == CPU_486) {
1570                         /*
1571                          * These conditions are equivalent to:
1572                          *     - CPU does not support cpuid instruction.
1573                          *     - Cyrix/IBM CPU is detected.
1574                          */
1575                         if (identblue() == IDENTBLUE_IBMCPU) {
1576                                 strcpy(cpu_vendor, "IBM");
1577                                 cpu_vendor_id = CPU_VENDOR_IBM;
1578                                 cpu = CPU_BLUE;
1579                                 return;
1580                         }
1581                 }
1582                 switch (cpu_id & 0xf00) {
1583                 case 0x600:
1584                         /*
1585                          * Cyrix's datasheet does not describe DIRs.
1586                          * Therefor, I assume it does not have them
1587                          * and use the result of the cpuid instruction.
1588                          * XXX they seem to have it for now at least. -Peter
1589                          */
1590                         identifycyrix();
1591                         cpu = CPU_M2;
1592                         break;
1593                 default:
1594                         identifycyrix();
1595                         /*
1596                          * This routine contains a trick.
1597                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1598                          */
1599                         switch (cyrix_did & 0x00f0) {
1600                         case 0x00:
1601                         case 0xf0:
1602                                 cpu = CPU_486DLC;
1603                                 break;
1604                         case 0x10:
1605                                 cpu = CPU_CY486DX;
1606                                 break;
1607                         case 0x20:
1608                                 if ((cyrix_did & 0x000f) < 8)
1609                                         cpu = CPU_M1;
1610                                 else
1611                                         cpu = CPU_M1SC;
1612                                 break;
1613                         case 0x30:
1614                                 cpu = CPU_M1;
1615                                 break;
1616                         case 0x40:
1617                                 /* MediaGX CPU */
1618                                 cpu = CPU_M1SC;
1619                                 break;
1620                         default:
1621                                 /* M2 and later CPUs are treated as M2. */
1622                                 cpu = CPU_M2;
1623
1624                                 /*
1625                                  * enable cpuid instruction.
1626                                  */
1627                                 ccr3 = read_cyrix_reg(CCR3);
1628                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1629                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1630                                 write_cyrix_reg(CCR3, ccr3);
1631
1632                                 do_cpuid(0, regs);
1633                                 cpu_high = regs[0];     /* eax */
1634                                 do_cpuid(1, regs);
1635                                 cpu_id = regs[0];       /* eax */
1636                                 cpu_feature = regs[3];  /* edx */
1637                                 break;
1638                         }
1639                 }
1640         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1641                 /*
1642                  * There are BlueLightning CPUs that do not change
1643                  * undefined flags by dividing 5 by 2.  In this case,
1644                  * the CPU identification routine in locore.s leaves
1645                  * cpu_vendor null string and puts CPU_486 into the
1646                  * cpu.
1647                  */
1648                 if (identblue() == IDENTBLUE_IBMCPU) {
1649                         strcpy(cpu_vendor, "IBM");
1650                         cpu_vendor_id = CPU_VENDOR_IBM;
1651                         cpu = CPU_BLUE;
1652                         return;
1653                 }
1654         }
1655 #endif
1656 }
1657
1658 int
1659 pti_get_default(void)
1660 {
1661
1662         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1663                 return (0);
1664         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1665                 return (0);
1666         return (1);
1667 }
1668
1669 static u_int
1670 find_cpu_vendor_id(void)
1671 {
1672         int     i;
1673
1674         for (i = 0; i < nitems(cpu_vendors); i++)
1675                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1676                         return (cpu_vendors[i].vendor_id);
1677         return (0);
1678 }
1679
1680 static void
1681 print_AMD_assoc(int i)
1682 {
1683         if (i == 255)
1684                 printf(", fully associative\n");
1685         else
1686                 printf(", %d-way associative\n", i);
1687 }
1688
1689 static void
1690 print_AMD_l2_assoc(int i)
1691 {
1692         switch (i & 0x0f) {
1693         case 0: printf(", disabled/not present\n"); break;
1694         case 1: printf(", direct mapped\n"); break;
1695         case 2: printf(", 2-way associative\n"); break;
1696         case 4: printf(", 4-way associative\n"); break;
1697         case 6: printf(", 8-way associative\n"); break;
1698         case 8: printf(", 16-way associative\n"); break;
1699         case 15: printf(", fully associative\n"); break;
1700         default: printf(", reserved configuration\n"); break;
1701         }
1702 }
1703
1704 static void
1705 print_AMD_info(void)
1706 {
1707 #ifdef __i386__
1708         uint64_t amd_whcr;
1709 #endif
1710         u_int regs[4];
1711
1712         if (cpu_exthigh >= 0x80000005) {
1713                 do_cpuid(0x80000005, regs);
1714                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1715                 print_AMD_assoc(regs[0] >> 24);
1716
1717                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1718                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1719
1720                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1721                 print_AMD_assoc(regs[1] >> 24);
1722
1723                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1724                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1725
1726                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1727                 printf(", %d bytes/line", regs[2] & 0xff);
1728                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1729                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1730
1731                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1732                 printf(", %d bytes/line", regs[3] & 0xff);
1733                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1734                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1735         }
1736
1737         if (cpu_exthigh >= 0x80000006) {
1738                 do_cpuid(0x80000006, regs);
1739                 if ((regs[0] >> 16) != 0) {
1740                         printf("L2 2MB data TLB: %d entries",
1741                             (regs[0] >> 16) & 0xfff);
1742                         print_AMD_l2_assoc(regs[0] >> 28);
1743                         printf("L2 2MB instruction TLB: %d entries",
1744                             regs[0] & 0xfff);
1745                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1746                 } else {
1747                         printf("L2 2MB unified TLB: %d entries",
1748                             regs[0] & 0xfff);
1749                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1750                 }
1751                 if ((regs[1] >> 16) != 0) {
1752                         printf("L2 4KB data TLB: %d entries",
1753                             (regs[1] >> 16) & 0xfff);
1754                         print_AMD_l2_assoc(regs[1] >> 28);
1755
1756                         printf("L2 4KB instruction TLB: %d entries",
1757                             (regs[1] >> 16) & 0xfff);
1758                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1759                 } else {
1760                         printf("L2 4KB unified TLB: %d entries",
1761                             (regs[1] >> 16) & 0xfff);
1762                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1763                 }
1764                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1765                 printf(", %d bytes/line", regs[2] & 0xff);
1766                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1767                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1768         }
1769
1770 #ifdef __i386__
1771         if (((cpu_id & 0xf00) == 0x500)
1772             && (((cpu_id & 0x0f0) > 0x80)
1773                 || (((cpu_id & 0x0f0) == 0x80)
1774                     && (cpu_id & 0x00f) > 0x07))) {
1775                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1776                 amd_whcr = rdmsr(0xc0000082);
1777                 if (!(amd_whcr & (0x3ff << 22))) {
1778                         printf("Write Allocate Disable\n");
1779                 } else {
1780                         printf("Write Allocate Enable Limit: %dM bytes\n",
1781                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1782                         printf("Write Allocate 15-16M bytes: %s\n",
1783                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1784                 }
1785         } else if (((cpu_id & 0xf00) == 0x500)
1786                    && ((cpu_id & 0x0f0) > 0x50)) {
1787                 /* K6, K6-2(old core) */
1788                 amd_whcr = rdmsr(0xc0000082);
1789                 if (!(amd_whcr & (0x7f << 1))) {
1790                         printf("Write Allocate Disable\n");
1791                 } else {
1792                         printf("Write Allocate Enable Limit: %dM bytes\n",
1793                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1794                         printf("Write Allocate 15-16M bytes: %s\n",
1795                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1796                         printf("Hardware Write Allocate Control: %s\n",
1797                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1798                 }
1799         }
1800 #endif
1801         /*
1802          * Opteron Rev E shows a bug as in very rare occasions a read memory
1803          * barrier is not performed as expected if it is followed by a
1804          * non-atomic read-modify-write instruction.
1805          * As long as that bug pops up very rarely (intensive machine usage
1806          * on other operating systems generally generates one unexplainable
1807          * crash any 2 months) and as long as a model specific fix would be
1808          * impractical at this stage, print out a warning string if the broken
1809          * model and family are identified.
1810          */
1811         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1812             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1813                 printf("WARNING: This architecture revision has known SMP "
1814                     "hardware bugs which may cause random instability\n");
1815 }
1816
1817 static void
1818 print_INTEL_info(void)
1819 {
1820         u_int regs[4];
1821         u_int rounds, regnum;
1822         u_int nwaycode, nway;
1823
1824         if (cpu_high >= 2) {
1825                 rounds = 0;
1826                 do {
1827                         do_cpuid(0x2, regs);
1828                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1829                                 break;  /* we have a buggy CPU */
1830
1831                         for (regnum = 0; regnum <= 3; ++regnum) {
1832                                 if (regs[regnum] & (1<<31))
1833                                         continue;
1834                                 if (regnum != 0)
1835                                         print_INTEL_TLB(regs[regnum] & 0xff);
1836                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1837                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1838                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1839                         }
1840                 } while (--rounds > 0);
1841         }
1842
1843         if (cpu_exthigh >= 0x80000006) {
1844                 do_cpuid(0x80000006, regs);
1845                 nwaycode = (regs[2] >> 12) & 0x0f;
1846                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1847                         nway = 1 << (nwaycode / 2);
1848                 else
1849                         nway = 0;
1850                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1851                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1852         }
1853 }
1854
1855 static void
1856 print_INTEL_TLB(u_int data)
1857 {
1858         switch (data) {
1859         case 0x0:
1860         case 0x40:
1861         default:
1862                 break;
1863         case 0x1:
1864                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1865                 break;
1866         case 0x2:
1867                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1868                 break;
1869         case 0x3:
1870                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1871                 break;
1872         case 0x4:
1873                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1874                 break;
1875         case 0x6:
1876                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1877                 break;
1878         case 0x8:
1879                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1880                 break;
1881         case 0x9:
1882                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1883                 break;
1884         case 0xa:
1885                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1886                 break;
1887         case 0xb:
1888                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1889                 break;
1890         case 0xc:
1891                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1892                 break;
1893         case 0xd:
1894                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1895                 break;
1896         case 0xe:
1897                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1898                 break;
1899         case 0x1d:
1900                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1901                 break;
1902         case 0x21:
1903                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1904                 break;
1905         case 0x22:
1906                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1907                 break;
1908         case 0x23:
1909                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1910                 break;
1911         case 0x24:
1912                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1913                 break;
1914         case 0x25:
1915                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1916                 break;
1917         case 0x29:
1918                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1919                 break;
1920         case 0x2c:
1921                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1922                 break;
1923         case 0x30:
1924                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1925                 break;
1926         case 0x39: /* De-listed in SDM rev. 54 */
1927                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1928                 break;
1929         case 0x3b: /* De-listed in SDM rev. 54 */
1930                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1931                 break;
1932         case 0x3c: /* De-listed in SDM rev. 54 */
1933                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1934                 break;
1935         case 0x41:
1936                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1937                 break;
1938         case 0x42:
1939                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1940                 break;
1941         case 0x43:
1942                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1943                 break;
1944         case 0x44:
1945                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1946                 break;
1947         case 0x45:
1948                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1949                 break;
1950         case 0x46:
1951                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1952                 break;
1953         case 0x47:
1954                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1955                 break;
1956         case 0x48:
1957                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1958                 break;
1959         case 0x49:
1960                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1961                     CPUID_TO_MODEL(cpu_id) == 0x6)
1962                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1963                 else
1964                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1965                 break;
1966         case 0x4a:
1967                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1968                 break;
1969         case 0x4b:
1970                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1971                 break;
1972         case 0x4c:
1973                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1974                 break;
1975         case 0x4d:
1976                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1977                 break;
1978         case 0x4e:
1979                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1980                 break;
1981         case 0x4f:
1982                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1983                 break;
1984         case 0x50:
1985                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1986                 break;
1987         case 0x51:
1988                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1989                 break;
1990         case 0x52:
1991                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1992                 break;
1993         case 0x55:
1994                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1995                 break;
1996         case 0x56:
1997                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1998                 break;
1999         case 0x57:
2000                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2001                 break;
2002         case 0x59:
2003                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2004                 break;
2005         case 0x5a:
2006                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2007                 break;
2008         case 0x5b:
2009                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2010                 break;
2011         case 0x5c:
2012                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2013                 break;
2014         case 0x5d:
2015                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2016                 break;
2017         case 0x60:
2018                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2019                 break;
2020         case 0x61:
2021                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2022                 break;
2023         case 0x63:
2024                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2025                 break;
2026         case 0x64:
2027                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2028                 break;
2029         case 0x66:
2030                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2031                 break;
2032         case 0x67:
2033                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2034                 break;
2035         case 0x68:
2036                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2037                 break;
2038         case 0x6a:
2039                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2040                 break;
2041         case 0x6b:
2042                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2043                 break;
2044         case 0x6c:
2045                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2046                 break;
2047         case 0x6d:
2048                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2049                 break;
2050         case 0x70:
2051                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2052                 break;
2053         case 0x71:
2054                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2055                 break;
2056         case 0x72:
2057                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2058                 break;
2059         case 0x76:
2060                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2061                 break;
2062         case 0x78:
2063                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2064                 break;
2065         case 0x79:
2066                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2067                 break;
2068         case 0x7a:
2069                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2070                 break;
2071         case 0x7b:
2072                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2073                 break;
2074         case 0x7c:
2075                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2076                 break;
2077         case 0x7d:
2078                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2079                 break;
2080         case 0x7f:
2081                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2082                 break;
2083         case 0x80:
2084                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2085                 break;
2086         case 0x82:
2087                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2088                 break;
2089         case 0x83:
2090                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2091                 break;
2092         case 0x84:
2093                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2094                 break;
2095         case 0x85:
2096                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2097                 break;
2098         case 0x86:
2099                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2100                 break;
2101         case 0x87:
2102                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2103                 break;
2104         case 0xa0:
2105                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2106                 break;
2107         case 0xb0:
2108                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2109                 break;
2110         case 0xb1:
2111                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2112                 break;
2113         case 0xb2:
2114                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2115                 break;
2116         case 0xb3:
2117                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2118                 break;
2119         case 0xb4:
2120                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2121                 break;
2122         case 0xb5:
2123                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2124                 break;
2125         case 0xb6:
2126                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2127                 break;
2128         case 0xba:
2129                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2130                 break;
2131         case 0xc0:
2132                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2133                 break;
2134         case 0xc1:
2135                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2136                 break;
2137         case 0xc2:
2138                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2139                 break;
2140         case 0xc3:
2141                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2142                 break;
2143         case 0xc4:
2144                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2145                 break;
2146         case 0xca:
2147                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2148                 break;
2149         case 0xd0:
2150                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2151                 break;
2152         case 0xd1:
2153                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2154                 break;
2155         case 0xd2:
2156                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2157                 break;
2158         case 0xd6:
2159                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2160                 break;
2161         case 0xd7:
2162                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2163                 break;
2164         case 0xd8:
2165                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2166                 break;
2167         case 0xdc:
2168                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2169                 break;
2170         case 0xdd:
2171                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2172                 break;
2173         case 0xde:
2174                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2175                 break;
2176         case 0xe2:
2177                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2178                 break;
2179         case 0xe3:
2180                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2181                 break;
2182         case 0xe4:
2183                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2184                 break;
2185         case 0xea:
2186                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2187                 break;
2188         case 0xeb:
2189                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2190                 break;
2191         case 0xec:
2192                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2193                 break;
2194         case 0xf0:
2195                 printf("64-Byte prefetching\n");
2196                 break;
2197         case 0xf1:
2198                 printf("128-Byte prefetching\n");
2199                 break;
2200         }
2201 }
2202
2203 static void
2204 print_svm_info(void)
2205 {
2206         u_int features, regs[4];
2207         uint64_t msr;
2208         int comma;
2209
2210         printf("\n  SVM: ");
2211         do_cpuid(0x8000000A, regs);
2212         features = regs[3];
2213
2214         msr = rdmsr(MSR_VM_CR);
2215         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2216                 printf("(disabled in BIOS) ");
2217
2218         if (!bootverbose) {
2219                 comma = 0;
2220                 if (features & (1 << 0)) {
2221                         printf("%sNP", comma ? "," : "");
2222                         comma = 1;
2223                 }
2224                 if (features & (1 << 3)) {
2225                         printf("%sNRIP", comma ? "," : "");
2226                         comma = 1;
2227                 }
2228                 if (features & (1 << 5)) {
2229                         printf("%sVClean", comma ? "," : "");
2230                         comma = 1;
2231                 }
2232                 if (features & (1 << 6)) {
2233                         printf("%sAFlush", comma ? "," : "");
2234                         comma = 1;
2235                 }
2236                 if (features & (1 << 7)) {
2237                         printf("%sDAssist", comma ? "," : "");
2238                         comma = 1;
2239                 }
2240                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2241                 return;
2242         }
2243
2244         printf("Features=0x%b", features,
2245                "\020"
2246                "\001NP"                 /* Nested paging */
2247                "\002LbrVirt"            /* LBR virtualization */
2248                "\003SVML"               /* SVM lock */
2249                "\004NRIPS"              /* NRIP save */
2250                "\005TscRateMsr"         /* MSR based TSC rate control */
2251                "\006VmcbClean"          /* VMCB clean bits */
2252                "\007FlushByAsid"        /* Flush by ASID */
2253                "\010DecodeAssist"       /* Decode assist */
2254                "\011<b8>"
2255                "\012<b9>"
2256                "\013PauseFilter"        /* PAUSE intercept filter */
2257                "\014EncryptedMcodePatch"
2258                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2259                "\016AVIC"               /* virtual interrupt controller */
2260                "\017<b14>"
2261                "\020V_VMSAVE_VMLOAD"
2262                "\021vGIF"
2263                "\022<b17>"
2264                "\023<b18>"
2265                "\024<b19>"
2266                "\025<b20>"
2267                "\026<b21>"
2268                "\027<b22>"
2269                "\030<b23>"
2270                "\031<b24>"
2271                "\032<b25>"
2272                "\033<b26>"
2273                "\034<b27>"
2274                "\035<b28>"
2275                "\036<b29>"
2276                "\037<b30>"
2277                "\040<b31>"
2278                 );
2279         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2280 }
2281
2282 #ifdef __i386__
2283 static void
2284 print_transmeta_info(void)
2285 {
2286         u_int regs[4], nreg = 0;
2287
2288         do_cpuid(0x80860000, regs);
2289         nreg = regs[0];
2290         if (nreg >= 0x80860001) {
2291                 do_cpuid(0x80860001, regs);
2292                 printf("  Processor revision %u.%u.%u.%u\n",
2293                        (regs[1] >> 24) & 0xff,
2294                        (regs[1] >> 16) & 0xff,
2295                        (regs[1] >> 8) & 0xff,
2296                        regs[1] & 0xff);
2297         }
2298         if (nreg >= 0x80860002) {
2299                 do_cpuid(0x80860002, regs);
2300                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2301                        (regs[1] >> 24) & 0xff,
2302                        (regs[1] >> 16) & 0xff,
2303                        (regs[1] >> 8) & 0xff,
2304                        regs[1] & 0xff,
2305                        regs[2]);
2306         }
2307         if (nreg >= 0x80860006) {
2308                 char info[65];
2309                 do_cpuid(0x80860003, (u_int*) &info[0]);
2310                 do_cpuid(0x80860004, (u_int*) &info[16]);
2311                 do_cpuid(0x80860005, (u_int*) &info[32]);
2312                 do_cpuid(0x80860006, (u_int*) &info[48]);
2313                 info[64] = 0;
2314                 printf("  %s\n", info);
2315         }
2316 }
2317 #endif
2318
2319 static void
2320 print_via_padlock_info(void)
2321 {
2322         u_int regs[4];
2323
2324         do_cpuid(0xc0000001, regs);
2325         printf("\n  VIA Padlock Features=0x%b", regs[3],
2326         "\020"
2327         "\003RNG"               /* RNG */
2328         "\007AES"               /* ACE */
2329         "\011AES-CTR"           /* ACE2 */
2330         "\013SHA1,SHA256"       /* PHE */
2331         "\015RSA"               /* PMM */
2332         );
2333 }
2334
2335 static uint32_t
2336 vmx_settable(uint64_t basic, int msr, int true_msr)
2337 {
2338         uint64_t val;
2339
2340         if (basic & (1ULL << 55))
2341                 val = rdmsr(true_msr);
2342         else
2343                 val = rdmsr(msr);
2344
2345         /* Just report the controls that can be set to 1. */
2346         return (val >> 32);
2347 }
2348
2349 static void
2350 print_vmx_info(void)
2351 {
2352         uint64_t basic, msr;
2353         uint32_t entry, exit, mask, pin, proc, proc2;
2354         int comma;
2355
2356         printf("\n  VT-x: ");
2357         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2358         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2359                 printf("(disabled in BIOS) ");
2360         basic = rdmsr(MSR_VMX_BASIC);
2361         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2362             MSR_VMX_TRUE_PINBASED_CTLS);
2363         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2364             MSR_VMX_TRUE_PROCBASED_CTLS);
2365         if (proc & PROCBASED_SECONDARY_CONTROLS)
2366                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2367                     MSR_VMX_PROCBASED_CTLS2);
2368         else
2369                 proc2 = 0;
2370         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2371         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2372
2373         if (!bootverbose) {
2374                 comma = 0;
2375                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2376                     entry & VM_ENTRY_LOAD_PAT) {
2377                         printf("%sPAT", comma ? "," : "");
2378                         comma = 1;
2379                 }
2380                 if (proc & PROCBASED_HLT_EXITING) {
2381                         printf("%sHLT", comma ? "," : "");
2382                         comma = 1;
2383                 }
2384                 if (proc & PROCBASED_MTF) {
2385                         printf("%sMTF", comma ? "," : "");
2386                         comma = 1;
2387                 }
2388                 if (proc & PROCBASED_PAUSE_EXITING) {
2389                         printf("%sPAUSE", comma ? "," : "");
2390                         comma = 1;
2391                 }
2392                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2393                         printf("%sEPT", comma ? "," : "");
2394                         comma = 1;
2395                 }
2396                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2397                         printf("%sUG", comma ? "," : "");
2398                         comma = 1;
2399                 }
2400                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2401                         printf("%sVPID", comma ? "," : "");
2402                         comma = 1;
2403                 }
2404                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2405                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2406                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2407                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2408                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2409                         printf("%sVID", comma ? "," : "");
2410                         comma = 1;
2411                         if (pin & PINBASED_POSTED_INTERRUPT)
2412                                 printf(",PostIntr");
2413                 }
2414                 return;
2415         }
2416
2417         mask = basic >> 32;
2418         printf("Basic Features=0x%b", mask,
2419         "\020"
2420         "\02132PA"              /* 32-bit physical addresses */
2421         "\022SMM"               /* SMM dual-monitor */
2422         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2423         "\030TRUE"              /* TRUE_CTLS MSRs */
2424         );
2425         printf("\n        Pin-Based Controls=0x%b", pin,
2426         "\020"
2427         "\001ExtINT"            /* External-interrupt exiting */
2428         "\004NMI"               /* NMI exiting */
2429         "\006VNMI"              /* Virtual NMIs */
2430         "\007PreTmr"            /* Activate VMX-preemption timer */
2431         "\010PostIntr"          /* Process posted interrupts */
2432         );
2433         printf("\n        Primary Processor Controls=0x%b", proc,
2434         "\020"
2435         "\003INTWIN"            /* Interrupt-window exiting */
2436         "\004TSCOff"            /* Use TSC offsetting */
2437         "\010HLT"               /* HLT exiting */
2438         "\012INVLPG"            /* INVLPG exiting */
2439         "\013MWAIT"             /* MWAIT exiting */
2440         "\014RDPMC"             /* RDPMC exiting */
2441         "\015RDTSC"             /* RDTSC exiting */
2442         "\020CR3-LD"            /* CR3-load exiting */
2443         "\021CR3-ST"            /* CR3-store exiting */
2444         "\024CR8-LD"            /* CR8-load exiting */
2445         "\025CR8-ST"            /* CR8-store exiting */
2446         "\026TPR"               /* Use TPR shadow */
2447         "\027NMIWIN"            /* NMI-window exiting */
2448         "\030MOV-DR"            /* MOV-DR exiting */
2449         "\031IO"                /* Unconditional I/O exiting */
2450         "\032IOmap"             /* Use I/O bitmaps */
2451         "\034MTF"               /* Monitor trap flag */
2452         "\035MSRmap"            /* Use MSR bitmaps */
2453         "\036MONITOR"           /* MONITOR exiting */
2454         "\037PAUSE"             /* PAUSE exiting */
2455         );
2456         if (proc & PROCBASED_SECONDARY_CONTROLS)
2457                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2458                 "\020"
2459                 "\001APIC"              /* Virtualize APIC accesses */
2460                 "\002EPT"               /* Enable EPT */
2461                 "\003DT"                /* Descriptor-table exiting */
2462                 "\004RDTSCP"            /* Enable RDTSCP */
2463                 "\005x2APIC"            /* Virtualize x2APIC mode */
2464                 "\006VPID"              /* Enable VPID */
2465                 "\007WBINVD"            /* WBINVD exiting */
2466                 "\010UG"                /* Unrestricted guest */
2467                 "\011APIC-reg"          /* APIC-register virtualization */
2468                 "\012VID"               /* Virtual-interrupt delivery */
2469                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2470                 "\014RDRAND"            /* RDRAND exiting */
2471                 "\015INVPCID"           /* Enable INVPCID */
2472                 "\016VMFUNC"            /* Enable VM functions */
2473                 "\017VMCS"              /* VMCS shadowing */
2474                 "\020EPT#VE"            /* EPT-violation #VE */
2475                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2476                 );
2477         printf("\n        Exit Controls=0x%b", mask,
2478         "\020"
2479         "\003DR"                /* Save debug controls */
2480                                 /* Ignore Host address-space size */
2481         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2482         "\020AckInt"            /* Acknowledge interrupt on exit */
2483         "\023PAT-SV"            /* Save MSR_PAT */
2484         "\024PAT-LD"            /* Load MSR_PAT */
2485         "\025EFER-SV"           /* Save MSR_EFER */
2486         "\026EFER-LD"           /* Load MSR_EFER */
2487         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2488         );
2489         printf("\n        Entry Controls=0x%b", mask,
2490         "\020"
2491         "\003DR"                /* Save debug controls */
2492                                 /* Ignore IA-32e mode guest */
2493                                 /* Ignore Entry to SMM */
2494                                 /* Ignore Deactivate dual-monitor treatment */
2495         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2496         "\017PAT"               /* Load MSR_PAT */
2497         "\020EFER"              /* Load MSR_EFER */
2498         );
2499         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2500             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2501                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2502                 mask = msr;
2503                 printf("\n        EPT Features=0x%b", mask,
2504                 "\020"
2505                 "\001XO"                /* Execute-only translations */
2506                 "\007PW4"               /* Page-walk length of 4 */
2507                 "\011UC"                /* EPT paging-structure mem can be UC */
2508                 "\017WB"                /* EPT paging-structure mem can be WB */
2509                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2510                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2511                 "\025INVEPT"            /* INVEPT is supported */
2512                 "\026AD"                /* Accessed and dirty flags for EPT */
2513                 "\032single"            /* INVEPT single-context type */
2514                 "\033all"               /* INVEPT all-context type */
2515                 );
2516                 mask = msr >> 32;
2517                 printf("\n        VPID Features=0x%b", mask,
2518                 "\020"
2519                 "\001INVVPID"           /* INVVPID is supported */
2520                 "\011individual"        /* INVVPID individual-address type */
2521                 "\012single"            /* INVVPID single-context type */
2522                 "\013all"               /* INVVPID all-context type */
2523                  /* INVVPID single-context-retaining-globals type */
2524                 "\014single-globals"
2525                 );
2526         }
2527 }
2528
2529 static void
2530 print_hypervisor_info(void)
2531 {
2532
2533         if (*hv_vendor)
2534                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2535 }