sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_pminfo;             /* AMD advanced power management info */
  95 u_int   via_feature_rng;        /* VIA RNG features */
  96 u_int   via_feature_xcrypt;     /* VIA ACE features */
  97 u_int   cpu_high;               /* Highest arg to CPUID */
  98 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  99 u_int   cpu_id;                 /* Stepping ID */
 100 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 101 u_int   cpu_procinfo2;          /* Multicore info */
 102 char    cpu_vendor[20];         /* CPU Origin code */
 103 u_int   cpu_vendor_id;          /* CPU vendor ID */
 104 u_int   cpu_fxsr;               /* SSE enabled */
 105 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 106 u_int   cpu_clflush_line_size = 32;
 107 u_int   cpu_stdext_feature;
 108 u_int   cpu_stdext_feature2;
 109 u_int   cpu_max_ext_state_size;
 110 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 111 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 112 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 113 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 114 char machine[] = MACHINE;
 115
 116 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 117     &via_feature_rng, 0,
 118     "VIA RNG feature available in CPU");
 119 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 120     &via_feature_xcrypt, 0,
 121     "VIA xcrypt feature available in CPU");
 122
 123 #ifdef __amd64__
 124 #ifdef SCTL_MASK32
 125 extern int adaptive_machine_arch;
 126 #endif
 127
 128 static int
 129 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 130 {
 131 #ifdef SCTL_MASK32
 132         static const char machine32[] = "i386";
 133 #endif
 134         int error;
 135
 136 #ifdef SCTL_MASK32
 137         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 138                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 139         else
 140 #endif
 141                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 142         return (error);
 143
 144 }
 145 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 146     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 147 #else
 148 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 149     machine, 0, "Machine class");
 150 #endif
 151
 152 static char cpu_model[128];
 153 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 154     cpu_model, 0, "Machine model");
 155
 156 static int hw_clockrate;
 157 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 158     &hw_clockrate, 0, "CPU instruction clock rate");
 159
 160 u_int hv_high;
 161 char hv_vendor[16];
 162 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 163     0, "Hypervisor vendor");
 164
 165 static eventhandler_tag tsc_post_tag;
 166
 167 static char cpu_brand[48];
 168
 169 #ifdef __i386__
 170 #define MAX_BRAND_INDEX 8
 171
 172 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 173         NULL,                   /* No brand */
 174         "Intel Celeron",
 175         "Intel Pentium III",
 176         "Intel Pentium III Xeon",
 177         NULL,
 178         NULL,
 179         NULL,
 180         NULL,
 181         "Intel Pentium 4"
 182 };
 183
 184 static struct {
 185         char    *cpu_name;
 186         int     cpu_class;
 187 } cpus[] = {
 188         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 189         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 190         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 191         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 192         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 193         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 194         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 195         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 196         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 197         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 198         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 199         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 200         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 201         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 202         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 203         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 204         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 205 };
 206 #endif
 207
 208 static struct {
 209         char    *vendor;
 210         u_int   vendor_id;
 211 } cpu_vendors[] = {
 212         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 213         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 214         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 215 #ifdef __i386__
 216         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 217         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 218         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 219         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 220         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 221         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 222         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 223 #if 0
 224         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 225         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 226 #endif
 227 #endif
 228 };
 229
 230 void
 231 printcpuinfo(void)
 232 {
 233         u_int regs[4], i;
 234         char *brand;
 235
 236         printf("CPU: ");
 237 #ifdef __i386__
 238         cpu_class = cpus[cpu].cpu_class;
 239         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 240 #else
 241         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 242 #endif
 243
 244         /* Check for extended CPUID information and a processor name. */
 245         if (cpu_exthigh >= 0x80000004) {
 246                 brand = cpu_brand;
 247                 for (i = 0x80000002; i < 0x80000005; i++) {
 248                         do_cpuid(i, regs);
 249                         memcpy(brand, regs, sizeof(regs));
 250                         brand += sizeof(regs);
 251                 }
 252         }
 253
 254         switch (cpu_vendor_id) {
 255         case CPU_VENDOR_INTEL:
 256 #ifdef __i386__
 257                 if ((cpu_id & 0xf00) > 0x300) {
 258                         u_int brand_index;
 259
 260                         cpu_model[0] = '\0';
 261
 262                         switch (cpu_id & 0x3000) {
 263                         case 0x1000:
 264                                 strcpy(cpu_model, "Overdrive ");
 265                                 break;
 266                         case 0x2000:
 267                                 strcpy(cpu_model, "Dual ");
 268                                 break;
 269                         }
 270
 271                         switch (cpu_id & 0xf00) {
 272                         case 0x400:
 273                                 strcat(cpu_model, "i486 ");
 274                                 /* Check the particular flavor of 486 */
 275                                 switch (cpu_id & 0xf0) {
 276                                 case 0x00:
 277                                 case 0x10:
 278                                         strcat(cpu_model, "DX");
 279                                         break;
 280                                 case 0x20:
 281                                         strcat(cpu_model, "SX");
 282                                         break;
 283                                 case 0x30:
 284                                         strcat(cpu_model, "DX2");
 285                                         break;
 286                                 case 0x40:
 287                                         strcat(cpu_model, "SL");
 288                                         break;
 289                                 case 0x50:
 290                                         strcat(cpu_model, "SX2");
 291                                         break;
 292                                 case 0x70:
 293                                         strcat(cpu_model,
 294                                             "DX2 Write-Back Enhanced");
 295                                         break;
 296                                 case 0x80:
 297                                         strcat(cpu_model, "DX4");
 298                                         break;
 299                                 }
 300                                 break;
 301                         case 0x500:
 302                                 /* Check the particular flavor of 586 */
 303                                 strcat(cpu_model, "Pentium");
 304                                 switch (cpu_id & 0xf0) {
 305                                 case 0x00:
 306                                         strcat(cpu_model, " A-step");
 307                                         break;
 308                                 case 0x10:
 309                                         strcat(cpu_model, "/P5");
 310                                         break;
 311                                 case 0x20:
 312                                         strcat(cpu_model, "/P54C");
 313                                         break;
 314                                 case 0x30:
 315                                         strcat(cpu_model, "/P24T");
 316                                         break;
 317                                 case 0x40:
 318                                         strcat(cpu_model, "/P55C");
 319                                         break;
 320                                 case 0x70:
 321                                         strcat(cpu_model, "/P54C");
 322                                         break;
 323                                 case 0x80:
 324                                         strcat(cpu_model, "/P55C (quarter-micron)");
 325                                         break;
 326                                 default:
 327                                         /* nothing */
 328                                         break;
 329                                 }
 330 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 331                                 /*
 332                                  * XXX - If/when Intel fixes the bug, this
 333                                  * should also check the version of the
 334                                  * CPU, not just that it's a Pentium.
 335                                  */
 336                                 has_f00f_bug = 1;
 337 #endif
 338                                 break;
 339                         case 0x600:
 340                                 /* Check the particular flavor of 686 */
 341                                 switch (cpu_id & 0xf0) {
 342                                 case 0x00:
 343                                         strcat(cpu_model, "Pentium Pro A-step");
 344                                         break;
 345                                 case 0x10:
 346                                         strcat(cpu_model, "Pentium Pro");
 347                                         break;
 348                                 case 0x30:
 349                                 case 0x50:
 350                                 case 0x60:
 351                                         strcat(cpu_model,
 352                                 "Pentium II/Pentium II Xeon/Celeron");
 353                                         cpu = CPU_PII;
 354                                         break;
 355                                 case 0x70:
 356                                 case 0x80:
 357                                 case 0xa0:
 358                                 case 0xb0:
 359                                         strcat(cpu_model,
 360                                         "Pentium III/Pentium III Xeon/Celeron");
 361                                         cpu = CPU_PIII;
 362                                         break;
 363                                 default:
 364                                         strcat(cpu_model, "Unknown 80686");
 365                                         break;
 366                                 }
 367                                 break;
 368                         case 0xf00:
 369                                 strcat(cpu_model, "Pentium 4");
 370                                 cpu = CPU_P4;
 371                                 break;
 372                         default:
 373                                 strcat(cpu_model, "unknown");
 374                                 break;
 375                         }
 376
 377                         /*
 378                          * If we didn't get a brand name from the extended
 379                          * CPUID, try to look it up in the brand table.
 380                          */
 381                         if (cpu_high > 0 && *cpu_brand == '\0') {
 382                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 383                                 if (brand_index <= MAX_BRAND_INDEX &&
 384                                     cpu_brandtable[brand_index] != NULL)
 385                                         strcpy(cpu_brand,
 386                                             cpu_brandtable[brand_index]);
 387                         }
 388                 }
 389 #else
 390                 /* Please make up your mind folks! */
 391                 strcat(cpu_model, "EM64T");
 392 #endif
 393                 break;
 394         case CPU_VENDOR_AMD:
 395                 /*
 396                  * Values taken from AMD Processor Recognition
 397                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 398                  * (also describes ``Features'' encodings.
 399                  */
 400                 strcpy(cpu_model, "AMD ");
 401 #ifdef __i386__
 402                 switch (cpu_id & 0xFF0) {
 403                 case 0x410:
 404                         strcat(cpu_model, "Standard Am486DX");
 405                         break;
 406                 case 0x430:
 407                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 408                         break;
 409                 case 0x470:
 410                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 411                         break;
 412                 case 0x480:
 413                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 414                         break;
 415                 case 0x490:
 416                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 417                         break;
 418                 case 0x4E0:
 419                         strcat(cpu_model, "Am5x86 Write-Through");
 420                         break;
 421                 case 0x4F0:
 422                         strcat(cpu_model, "Am5x86 Write-Back");
 423                         break;
 424                 case 0x500:
 425                         strcat(cpu_model, "K5 model 0");
 426                         break;
 427                 case 0x510:
 428                         strcat(cpu_model, "K5 model 1");
 429                         break;
 430                 case 0x520:
 431                         strcat(cpu_model, "K5 PR166 (model 2)");
 432                         break;
 433                 case 0x530:
 434                         strcat(cpu_model, "K5 PR200 (model 3)");
 435                         break;
 436                 case 0x560:
 437                         strcat(cpu_model, "K6");
 438                         break;
 439                 case 0x570:
 440                         strcat(cpu_model, "K6 266 (model 1)");
 441                         break;
 442                 case 0x580:
 443                         strcat(cpu_model, "K6-2");
 444                         break;
 445                 case 0x590:
 446                         strcat(cpu_model, "K6-III");
 447                         break;
 448                 case 0x5a0:
 449                         strcat(cpu_model, "Geode LX");
 450                         break;
 451                 default:
 452                         strcat(cpu_model, "Unknown");
 453                         break;
 454                 }
 455 #else
 456                 if ((cpu_id & 0xf00) == 0xf00)
 457                         strcat(cpu_model, "AMD64 Processor");
 458                 else
 459                         strcat(cpu_model, "Unknown");
 460 #endif
 461                 break;
 462 #ifdef __i386__
 463         case CPU_VENDOR_CYRIX:
 464                 strcpy(cpu_model, "Cyrix ");
 465                 switch (cpu_id & 0xff0) {
 466                 case 0x440:
 467                         strcat(cpu_model, "MediaGX");
 468                         break;
 469                 case 0x520:
 470                         strcat(cpu_model, "6x86");
 471                         break;
 472                 case 0x540:
 473                         cpu_class = CPUCLASS_586;
 474                         strcat(cpu_model, "GXm");
 475                         break;
 476                 case 0x600:
 477                         strcat(cpu_model, "6x86MX");
 478                         break;
 479                 default:
 480                         /*
 481                          * Even though CPU supports the cpuid
 482                          * instruction, it can be disabled.
 483                          * Therefore, this routine supports all Cyrix
 484                          * CPUs.
 485                          */
 486                         switch (cyrix_did & 0xf0) {
 487                         case 0x00:
 488                                 switch (cyrix_did & 0x0f) {
 489                                 case 0x00:
 490                                         strcat(cpu_model, "486SLC");
 491                                         break;
 492                                 case 0x01:
 493                                         strcat(cpu_model, "486DLC");
 494                                         break;
 495                                 case 0x02:
 496                                         strcat(cpu_model, "486SLC2");
 497                                         break;
 498                                 case 0x03:
 499                                         strcat(cpu_model, "486DLC2");
 500                                         break;
 501                                 case 0x04:
 502                                         strcat(cpu_model, "486SRx");
 503                                         break;
 504                                 case 0x05:
 505                                         strcat(cpu_model, "486DRx");
 506                                         break;
 507                                 case 0x06:
 508                                         strcat(cpu_model, "486SRx2");
 509                                         break;
 510                                 case 0x07:
 511                                         strcat(cpu_model, "486DRx2");
 512                                         break;
 513                                 case 0x08:
 514                                         strcat(cpu_model, "486SRu");
 515                                         break;
 516                                 case 0x09:
 517                                         strcat(cpu_model, "486DRu");
 518                                         break;
 519                                 case 0x0a:
 520                                         strcat(cpu_model, "486SRu2");
 521                                         break;
 522                                 case 0x0b:
 523                                         strcat(cpu_model, "486DRu2");
 524                                         break;
 525                                 default:
 526                                         strcat(cpu_model, "Unknown");
 527                                         break;
 528                                 }
 529                                 break;
 530                         case 0x10:
 531                                 switch (cyrix_did & 0x0f) {
 532                                 case 0x00:
 533                                         strcat(cpu_model, "486S");
 534                                         break;
 535                                 case 0x01:
 536                                         strcat(cpu_model, "486S2");
 537                                         break;
 538                                 case 0x02:
 539                                         strcat(cpu_model, "486Se");
 540                                         break;
 541                                 case 0x03:
 542                                         strcat(cpu_model, "486S2e");
 543                                         break;
 544                                 case 0x0a:
 545                                         strcat(cpu_model, "486DX");
 546                                         break;
 547                                 case 0x0b:
 548                                         strcat(cpu_model, "486DX2");
 549                                         break;
 550                                 case 0x0f:
 551                                         strcat(cpu_model, "486DX4");
 552                                         break;
 553                                 default:
 554                                         strcat(cpu_model, "Unknown");
 555                                         break;
 556                                 }
 557                                 break;
 558                         case 0x20:
 559                                 if ((cyrix_did & 0x0f) < 8)
 560                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 561                                 else
 562                                         strcat(cpu_model, "5x86");
 563                                 break;
 564                         case 0x30:
 565                                 strcat(cpu_model, "6x86");
 566                                 break;
 567                         case 0x40:
 568                                 if ((cyrix_did & 0xf000) == 0x3000) {
 569                                         cpu_class = CPUCLASS_586;
 570                                         strcat(cpu_model, "GXm");
 571                                 } else
 572                                         strcat(cpu_model, "MediaGX");
 573                                 break;
 574                         case 0x50:
 575                                 strcat(cpu_model, "6x86MX");
 576                                 break;
 577                         case 0xf0:
 578                                 switch (cyrix_did & 0x0f) {
 579                                 case 0x0d:
 580                                         strcat(cpu_model, "Overdrive CPU");
 581                                         break;
 582                                 case 0x0e:
 583                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 584                                         break;
 585                                 case 0x0f:
 586                                         strcat(cpu_model, "486SLC/DLC");
 587                                         break;
 588                                 default:
 589                                         strcat(cpu_model, "Unknown");
 590                                         break;
 591                                 }
 592                                 break;
 593                         default:
 594                                 strcat(cpu_model, "Unknown");
 595                                 break;
 596                         }
 597                         break;
 598                 }
 599                 break;
 600         case CPU_VENDOR_RISE:
 601                 strcpy(cpu_model, "Rise ");
 602                 switch (cpu_id & 0xff0) {
 603                 case 0x500:     /* 6401 and 6441 (Kirin) */
 604                 case 0x520:     /* 6510 (Lynx) */
 605                         strcat(cpu_model, "mP6");
 606                         break;
 607                 default:
 608                         strcat(cpu_model, "Unknown");
 609                 }
 610                 break;
 611 #endif
 612         case CPU_VENDOR_CENTAUR:
 613 #ifdef __i386__
 614                 switch (cpu_id & 0xff0) {
 615                 case 0x540:
 616                         strcpy(cpu_model, "IDT WinChip C6");
 617                         break;
 618                 case 0x580:
 619                         strcpy(cpu_model, "IDT WinChip 2");
 620                         break;
 621                 case 0x590:
 622                         strcpy(cpu_model, "IDT WinChip 3");
 623                         break;
 624                 case 0x660:
 625                         strcpy(cpu_model, "VIA C3 Samuel");
 626                         break;
 627                 case 0x670:
 628                         if (cpu_id & 0x8)
 629                                 strcpy(cpu_model, "VIA C3 Ezra");
 630                         else
 631                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 632                         break;
 633                 case 0x680:
 634                         strcpy(cpu_model, "VIA C3 Ezra-T");
 635                         break;
 636                 case 0x690:
 637                         strcpy(cpu_model, "VIA C3 Nehemiah");
 638                         break;
 639                 case 0x6a0:
 640                 case 0x6d0:
 641                         strcpy(cpu_model, "VIA C7 Esther");
 642                         break;
 643                 case 0x6f0:
 644                         strcpy(cpu_model, "VIA Nano");
 645                         break;
 646                 default:
 647                         strcpy(cpu_model, "VIA/IDT Unknown");
 648                 }
 649 #else
 650                 strcpy(cpu_model, "VIA ");
 651                 if ((cpu_id & 0xff0) == 0x6f0)
 652                         strcat(cpu_model, "Nano Processor");
 653                 else
 654                         strcat(cpu_model, "Unknown");
 655 #endif
 656                 break;
 657 #ifdef __i386__
 658         case CPU_VENDOR_IBM:
 659                 strcpy(cpu_model, "Blue Lightning CPU");
 660                 break;
 661         case CPU_VENDOR_NSC:
 662                 switch (cpu_id & 0xff0) {
 663                 case 0x540:
 664                         strcpy(cpu_model, "Geode SC1100");
 665                         cpu = CPU_GEODE1100;
 666                         break;
 667                 default:
 668                         strcpy(cpu_model, "Geode/NSC unknown");
 669                         break;
 670                 }
 671                 break;
 672 #endif
 673         default:
 674                 strcat(cpu_model, "Unknown");
 675                 break;
 676         }
 677
 678         /*
 679          * Replace cpu_model with cpu_brand minus leading spaces if
 680          * we have one.
 681          */
 682         brand = cpu_brand;
 683         while (*brand == ' ')
 684                 ++brand;
 685         if (*brand != '\0')
 686                 strcpy(cpu_model, brand);
 687
 688         printf("%s (", cpu_model);
 689         if (tsc_freq != 0) {
 690                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 691                 printf("%jd.%02d-MHz ",
 692                     (intmax_t)(tsc_freq + 4999) / 1000000,
 693                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 694         }
 695 #ifdef __i386__
 696         switch(cpu_class) {
 697         case CPUCLASS_286:
 698                 printf("286");
 699                 break;
 700         case CPUCLASS_386:
 701                 printf("386");
 702                 break;
 703 #if defined(I486_CPU)
 704         case CPUCLASS_486:
 705                 printf("486");
 706                 break;
 707 #endif
 708 #if defined(I586_CPU)
 709         case CPUCLASS_586:
 710                 printf("586");
 711                 break;
 712 #endif
 713 #if defined(I686_CPU)
 714         case CPUCLASS_686:
 715                 printf("686");
 716                 break;
 717 #endif
 718         default:
 719                 printf("Unknown");      /* will panic below... */
 720         }
 721 #else
 722         printf("K8");
 723 #endif
 724         printf("-class CPU)\n");
 725         if (*cpu_vendor)
 726                 printf("  Origin=\"%s\"", cpu_vendor);
 727         if (cpu_id)
 728                 printf("  Id=0x%x", cpu_id);
 729
 730         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 731             cpu_vendor_id == CPU_VENDOR_AMD ||
 732             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 733 #ifdef __i386__
 734             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 735             cpu_vendor_id == CPU_VENDOR_RISE ||
 736             cpu_vendor_id == CPU_VENDOR_NSC ||
 737             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 738 #endif
 739             0) {
 740                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 741                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 742                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 743 #ifdef __i386__
 744                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 745                         printf("\n  DIR=0x%04x", cyrix_did);
 746 #endif
 747
 748                 /*
 749                  * AMD CPUID Specification
 750                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 751                  *
 752                  * Intel Processor Identification and CPUID Instruction
 753                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 754                  */
 755                 if (cpu_high > 0) {
 756
 757                         /*
 758                          * Here we should probably set up flags indicating
 759                          * whether or not various features are available.
 760                          * The interesting ones are probably VME, PSE, PAE,
 761                          * and PGE.  The code already assumes without bothering
 762                          * to check that all CPUs >= Pentium have a TSC and
 763                          * MSRs.
 764                          */
 765                         printf("\n  Features=0x%b", cpu_feature,
 766                         "\020"
 767                         "\001FPU"       /* Integral FPU */
 768                         "\002VME"       /* Extended VM86 mode support */
 769                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 770                         "\004PSE"       /* 4MByte page tables */
 771                         "\005TSC"       /* Timestamp counter */
 772                         "\006MSR"       /* Machine specific registers */
 773                         "\007PAE"       /* Physical address extension */
 774                         "\010MCE"       /* Machine Check support */
 775                         "\011CX8"       /* CMPEXCH8 instruction */
 776                         "\012APIC"      /* SMP local APIC */
 777                         "\013oldMTRR"   /* Previous implementation of MTRR */
 778                         "\014SEP"       /* Fast System Call */
 779                         "\015MTRR"      /* Memory Type Range Registers */
 780                         "\016PGE"       /* PG_G (global bit) support */
 781                         "\017MCA"       /* Machine Check Architecture */
 782                         "\020CMOV"      /* CMOV instruction */
 783                         "\021PAT"       /* Page attributes table */
 784                         "\022PSE36"     /* 36 bit address space support */
 785                         "\023PN"        /* Processor Serial number */
 786                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 787                         "\025<b20>"
 788                         "\026DTS"       /* Debug Trace Store */
 789                         "\027ACPI"      /* ACPI support */
 790                         "\030MMX"       /* MMX instructions */
 791                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 792                         "\032SSE"       /* Streaming SIMD Extensions */
 793                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 794                         "\034SS"        /* Self snoop */
 795                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 796                         "\036TM"        /* Thermal Monitor clock slowdown */
 797                         "\037IA64"      /* CPU can execute IA64 instructions */
 798                         "\040PBE"       /* Pending Break Enable */
 799                         );
 800
 801                         if (cpu_feature2 != 0) {
 802                                 printf("\n  Features2=0x%b", cpu_feature2,
 803                                 "\020"
 804                                 "\001SSE3"      /* SSE3 */
 805                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 806                                 "\003DTES64"    /* 64-bit Debug Trace */
 807                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 808                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 809                                 "\006VMX"       /* Virtual Machine Extensions */
 810                                 "\007SMX"       /* Safer Mode Extensions */
 811                                 "\010EST"       /* Enhanced SpeedStep */
 812                                 "\011TM2"       /* Thermal Monitor 2 */
 813                                 "\012SSSE3"     /* SSSE3 */
 814                                 "\013CNXT-ID"   /* L1 context ID available */
 815                                 "\014SDBG"      /* IA32 silicon debug */
 816                                 "\015FMA"       /* Fused Multiply Add */
 817                                 "\016CX16"      /* CMPXCHG16B Instruction */
 818                                 "\017xTPR"      /* Send Task Priority Messages*/
 819                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 820                                 "\021<b16>"
 821                                 "\022PCID"      /* Process-context Identifiers*/
 822                                 "\023DCA"       /* Direct Cache Access */
 823                                 "\024SSE4.1"    /* SSE 4.1 */
 824                                 "\025SSE4.2"    /* SSE 4.2 */
 825                                 "\026x2APIC"    /* xAPIC Extensions */
 826                                 "\027MOVBE"     /* MOVBE Instruction */
 827                                 "\030POPCNT"    /* POPCNT Instruction */
 828                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 829                                 "\032AESNI"     /* AES Crypto */
 830                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 831                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 832                                 "\035AVX"       /* Advanced Vector Extensions */
 833                                 "\036F16C"      /* Half-precision conversions */
 834                                 "\037RDRAND"    /* RDRAND Instruction */
 835                                 "\040HV"        /* Hypervisor */
 836                                 );
 837                         }
 838
 839                         if (amd_feature != 0) {
 840                                 printf("\n  AMD Features=0x%b", amd_feature,
 841                                 "\020"          /* in hex */
 842                                 "\001<s0>"      /* Same */
 843                                 "\002<s1>"      /* Same */
 844                                 "\003<s2>"      /* Same */
 845                                 "\004<s3>"      /* Same */
 846                                 "\005<s4>"      /* Same */
 847                                 "\006<s5>"      /* Same */
 848                                 "\007<s6>"      /* Same */
 849                                 "\010<s7>"      /* Same */
 850                                 "\011<s8>"      /* Same */
 851                                 "\012<s9>"      /* Same */
 852                                 "\013<b10>"     /* Undefined */
 853                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 854                                 "\015<s12>"     /* Same */
 855                                 "\016<s13>"     /* Same */
 856                                 "\017<s14>"     /* Same */
 857                                 "\020<s15>"     /* Same */
 858                                 "\021<s16>"     /* Same */
 859                                 "\022<s17>"     /* Same */
 860                                 "\023<b18>"     /* Reserved, unknown */
 861                                 "\024MP"        /* Multiprocessor Capable */
 862                                 "\025NX"        /* Has EFER.NXE, NX */
 863                                 "\026<b21>"     /* Undefined */
 864                                 "\027MMX+"      /* AMD MMX Extensions */
 865                                 "\030<s23>"     /* Same */
 866                                 "\031<s24>"     /* Same */
 867                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 868                                 "\033Page1GB"   /* 1-GB large page support */
 869                                 "\034RDTSCP"    /* RDTSCP */
 870                                 "\035<b28>"     /* Undefined */
 871                                 "\036LM"        /* 64 bit long mode */
 872                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 873                                 "\0403DNow!"    /* AMD 3DNow! */
 874                                 );
 875                         }
 876
 877                         if (amd_feature2 != 0) {
 878                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 879                                 "\020"
 880                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 881                                 "\002CMP"       /* CMP legacy */
 882                                 "\003SVM"       /* Secure Virtual Mode */
 883                                 "\004ExtAPIC"   /* Extended APIC register */
 884                                 "\005CR8"       /* CR8 in legacy mode */
 885                                 "\006ABM"       /* LZCNT instruction */
 886                                 "\007SSE4A"     /* SSE4A */
 887                                 "\010MAS"       /* Misaligned SSE mode */
 888                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 889                                 "\012OSVW"      /* OS visible workaround */
 890                                 "\013IBS"       /* Instruction based sampling */
 891                                 "\014XOP"       /* XOP extended instructions */
 892                                 "\015SKINIT"    /* SKINIT/STGI */
 893                                 "\016WDT"       /* Watchdog timer */
 894                                 "\017<b14>"
 895                                 "\020LWP"       /* Lightweight Profiling */
 896                                 "\021FMA4"      /* 4-operand FMA instructions */
 897                                 "\022TCE"       /* Translation Cache Extension */
 898                                 "\023<b18>"
 899                                 "\024NodeId"    /* NodeId MSR support */
 900                                 "\025<b20>"
 901                                 "\026TBM"       /* Trailing Bit Manipulation */
 902                                 "\027Topology"  /* Topology Extensions */
 903                                 "\030PCXC"      /* Core perf count */
 904                                 "\031PNXC"      /* NB perf count */
 905                                 "\032<b25>"
 906                                 "\033DBE"       /* Data Breakpoint extension */
 907                                 "\034PTSC"      /* Performance TSC */
 908                                 "\035PL2I"      /* L2I perf count */
 909                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 910                                 "\037<b30>"
 911                                 "\040<b31>"
 912                                 );
 913                         }
 914
 915                         if (cpu_stdext_feature != 0) {
 916                                 printf("\n  Structured Extended Features=0x%b",
 917                                     cpu_stdext_feature,
 918                                        "\020"
 919                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 920                                        "\001FSGSBASE"
 921                                        "\002TSCADJ"
 922                                        "\003SGX"
 923                                        /* Bit Manipulation Instructions */
 924                                        "\004BMI1"
 925                                        /* Hardware Lock Elision */
 926                                        "\005HLE"
 927                                        /* Advanced Vector Instructions 2 */
 928                                        "\006AVX2"
 929                                        /* FDP_EXCPTN_ONLY */
 930                                        "\007FDPEXC"
 931                                        /* Supervisor Mode Execution Prot. */
 932                                        "\010SMEP"
 933                                        /* Bit Manipulation Instructions */
 934                                        "\011BMI2"
 935                                        "\012ERMS"
 936                                        /* Invalidate Processor Context ID */
 937                                        "\013INVPCID"
 938                                        /* Restricted Transactional Memory */
 939                                        "\014RTM"
 940                                        "\015PQM"
 941                                        "\016NFPUSG"
 942                                        /* Intel Memory Protection Extensions */
 943                                        "\017MPX"
 944                                        "\020PQE"
 945                                        /* AVX512 Foundation */
 946                                        "\021AVX512F"
 947                                        "\022AVX512DQ"
 948                                        /* Enhanced NRBG */
 949                                        "\023RDSEED"
 950                                        /* ADCX + ADOX */
 951                                        "\024ADX"
 952                                        /* Supervisor Mode Access Prevention */
 953                                        "\025SMAP"
 954                                        "\026AVX512IFMA"
 955                                        "\027PCOMMIT"
 956                                        "\030CLFLUSHOPT"
 957                                        "\031CLWB"
 958                                        "\032PROCTRACE"
 959                                        "\033AVX512PF"
 960                                        "\034AVX512ER"
 961                                        "\035AVX512CD"
 962                                        "\036SHA"
 963                                        "\037AVX512BW"
 964                                        );
 965                         }
 966
 967                         if (cpu_stdext_feature2 != 0) {
 968                                 printf("\n  Structured Extended Features2=0x%b",
 969                                     cpu_stdext_feature2,
 970                                        "\020"
 971                                        "\001PREFETCHWT1"
 972                                        "\002AVX512VBMI"
 973                                        "\003UMIP"
 974                                        "\004PKU"
 975                                        "\005OSPKE"
 976                                        "\027RDPID"
 977                                        "\037SGXLC"
 978                                        );
 979                         }
 980
 981                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 982                                 cpuid_count(0xd, 0x1, regs);
 983                                 if (regs[0] != 0) {
 984                                         printf("\n  XSAVE Features=0x%b",
 985                                             regs[0],
 986                                             "\020"
 987                                             "\001XSAVEOPT"
 988                                             "\002XSAVEC"
 989                                             "\003XINUSE"
 990                                             "\004XSAVES");
 991                                 }
 992                         }
 993
 994                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 995                                 print_via_padlock_info();
 996
 997                         if (cpu_feature2 & CPUID2_VMX)
 998                                 print_vmx_info();
 999
1000                         if (amd_feature2 & AMDID2_SVM)
1001                                 print_svm_info();
1002
1003                         if ((cpu_feature & CPUID_HTT) &&
1004                             cpu_vendor_id == CPU_VENDOR_AMD)
1005                                 cpu_feature &= ~CPUID_HTT;
1006
1007                         /*
1008                          * If this CPU supports P-state invariant TSC then
1009                          * mention the capability.
1010                          */
1011                         if (tsc_is_invariant) {
1012                                 printf("\n  TSC: P-state invariant");
1013                                 if (tsc_perf_stat)
1014                                         printf(", performance statistics");
1015                         }
1016                 }
1017 #ifdef __i386__
1018         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1019                 printf("  DIR=0x%04x", cyrix_did);
1020                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1021                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1022 #ifndef CYRIX_CACHE_REALLY_WORKS
1023                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1024                         printf("\n  CPU cache: write-through mode");
1025 #endif
1026 #endif
1027         }
1028
1029         /* Avoid ugly blank lines: only print newline when we have to. */
1030         if (*cpu_vendor || cpu_id)
1031                 printf("\n");
1032
1033         if (bootverbose) {
1034                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1035                         print_AMD_info();
1036                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1037                         print_INTEL_info();
1038 #ifdef __i386__
1039                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1040                         print_transmeta_info();
1041 #endif
1042         }
1043
1044         print_hypervisor_info();
1045 }
1046
1047 #ifdef __i386__
1048 void
1049 panicifcpuunsupported(void)
1050 {
1051
1052 #if !defined(lint)
1053 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1054 #error This kernel is not configured for one of the supported CPUs
1055 #endif
1056 #else /* lint */
1057 #endif /* lint */
1058         /*
1059          * Now that we have told the user what they have,
1060          * let them know if that machine type isn't configured.
1061          */
1062         switch (cpu_class) {
1063         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1064         case CPUCLASS_386:
1065 #if !defined(I486_CPU)
1066         case CPUCLASS_486:
1067 #endif
1068 #if !defined(I586_CPU)
1069         case CPUCLASS_586:
1070 #endif
1071 #if !defined(I686_CPU)
1072         case CPUCLASS_686:
1073 #endif
1074                 panic("CPU class not configured");
1075         default:
1076                 break;
1077         }
1078 }
1079
1080 static  volatile u_int trap_by_rdmsr;
1081
1082 /*
1083  * Special exception 6 handler.
1084  * The rdmsr instruction generates invalid opcodes fault on 486-class
1085  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1086  * function identblue() when this handler is called.  Stacked eip should
1087  * be advanced.
1088  */
1089 inthand_t       bluetrap6;
1090 #ifdef __GNUCLIKE_ASM
1091 __asm
1092 ("                                                                      \n\
1093         .text                                                           \n\
1094         .p2align 2,0x90                                                 \n\
1095         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1096 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1097         ss                                                              \n\
1098         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1099         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1100         iret                                                            \n\
1101 ");
1102 #endif
1103
1104 /*
1105  * Special exception 13 handler.
1106  * Accessing non-existent MSR generates general protection fault.
1107  */
1108 inthand_t       bluetrap13;
1109 #ifdef __GNUCLIKE_ASM
1110 __asm
1111 ("                                                                      \n\
1112         .text                                                           \n\
1113         .p2align 2,0x90                                                 \n\
1114         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1115 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1116         ss                                                              \n\
1117         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1118         popl    %eax            /* discard error code */                \n\
1119         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1120         iret                                                            \n\
1121 ");
1122 #endif
1123
1124 /*
1125  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1126  * support cpuid instruction.  This function should be called after
1127  * loading interrupt descriptor table register.
1128  *
1129  * I don't like this method that handles fault, but I couldn't get
1130  * information for any other methods.  Does blue giant know?
1131  */
1132 static int
1133 identblue(void)
1134 {
1135
1136         trap_by_rdmsr = 0;
1137
1138         /*
1139          * Cyrix 486-class CPU does not support rdmsr instruction.
1140          * The rdmsr instruction generates invalid opcode fault, and exception
1141          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1142          * bluetrap6() set the magic number to trap_by_rdmsr.
1143          */
1144         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1145             GSEL(GCODE_SEL, SEL_KPL));
1146
1147         /*
1148          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1149          * In this case, rdmsr generates general protection fault, and
1150          * exception will be trapped by bluetrap13().
1151          */
1152         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1153             GSEL(GCODE_SEL, SEL_KPL));
1154
1155         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1156
1157         if (trap_by_rdmsr == 0xa8c1d)
1158                 return IDENTBLUE_CYRIX486;
1159         else if (trap_by_rdmsr == 0xa89c4)
1160                 return IDENTBLUE_CYRIXM2;
1161         return IDENTBLUE_IBMCPU;
1162 }
1163
1164
1165 /*
1166  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1167  *
1168  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1169  * +-------+-------+---------------+
1170  * |  SID  |  RID  |   Device ID   |
1171  * |    (DIR 1)    |    (DIR 0)    |
1172  * +-------+-------+---------------+
1173  */
1174 static void
1175 identifycyrix(void)
1176 {
1177         register_t saveintr;
1178         int     ccr2_test = 0, dir_test = 0;
1179         u_char  ccr2, ccr3;
1180
1181         saveintr = intr_disable();
1182
1183         ccr2 = read_cyrix_reg(CCR2);
1184         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1185         read_cyrix_reg(CCR2);
1186         if (read_cyrix_reg(CCR2) != ccr2)
1187                 ccr2_test = 1;
1188         write_cyrix_reg(CCR2, ccr2);
1189
1190         ccr3 = read_cyrix_reg(CCR3);
1191         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1192         read_cyrix_reg(CCR3);
1193         if (read_cyrix_reg(CCR3) != ccr3)
1194                 dir_test = 1;                                   /* CPU supports DIRs. */
1195         write_cyrix_reg(CCR3, ccr3);
1196
1197         if (dir_test) {
1198                 /* Device ID registers are available. */
1199                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1200                 cyrix_did += read_cyrix_reg(DIR0);
1201         } else if (ccr2_test)
1202                 cyrix_did = 0x0010;             /* 486S A-step */
1203         else
1204                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1205
1206         intr_restore(saveintr);
1207 }
1208 #endif
1209
1210 /* Update TSC freq with the value indicated by the caller. */
1211 static void
1212 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1213 {
1214
1215         /* If there was an error during the transition, don't do anything. */
1216         if (status != 0)
1217                 return;
1218
1219         /* Total setting for this level gives the new frequency in MHz. */
1220         hw_clockrate = level->total_set.freq;
1221 }
1222
1223 static void
1224 hook_tsc_freq(void *arg __unused)
1225 {
1226
1227         if (tsc_is_invariant)
1228                 return;
1229
1230         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1231             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1232 }
1233
1234 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1235
1236 static const char *const vm_bnames[] = {
1237         "QEMU",                         /* QEMU */
1238         "Plex86",                       /* Plex86 */
1239         "Bochs",                        /* Bochs */
1240         "Xen",                          /* Xen */
1241         "BHYVE",                        /* bhyve */
1242         "Seabios",                      /* KVM */
1243         NULL
1244 };
1245
1246 static const char *const vm_pnames[] = {
1247         "VMware Virtual Platform",      /* VMWare VM */
1248         "Virtual Machine",              /* Microsoft VirtualPC */
1249         "VirtualBox",                   /* Sun xVM VirtualBox */
1250         "Parallels Virtual Platform",   /* Parallels VM */
1251         "KVM",                          /* KVM */
1252         NULL
1253 };
1254
1255 static void
1256 identify_hypervisor(void)
1257 {
1258         u_int regs[4];
1259         char *p;
1260         int i;
1261
1262         /*
1263          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1264          * http://lkml.org/lkml/2008/10/1/246
1265          *
1266          * KB1009458: Mechanisms to determine if software is running in
1267          * a VMware virtual machine
1268          * http://kb.vmware.com/kb/1009458
1269          */
1270         if (cpu_feature2 & CPUID2_HV) {
1271                 vm_guest = VM_GUEST_VM;
1272                 do_cpuid(0x40000000, regs);
1273                 if (regs[0] >= 0x40000000) {
1274                         hv_high = regs[0];
1275                         ((u_int *)&hv_vendor)[0] = regs[1];
1276                         ((u_int *)&hv_vendor)[1] = regs[2];
1277                         ((u_int *)&hv_vendor)[2] = regs[3];
1278                         hv_vendor[12] = '\0';
1279                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1280                                 vm_guest = VM_GUEST_VMWARE;
1281                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1282                                 vm_guest = VM_GUEST_HV;
1283                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1284                                 vm_guest = VM_GUEST_KVM;
1285                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1286                                 vm_guest = VM_GUEST_BHYVE;
1287                 }
1288                 return;
1289         }
1290
1291         /*
1292          * Examine SMBIOS strings for older hypervisors.
1293          */
1294         p = kern_getenv("smbios.system.serial");
1295         if (p != NULL) {
1296                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1297                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1298                         if (regs[1] == VMW_HVMAGIC) {
1299                                 vm_guest = VM_GUEST_VMWARE;
1300                                 freeenv(p);
1301                                 return;
1302                         }
1303                 }
1304                 freeenv(p);
1305         }
1306
1307         /*
1308          * XXX: Some of these entries may not be needed since they were
1309          * added to FreeBSD before the checks above.
1310          */
1311         p = kern_getenv("smbios.bios.vendor");
1312         if (p != NULL) {
1313                 for (i = 0; vm_bnames[i] != NULL; i++)
1314                         if (strcmp(p, vm_bnames[i]) == 0) {
1315                                 vm_guest = VM_GUEST_VM;
1316                                 freeenv(p);
1317                                 return;
1318                         }
1319                 freeenv(p);
1320         }
1321         p = kern_getenv("smbios.system.product");
1322         if (p != NULL) {
1323                 for (i = 0; vm_pnames[i] != NULL; i++)
1324                         if (strcmp(p, vm_pnames[i]) == 0) {
1325                                 vm_guest = VM_GUEST_VM;
1326                                 freeenv(p);
1327                                 return;
1328                         }
1329                 freeenv(p);
1330         }
1331 }
1332
1333 bool
1334 fix_cpuid(void)
1335 {
1336         uint64_t msr;
1337
1338         /*
1339          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1340          * get the largest standard CPUID function number again if it is set
1341          * from BIOS.  It is necessary for probing correct CPU topology later
1342          * and for the correct operation of the AVX-aware userspace.
1343          */
1344         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1345             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1346             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1347             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1348             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1349                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1350                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1351                         msr &= ~IA32_MISC_EN_LIMCPUID;
1352                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1353                         return (true);
1354                 }
1355         }
1356
1357         /*
1358          * Re-enable AMD Topology Extension that could be disabled by BIOS
1359          * on some notebook processors.  Without the extension it's really
1360          * hard to determine the correct CPU cache topology.
1361          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1362          * Models 60h-6Fh Processors, Publication # 50742.
1363          */
1364         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1365                 msr = rdmsr(MSR_EXTFEATURES);
1366                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1367                         msr |= (uint64_t)1 << 54;
1368                         wrmsr(MSR_EXTFEATURES, msr);
1369                         return (true);
1370                 }
1371         }
1372         return (false);
1373 }
1374
1375 /*
1376  * Final stage of CPU identification.
1377  */
1378 #ifdef __i386__
1379 void
1380 finishidentcpu(void)
1381 #else
1382 void
1383 identify_cpu(void)
1384 #endif
1385 {
1386         u_int regs[4], cpu_stdext_disable;
1387 #ifdef __i386__
1388         u_char ccr3;
1389 #endif
1390
1391 #ifdef __amd64__
1392         do_cpuid(0, regs);
1393         cpu_high = regs[0];
1394         ((u_int *)&cpu_vendor)[0] = regs[1];
1395         ((u_int *)&cpu_vendor)[1] = regs[3];
1396         ((u_int *)&cpu_vendor)[2] = regs[2];
1397         cpu_vendor[12] = '\0';
1398
1399         do_cpuid(1, regs);
1400         cpu_id = regs[0];
1401         cpu_procinfo = regs[1];
1402         cpu_feature = regs[3];
1403         cpu_feature2 = regs[2];
1404 #endif
1405
1406         identify_hypervisor();
1407         cpu_vendor_id = find_cpu_vendor_id();
1408
1409         if (fix_cpuid()) {
1410                 do_cpuid(0, regs);
1411                 cpu_high = regs[0];
1412         }
1413
1414         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1415                 do_cpuid(5, regs);
1416                 cpu_mon_mwait_flags = regs[2];
1417                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1418                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1419         }
1420
1421         if (cpu_high >= 7) {
1422                 cpuid_count(7, 0, regs);
1423                 cpu_stdext_feature = regs[1];
1424
1425                 /*
1426                  * Some hypervisors fail to filter out unsupported
1427                  * extended features.  For now, disable the
1428                  * extensions, activation of which requires setting a
1429                  * bit in CR4, and which VM monitors do not support.
1430                  */
1431                 if (cpu_feature2 & CPUID2_HV) {
1432                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1433                             CPUID_STDEXT_SMEP;
1434                 } else
1435                         cpu_stdext_disable = 0;
1436                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1437                 cpu_stdext_feature &= ~cpu_stdext_disable;
1438                 cpu_stdext_feature2 = regs[2];
1439         }
1440
1441 #ifdef __i386__
1442         if (cpu_high > 0 &&
1443             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1444              cpu_vendor_id == CPU_VENDOR_AMD ||
1445              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1446              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1447              cpu_vendor_id == CPU_VENDOR_NSC)) {
1448                 do_cpuid(0x80000000, regs);
1449                 if (regs[0] >= 0x80000000)
1450                         cpu_exthigh = regs[0];
1451         }
1452 #else
1453         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1454             cpu_vendor_id == CPU_VENDOR_AMD ||
1455             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1456                 do_cpuid(0x80000000, regs);
1457                 cpu_exthigh = regs[0];
1458         }
1459 #endif
1460         if (cpu_exthigh >= 0x80000001) {
1461                 do_cpuid(0x80000001, regs);
1462                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1463                 amd_feature2 = regs[2];
1464         }
1465         if (cpu_exthigh >= 0x80000007) {
1466                 do_cpuid(0x80000007, regs);
1467                 amd_pminfo = regs[3];
1468         }
1469         if (cpu_exthigh >= 0x80000008) {
1470                 do_cpuid(0x80000008, regs);
1471                 cpu_maxphyaddr = regs[0] & 0xff;
1472                 cpu_procinfo2 = regs[2];
1473         } else {
1474                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1475         }
1476
1477 #ifdef __i386__
1478         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1479                 if (cpu == CPU_486) {
1480                         /*
1481                          * These conditions are equivalent to:
1482                          *     - CPU does not support cpuid instruction.
1483                          *     - Cyrix/IBM CPU is detected.
1484                          */
1485                         if (identblue() == IDENTBLUE_IBMCPU) {
1486                                 strcpy(cpu_vendor, "IBM");
1487                                 cpu_vendor_id = CPU_VENDOR_IBM;
1488                                 cpu = CPU_BLUE;
1489                                 return;
1490                         }
1491                 }
1492                 switch (cpu_id & 0xf00) {
1493                 case 0x600:
1494                         /*
1495                          * Cyrix's datasheet does not describe DIRs.
1496                          * Therefor, I assume it does not have them
1497                          * and use the result of the cpuid instruction.
1498                          * XXX they seem to have it for now at least. -Peter
1499                          */
1500                         identifycyrix();
1501                         cpu = CPU_M2;
1502                         break;
1503                 default:
1504                         identifycyrix();
1505                         /*
1506                          * This routine contains a trick.
1507                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1508                          */
1509                         switch (cyrix_did & 0x00f0) {
1510                         case 0x00:
1511                         case 0xf0:
1512                                 cpu = CPU_486DLC;
1513                                 break;
1514                         case 0x10:
1515                                 cpu = CPU_CY486DX;
1516                                 break;
1517                         case 0x20:
1518                                 if ((cyrix_did & 0x000f) < 8)
1519                                         cpu = CPU_M1;
1520                                 else
1521                                         cpu = CPU_M1SC;
1522                                 break;
1523                         case 0x30:
1524                                 cpu = CPU_M1;
1525                                 break;
1526                         case 0x40:
1527                                 /* MediaGX CPU */
1528                                 cpu = CPU_M1SC;
1529                                 break;
1530                         default:
1531                                 /* M2 and later CPUs are treated as M2. */
1532                                 cpu = CPU_M2;
1533
1534                                 /*
1535                                  * enable cpuid instruction.
1536                                  */
1537                                 ccr3 = read_cyrix_reg(CCR3);
1538                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1539                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1540                                 write_cyrix_reg(CCR3, ccr3);
1541
1542                                 do_cpuid(0, regs);
1543                                 cpu_high = regs[0];     /* eax */
1544                                 do_cpuid(1, regs);
1545                                 cpu_id = regs[0];       /* eax */
1546                                 cpu_feature = regs[3];  /* edx */
1547                                 break;
1548                         }
1549                 }
1550         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1551                 /*
1552                  * There are BlueLightning CPUs that do not change
1553                  * undefined flags by dividing 5 by 2.  In this case,
1554                  * the CPU identification routine in locore.s leaves
1555                  * cpu_vendor null string and puts CPU_486 into the
1556                  * cpu.
1557                  */
1558                 if (identblue() == IDENTBLUE_IBMCPU) {
1559                         strcpy(cpu_vendor, "IBM");
1560                         cpu_vendor_id = CPU_VENDOR_IBM;
1561                         cpu = CPU_BLUE;
1562                         return;
1563                 }
1564         }
1565 #endif
1566 }
1567
1568 static u_int
1569 find_cpu_vendor_id(void)
1570 {
1571         int     i;
1572
1573         for (i = 0; i < nitems(cpu_vendors); i++)
1574                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1575                         return (cpu_vendors[i].vendor_id);
1576         return (0);
1577 }
1578
1579 static void
1580 print_AMD_assoc(int i)
1581 {
1582         if (i == 255)
1583                 printf(", fully associative\n");
1584         else
1585                 printf(", %d-way associative\n", i);
1586 }
1587
1588 static void
1589 print_AMD_l2_assoc(int i)
1590 {
1591         switch (i & 0x0f) {
1592         case 0: printf(", disabled/not present\n"); break;
1593         case 1: printf(", direct mapped\n"); break;
1594         case 2: printf(", 2-way associative\n"); break;
1595         case 4: printf(", 4-way associative\n"); break;
1596         case 6: printf(", 8-way associative\n"); break;
1597         case 8: printf(", 16-way associative\n"); break;
1598         case 15: printf(", fully associative\n"); break;
1599         default: printf(", reserved configuration\n"); break;
1600         }
1601 }
1602
1603 static void
1604 print_AMD_info(void)
1605 {
1606 #ifdef __i386__
1607         uint64_t amd_whcr;
1608 #endif
1609         u_int regs[4];
1610
1611         if (cpu_exthigh >= 0x80000005) {
1612                 do_cpuid(0x80000005, regs);
1613                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1614                 print_AMD_assoc(regs[0] >> 24);
1615
1616                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1617                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1618
1619                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1620                 print_AMD_assoc(regs[1] >> 24);
1621
1622                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1623                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1624
1625                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1626                 printf(", %d bytes/line", regs[2] & 0xff);
1627                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1628                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1629
1630                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1631                 printf(", %d bytes/line", regs[3] & 0xff);
1632                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1633                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1634         }
1635
1636         if (cpu_exthigh >= 0x80000006) {
1637                 do_cpuid(0x80000006, regs);
1638                 if ((regs[0] >> 16) != 0) {
1639                         printf("L2 2MB data TLB: %d entries",
1640                             (regs[0] >> 16) & 0xfff);
1641                         print_AMD_l2_assoc(regs[0] >> 28);
1642                         printf("L2 2MB instruction TLB: %d entries",
1643                             regs[0] & 0xfff);
1644                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1645                 } else {
1646                         printf("L2 2MB unified TLB: %d entries",
1647                             regs[0] & 0xfff);
1648                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1649                 }
1650                 if ((regs[1] >> 16) != 0) {
1651                         printf("L2 4KB data TLB: %d entries",
1652                             (regs[1] >> 16) & 0xfff);
1653                         print_AMD_l2_assoc(regs[1] >> 28);
1654
1655                         printf("L2 4KB instruction TLB: %d entries",
1656                             (regs[1] >> 16) & 0xfff);
1657                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1658                 } else {
1659                         printf("L2 4KB unified TLB: %d entries",
1660                             (regs[1] >> 16) & 0xfff);
1661                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1662                 }
1663                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1664                 printf(", %d bytes/line", regs[2] & 0xff);
1665                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1666                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1667         }
1668
1669 #ifdef __i386__
1670         if (((cpu_id & 0xf00) == 0x500)
1671             && (((cpu_id & 0x0f0) > 0x80)
1672                 || (((cpu_id & 0x0f0) == 0x80)
1673                     && (cpu_id & 0x00f) > 0x07))) {
1674                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1675                 amd_whcr = rdmsr(0xc0000082);
1676                 if (!(amd_whcr & (0x3ff << 22))) {
1677                         printf("Write Allocate Disable\n");
1678                 } else {
1679                         printf("Write Allocate Enable Limit: %dM bytes\n",
1680                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1681                         printf("Write Allocate 15-16M bytes: %s\n",
1682                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1683                 }
1684         } else if (((cpu_id & 0xf00) == 0x500)
1685                    && ((cpu_id & 0x0f0) > 0x50)) {
1686                 /* K6, K6-2(old core) */
1687                 amd_whcr = rdmsr(0xc0000082);
1688                 if (!(amd_whcr & (0x7f << 1))) {
1689                         printf("Write Allocate Disable\n");
1690                 } else {
1691                         printf("Write Allocate Enable Limit: %dM bytes\n",
1692                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1693                         printf("Write Allocate 15-16M bytes: %s\n",
1694                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1695                         printf("Hardware Write Allocate Control: %s\n",
1696                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1697                 }
1698         }
1699 #endif
1700         /*
1701          * Opteron Rev E shows a bug as in very rare occasions a read memory
1702          * barrier is not performed as expected if it is followed by a
1703          * non-atomic read-modify-write instruction.
1704          * As long as that bug pops up very rarely (intensive machine usage
1705          * on other operating systems generally generates one unexplainable
1706          * crash any 2 months) and as long as a model specific fix would be
1707          * impractical at this stage, print out a warning string if the broken
1708          * model and family are identified.
1709          */
1710         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1711             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1712                 printf("WARNING: This architecture revision has known SMP "
1713                     "hardware bugs which may cause random instability\n");
1714 }
1715
1716 static void
1717 print_INTEL_info(void)
1718 {
1719         u_int regs[4];
1720         u_int rounds, regnum;
1721         u_int nwaycode, nway;
1722
1723         if (cpu_high >= 2) {
1724                 rounds = 0;
1725                 do {
1726                         do_cpuid(0x2, regs);
1727                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1728                                 break;  /* we have a buggy CPU */
1729
1730                         for (regnum = 0; regnum <= 3; ++regnum) {
1731                                 if (regs[regnum] & (1<<31))
1732                                         continue;
1733                                 if (regnum != 0)
1734                                         print_INTEL_TLB(regs[regnum] & 0xff);
1735                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1736                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1737                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1738                         }
1739                 } while (--rounds > 0);
1740         }
1741
1742         if (cpu_exthigh >= 0x80000006) {
1743                 do_cpuid(0x80000006, regs);
1744                 nwaycode = (regs[2] >> 12) & 0x0f;
1745                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1746                         nway = 1 << (nwaycode / 2);
1747                 else
1748                         nway = 0;
1749                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1750                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1751         }
1752 }
1753
1754 static void
1755 print_INTEL_TLB(u_int data)
1756 {
1757         switch (data) {
1758         case 0x0:
1759         case 0x40:
1760         default:
1761                 break;
1762         case 0x1:
1763                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1764                 break;
1765         case 0x2:
1766                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1767                 break;
1768         case 0x3:
1769                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1770                 break;
1771         case 0x4:
1772                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1773                 break;
1774         case 0x6:
1775                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1776                 break;
1777         case 0x8:
1778                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1779                 break;
1780         case 0x9:
1781                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1782                 break;
1783         case 0xa:
1784                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1785                 break;
1786         case 0xb:
1787                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1788                 break;
1789         case 0xc:
1790                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1791                 break;
1792         case 0xd:
1793                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1794                 break;
1795         case 0xe:
1796                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1797                 break;
1798         case 0x1d:
1799                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1800                 break;
1801         case 0x21:
1802                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1803                 break;
1804         case 0x22:
1805                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1806                 break;
1807         case 0x23:
1808                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1809                 break;
1810         case 0x24:
1811                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1812                 break;
1813         case 0x25:
1814                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1815                 break;
1816         case 0x29:
1817                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1818                 break;
1819         case 0x2c:
1820                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1821                 break;
1822         case 0x30:
1823                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1824                 break;
1825         case 0x39: /* De-listed in SDM rev. 54 */
1826                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1827                 break;
1828         case 0x3b: /* De-listed in SDM rev. 54 */
1829                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1830                 break;
1831         case 0x3c: /* De-listed in SDM rev. 54 */
1832                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1833                 break;
1834         case 0x41:
1835                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1836                 break;
1837         case 0x42:
1838                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1839                 break;
1840         case 0x43:
1841                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1842                 break;
1843         case 0x44:
1844                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1845                 break;
1846         case 0x45:
1847                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1848                 break;
1849         case 0x46:
1850                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1851                 break;
1852         case 0x47:
1853                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1854                 break;
1855         case 0x48:
1856                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1857                 break;
1858         case 0x49:
1859                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1860                     CPUID_TO_MODEL(cpu_id) == 0x6)
1861                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1862                 else
1863                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1864                 break;
1865         case 0x4a:
1866                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1867                 break;
1868         case 0x4b:
1869                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1870                 break;
1871         case 0x4c:
1872                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1873                 break;
1874         case 0x4d:
1875                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1876                 break;
1877         case 0x4e:
1878                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1879                 break;
1880         case 0x4f:
1881                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1882                 break;
1883         case 0x50:
1884                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1885                 break;
1886         case 0x51:
1887                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1888                 break;
1889         case 0x52:
1890                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1891                 break;
1892         case 0x55:
1893                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1894                 break;
1895         case 0x56:
1896                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1897                 break;
1898         case 0x57:
1899                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1900                 break;
1901         case 0x59:
1902                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1903                 break;
1904         case 0x5a:
1905                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1906                 break;
1907         case 0x5b:
1908                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1909                 break;
1910         case 0x5c:
1911                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1912                 break;
1913         case 0x5d:
1914                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1915                 break;
1916         case 0x60:
1917                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1918                 break;
1919         case 0x61:
1920                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1921                 break;
1922         case 0x63:
1923                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1924                 break;
1925         case 0x64:
1926                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1927                 break;
1928         case 0x66:
1929                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1930                 break;
1931         case 0x67:
1932                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1933                 break;
1934         case 0x68:
1935                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1936                 break;
1937         case 0x6a:
1938                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1939                 break;
1940         case 0x6b:
1941                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1942                 break;
1943         case 0x6c:
1944                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1945                 break;
1946         case 0x6d:
1947                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1948                 break;
1949         case 0x70:
1950                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1951                 break;
1952         case 0x71:
1953                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1954                 break;
1955         case 0x72:
1956                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1957                 break;
1958         case 0x76:
1959                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1960                 break;
1961         case 0x78:
1962                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1963                 break;
1964         case 0x79:
1965                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1966                 break;
1967         case 0x7a:
1968                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1969                 break;
1970         case 0x7b:
1971                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1972                 break;
1973         case 0x7c:
1974                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1975                 break;
1976         case 0x7d:
1977                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1978                 break;
1979         case 0x7f:
1980                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1981                 break;
1982         case 0x80:
1983                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1984                 break;
1985         case 0x82:
1986                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1987                 break;
1988         case 0x83:
1989                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1990                 break;
1991         case 0x84:
1992                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1993                 break;
1994         case 0x85:
1995                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1996                 break;
1997         case 0x86:
1998                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1999                 break;
2000         case 0x87:
2001                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2002                 break;
2003         case 0xa0:
2004                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2005                 break;
2006         case 0xb0:
2007                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2008                 break;
2009         case 0xb1:
2010                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2011                 break;
2012         case 0xb2:
2013                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2014                 break;
2015         case 0xb3:
2016                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2017                 break;
2018         case 0xb4:
2019                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2020                 break;
2021         case 0xb5:
2022                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2023                 break;
2024         case 0xb6:
2025                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2026                 break;
2027         case 0xba:
2028                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2029                 break;
2030         case 0xc0:
2031                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2032                 break;
2033         case 0xc1:
2034                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2035                 break;
2036         case 0xc2:
2037                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2038                 break;
2039         case 0xc3:
2040                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2041                 break;
2042         case 0xc4:
2043                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2044                 break;
2045         case 0xca:
2046                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2047                 break;
2048         case 0xd0:
2049                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2050                 break;
2051         case 0xd1:
2052                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2053                 break;
2054         case 0xd2:
2055                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2056                 break;
2057         case 0xd6:
2058                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2059                 break;
2060         case 0xd7:
2061                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2062                 break;
2063         case 0xd8:
2064                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2065                 break;
2066         case 0xdc:
2067                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2068                 break;
2069         case 0xdd:
2070                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2071                 break;
2072         case 0xde:
2073                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2074                 break;
2075         case 0xe2:
2076                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2077                 break;
2078         case 0xe3:
2079                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2080                 break;
2081         case 0xe4:
2082                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2083                 break;
2084         case 0xea:
2085                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2086                 break;
2087         case 0xeb:
2088                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2089                 break;
2090         case 0xec:
2091                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2092                 break;
2093         case 0xf0:
2094                 printf("64-Byte prefetching\n");
2095                 break;
2096         case 0xf1:
2097                 printf("128-Byte prefetching\n");
2098                 break;
2099         }
2100 }
2101
2102 static void
2103 print_svm_info(void)
2104 {
2105         u_int features, regs[4];
2106         uint64_t msr;
2107         int comma;
2108
2109         printf("\n  SVM: ");
2110         do_cpuid(0x8000000A, regs);
2111         features = regs[3];
2112
2113         msr = rdmsr(MSR_VM_CR);
2114         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2115                 printf("(disabled in BIOS) ");
2116
2117         if (!bootverbose) {
2118                 comma = 0;
2119                 if (features & (1 << 0)) {
2120                         printf("%sNP", comma ? "," : "");
2121                         comma = 1;
2122                 }
2123                 if (features & (1 << 3)) {
2124                         printf("%sNRIP", comma ? "," : "");
2125                         comma = 1;
2126                 }
2127                 if (features & (1 << 5)) {
2128                         printf("%sVClean", comma ? "," : "");
2129                         comma = 1;
2130                 }
2131                 if (features & (1 << 6)) {
2132                         printf("%sAFlush", comma ? "," : "");
2133                         comma = 1;
2134                 }
2135                 if (features & (1 << 7)) {
2136                         printf("%sDAssist", comma ? "," : "");
2137                         comma = 1;
2138                 }
2139                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2140                 return;
2141         }
2142
2143         printf("Features=0x%b", features,
2144                "\020"
2145                "\001NP"                 /* Nested paging */
2146                "\002LbrVirt"            /* LBR virtualization */
2147                "\003SVML"               /* SVM lock */
2148                "\004NRIPS"              /* NRIP save */
2149                "\005TscRateMsr"         /* MSR based TSC rate control */
2150                "\006VmcbClean"          /* VMCB clean bits */
2151                "\007FlushByAsid"        /* Flush by ASID */
2152                "\010DecodeAssist"       /* Decode assist */
2153                "\011<b8>"
2154                "\012<b9>"
2155                "\013PauseFilter"        /* PAUSE intercept filter */
2156                "\014<b11>"
2157                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2158                "\016AVIC"               /* virtual interrupt controller */
2159                 );
2160         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2161 }
2162
2163 #ifdef __i386__
2164 static void
2165 print_transmeta_info(void)
2166 {
2167         u_int regs[4], nreg = 0;
2168
2169         do_cpuid(0x80860000, regs);
2170         nreg = regs[0];
2171         if (nreg >= 0x80860001) {
2172                 do_cpuid(0x80860001, regs);
2173                 printf("  Processor revision %u.%u.%u.%u\n",
2174                        (regs[1] >> 24) & 0xff,
2175                        (regs[1] >> 16) & 0xff,
2176                        (regs[1] >> 8) & 0xff,
2177                        regs[1] & 0xff);
2178         }
2179         if (nreg >= 0x80860002) {
2180                 do_cpuid(0x80860002, regs);
2181                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2182                        (regs[1] >> 24) & 0xff,
2183                        (regs[1] >> 16) & 0xff,
2184                        (regs[1] >> 8) & 0xff,
2185                        regs[1] & 0xff,
2186                        regs[2]);
2187         }
2188         if (nreg >= 0x80860006) {
2189                 char info[65];
2190                 do_cpuid(0x80860003, (u_int*) &info[0]);
2191                 do_cpuid(0x80860004, (u_int*) &info[16]);
2192                 do_cpuid(0x80860005, (u_int*) &info[32]);
2193                 do_cpuid(0x80860006, (u_int*) &info[48]);
2194                 info[64] = 0;
2195                 printf("  %s\n", info);
2196         }
2197 }
2198 #endif
2199
2200 static void
2201 print_via_padlock_info(void)
2202 {
2203         u_int regs[4];
2204
2205         do_cpuid(0xc0000001, regs);
2206         printf("\n  VIA Padlock Features=0x%b", regs[3],
2207         "\020"
2208         "\003RNG"               /* RNG */
2209         "\007AES"               /* ACE */
2210         "\011AES-CTR"           /* ACE2 */
2211         "\013SHA1,SHA256"       /* PHE */
2212         "\015RSA"               /* PMM */
2213         );
2214 }
2215
2216 static uint32_t
2217 vmx_settable(uint64_t basic, int msr, int true_msr)
2218 {
2219         uint64_t val;
2220
2221         if (basic & (1ULL << 55))
2222                 val = rdmsr(true_msr);
2223         else
2224                 val = rdmsr(msr);
2225
2226         /* Just report the controls that can be set to 1. */
2227         return (val >> 32);
2228 }
2229
2230 static void
2231 print_vmx_info(void)
2232 {
2233         uint64_t basic, msr;
2234         uint32_t entry, exit, mask, pin, proc, proc2;
2235         int comma;
2236
2237         printf("\n  VT-x: ");
2238         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2239         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2240                 printf("(disabled in BIOS) ");
2241         basic = rdmsr(MSR_VMX_BASIC);
2242         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2243             MSR_VMX_TRUE_PINBASED_CTLS);
2244         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2245             MSR_VMX_TRUE_PROCBASED_CTLS);
2246         if (proc & PROCBASED_SECONDARY_CONTROLS)
2247                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2248                     MSR_VMX_PROCBASED_CTLS2);
2249         else
2250                 proc2 = 0;
2251         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2252         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2253
2254         if (!bootverbose) {
2255                 comma = 0;
2256                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2257                     entry & VM_ENTRY_LOAD_PAT) {
2258                         printf("%sPAT", comma ? "," : "");
2259                         comma = 1;
2260                 }
2261                 if (proc & PROCBASED_HLT_EXITING) {
2262                         printf("%sHLT", comma ? "," : "");
2263                         comma = 1;
2264                 }
2265                 if (proc & PROCBASED_MTF) {
2266                         printf("%sMTF", comma ? "," : "");
2267                         comma = 1;
2268                 }
2269                 if (proc & PROCBASED_PAUSE_EXITING) {
2270                         printf("%sPAUSE", comma ? "," : "");
2271                         comma = 1;
2272                 }
2273                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2274                         printf("%sEPT", comma ? "," : "");
2275                         comma = 1;
2276                 }
2277                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2278                         printf("%sUG", comma ? "," : "");
2279                         comma = 1;
2280                 }
2281                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2282                         printf("%sVPID", comma ? "," : "");
2283                         comma = 1;
2284                 }
2285                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2286                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2287                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2288                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2289                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2290                         printf("%sVID", comma ? "," : "");
2291                         comma = 1;
2292                         if (pin & PINBASED_POSTED_INTERRUPT)
2293                                 printf(",PostIntr");
2294                 }
2295                 return;
2296         }
2297
2298         mask = basic >> 32;
2299         printf("Basic Features=0x%b", mask,
2300         "\020"
2301         "\02132PA"              /* 32-bit physical addresses */
2302         "\022SMM"               /* SMM dual-monitor */
2303         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2304         "\030TRUE"              /* TRUE_CTLS MSRs */
2305         );
2306         printf("\n        Pin-Based Controls=0x%b", pin,
2307         "\020"
2308         "\001ExtINT"            /* External-interrupt exiting */
2309         "\004NMI"               /* NMI exiting */
2310         "\006VNMI"              /* Virtual NMIs */
2311         "\007PreTmr"            /* Activate VMX-preemption timer */
2312         "\010PostIntr"          /* Process posted interrupts */
2313         );
2314         printf("\n        Primary Processor Controls=0x%b", proc,
2315         "\020"
2316         "\003INTWIN"            /* Interrupt-window exiting */
2317         "\004TSCOff"            /* Use TSC offsetting */
2318         "\010HLT"               /* HLT exiting */
2319         "\012INVLPG"            /* INVLPG exiting */
2320         "\013MWAIT"             /* MWAIT exiting */
2321         "\014RDPMC"             /* RDPMC exiting */
2322         "\015RDTSC"             /* RDTSC exiting */
2323         "\020CR3-LD"            /* CR3-load exiting */
2324         "\021CR3-ST"            /* CR3-store exiting */
2325         "\024CR8-LD"            /* CR8-load exiting */
2326         "\025CR8-ST"            /* CR8-store exiting */
2327         "\026TPR"               /* Use TPR shadow */
2328         "\027NMIWIN"            /* NMI-window exiting */
2329         "\030MOV-DR"            /* MOV-DR exiting */
2330         "\031IO"                /* Unconditional I/O exiting */
2331         "\032IOmap"             /* Use I/O bitmaps */
2332         "\034MTF"               /* Monitor trap flag */
2333         "\035MSRmap"            /* Use MSR bitmaps */
2334         "\036MONITOR"           /* MONITOR exiting */
2335         "\037PAUSE"             /* PAUSE exiting */
2336         );
2337         if (proc & PROCBASED_SECONDARY_CONTROLS)
2338                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2339                 "\020"
2340                 "\001APIC"              /* Virtualize APIC accesses */
2341                 "\002EPT"               /* Enable EPT */
2342                 "\003DT"                /* Descriptor-table exiting */
2343                 "\004RDTSCP"            /* Enable RDTSCP */
2344                 "\005x2APIC"            /* Virtualize x2APIC mode */
2345                 "\006VPID"              /* Enable VPID */
2346                 "\007WBINVD"            /* WBINVD exiting */
2347                 "\010UG"                /* Unrestricted guest */
2348                 "\011APIC-reg"          /* APIC-register virtualization */
2349                 "\012VID"               /* Virtual-interrupt delivery */
2350                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2351                 "\014RDRAND"            /* RDRAND exiting */
2352                 "\015INVPCID"           /* Enable INVPCID */
2353                 "\016VMFUNC"            /* Enable VM functions */
2354                 "\017VMCS"              /* VMCS shadowing */
2355                 "\020EPT#VE"            /* EPT-violation #VE */
2356                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2357                 );
2358         printf("\n        Exit Controls=0x%b", mask,
2359         "\020"
2360         "\003DR"                /* Save debug controls */
2361                                 /* Ignore Host address-space size */
2362         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2363         "\020AckInt"            /* Acknowledge interrupt on exit */
2364         "\023PAT-SV"            /* Save MSR_PAT */
2365         "\024PAT-LD"            /* Load MSR_PAT */
2366         "\025EFER-SV"           /* Save MSR_EFER */
2367         "\026EFER-LD"           /* Load MSR_EFER */
2368         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2369         );
2370         printf("\n        Entry Controls=0x%b", mask,
2371         "\020"
2372         "\003DR"                /* Save debug controls */
2373                                 /* Ignore IA-32e mode guest */
2374                                 /* Ignore Entry to SMM */
2375                                 /* Ignore Deactivate dual-monitor treatment */
2376         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2377         "\017PAT"               /* Load MSR_PAT */
2378         "\020EFER"              /* Load MSR_EFER */
2379         );
2380         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2381             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2382                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2383                 mask = msr;
2384                 printf("\n        EPT Features=0x%b", mask,
2385                 "\020"
2386                 "\001XO"                /* Execute-only translations */
2387                 "\007PW4"               /* Page-walk length of 4 */
2388                 "\011UC"                /* EPT paging-structure mem can be UC */
2389                 "\017WB"                /* EPT paging-structure mem can be WB */
2390                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2391                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2392                 "\025INVEPT"            /* INVEPT is supported */
2393                 "\026AD"                /* Accessed and dirty flags for EPT */
2394                 "\032single"            /* INVEPT single-context type */
2395                 "\033all"               /* INVEPT all-context type */
2396                 );
2397                 mask = msr >> 32;
2398                 printf("\n        VPID Features=0x%b", mask,
2399                 "\020"
2400                 "\001INVVPID"           /* INVVPID is supported */
2401                 "\011individual"        /* INVVPID individual-address type */
2402                 "\012single"            /* INVVPID single-context type */
2403                 "\013all"               /* INVVPID all-context type */
2404                  /* INVVPID single-context-retaining-globals type */
2405                 "\014single-globals"
2406                 );
2407         }
2408 }
2409
2410 static void
2411 print_hypervisor_info(void)
2412 {
2413
2414         if (*hv_vendor)
2415                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2416 }