2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
56 #include <machine/asmacros.h>
57 #include <machine/clock.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/md_var.h>
62 #include <machine/segments.h>
63 #include <machine/specialreg.h>
65 #include <amd64/vmm/intel/vmx_controls.h>
66 #include <x86/isa/icu.h>
67 #include <x86/vmware.h>
70 #define IDENTBLUE_CYRIX486 0
71 #define IDENTBLUE_IBMCPU 1
72 #define IDENTBLUE_CYRIXM2 2
74 static void identifycyrix(void);
75 static void print_transmeta_info(void);
77 static u_int find_cpu_vendor_id(void);
78 static void print_AMD_info(void);
79 static void print_INTEL_info(void);
80 static void print_INTEL_TLB(u_int data);
81 static void print_hypervisor_info(void);
82 static void print_svm_info(void);
83 static void print_via_padlock_info(void);
84 static void print_vmx_info(void);
87 int cpu; /* Are we 386, 386sx, 486, etc? */
90 u_int cpu_feature; /* Feature flags */
91 u_int cpu_feature2; /* Feature flags */
92 u_int amd_feature; /* AMD feature flags */
93 u_int amd_feature2; /* AMD feature flags */
94 u_int amd_rascap; /* AMD RAS capabilities */
95 u_int amd_pminfo; /* AMD advanced power management info */
96 u_int amd_extended_feature_extensions;
97 u_int via_feature_rng; /* VIA RNG features */
98 u_int via_feature_xcrypt; /* VIA ACE features */
99 u_int cpu_high; /* Highest arg to CPUID */
100 u_int cpu_exthigh; /* Highest arg to extended CPUID */
101 u_int cpu_id; /* Stepping ID */
102 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
103 u_int cpu_procinfo2; /* Multicore info */
104 char cpu_vendor[20]; /* CPU Origin code */
105 u_int cpu_vendor_id; /* CPU vendor ID */
106 u_int cpu_fxsr; /* SSE enabled */
107 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
108 u_int cpu_clflush_line_size = 32;
109 u_int cpu_stdext_feature; /* %ebx */
110 u_int cpu_stdext_feature2; /* %ecx */
111 u_int cpu_stdext_feature3; /* %edx */
112 uint64_t cpu_ia32_arch_caps;
113 u_int cpu_max_ext_state_size;
114 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
115 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
116 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
117 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
118 char machine[] = MACHINE;
120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
122 "VIA RNG feature available in CPU");
123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
124 &via_feature_xcrypt, 0,
125 "VIA xcrypt feature available in CPU");
129 extern int adaptive_machine_arch;
133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
136 static const char machine32[] = "i386";
141 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
142 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
145 error = SYSCTL_OUT(req, machine, sizeof(machine));
149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
150 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
153 machine, 0, "Machine class");
156 static char cpu_model[128];
157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
158 cpu_model, 0, "Machine model");
160 static int hw_clockrate;
161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
162 &hw_clockrate, 0, "CPU instruction clock rate");
166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
167 0, "Hypervisor vendor");
169 static eventhandler_tag tsc_post_tag;
171 static char cpu_brand[48];
174 #define MAX_BRAND_INDEX 8
176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
180 "Intel Pentium III Xeon",
192 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
193 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
194 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
195 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
196 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
197 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
198 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
199 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
200 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
201 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
202 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
203 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
204 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
205 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
206 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
207 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
208 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
216 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
217 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
218 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
220 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
221 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
222 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
223 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
224 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
225 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
226 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
228 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
229 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
242 cpu_class = cpus[cpu].cpu_class;
243 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
245 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
248 /* Check for extended CPUID information and a processor name. */
249 if (cpu_exthigh >= 0x80000004) {
251 for (i = 0x80000002; i < 0x80000005; i++) {
253 memcpy(brand, regs, sizeof(regs));
254 brand += sizeof(regs);
258 switch (cpu_vendor_id) {
259 case CPU_VENDOR_INTEL:
261 if ((cpu_id & 0xf00) > 0x300) {
266 switch (cpu_id & 0x3000) {
268 strcpy(cpu_model, "Overdrive ");
271 strcpy(cpu_model, "Dual ");
275 switch (cpu_id & 0xf00) {
277 strcat(cpu_model, "i486 ");
278 /* Check the particular flavor of 486 */
279 switch (cpu_id & 0xf0) {
282 strcat(cpu_model, "DX");
285 strcat(cpu_model, "SX");
288 strcat(cpu_model, "DX2");
291 strcat(cpu_model, "SL");
294 strcat(cpu_model, "SX2");
298 "DX2 Write-Back Enhanced");
301 strcat(cpu_model, "DX4");
306 /* Check the particular flavor of 586 */
307 strcat(cpu_model, "Pentium");
308 switch (cpu_id & 0xf0) {
310 strcat(cpu_model, " A-step");
313 strcat(cpu_model, "/P5");
316 strcat(cpu_model, "/P54C");
319 strcat(cpu_model, "/P24T");
322 strcat(cpu_model, "/P55C");
325 strcat(cpu_model, "/P54C");
328 strcat(cpu_model, "/P55C (quarter-micron)");
334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
336 * XXX - If/when Intel fixes the bug, this
337 * should also check the version of the
338 * CPU, not just that it's a Pentium.
344 /* Check the particular flavor of 686 */
345 switch (cpu_id & 0xf0) {
347 strcat(cpu_model, "Pentium Pro A-step");
350 strcat(cpu_model, "Pentium Pro");
356 "Pentium II/Pentium II Xeon/Celeron");
364 "Pentium III/Pentium III Xeon/Celeron");
368 strcat(cpu_model, "Unknown 80686");
373 strcat(cpu_model, "Pentium 4");
377 strcat(cpu_model, "unknown");
382 * If we didn't get a brand name from the extended
383 * CPUID, try to look it up in the brand table.
385 if (cpu_high > 0 && *cpu_brand == '\0') {
386 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
387 if (brand_index <= MAX_BRAND_INDEX &&
388 cpu_brandtable[brand_index] != NULL)
390 cpu_brandtable[brand_index]);
394 /* Please make up your mind folks! */
395 strcat(cpu_model, "EM64T");
400 * Values taken from AMD Processor Recognition
401 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
402 * (also describes ``Features'' encodings.
404 strcpy(cpu_model, "AMD ");
406 switch (cpu_id & 0xFF0) {
408 strcat(cpu_model, "Standard Am486DX");
411 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
414 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
417 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
420 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
423 strcat(cpu_model, "Am5x86 Write-Through");
426 strcat(cpu_model, "Am5x86 Write-Back");
429 strcat(cpu_model, "K5 model 0");
432 strcat(cpu_model, "K5 model 1");
435 strcat(cpu_model, "K5 PR166 (model 2)");
438 strcat(cpu_model, "K5 PR200 (model 3)");
441 strcat(cpu_model, "K6");
444 strcat(cpu_model, "K6 266 (model 1)");
447 strcat(cpu_model, "K6-2");
450 strcat(cpu_model, "K6-III");
453 strcat(cpu_model, "Geode LX");
456 strcat(cpu_model, "Unknown");
460 if ((cpu_id & 0xf00) == 0xf00)
461 strcat(cpu_model, "AMD64 Processor");
463 strcat(cpu_model, "Unknown");
467 case CPU_VENDOR_CYRIX:
468 strcpy(cpu_model, "Cyrix ");
469 switch (cpu_id & 0xff0) {
471 strcat(cpu_model, "MediaGX");
474 strcat(cpu_model, "6x86");
477 cpu_class = CPUCLASS_586;
478 strcat(cpu_model, "GXm");
481 strcat(cpu_model, "6x86MX");
485 * Even though CPU supports the cpuid
486 * instruction, it can be disabled.
487 * Therefore, this routine supports all Cyrix
490 switch (cyrix_did & 0xf0) {
492 switch (cyrix_did & 0x0f) {
494 strcat(cpu_model, "486SLC");
497 strcat(cpu_model, "486DLC");
500 strcat(cpu_model, "486SLC2");
503 strcat(cpu_model, "486DLC2");
506 strcat(cpu_model, "486SRx");
509 strcat(cpu_model, "486DRx");
512 strcat(cpu_model, "486SRx2");
515 strcat(cpu_model, "486DRx2");
518 strcat(cpu_model, "486SRu");
521 strcat(cpu_model, "486DRu");
524 strcat(cpu_model, "486SRu2");
527 strcat(cpu_model, "486DRu2");
530 strcat(cpu_model, "Unknown");
535 switch (cyrix_did & 0x0f) {
537 strcat(cpu_model, "486S");
540 strcat(cpu_model, "486S2");
543 strcat(cpu_model, "486Se");
546 strcat(cpu_model, "486S2e");
549 strcat(cpu_model, "486DX");
552 strcat(cpu_model, "486DX2");
555 strcat(cpu_model, "486DX4");
558 strcat(cpu_model, "Unknown");
563 if ((cyrix_did & 0x0f) < 8)
564 strcat(cpu_model, "6x86"); /* Where did you get it? */
566 strcat(cpu_model, "5x86");
569 strcat(cpu_model, "6x86");
572 if ((cyrix_did & 0xf000) == 0x3000) {
573 cpu_class = CPUCLASS_586;
574 strcat(cpu_model, "GXm");
576 strcat(cpu_model, "MediaGX");
579 strcat(cpu_model, "6x86MX");
582 switch (cyrix_did & 0x0f) {
584 strcat(cpu_model, "Overdrive CPU");
587 strcpy(cpu_model, "Texas Instruments 486SXL");
590 strcat(cpu_model, "486SLC/DLC");
593 strcat(cpu_model, "Unknown");
598 strcat(cpu_model, "Unknown");
604 case CPU_VENDOR_RISE:
605 strcpy(cpu_model, "Rise ");
606 switch (cpu_id & 0xff0) {
607 case 0x500: /* 6401 and 6441 (Kirin) */
608 case 0x520: /* 6510 (Lynx) */
609 strcat(cpu_model, "mP6");
612 strcat(cpu_model, "Unknown");
616 case CPU_VENDOR_CENTAUR:
618 switch (cpu_id & 0xff0) {
620 strcpy(cpu_model, "IDT WinChip C6");
623 strcpy(cpu_model, "IDT WinChip 2");
626 strcpy(cpu_model, "IDT WinChip 3");
629 strcpy(cpu_model, "VIA C3 Samuel");
633 strcpy(cpu_model, "VIA C3 Ezra");
635 strcpy(cpu_model, "VIA C3 Samuel 2");
638 strcpy(cpu_model, "VIA C3 Ezra-T");
641 strcpy(cpu_model, "VIA C3 Nehemiah");
645 strcpy(cpu_model, "VIA C7 Esther");
648 strcpy(cpu_model, "VIA Nano");
651 strcpy(cpu_model, "VIA/IDT Unknown");
654 strcpy(cpu_model, "VIA ");
655 if ((cpu_id & 0xff0) == 0x6f0)
656 strcat(cpu_model, "Nano Processor");
658 strcat(cpu_model, "Unknown");
663 strcpy(cpu_model, "Blue Lightning CPU");
666 switch (cpu_id & 0xff0) {
668 strcpy(cpu_model, "Geode SC1100");
672 strcpy(cpu_model, "Geode/NSC unknown");
678 strcat(cpu_model, "Unknown");
683 * Replace cpu_model with cpu_brand minus leading spaces if
687 while (*brand == ' ')
690 strcpy(cpu_model, brand);
692 printf("%s (", cpu_model);
694 hw_clockrate = (tsc_freq + 5000) / 1000000;
695 printf("%jd.%02d-MHz ",
696 (intmax_t)(tsc_freq + 4999) / 1000000,
697 (u_int)((tsc_freq + 4999) / 10000) % 100);
707 #if defined(I486_CPU)
712 #if defined(I586_CPU)
717 #if defined(I686_CPU)
723 printf("Unknown"); /* will panic below... */
728 printf("-class CPU)\n");
730 printf(" Origin=\"%s\"", cpu_vendor);
732 printf(" Id=0x%x", cpu_id);
734 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
735 cpu_vendor_id == CPU_VENDOR_AMD ||
736 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
738 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
739 cpu_vendor_id == CPU_VENDOR_RISE ||
740 cpu_vendor_id == CPU_VENDOR_NSC ||
741 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
744 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
745 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
746 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
748 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
749 printf("\n DIR=0x%04x", cyrix_did);
753 * AMD CPUID Specification
754 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
756 * Intel Processor Identification and CPUID Instruction
757 * http://www.intel.com/assets/pdf/appnote/241618.pdf
762 * Here we should probably set up flags indicating
763 * whether or not various features are available.
764 * The interesting ones are probably VME, PSE, PAE,
765 * and PGE. The code already assumes without bothering
766 * to check that all CPUs >= Pentium have a TSC and
769 printf("\n Features=0x%b", cpu_feature,
771 "\001FPU" /* Integral FPU */
772 "\002VME" /* Extended VM86 mode support */
773 "\003DE" /* Debugging Extensions (CR4.DE) */
774 "\004PSE" /* 4MByte page tables */
775 "\005TSC" /* Timestamp counter */
776 "\006MSR" /* Machine specific registers */
777 "\007PAE" /* Physical address extension */
778 "\010MCE" /* Machine Check support */
779 "\011CX8" /* CMPEXCH8 instruction */
780 "\012APIC" /* SMP local APIC */
781 "\013oldMTRR" /* Previous implementation of MTRR */
782 "\014SEP" /* Fast System Call */
783 "\015MTRR" /* Memory Type Range Registers */
784 "\016PGE" /* PG_G (global bit) support */
785 "\017MCA" /* Machine Check Architecture */
786 "\020CMOV" /* CMOV instruction */
787 "\021PAT" /* Page attributes table */
788 "\022PSE36" /* 36 bit address space support */
789 "\023PN" /* Processor Serial number */
790 "\024CLFLUSH" /* Has the CLFLUSH instruction */
792 "\026DTS" /* Debug Trace Store */
793 "\027ACPI" /* ACPI support */
794 "\030MMX" /* MMX instructions */
795 "\031FXSR" /* FXSAVE/FXRSTOR */
796 "\032SSE" /* Streaming SIMD Extensions */
797 "\033SSE2" /* Streaming SIMD Extensions #2 */
798 "\034SS" /* Self snoop */
799 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
800 "\036TM" /* Thermal Monitor clock slowdown */
801 "\037IA64" /* CPU can execute IA64 instructions */
802 "\040PBE" /* Pending Break Enable */
805 if (cpu_feature2 != 0) {
806 printf("\n Features2=0x%b", cpu_feature2,
808 "\001SSE3" /* SSE3 */
809 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
810 "\003DTES64" /* 64-bit Debug Trace */
811 "\004MON" /* MONITOR/MWAIT Instructions */
812 "\005DS_CPL" /* CPL Qualified Debug Store */
813 "\006VMX" /* Virtual Machine Extensions */
814 "\007SMX" /* Safer Mode Extensions */
815 "\010EST" /* Enhanced SpeedStep */
816 "\011TM2" /* Thermal Monitor 2 */
817 "\012SSSE3" /* SSSE3 */
818 "\013CNXT-ID" /* L1 context ID available */
819 "\014SDBG" /* IA32 silicon debug */
820 "\015FMA" /* Fused Multiply Add */
821 "\016CX16" /* CMPXCHG16B Instruction */
822 "\017xTPR" /* Send Task Priority Messages*/
823 "\020PDCM" /* Perf/Debug Capability MSR */
825 "\022PCID" /* Process-context Identifiers*/
826 "\023DCA" /* Direct Cache Access */
827 "\024SSE4.1" /* SSE 4.1 */
828 "\025SSE4.2" /* SSE 4.2 */
829 "\026x2APIC" /* xAPIC Extensions */
830 "\027MOVBE" /* MOVBE Instruction */
831 "\030POPCNT" /* POPCNT Instruction */
832 "\031TSCDLT" /* TSC-Deadline Timer */
833 "\032AESNI" /* AES Crypto */
834 "\033XSAVE" /* XSAVE/XRSTOR States */
835 "\034OSXSAVE" /* OS-Enabled State Management*/
836 "\035AVX" /* Advanced Vector Extensions */
837 "\036F16C" /* Half-precision conversions */
838 "\037RDRAND" /* RDRAND Instruction */
839 "\040HV" /* Hypervisor */
843 if (amd_feature != 0) {
844 printf("\n AMD Features=0x%b", amd_feature,
846 "\001<s0>" /* Same */
847 "\002<s1>" /* Same */
848 "\003<s2>" /* Same */
849 "\004<s3>" /* Same */
850 "\005<s4>" /* Same */
851 "\006<s5>" /* Same */
852 "\007<s6>" /* Same */
853 "\010<s7>" /* Same */
854 "\011<s8>" /* Same */
855 "\012<s9>" /* Same */
856 "\013<b10>" /* Undefined */
857 "\014SYSCALL" /* Have SYSCALL/SYSRET */
858 "\015<s12>" /* Same */
859 "\016<s13>" /* Same */
860 "\017<s14>" /* Same */
861 "\020<s15>" /* Same */
862 "\021<s16>" /* Same */
863 "\022<s17>" /* Same */
864 "\023<b18>" /* Reserved, unknown */
865 "\024MP" /* Multiprocessor Capable */
866 "\025NX" /* Has EFER.NXE, NX */
867 "\026<b21>" /* Undefined */
868 "\027MMX+" /* AMD MMX Extensions */
869 "\030<s23>" /* Same */
870 "\031<s24>" /* Same */
871 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
872 "\033Page1GB" /* 1-GB large page support */
873 "\034RDTSCP" /* RDTSCP */
874 "\035<b28>" /* Undefined */
875 "\036LM" /* 64 bit long mode */
876 "\0373DNow!+" /* AMD 3DNow! Extensions */
877 "\0403DNow!" /* AMD 3DNow! */
881 if (amd_feature2 != 0) {
882 printf("\n AMD Features2=0x%b", amd_feature2,
884 "\001LAHF" /* LAHF/SAHF in long mode */
885 "\002CMP" /* CMP legacy */
886 "\003SVM" /* Secure Virtual Mode */
887 "\004ExtAPIC" /* Extended APIC register */
888 "\005CR8" /* CR8 in legacy mode */
889 "\006ABM" /* LZCNT instruction */
890 "\007SSE4A" /* SSE4A */
891 "\010MAS" /* Misaligned SSE mode */
892 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
893 "\012OSVW" /* OS visible workaround */
894 "\013IBS" /* Instruction based sampling */
895 "\014XOP" /* XOP extended instructions */
896 "\015SKINIT" /* SKINIT/STGI */
897 "\016WDT" /* Watchdog timer */
899 "\020LWP" /* Lightweight Profiling */
900 "\021FMA4" /* 4-operand FMA instructions */
901 "\022TCE" /* Translation Cache Extension */
903 "\024NodeId" /* NodeId MSR support */
905 "\026TBM" /* Trailing Bit Manipulation */
906 "\027Topology" /* Topology Extensions */
907 "\030PCXC" /* Core perf count */
908 "\031PNXC" /* NB perf count */
910 "\033DBE" /* Data Breakpoint extension */
911 "\034PTSC" /* Performance TSC */
912 "\035PL2I" /* L2I perf count */
913 "\036MWAITX" /* MONITORX/MWAITX instructions */
919 if (cpu_stdext_feature != 0) {
920 printf("\n Structured Extended Features=0x%b",
923 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
927 /* Bit Manipulation Instructions */
929 /* Hardware Lock Elision */
931 /* Advanced Vector Instructions 2 */
933 /* FDP_EXCPTN_ONLY */
935 /* Supervisor Mode Execution Prot. */
937 /* Bit Manipulation Instructions */
940 /* Invalidate Processor Context ID */
942 /* Restricted Transactional Memory */
946 /* Intel Memory Protection Extensions */
949 /* AVX512 Foundation */
956 /* Supervisor Mode Access Prevention */
972 if (cpu_stdext_feature2 != 0) {
973 printf("\n Structured Extended Features2=0x%b",
986 if (cpu_stdext_feature3 != 0) {
987 printf("\n Structured Extended Features3=0x%b",
996 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
997 cpuid_count(0xd, 0x1, regs);
999 printf("\n XSAVE Features=0x%b",
1009 if (cpu_ia32_arch_caps != 0) {
1010 printf("\n IA32_ARCH_CAPS=0x%b",
1011 (u_int)cpu_ia32_arch_caps,
1018 if (amd_extended_feature_extensions != 0) {
1020 "AMD Extended Feature Extensions ID EBX="
1021 "0x%b", amd_extended_feature_extensions,
1028 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1029 print_via_padlock_info();
1031 if (cpu_feature2 & CPUID2_VMX)
1034 if (amd_feature2 & AMDID2_SVM)
1037 if ((cpu_feature & CPUID_HTT) &&
1038 cpu_vendor_id == CPU_VENDOR_AMD)
1039 cpu_feature &= ~CPUID_HTT;
1042 * If this CPU supports P-state invariant TSC then
1043 * mention the capability.
1045 if (tsc_is_invariant) {
1046 printf("\n TSC: P-state invariant");
1048 printf(", performance statistics");
1052 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1053 printf(" DIR=0x%04x", cyrix_did);
1054 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1055 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1056 #ifndef CYRIX_CACHE_REALLY_WORKS
1057 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1058 printf("\n CPU cache: write-through mode");
1063 /* Avoid ugly blank lines: only print newline when we have to. */
1064 if (*cpu_vendor || cpu_id)
1068 if (cpu_vendor_id == CPU_VENDOR_AMD)
1070 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1073 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1074 print_transmeta_info();
1078 print_hypervisor_info();
1083 panicifcpuunsupported(void)
1087 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1088 #error This kernel is not configured for one of the supported CPUs
1093 * Now that we have told the user what they have,
1094 * let them know if that machine type isn't configured.
1096 switch (cpu_class) {
1097 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1099 #if !defined(I486_CPU)
1102 #if !defined(I586_CPU)
1105 #if !defined(I686_CPU)
1108 panic("CPU class not configured");
1114 static volatile u_int trap_by_rdmsr;
1117 * Special exception 6 handler.
1118 * The rdmsr instruction generates invalid opcodes fault on 486-class
1119 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1120 * function identblue() when this handler is called. Stacked eip should
1123 inthand_t bluetrap6;
1124 #ifdef __GNUCLIKE_ASM
1129 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1130 " __XSTRING(CNAME(bluetrap6)) ": \n\
1132 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1133 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1139 * Special exception 13 handler.
1140 * Accessing non-existent MSR generates general protection fault.
1142 inthand_t bluetrap13;
1143 #ifdef __GNUCLIKE_ASM
1148 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1149 " __XSTRING(CNAME(bluetrap13)) ": \n\
1151 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1152 popl %eax /* discard error code */ \n\
1153 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1159 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1160 * support cpuid instruction. This function should be called after
1161 * loading interrupt descriptor table register.
1163 * I don't like this method that handles fault, but I couldn't get
1164 * information for any other methods. Does blue giant know?
1173 * Cyrix 486-class CPU does not support rdmsr instruction.
1174 * The rdmsr instruction generates invalid opcode fault, and exception
1175 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1176 * bluetrap6() set the magic number to trap_by_rdmsr.
1178 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1179 GSEL(GCODE_SEL, SEL_KPL));
1182 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1183 * In this case, rdmsr generates general protection fault, and
1184 * exception will be trapped by bluetrap13().
1186 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1187 GSEL(GCODE_SEL, SEL_KPL));
1189 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1191 if (trap_by_rdmsr == 0xa8c1d)
1192 return IDENTBLUE_CYRIX486;
1193 else if (trap_by_rdmsr == 0xa89c4)
1194 return IDENTBLUE_CYRIXM2;
1195 return IDENTBLUE_IBMCPU;
1200 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1202 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1203 * +-------+-------+---------------+
1204 * | SID | RID | Device ID |
1205 * | (DIR 1) | (DIR 0) |
1206 * +-------+-------+---------------+
1211 register_t saveintr;
1212 int ccr2_test = 0, dir_test = 0;
1215 saveintr = intr_disable();
1217 ccr2 = read_cyrix_reg(CCR2);
1218 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1219 read_cyrix_reg(CCR2);
1220 if (read_cyrix_reg(CCR2) != ccr2)
1222 write_cyrix_reg(CCR2, ccr2);
1224 ccr3 = read_cyrix_reg(CCR3);
1225 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1226 read_cyrix_reg(CCR3);
1227 if (read_cyrix_reg(CCR3) != ccr3)
1228 dir_test = 1; /* CPU supports DIRs. */
1229 write_cyrix_reg(CCR3, ccr3);
1232 /* Device ID registers are available. */
1233 cyrix_did = read_cyrix_reg(DIR1) << 8;
1234 cyrix_did += read_cyrix_reg(DIR0);
1235 } else if (ccr2_test)
1236 cyrix_did = 0x0010; /* 486S A-step */
1238 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1240 intr_restore(saveintr);
1244 /* Update TSC freq with the value indicated by the caller. */
1246 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1249 /* If there was an error during the transition, don't do anything. */
1253 /* Total setting for this level gives the new frequency in MHz. */
1254 hw_clockrate = level->total_set.freq;
1258 hook_tsc_freq(void *arg __unused)
1261 if (tsc_is_invariant)
1264 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1265 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1268 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1270 static const char *const vm_bnames[] = {
1272 "Plex86", /* Plex86 */
1273 "Bochs", /* Bochs */
1275 "BHYVE", /* bhyve */
1276 "Seabios", /* KVM */
1280 static const char *const vm_pnames[] = {
1281 "VMware Virtual Platform", /* VMWare VM */
1282 "Virtual Machine", /* Microsoft VirtualPC */
1283 "VirtualBox", /* Sun xVM VirtualBox */
1284 "Parallels Virtual Platform", /* Parallels VM */
1290 identify_hypervisor(void)
1297 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1298 * http://lkml.org/lkml/2008/10/1/246
1300 * KB1009458: Mechanisms to determine if software is running in
1301 * a VMware virtual machine
1302 * http://kb.vmware.com/kb/1009458
1304 if (cpu_feature2 & CPUID2_HV) {
1305 vm_guest = VM_GUEST_VM;
1306 do_cpuid(0x40000000, regs);
1307 if (regs[0] >= 0x40000000) {
1309 ((u_int *)&hv_vendor)[0] = regs[1];
1310 ((u_int *)&hv_vendor)[1] = regs[2];
1311 ((u_int *)&hv_vendor)[2] = regs[3];
1312 hv_vendor[12] = '\0';
1313 if (strcmp(hv_vendor, "VMwareVMware") == 0)
1314 vm_guest = VM_GUEST_VMWARE;
1315 else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1316 vm_guest = VM_GUEST_HV;
1317 else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1318 vm_guest = VM_GUEST_KVM;
1319 else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1320 vm_guest = VM_GUEST_BHYVE;
1326 * Examine SMBIOS strings for older hypervisors.
1328 p = kern_getenv("smbios.system.serial");
1330 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1331 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1332 if (regs[1] == VMW_HVMAGIC) {
1333 vm_guest = VM_GUEST_VMWARE;
1342 * XXX: Some of these entries may not be needed since they were
1343 * added to FreeBSD before the checks above.
1345 p = kern_getenv("smbios.bios.vendor");
1347 for (i = 0; vm_bnames[i] != NULL; i++)
1348 if (strcmp(p, vm_bnames[i]) == 0) {
1349 vm_guest = VM_GUEST_VM;
1355 p = kern_getenv("smbios.system.product");
1357 for (i = 0; vm_pnames[i] != NULL; i++)
1358 if (strcmp(p, vm_pnames[i]) == 0) {
1359 vm_guest = VM_GUEST_VM;
1373 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1374 * get the largest standard CPUID function number again if it is set
1375 * from BIOS. It is necessary for probing correct CPU topology later
1376 * and for the correct operation of the AVX-aware userspace.
1378 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1379 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1380 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1381 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1382 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1383 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1384 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1385 msr &= ~IA32_MISC_EN_LIMCPUID;
1386 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1392 * Re-enable AMD Topology Extension that could be disabled by BIOS
1393 * on some notebook processors. Without the extension it's really
1394 * hard to determine the correct CPU cache topology.
1395 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1396 * Models 60h-6Fh Processors, Publication # 50742.
1398 if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1399 msr = rdmsr(MSR_EXTFEATURES);
1400 if ((msr & ((uint64_t)1 << 54)) == 0) {
1401 msr |= (uint64_t)1 << 54;
1402 wrmsr(MSR_EXTFEATURES, msr);
1416 ((u_int *)&cpu_vendor)[0] = regs[1];
1417 ((u_int *)&cpu_vendor)[1] = regs[3];
1418 ((u_int *)&cpu_vendor)[2] = regs[2];
1419 cpu_vendor[12] = '\0';
1423 cpu_procinfo = regs[1];
1424 cpu_feature = regs[3];
1425 cpu_feature2 = regs[2];
1431 u_int regs[4], cpu_stdext_disable;
1433 if (cpu_high >= 7) {
1434 cpuid_count(7, 0, regs);
1435 cpu_stdext_feature = regs[1];
1438 * Some hypervisors failed to filter out unsupported
1439 * extended features. Allow to disable the
1440 * extensions, activation of which requires setting a
1441 * bit in CR4, and which VM monitors do not support.
1443 cpu_stdext_disable = 0;
1444 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1445 cpu_stdext_feature &= ~cpu_stdext_disable;
1447 cpu_stdext_feature2 = regs[2];
1448 cpu_stdext_feature3 = regs[3];
1450 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1451 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1456 * Final stage of CPU identification.
1459 finishidentcpu(void)
1466 cpu_vendor_id = find_cpu_vendor_id();
1473 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1475 cpu_mon_mwait_flags = regs[2];
1476 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1477 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1484 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1485 cpu_vendor_id == CPU_VENDOR_AMD ||
1486 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1487 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1488 cpu_vendor_id == CPU_VENDOR_NSC)) {
1489 do_cpuid(0x80000000, regs);
1490 if (regs[0] >= 0x80000000)
1491 cpu_exthigh = regs[0];
1494 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1495 cpu_vendor_id == CPU_VENDOR_AMD ||
1496 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1497 do_cpuid(0x80000000, regs);
1498 cpu_exthigh = regs[0];
1501 if (cpu_exthigh >= 0x80000001) {
1502 do_cpuid(0x80000001, regs);
1503 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1504 amd_feature2 = regs[2];
1506 if (cpu_exthigh >= 0x80000007) {
1507 do_cpuid(0x80000007, regs);
1508 amd_rascap = regs[1];
1509 amd_pminfo = regs[3];
1511 if (cpu_exthigh >= 0x80000008) {
1512 do_cpuid(0x80000008, regs);
1513 cpu_maxphyaddr = regs[0] & 0xff;
1514 amd_extended_feature_extensions = regs[1];
1515 cpu_procinfo2 = regs[2];
1517 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1521 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1522 if (cpu == CPU_486) {
1524 * These conditions are equivalent to:
1525 * - CPU does not support cpuid instruction.
1526 * - Cyrix/IBM CPU is detected.
1528 if (identblue() == IDENTBLUE_IBMCPU) {
1529 strcpy(cpu_vendor, "IBM");
1530 cpu_vendor_id = CPU_VENDOR_IBM;
1535 switch (cpu_id & 0xf00) {
1538 * Cyrix's datasheet does not describe DIRs.
1539 * Therefor, I assume it does not have them
1540 * and use the result of the cpuid instruction.
1541 * XXX they seem to have it for now at least. -Peter
1549 * This routine contains a trick.
1550 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1552 switch (cyrix_did & 0x00f0) {
1561 if ((cyrix_did & 0x000f) < 8)
1574 /* M2 and later CPUs are treated as M2. */
1578 * enable cpuid instruction.
1580 ccr3 = read_cyrix_reg(CCR3);
1581 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1582 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1583 write_cyrix_reg(CCR3, ccr3);
1586 cpu_high = regs[0]; /* eax */
1588 cpu_id = regs[0]; /* eax */
1589 cpu_feature = regs[3]; /* edx */
1593 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1595 * There are BlueLightning CPUs that do not change
1596 * undefined flags by dividing 5 by 2. In this case,
1597 * the CPU identification routine in locore.s leaves
1598 * cpu_vendor null string and puts CPU_486 into the
1601 if (identblue() == IDENTBLUE_IBMCPU) {
1602 strcpy(cpu_vendor, "IBM");
1603 cpu_vendor_id = CPU_VENDOR_IBM;
1612 pti_get_default(void)
1615 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1617 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1623 find_cpu_vendor_id(void)
1627 for (i = 0; i < nitems(cpu_vendors); i++)
1628 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1629 return (cpu_vendors[i].vendor_id);
1634 print_AMD_assoc(int i)
1637 printf(", fully associative\n");
1639 printf(", %d-way associative\n", i);
1643 print_AMD_l2_assoc(int i)
1646 case 0: printf(", disabled/not present\n"); break;
1647 case 1: printf(", direct mapped\n"); break;
1648 case 2: printf(", 2-way associative\n"); break;
1649 case 4: printf(", 4-way associative\n"); break;
1650 case 6: printf(", 8-way associative\n"); break;
1651 case 8: printf(", 16-way associative\n"); break;
1652 case 15: printf(", fully associative\n"); break;
1653 default: printf(", reserved configuration\n"); break;
1658 print_AMD_info(void)
1665 if (cpu_exthigh >= 0x80000005) {
1666 do_cpuid(0x80000005, regs);
1667 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1668 print_AMD_assoc(regs[0] >> 24);
1670 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1671 print_AMD_assoc((regs[0] >> 8) & 0xff);
1673 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1674 print_AMD_assoc(regs[1] >> 24);
1676 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1677 print_AMD_assoc((regs[1] >> 8) & 0xff);
1679 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1680 printf(", %d bytes/line", regs[2] & 0xff);
1681 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1682 print_AMD_assoc((regs[2] >> 16) & 0xff);
1684 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1685 printf(", %d bytes/line", regs[3] & 0xff);
1686 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1687 print_AMD_assoc((regs[3] >> 16) & 0xff);
1690 if (cpu_exthigh >= 0x80000006) {
1691 do_cpuid(0x80000006, regs);
1692 if ((regs[0] >> 16) != 0) {
1693 printf("L2 2MB data TLB: %d entries",
1694 (regs[0] >> 16) & 0xfff);
1695 print_AMD_l2_assoc(regs[0] >> 28);
1696 printf("L2 2MB instruction TLB: %d entries",
1698 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1700 printf("L2 2MB unified TLB: %d entries",
1702 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1704 if ((regs[1] >> 16) != 0) {
1705 printf("L2 4KB data TLB: %d entries",
1706 (regs[1] >> 16) & 0xfff);
1707 print_AMD_l2_assoc(regs[1] >> 28);
1709 printf("L2 4KB instruction TLB: %d entries",
1710 (regs[1] >> 16) & 0xfff);
1711 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1713 printf("L2 4KB unified TLB: %d entries",
1714 (regs[1] >> 16) & 0xfff);
1715 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1717 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1718 printf(", %d bytes/line", regs[2] & 0xff);
1719 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1720 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1724 if (((cpu_id & 0xf00) == 0x500)
1725 && (((cpu_id & 0x0f0) > 0x80)
1726 || (((cpu_id & 0x0f0) == 0x80)
1727 && (cpu_id & 0x00f) > 0x07))) {
1728 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1729 amd_whcr = rdmsr(0xc0000082);
1730 if (!(amd_whcr & (0x3ff << 22))) {
1731 printf("Write Allocate Disable\n");
1733 printf("Write Allocate Enable Limit: %dM bytes\n",
1734 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1735 printf("Write Allocate 15-16M bytes: %s\n",
1736 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1738 } else if (((cpu_id & 0xf00) == 0x500)
1739 && ((cpu_id & 0x0f0) > 0x50)) {
1740 /* K6, K6-2(old core) */
1741 amd_whcr = rdmsr(0xc0000082);
1742 if (!(amd_whcr & (0x7f << 1))) {
1743 printf("Write Allocate Disable\n");
1745 printf("Write Allocate Enable Limit: %dM bytes\n",
1746 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1747 printf("Write Allocate 15-16M bytes: %s\n",
1748 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1749 printf("Hardware Write Allocate Control: %s\n",
1750 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1755 * Opteron Rev E shows a bug as in very rare occasions a read memory
1756 * barrier is not performed as expected if it is followed by a
1757 * non-atomic read-modify-write instruction.
1758 * As long as that bug pops up very rarely (intensive machine usage
1759 * on other operating systems generally generates one unexplainable
1760 * crash any 2 months) and as long as a model specific fix would be
1761 * impractical at this stage, print out a warning string if the broken
1762 * model and family are identified.
1764 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1765 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1766 printf("WARNING: This architecture revision has known SMP "
1767 "hardware bugs which may cause random instability\n");
1771 print_INTEL_info(void)
1774 u_int rounds, regnum;
1775 u_int nwaycode, nway;
1777 if (cpu_high >= 2) {
1780 do_cpuid(0x2, regs);
1781 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1782 break; /* we have a buggy CPU */
1784 for (regnum = 0; regnum <= 3; ++regnum) {
1785 if (regs[regnum] & (1<<31))
1788 print_INTEL_TLB(regs[regnum] & 0xff);
1789 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1790 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1791 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1793 } while (--rounds > 0);
1796 if (cpu_exthigh >= 0x80000006) {
1797 do_cpuid(0x80000006, regs);
1798 nwaycode = (regs[2] >> 12) & 0x0f;
1799 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1800 nway = 1 << (nwaycode / 2);
1803 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1804 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1809 print_INTEL_TLB(u_int data)
1817 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1820 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1823 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1826 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1829 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1832 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1835 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1838 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1841 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1844 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1847 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1850 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1853 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1856 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1859 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1862 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1865 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1868 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1871 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1874 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1877 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1879 case 0x39: /* De-listed in SDM rev. 54 */
1880 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1882 case 0x3b: /* De-listed in SDM rev. 54 */
1883 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1885 case 0x3c: /* De-listed in SDM rev. 54 */
1886 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1889 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1892 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1895 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1898 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1901 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1904 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1907 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1910 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1913 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1914 CPUID_TO_MODEL(cpu_id) == 0x6)
1915 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1917 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1920 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1923 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1926 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1929 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1932 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1935 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1938 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1941 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1944 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1947 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1950 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1953 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1956 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1959 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1962 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1965 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1968 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1971 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1974 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1977 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1980 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1983 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1986 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1989 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1992 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1995 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1998 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2001 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2004 printf("Trace cache: 12K-uops, 8-way set associative\n");
2007 printf("Trace cache: 16K-uops, 8-way set associative\n");
2010 printf("Trace cache: 32K-uops, 8-way set associative\n");
2013 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2016 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2019 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2022 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2025 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2028 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2031 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2034 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2037 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2040 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2043 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2046 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2049 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2052 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2055 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2058 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2061 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2064 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2067 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2070 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2073 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2076 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2079 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2082 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2085 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2088 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2091 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2094 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2097 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2100 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2103 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2106 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2109 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2112 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2115 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2118 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2121 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2124 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2127 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2130 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2133 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2136 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2139 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2142 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2145 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2148 printf("64-Byte prefetching\n");
2151 printf("128-Byte prefetching\n");
2157 print_svm_info(void)
2159 u_int features, regs[4];
2164 do_cpuid(0x8000000A, regs);
2167 msr = rdmsr(MSR_VM_CR);
2168 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2169 printf("(disabled in BIOS) ");
2173 if (features & (1 << 0)) {
2174 printf("%sNP", comma ? "," : "");
2177 if (features & (1 << 3)) {
2178 printf("%sNRIP", comma ? "," : "");
2181 if (features & (1 << 5)) {
2182 printf("%sVClean", comma ? "," : "");
2185 if (features & (1 << 6)) {
2186 printf("%sAFlush", comma ? "," : "");
2189 if (features & (1 << 7)) {
2190 printf("%sDAssist", comma ? "," : "");
2193 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2197 printf("Features=0x%b", features,
2199 "\001NP" /* Nested paging */
2200 "\002LbrVirt" /* LBR virtualization */
2201 "\003SVML" /* SVM lock */
2202 "\004NRIPS" /* NRIP save */
2203 "\005TscRateMsr" /* MSR based TSC rate control */
2204 "\006VmcbClean" /* VMCB clean bits */
2205 "\007FlushByAsid" /* Flush by ASID */
2206 "\010DecodeAssist" /* Decode assist */
2209 "\013PauseFilter" /* PAUSE intercept filter */
2210 "\014EncryptedMcodePatch"
2211 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2212 "\016AVIC" /* virtual interrupt controller */
2214 "\020V_VMSAVE_VMLOAD"
2232 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2237 print_transmeta_info(void)
2239 u_int regs[4], nreg = 0;
2241 do_cpuid(0x80860000, regs);
2243 if (nreg >= 0x80860001) {
2244 do_cpuid(0x80860001, regs);
2245 printf(" Processor revision %u.%u.%u.%u\n",
2246 (regs[1] >> 24) & 0xff,
2247 (regs[1] >> 16) & 0xff,
2248 (regs[1] >> 8) & 0xff,
2251 if (nreg >= 0x80860002) {
2252 do_cpuid(0x80860002, regs);
2253 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2254 (regs[1] >> 24) & 0xff,
2255 (regs[1] >> 16) & 0xff,
2256 (regs[1] >> 8) & 0xff,
2260 if (nreg >= 0x80860006) {
2262 do_cpuid(0x80860003, (u_int*) &info[0]);
2263 do_cpuid(0x80860004, (u_int*) &info[16]);
2264 do_cpuid(0x80860005, (u_int*) &info[32]);
2265 do_cpuid(0x80860006, (u_int*) &info[48]);
2267 printf(" %s\n", info);
2273 print_via_padlock_info(void)
2277 do_cpuid(0xc0000001, regs);
2278 printf("\n VIA Padlock Features=0x%b", regs[3],
2282 "\011AES-CTR" /* ACE2 */
2283 "\013SHA1,SHA256" /* PHE */
2289 vmx_settable(uint64_t basic, int msr, int true_msr)
2293 if (basic & (1ULL << 55))
2294 val = rdmsr(true_msr);
2298 /* Just report the controls that can be set to 1. */
2303 print_vmx_info(void)
2305 uint64_t basic, msr;
2306 uint32_t entry, exit, mask, pin, proc, proc2;
2309 printf("\n VT-x: ");
2310 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2311 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2312 printf("(disabled in BIOS) ");
2313 basic = rdmsr(MSR_VMX_BASIC);
2314 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2315 MSR_VMX_TRUE_PINBASED_CTLS);
2316 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2317 MSR_VMX_TRUE_PROCBASED_CTLS);
2318 if (proc & PROCBASED_SECONDARY_CONTROLS)
2319 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2320 MSR_VMX_PROCBASED_CTLS2);
2323 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2324 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2328 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2329 entry & VM_ENTRY_LOAD_PAT) {
2330 printf("%sPAT", comma ? "," : "");
2333 if (proc & PROCBASED_HLT_EXITING) {
2334 printf("%sHLT", comma ? "," : "");
2337 if (proc & PROCBASED_MTF) {
2338 printf("%sMTF", comma ? "," : "");
2341 if (proc & PROCBASED_PAUSE_EXITING) {
2342 printf("%sPAUSE", comma ? "," : "");
2345 if (proc2 & PROCBASED2_ENABLE_EPT) {
2346 printf("%sEPT", comma ? "," : "");
2349 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2350 printf("%sUG", comma ? "," : "");
2353 if (proc2 & PROCBASED2_ENABLE_VPID) {
2354 printf("%sVPID", comma ? "," : "");
2357 if (proc & PROCBASED_USE_TPR_SHADOW &&
2358 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2359 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2360 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2361 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2362 printf("%sVID", comma ? "," : "");
2364 if (pin & PINBASED_POSTED_INTERRUPT)
2365 printf(",PostIntr");
2371 printf("Basic Features=0x%b", mask,
2373 "\02132PA" /* 32-bit physical addresses */
2374 "\022SMM" /* SMM dual-monitor */
2375 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2376 "\030TRUE" /* TRUE_CTLS MSRs */
2378 printf("\n Pin-Based Controls=0x%b", pin,
2380 "\001ExtINT" /* External-interrupt exiting */
2381 "\004NMI" /* NMI exiting */
2382 "\006VNMI" /* Virtual NMIs */
2383 "\007PreTmr" /* Activate VMX-preemption timer */
2384 "\010PostIntr" /* Process posted interrupts */
2386 printf("\n Primary Processor Controls=0x%b", proc,
2388 "\003INTWIN" /* Interrupt-window exiting */
2389 "\004TSCOff" /* Use TSC offsetting */
2390 "\010HLT" /* HLT exiting */
2391 "\012INVLPG" /* INVLPG exiting */
2392 "\013MWAIT" /* MWAIT exiting */
2393 "\014RDPMC" /* RDPMC exiting */
2394 "\015RDTSC" /* RDTSC exiting */
2395 "\020CR3-LD" /* CR3-load exiting */
2396 "\021CR3-ST" /* CR3-store exiting */
2397 "\024CR8-LD" /* CR8-load exiting */
2398 "\025CR8-ST" /* CR8-store exiting */
2399 "\026TPR" /* Use TPR shadow */
2400 "\027NMIWIN" /* NMI-window exiting */
2401 "\030MOV-DR" /* MOV-DR exiting */
2402 "\031IO" /* Unconditional I/O exiting */
2403 "\032IOmap" /* Use I/O bitmaps */
2404 "\034MTF" /* Monitor trap flag */
2405 "\035MSRmap" /* Use MSR bitmaps */
2406 "\036MONITOR" /* MONITOR exiting */
2407 "\037PAUSE" /* PAUSE exiting */
2409 if (proc & PROCBASED_SECONDARY_CONTROLS)
2410 printf("\n Secondary Processor Controls=0x%b", proc2,
2412 "\001APIC" /* Virtualize APIC accesses */
2413 "\002EPT" /* Enable EPT */
2414 "\003DT" /* Descriptor-table exiting */
2415 "\004RDTSCP" /* Enable RDTSCP */
2416 "\005x2APIC" /* Virtualize x2APIC mode */
2417 "\006VPID" /* Enable VPID */
2418 "\007WBINVD" /* WBINVD exiting */
2419 "\010UG" /* Unrestricted guest */
2420 "\011APIC-reg" /* APIC-register virtualization */
2421 "\012VID" /* Virtual-interrupt delivery */
2422 "\013PAUSE-loop" /* PAUSE-loop exiting */
2423 "\014RDRAND" /* RDRAND exiting */
2424 "\015INVPCID" /* Enable INVPCID */
2425 "\016VMFUNC" /* Enable VM functions */
2426 "\017VMCS" /* VMCS shadowing */
2427 "\020EPT#VE" /* EPT-violation #VE */
2428 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2430 printf("\n Exit Controls=0x%b", mask,
2432 "\003DR" /* Save debug controls */
2433 /* Ignore Host address-space size */
2434 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2435 "\020AckInt" /* Acknowledge interrupt on exit */
2436 "\023PAT-SV" /* Save MSR_PAT */
2437 "\024PAT-LD" /* Load MSR_PAT */
2438 "\025EFER-SV" /* Save MSR_EFER */
2439 "\026EFER-LD" /* Load MSR_EFER */
2440 "\027PTMR-SV" /* Save VMX-preemption timer value */
2442 printf("\n Entry Controls=0x%b", mask,
2444 "\003DR" /* Save debug controls */
2445 /* Ignore IA-32e mode guest */
2446 /* Ignore Entry to SMM */
2447 /* Ignore Deactivate dual-monitor treatment */
2448 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2449 "\017PAT" /* Load MSR_PAT */
2450 "\020EFER" /* Load MSR_EFER */
2452 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2453 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2454 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2456 printf("\n EPT Features=0x%b", mask,
2458 "\001XO" /* Execute-only translations */
2459 "\007PW4" /* Page-walk length of 4 */
2460 "\011UC" /* EPT paging-structure mem can be UC */
2461 "\017WB" /* EPT paging-structure mem can be WB */
2462 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2463 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2464 "\025INVEPT" /* INVEPT is supported */
2465 "\026AD" /* Accessed and dirty flags for EPT */
2466 "\032single" /* INVEPT single-context type */
2467 "\033all" /* INVEPT all-context type */
2470 printf("\n VPID Features=0x%b", mask,
2472 "\001INVVPID" /* INVVPID is supported */
2473 "\011individual" /* INVVPID individual-address type */
2474 "\012single" /* INVVPID single-context type */
2475 "\013all" /* INVVPID all-context type */
2476 /* INVVPID single-context-retaining-globals type */
2477 "\014single-globals"
2483 print_hypervisor_info(void)
2487 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);