sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 122 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %ebx */
 123 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %ecx */
 124 u_int   cpu_power_edx;          /* 06H: Power management leaf, %edx */
 125 char machine[] = MACHINE;
 126
 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 128     &via_feature_rng, 0,
 129     "VIA RNG feature available in CPU");
 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 131     &via_feature_xcrypt, 0,
 132     "VIA xcrypt feature available in CPU");
 133
 134 #ifdef __amd64__
 135 #ifdef SCTL_MASK32
 136 extern int adaptive_machine_arch;
 137 #endif
 138
 139 static int
 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 141 {
 142 #ifdef SCTL_MASK32
 143         static const char machine32[] = "i386";
 144 #endif
 145         int error;
 146
 147 #ifdef SCTL_MASK32
 148         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 149                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 150         else
 151 #endif
 152                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 153         return (error);
 154
 155 }
 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 157     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 158 #else
 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 160     machine, 0, "Machine class");
 161 #endif
 162
 163 static char cpu_model[128];
 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 165     cpu_model, 0, "Machine model");
 166
 167 static int hw_clockrate;
 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 169     &hw_clockrate, 0, "CPU instruction clock rate");
 170
 171 u_int hv_base;
 172 u_int hv_high;
 173 char hv_vendor[16];
 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 175     0, "Hypervisor vendor");
 176
 177 static eventhandler_tag tsc_post_tag;
 178
 179 static char cpu_brand[48];
 180
 181 #ifdef __i386__
 182 #define MAX_BRAND_INDEX 8
 183
 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 185         NULL,                   /* No brand */
 186         "Intel Celeron",
 187         "Intel Pentium III",
 188         "Intel Pentium III Xeon",
 189         NULL,
 190         NULL,
 191         NULL,
 192         NULL,
 193         "Intel Pentium 4"
 194 };
 195
 196 static struct {
 197         char    *cpu_name;
 198         int     cpu_class;
 199 } cpus[] = {
 200         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 201         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 202         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 203         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 204         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 205         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 206         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 207         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 208         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 209         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 210         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 211         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 212         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 213         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 214         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 215         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 216         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 217 };
 218 #endif
 219
 220 static struct {
 221         char    *vendor;
 222         u_int   vendor_id;
 223 } cpu_vendors[] = {
 224         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 225         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 226         { HYGON_VENDOR_ID,      CPU_VENDOR_HYGON },     /* HygonGenuine*/
 227         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 228 #ifdef __i386__
 229         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 230         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 231         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 232         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 233         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 234         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 235         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 236 #if 0
 237         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 238         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 239 #endif
 240 #endif
 241 };
 242
 243 void
 244 printcpuinfo(void)
 245 {
 246         u_int regs[4], i;
 247         char *brand;
 248
 249         printf("CPU: ");
 250 #ifdef __i386__
 251         cpu_class = cpus[cpu].cpu_class;
 252         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 253 #else
 254         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 255 #endif
 256
 257         /* Check for extended CPUID information and a processor name. */
 258         if (cpu_exthigh >= 0x80000004) {
 259                 brand = cpu_brand;
 260                 for (i = 0x80000002; i < 0x80000005; i++) {
 261                         do_cpuid(i, regs);
 262                         memcpy(brand, regs, sizeof(regs));
 263                         brand += sizeof(regs);
 264                 }
 265         }
 266
 267         switch (cpu_vendor_id) {
 268         case CPU_VENDOR_INTEL:
 269 #ifdef __i386__
 270                 if ((cpu_id & 0xf00) > 0x300) {
 271                         u_int brand_index;
 272
 273                         cpu_model[0] = '\0';
 274
 275                         switch (cpu_id & 0x3000) {
 276                         case 0x1000:
 277                                 strcpy(cpu_model, "Overdrive ");
 278                                 break;
 279                         case 0x2000:
 280                                 strcpy(cpu_model, "Dual ");
 281                                 break;
 282                         }
 283
 284                         switch (cpu_id & 0xf00) {
 285                         case 0x400:
 286                                 strcat(cpu_model, "i486 ");
 287                                 /* Check the particular flavor of 486 */
 288                                 switch (cpu_id & 0xf0) {
 289                                 case 0x00:
 290                                 case 0x10:
 291                                         strcat(cpu_model, "DX");
 292                                         break;
 293                                 case 0x20:
 294                                         strcat(cpu_model, "SX");
 295                                         break;
 296                                 case 0x30:
 297                                         strcat(cpu_model, "DX2");
 298                                         break;
 299                                 case 0x40:
 300                                         strcat(cpu_model, "SL");
 301                                         break;
 302                                 case 0x50:
 303                                         strcat(cpu_model, "SX2");
 304                                         break;
 305                                 case 0x70:
 306                                         strcat(cpu_model,
 307                                             "DX2 Write-Back Enhanced");
 308                                         break;
 309                                 case 0x80:
 310                                         strcat(cpu_model, "DX4");
 311                                         break;
 312                                 }
 313                                 break;
 314                         case 0x500:
 315                                 /* Check the particular flavor of 586 */
 316                                 strcat(cpu_model, "Pentium");
 317                                 switch (cpu_id & 0xf0) {
 318                                 case 0x00:
 319                                         strcat(cpu_model, " A-step");
 320                                         break;
 321                                 case 0x10:
 322                                         strcat(cpu_model, "/P5");
 323                                         break;
 324                                 case 0x20:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x30:
 328                                         strcat(cpu_model, "/P24T");
 329                                         break;
 330                                 case 0x40:
 331                                         strcat(cpu_model, "/P55C");
 332                                         break;
 333                                 case 0x70:
 334                                         strcat(cpu_model, "/P54C");
 335                                         break;
 336                                 case 0x80:
 337                                         strcat(cpu_model, "/P55C (quarter-micron)");
 338                                         break;
 339                                 default:
 340                                         /* nothing */
 341                                         break;
 342                                 }
 343 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 344                                 /*
 345                                  * XXX - If/when Intel fixes the bug, this
 346                                  * should also check the version of the
 347                                  * CPU, not just that it's a Pentium.
 348                                  */
 349                                 has_f00f_bug = 1;
 350 #endif
 351                                 break;
 352                         case 0x600:
 353                                 /* Check the particular flavor of 686 */
 354                                 switch (cpu_id & 0xf0) {
 355                                 case 0x00:
 356                                         strcat(cpu_model, "Pentium Pro A-step");
 357                                         break;
 358                                 case 0x10:
 359                                         strcat(cpu_model, "Pentium Pro");
 360                                         break;
 361                                 case 0x30:
 362                                 case 0x50:
 363                                 case 0x60:
 364                                         strcat(cpu_model,
 365                                 "Pentium II/Pentium II Xeon/Celeron");
 366                                         cpu = CPU_PII;
 367                                         break;
 368                                 case 0x70:
 369                                 case 0x80:
 370                                 case 0xa0:
 371                                 case 0xb0:
 372                                         strcat(cpu_model,
 373                                         "Pentium III/Pentium III Xeon/Celeron");
 374                                         cpu = CPU_PIII;
 375                                         break;
 376                                 default:
 377                                         strcat(cpu_model, "Unknown 80686");
 378                                         break;
 379                                 }
 380                                 break;
 381                         case 0xf00:
 382                                 strcat(cpu_model, "Pentium 4");
 383                                 cpu = CPU_P4;
 384                                 break;
 385                         default:
 386                                 strcat(cpu_model, "unknown");
 387                                 break;
 388                         }
 389
 390                         /*
 391                          * If we didn't get a brand name from the extended
 392                          * CPUID, try to look it up in the brand table.
 393                          */
 394                         if (cpu_high > 0 && *cpu_brand == '\0') {
 395                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 396                                 if (brand_index <= MAX_BRAND_INDEX &&
 397                                     cpu_brandtable[brand_index] != NULL)
 398                                         strcpy(cpu_brand,
 399                                             cpu_brandtable[brand_index]);
 400                         }
 401                 }
 402 #else
 403                 /* Please make up your mind folks! */
 404                 strcat(cpu_model, "EM64T");
 405 #endif
 406                 break;
 407         case CPU_VENDOR_AMD:
 408                 /*
 409                  * Values taken from AMD Processor Recognition
 410                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 411                  * (also describes ``Features'' encodings.
 412                  */
 413                 strcpy(cpu_model, "AMD ");
 414 #ifdef __i386__
 415                 switch (cpu_id & 0xFF0) {
 416                 case 0x410:
 417                         strcat(cpu_model, "Standard Am486DX");
 418                         break;
 419                 case 0x430:
 420                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 421                         break;
 422                 case 0x470:
 423                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 424                         break;
 425                 case 0x480:
 426                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 427                         break;
 428                 case 0x490:
 429                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 430                         break;
 431                 case 0x4E0:
 432                         strcat(cpu_model, "Am5x86 Write-Through");
 433                         break;
 434                 case 0x4F0:
 435                         strcat(cpu_model, "Am5x86 Write-Back");
 436                         break;
 437                 case 0x500:
 438                         strcat(cpu_model, "K5 model 0");
 439                         break;
 440                 case 0x510:
 441                         strcat(cpu_model, "K5 model 1");
 442                         break;
 443                 case 0x520:
 444                         strcat(cpu_model, "K5 PR166 (model 2)");
 445                         break;
 446                 case 0x530:
 447                         strcat(cpu_model, "K5 PR200 (model 3)");
 448                         break;
 449                 case 0x560:
 450                         strcat(cpu_model, "K6");
 451                         break;
 452                 case 0x570:
 453                         strcat(cpu_model, "K6 266 (model 1)");
 454                         break;
 455                 case 0x580:
 456                         strcat(cpu_model, "K6-2");
 457                         break;
 458                 case 0x590:
 459                         strcat(cpu_model, "K6-III");
 460                         break;
 461                 case 0x5a0:
 462                         strcat(cpu_model, "Geode LX");
 463                         break;
 464                 default:
 465                         strcat(cpu_model, "Unknown");
 466                         break;
 467                 }
 468 #else
 469                 if ((cpu_id & 0xf00) == 0xf00)
 470                         strcat(cpu_model, "AMD64 Processor");
 471                 else
 472                         strcat(cpu_model, "Unknown");
 473 #endif
 474                 break;
 475 #ifdef __i386__
 476         case CPU_VENDOR_CYRIX:
 477                 strcpy(cpu_model, "Cyrix ");
 478                 switch (cpu_id & 0xff0) {
 479                 case 0x440:
 480                         strcat(cpu_model, "MediaGX");
 481                         break;
 482                 case 0x520:
 483                         strcat(cpu_model, "6x86");
 484                         break;
 485                 case 0x540:
 486                         cpu_class = CPUCLASS_586;
 487                         strcat(cpu_model, "GXm");
 488                         break;
 489                 case 0x600:
 490                         strcat(cpu_model, "6x86MX");
 491                         break;
 492                 default:
 493                         /*
 494                          * Even though CPU supports the cpuid
 495                          * instruction, it can be disabled.
 496                          * Therefore, this routine supports all Cyrix
 497                          * CPUs.
 498                          */
 499                         switch (cyrix_did & 0xf0) {
 500                         case 0x00:
 501                                 switch (cyrix_did & 0x0f) {
 502                                 case 0x00:
 503                                         strcat(cpu_model, "486SLC");
 504                                         break;
 505                                 case 0x01:
 506                                         strcat(cpu_model, "486DLC");
 507                                         break;
 508                                 case 0x02:
 509                                         strcat(cpu_model, "486SLC2");
 510                                         break;
 511                                 case 0x03:
 512                                         strcat(cpu_model, "486DLC2");
 513                                         break;
 514                                 case 0x04:
 515                                         strcat(cpu_model, "486SRx");
 516                                         break;
 517                                 case 0x05:
 518                                         strcat(cpu_model, "486DRx");
 519                                         break;
 520                                 case 0x06:
 521                                         strcat(cpu_model, "486SRx2");
 522                                         break;
 523                                 case 0x07:
 524                                         strcat(cpu_model, "486DRx2");
 525                                         break;
 526                                 case 0x08:
 527                                         strcat(cpu_model, "486SRu");
 528                                         break;
 529                                 case 0x09:
 530                                         strcat(cpu_model, "486DRu");
 531                                         break;
 532                                 case 0x0a:
 533                                         strcat(cpu_model, "486SRu2");
 534                                         break;
 535                                 case 0x0b:
 536                                         strcat(cpu_model, "486DRu2");
 537                                         break;
 538                                 default:
 539                                         strcat(cpu_model, "Unknown");
 540                                         break;
 541                                 }
 542                                 break;
 543                         case 0x10:
 544                                 switch (cyrix_did & 0x0f) {
 545                                 case 0x00:
 546                                         strcat(cpu_model, "486S");
 547                                         break;
 548                                 case 0x01:
 549                                         strcat(cpu_model, "486S2");
 550                                         break;
 551                                 case 0x02:
 552                                         strcat(cpu_model, "486Se");
 553                                         break;
 554                                 case 0x03:
 555                                         strcat(cpu_model, "486S2e");
 556                                         break;
 557                                 case 0x0a:
 558                                         strcat(cpu_model, "486DX");
 559                                         break;
 560                                 case 0x0b:
 561                                         strcat(cpu_model, "486DX2");
 562                                         break;
 563                                 case 0x0f:
 564                                         strcat(cpu_model, "486DX4");
 565                                         break;
 566                                 default:
 567                                         strcat(cpu_model, "Unknown");
 568                                         break;
 569                                 }
 570                                 break;
 571                         case 0x20:
 572                                 if ((cyrix_did & 0x0f) < 8)
 573                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 574                                 else
 575                                         strcat(cpu_model, "5x86");
 576                                 break;
 577                         case 0x30:
 578                                 strcat(cpu_model, "6x86");
 579                                 break;
 580                         case 0x40:
 581                                 if ((cyrix_did & 0xf000) == 0x3000) {
 582                                         cpu_class = CPUCLASS_586;
 583                                         strcat(cpu_model, "GXm");
 584                                 } else
 585                                         strcat(cpu_model, "MediaGX");
 586                                 break;
 587                         case 0x50:
 588                                 strcat(cpu_model, "6x86MX");
 589                                 break;
 590                         case 0xf0:
 591                                 switch (cyrix_did & 0x0f) {
 592                                 case 0x0d:
 593                                         strcat(cpu_model, "Overdrive CPU");
 594                                         break;
 595                                 case 0x0e:
 596                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 597                                         break;
 598                                 case 0x0f:
 599                                         strcat(cpu_model, "486SLC/DLC");
 600                                         break;
 601                                 default:
 602                                         strcat(cpu_model, "Unknown");
 603                                         break;
 604                                 }
 605                                 break;
 606                         default:
 607                                 strcat(cpu_model, "Unknown");
 608                                 break;
 609                         }
 610                         break;
 611                 }
 612                 break;
 613         case CPU_VENDOR_RISE:
 614                 strcpy(cpu_model, "Rise ");
 615                 switch (cpu_id & 0xff0) {
 616                 case 0x500:     /* 6401 and 6441 (Kirin) */
 617                 case 0x520:     /* 6510 (Lynx) */
 618                         strcat(cpu_model, "mP6");
 619                         break;
 620                 default:
 621                         strcat(cpu_model, "Unknown");
 622                 }
 623                 break;
 624 #endif
 625         case CPU_VENDOR_CENTAUR:
 626 #ifdef __i386__
 627                 switch (cpu_id & 0xff0) {
 628                 case 0x540:
 629                         strcpy(cpu_model, "IDT WinChip C6");
 630                         break;
 631                 case 0x580:
 632                         strcpy(cpu_model, "IDT WinChip 2");
 633                         break;
 634                 case 0x590:
 635                         strcpy(cpu_model, "IDT WinChip 3");
 636                         break;
 637                 case 0x660:
 638                         strcpy(cpu_model, "VIA C3 Samuel");
 639                         break;
 640                 case 0x670:
 641                         if (cpu_id & 0x8)
 642                                 strcpy(cpu_model, "VIA C3 Ezra");
 643                         else
 644                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 645                         break;
 646                 case 0x680:
 647                         strcpy(cpu_model, "VIA C3 Ezra-T");
 648                         break;
 649                 case 0x690:
 650                         strcpy(cpu_model, "VIA C3 Nehemiah");
 651                         break;
 652                 case 0x6a0:
 653                 case 0x6d0:
 654                         strcpy(cpu_model, "VIA C7 Esther");
 655                         break;
 656                 case 0x6f0:
 657                         strcpy(cpu_model, "VIA Nano");
 658                         break;
 659                 default:
 660                         strcpy(cpu_model, "VIA/IDT Unknown");
 661                 }
 662 #else
 663                 strcpy(cpu_model, "VIA ");
 664                 if ((cpu_id & 0xff0) == 0x6f0)
 665                         strcat(cpu_model, "Nano Processor");
 666                 else
 667                         strcat(cpu_model, "Unknown");
 668 #endif
 669                 break;
 670 #ifdef __i386__
 671         case CPU_VENDOR_IBM:
 672                 strcpy(cpu_model, "Blue Lightning CPU");
 673                 break;
 674         case CPU_VENDOR_NSC:
 675                 switch (cpu_id & 0xff0) {
 676                 case 0x540:
 677                         strcpy(cpu_model, "Geode SC1100");
 678                         cpu = CPU_GEODE1100;
 679                         break;
 680                 default:
 681                         strcpy(cpu_model, "Geode/NSC unknown");
 682                         break;
 683                 }
 684                 break;
 685 #endif
 686         case CPU_VENDOR_HYGON:
 687                 strcpy(cpu_model, "Hygon ");
 688 #ifdef __i386__
 689                 strcat(cpu_model, "Unknown");
 690 #else
 691                 if ((cpu_id & 0xf00) == 0xf00)
 692                         strcat(cpu_model, "AMD64 Processor");
 693                 else
 694                         strcat(cpu_model, "Unknown");
 695 #endif
 696                 break;
 697
 698         default:
 699                 strcat(cpu_model, "Unknown");
 700                 break;
 701         }
 702
 703         /*
 704          * Replace cpu_model with cpu_brand minus leading spaces if
 705          * we have one.
 706          */
 707         brand = cpu_brand;
 708         while (*brand == ' ')
 709                 ++brand;
 710         if (*brand != '\0')
 711                 strcpy(cpu_model, brand);
 712
 713         printf("%s (", cpu_model);
 714         if (tsc_freq != 0) {
 715                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 716                 printf("%jd.%02d-MHz ",
 717                     (intmax_t)(tsc_freq + 4999) / 1000000,
 718                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 719         }
 720 #ifdef __i386__
 721         switch(cpu_class) {
 722         case CPUCLASS_286:
 723                 printf("286");
 724                 break;
 725         case CPUCLASS_386:
 726                 printf("386");
 727                 break;
 728 #if defined(I486_CPU)
 729         case CPUCLASS_486:
 730                 printf("486");
 731                 break;
 732 #endif
 733 #if defined(I586_CPU)
 734         case CPUCLASS_586:
 735                 printf("586");
 736                 break;
 737 #endif
 738 #if defined(I686_CPU)
 739         case CPUCLASS_686:
 740                 printf("686");
 741                 break;
 742 #endif
 743         default:
 744                 printf("Unknown");      /* will panic below... */
 745         }
 746 #else
 747         printf("K8");
 748 #endif
 749         printf("-class CPU)\n");
 750         if (*cpu_vendor)
 751                 printf("  Origin=\"%s\"", cpu_vendor);
 752         if (cpu_id)
 753                 printf("  Id=0x%x", cpu_id);
 754
 755         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 756             cpu_vendor_id == CPU_VENDOR_AMD ||
 757             cpu_vendor_id == CPU_VENDOR_HYGON ||
 758             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 759 #ifdef __i386__
 760             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 761             cpu_vendor_id == CPU_VENDOR_RISE ||
 762             cpu_vendor_id == CPU_VENDOR_NSC ||
 763             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 764 #endif
 765             0) {
 766                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 767                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 768                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 769 #ifdef __i386__
 770                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 771                         printf("\n  DIR=0x%04x", cyrix_did);
 772 #endif
 773
 774                 /*
 775                  * AMD CPUID Specification
 776                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 777                  *
 778                  * Intel Processor Identification and CPUID Instruction
 779                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 780                  */
 781                 if (cpu_high > 0) {
 782
 783                         /*
 784                          * Here we should probably set up flags indicating
 785                          * whether or not various features are available.
 786                          * The interesting ones are probably VME, PSE, PAE,
 787                          * and PGE.  The code already assumes without bothering
 788                          * to check that all CPUs >= Pentium have a TSC and
 789                          * MSRs.
 790                          */
 791                         printf("\n  Features=0x%b", cpu_feature,
 792                         "\020"
 793                         "\001FPU"       /* Integral FPU */
 794                         "\002VME"       /* Extended VM86 mode support */
 795                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 796                         "\004PSE"       /* 4MByte page tables */
 797                         "\005TSC"       /* Timestamp counter */
 798                         "\006MSR"       /* Machine specific registers */
 799                         "\007PAE"       /* Physical address extension */
 800                         "\010MCE"       /* Machine Check support */
 801                         "\011CX8"       /* CMPEXCH8 instruction */
 802                         "\012APIC"      /* SMP local APIC */
 803                         "\013oldMTRR"   /* Previous implementation of MTRR */
 804                         "\014SEP"       /* Fast System Call */
 805                         "\015MTRR"      /* Memory Type Range Registers */
 806                         "\016PGE"       /* PG_G (global bit) support */
 807                         "\017MCA"       /* Machine Check Architecture */
 808                         "\020CMOV"      /* CMOV instruction */
 809                         "\021PAT"       /* Page attributes table */
 810                         "\022PSE36"     /* 36 bit address space support */
 811                         "\023PN"        /* Processor Serial number */
 812                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 813                         "\025<b20>"
 814                         "\026DTS"       /* Debug Trace Store */
 815                         "\027ACPI"      /* ACPI support */
 816                         "\030MMX"       /* MMX instructions */
 817                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 818                         "\032SSE"       /* Streaming SIMD Extensions */
 819                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 820                         "\034SS"        /* Self snoop */
 821                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 822                         "\036TM"        /* Thermal Monitor clock slowdown */
 823                         "\037IA64"      /* CPU can execute IA64 instructions */
 824                         "\040PBE"       /* Pending Break Enable */
 825                         );
 826
 827                         if (cpu_feature2 != 0) {
 828                                 printf("\n  Features2=0x%b", cpu_feature2,
 829                                 "\020"
 830                                 "\001SSE3"      /* SSE3 */
 831                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 832                                 "\003DTES64"    /* 64-bit Debug Trace */
 833                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 834                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 835                                 "\006VMX"       /* Virtual Machine Extensions */
 836                                 "\007SMX"       /* Safer Mode Extensions */
 837                                 "\010EST"       /* Enhanced SpeedStep */
 838                                 "\011TM2"       /* Thermal Monitor 2 */
 839                                 "\012SSSE3"     /* SSSE3 */
 840                                 "\013CNXT-ID"   /* L1 context ID available */
 841                                 "\014SDBG"      /* IA32 silicon debug */
 842                                 "\015FMA"       /* Fused Multiply Add */
 843                                 "\016CX16"      /* CMPXCHG16B Instruction */
 844                                 "\017xTPR"      /* Send Task Priority Messages*/
 845                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 846                                 "\021<b16>"
 847                                 "\022PCID"      /* Process-context Identifiers*/
 848                                 "\023DCA"       /* Direct Cache Access */
 849                                 "\024SSE4.1"    /* SSE 4.1 */
 850                                 "\025SSE4.2"    /* SSE 4.2 */
 851                                 "\026x2APIC"    /* xAPIC Extensions */
 852                                 "\027MOVBE"     /* MOVBE Instruction */
 853                                 "\030POPCNT"    /* POPCNT Instruction */
 854                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 855                                 "\032AESNI"     /* AES Crypto */
 856                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 857                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 858                                 "\035AVX"       /* Advanced Vector Extensions */
 859                                 "\036F16C"      /* Half-precision conversions */
 860                                 "\037RDRAND"    /* RDRAND Instruction */
 861                                 "\040HV"        /* Hypervisor */
 862                                 );
 863                         }
 864
 865                         if (amd_feature != 0) {
 866                                 printf("\n  AMD Features=0x%b", amd_feature,
 867                                 "\020"          /* in hex */
 868                                 "\001<s0>"      /* Same */
 869                                 "\002<s1>"      /* Same */
 870                                 "\003<s2>"      /* Same */
 871                                 "\004<s3>"      /* Same */
 872                                 "\005<s4>"      /* Same */
 873                                 "\006<s5>"      /* Same */
 874                                 "\007<s6>"      /* Same */
 875                                 "\010<s7>"      /* Same */
 876                                 "\011<s8>"      /* Same */
 877                                 "\012<s9>"      /* Same */
 878                                 "\013<b10>"     /* Undefined */
 879                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 880                                 "\015<s12>"     /* Same */
 881                                 "\016<s13>"     /* Same */
 882                                 "\017<s14>"     /* Same */
 883                                 "\020<s15>"     /* Same */
 884                                 "\021<s16>"     /* Same */
 885                                 "\022<s17>"     /* Same */
 886                                 "\023<b18>"     /* Reserved, unknown */
 887                                 "\024MP"        /* Multiprocessor Capable */
 888                                 "\025NX"        /* Has EFER.NXE, NX */
 889                                 "\026<b21>"     /* Undefined */
 890                                 "\027MMX+"      /* AMD MMX Extensions */
 891                                 "\030<s23>"     /* Same */
 892                                 "\031<s24>"     /* Same */
 893                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 894                                 "\033Page1GB"   /* 1-GB large page support */
 895                                 "\034RDTSCP"    /* RDTSCP */
 896                                 "\035<b28>"     /* Undefined */
 897                                 "\036LM"        /* 64 bit long mode */
 898                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 899                                 "\0403DNow!"    /* AMD 3DNow! */
 900                                 );
 901                         }
 902
 903                         if (amd_feature2 != 0) {
 904                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 905                                 "\020"
 906                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 907                                 "\002CMP"       /* CMP legacy */
 908                                 "\003SVM"       /* Secure Virtual Mode */
 909                                 "\004ExtAPIC"   /* Extended APIC register */
 910                                 "\005CR8"       /* CR8 in legacy mode */
 911                                 "\006ABM"       /* LZCNT instruction */
 912                                 "\007SSE4A"     /* SSE4A */
 913                                 "\010MAS"       /* Misaligned SSE mode */
 914                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 915                                 "\012OSVW"      /* OS visible workaround */
 916                                 "\013IBS"       /* Instruction based sampling */
 917                                 "\014XOP"       /* XOP extended instructions */
 918                                 "\015SKINIT"    /* SKINIT/STGI */
 919                                 "\016WDT"       /* Watchdog timer */
 920                                 "\017<b14>"
 921                                 "\020LWP"       /* Lightweight Profiling */
 922                                 "\021FMA4"      /* 4-operand FMA instructions */
 923                                 "\022TCE"       /* Translation Cache Extension */
 924                                 "\023<b18>"
 925                                 "\024NodeId"    /* NodeId MSR support */
 926                                 "\025<b20>"
 927                                 "\026TBM"       /* Trailing Bit Manipulation */
 928                                 "\027Topology"  /* Topology Extensions */
 929                                 "\030PCXC"      /* Core perf count */
 930                                 "\031PNXC"      /* NB perf count */
 931                                 "\032<b25>"
 932                                 "\033DBE"       /* Data Breakpoint extension */
 933                                 "\034PTSC"      /* Performance TSC */
 934                                 "\035PL2I"      /* L2I perf count */
 935                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 936                                 "\037ADMSKX"    /* Address mask extension */
 937                                 "\040<b31>"
 938                                 );
 939                         }
 940
 941                         if (cpu_stdext_feature != 0) {
 942                                 printf("\n  Structured Extended Features=0x%b",
 943                                     cpu_stdext_feature,
 944                                        "\020"
 945                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 946                                        "\001FSGSBASE"
 947                                        "\002TSCADJ"
 948                                        "\003SGX"
 949                                        /* Bit Manipulation Instructions */
 950                                        "\004BMI1"
 951                                        /* Hardware Lock Elision */
 952                                        "\005HLE"
 953                                        /* Advanced Vector Instructions 2 */
 954                                        "\006AVX2"
 955                                        /* FDP_EXCPTN_ONLY */
 956                                        "\007FDPEXC"
 957                                        /* Supervisor Mode Execution Prot. */
 958                                        "\010SMEP"
 959                                        /* Bit Manipulation Instructions */
 960                                        "\011BMI2"
 961                                        "\012ERMS"
 962                                        /* Invalidate Processor Context ID */
 963                                        "\013INVPCID"
 964                                        /* Restricted Transactional Memory */
 965                                        "\014RTM"
 966                                        "\015PQM"
 967                                        "\016NFPUSG"
 968                                        /* Intel Memory Protection Extensions */
 969                                        "\017MPX"
 970                                        "\020PQE"
 971                                        /* AVX512 Foundation */
 972                                        "\021AVX512F"
 973                                        "\022AVX512DQ"
 974                                        /* Enhanced NRBG */
 975                                        "\023RDSEED"
 976                                        /* ADCX + ADOX */
 977                                        "\024ADX"
 978                                        /* Supervisor Mode Access Prevention */
 979                                        "\025SMAP"
 980                                        "\026AVX512IFMA"
 981                                        /* Formerly PCOMMIT */
 982                                        "\027<b22>"
 983                                        "\030CLFLUSHOPT"
 984                                        "\031CLWB"
 985                                        "\032PROCTRACE"
 986                                        "\033AVX512PF"
 987                                        "\034AVX512ER"
 988                                        "\035AVX512CD"
 989                                        "\036SHA"
 990                                        "\037AVX512BW"
 991                                        "\040AVX512VL"
 992                                        );
 993                         }
 994
 995                         if (cpu_stdext_feature2 != 0) {
 996                                 printf("\n  Structured Extended Features2=0x%b",
 997                                     cpu_stdext_feature2,
 998                                        "\020"
 999                                        "\001PREFETCHWT1"
1000                                        "\002AVX512VBMI"
1001                                        "\003UMIP"
1002                                        "\004PKU"
1003                                        "\005OSPKE"
1004                                        "\006WAITPKG"
1005                                        "\007AVX512VBMI2"
1006                                        "\011GFNI"
1007                                        "\012VAES"
1008                                        "\013VPCLMULQDQ"
1009                                        "\014AVX512VNNI"
1010                                        "\015AVX512BITALG"
1011                                        "\016TME"
1012                                        "\017AVX512VPOPCNTDQ"
1013                                        "\021LA57"
1014                                        "\027RDPID"
1015                                        "\032CLDEMOTE"
1016                                        "\034MOVDIRI"
1017                                        "\035MOVDIR64B"
1018                                        "\036ENQCMD"
1019                                        "\037SGXLC"
1020                                        );
1021                         }
1022
1023                         if (cpu_stdext_feature3 != 0) {
1024                                 printf("\n  Structured Extended Features3=0x%b",
1025                                     cpu_stdext_feature3,
1026                                        "\020"
1027                                        "\003AVX512_4VNNIW"
1028                                        "\004AVX512_4FMAPS"
1029                                        "\005FSRM"
1030                                        "\011AVX512VP2INTERSECT"
1031                                        "\012MCUOPT"
1032                                        "\013MD_CLEAR"
1033                                        "\016TSXFA"
1034                                        "\023PCONFIG"
1035                                        "\025IBT"
1036                                        "\033IBPB"
1037                                        "\034STIBP"
1038                                        "\035L1DFL"
1039                                        "\036ARCH_CAP"
1040                                        "\037CORE_CAP"
1041                                        "\040SSBD"
1042                                        );
1043                         }
1044
1045                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1046                                 cpuid_count(0xd, 0x1, regs);
1047                                 if (regs[0] != 0) {
1048                                         printf("\n  XSAVE Features=0x%b",
1049                                             regs[0],
1050                                             "\020"
1051                                             "\001XSAVEOPT"
1052                                             "\002XSAVEC"
1053                                             "\003XINUSE"
1054                                             "\004XSAVES");
1055                                 }
1056                         }
1057
1058                         if (cpu_ia32_arch_caps != 0) {
1059                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1060                                     (u_int)cpu_ia32_arch_caps,
1061                                        "\020"
1062                                        "\001RDCL_NO"
1063                                        "\002IBRS_ALL"
1064                                        "\003RSBA"
1065                                        "\004SKIP_L1DFL_VME"
1066                                        "\005SSB_NO"
1067                                        "\006MDS_NO"
1068                                        "\010TSX_CTRL"
1069                                        "\011TAA_NO"
1070                                        );
1071                         }
1072
1073                         if (amd_extended_feature_extensions != 0) {
1074                                 u_int amd_fe_masked;
1075
1076                                 amd_fe_masked = amd_extended_feature_extensions;
1077                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1078                                         amd_fe_masked &=
1079                                             ~(AMDFEID_IBRS_ALWAYSON |
1080                                                 AMDFEID_PREFER_IBRS);
1081                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1082                                         amd_fe_masked &=
1083                                             ~AMDFEID_STIBP_ALWAYSON;
1084
1085                                 printf("\n  "
1086                                     "AMD Extended Feature Extensions ID EBX="
1087                                     "0x%b", amd_fe_masked,
1088                                     "\020"
1089                                     "\001CLZERO"
1090                                     "\002IRPerf"
1091                                     "\003XSaveErPtr"
1092                                     "\005RDPRU"
1093                                     "\011MCOMMIT"
1094                                     "\012WBNOINVD"
1095                                     "\015IBPB"
1096                                     "\017IBRS"
1097                                     "\020STIBP"
1098                                     "\021IBRS_ALWAYSON"
1099                                     "\022STIBP_ALWAYSON"
1100                                     "\023PREFER_IBRS"
1101                                     "\030PPIN"
1102                                     "\031SSBD"
1103                                     "\032VIRT_SSBD"
1104                                     "\033SSB_NO"
1105                                     );
1106                         }
1107
1108                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1109                                 print_via_padlock_info();
1110
1111                         if (cpu_feature2 & CPUID2_VMX)
1112                                 print_vmx_info();
1113
1114                         if (amd_feature2 & AMDID2_SVM)
1115                                 print_svm_info();
1116
1117                         if ((cpu_feature & CPUID_HTT) &&
1118                             (cpu_vendor_id == CPU_VENDOR_AMD ||
1119                              cpu_vendor_id == CPU_VENDOR_HYGON))
1120                                 cpu_feature &= ~CPUID_HTT;
1121
1122                         /*
1123                          * If this CPU supports P-state invariant TSC then
1124                          * mention the capability.
1125                          */
1126                         if (tsc_is_invariant) {
1127                                 printf("\n  TSC: P-state invariant");
1128                                 if (tsc_perf_stat)
1129                                         printf(", performance statistics");
1130                         }
1131                 }
1132 #ifdef __i386__
1133         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1134                 printf("  DIR=0x%04x", cyrix_did);
1135                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1136                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1137 #ifndef CYRIX_CACHE_REALLY_WORKS
1138                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1139                         printf("\n  CPU cache: write-through mode");
1140 #endif
1141 #endif
1142         }
1143
1144         /* Avoid ugly blank lines: only print newline when we have to. */
1145         if (*cpu_vendor || cpu_id)
1146                 printf("\n");
1147
1148         if (bootverbose) {
1149                 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1150                     cpu_vendor_id == CPU_VENDOR_HYGON)
1151                         print_AMD_info();
1152                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1153                         print_INTEL_info();
1154 #ifdef __i386__
1155                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1156                         print_transmeta_info();
1157 #endif
1158         }
1159
1160         print_hypervisor_info();
1161 }
1162
1163 #ifdef __i386__
1164 void
1165 panicifcpuunsupported(void)
1166 {
1167
1168 #if !defined(lint)
1169 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1170 #error This kernel is not configured for one of the supported CPUs
1171 #endif
1172 #else /* lint */
1173 #endif /* lint */
1174         /*
1175          * Now that we have told the user what they have,
1176          * let them know if that machine type isn't configured.
1177          */
1178         switch (cpu_class) {
1179         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1180         case CPUCLASS_386:
1181 #if !defined(I486_CPU)
1182         case CPUCLASS_486:
1183 #endif
1184 #if !defined(I586_CPU)
1185         case CPUCLASS_586:
1186 #endif
1187 #if !defined(I686_CPU)
1188         case CPUCLASS_686:
1189 #endif
1190                 panic("CPU class not configured");
1191         default:
1192                 break;
1193         }
1194 }
1195
1196 static  volatile u_int trap_by_rdmsr;
1197
1198 /*
1199  * Special exception 6 handler.
1200  * The rdmsr instruction generates invalid opcodes fault on 486-class
1201  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1202  * function identblue() when this handler is called.  Stacked eip should
1203  * be advanced.
1204  */
1205 inthand_t       bluetrap6;
1206 #ifdef __GNUCLIKE_ASM
1207 __asm
1208 ("                                                                      \n\
1209         .text                                                           \n\
1210         .p2align 2,0x90                                                 \n\
1211         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1212 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1213         ss                                                              \n\
1214         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1215         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1216         iret                                                            \n\
1217 ");
1218 #endif
1219
1220 /*
1221  * Special exception 13 handler.
1222  * Accessing non-existent MSR generates general protection fault.
1223  */
1224 inthand_t       bluetrap13;
1225 #ifdef __GNUCLIKE_ASM
1226 __asm
1227 ("                                                                      \n\
1228         .text                                                           \n\
1229         .p2align 2,0x90                                                 \n\
1230         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1231 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1232         ss                                                              \n\
1233         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1234         popl    %eax            /* discard error code */                \n\
1235         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1236         iret                                                            \n\
1237 ");
1238 #endif
1239
1240 /*
1241  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1242  * support cpuid instruction.  This function should be called after
1243  * loading interrupt descriptor table register.
1244  *
1245  * I don't like this method that handles fault, but I couldn't get
1246  * information for any other methods.  Does blue giant know?
1247  */
1248 static int
1249 identblue(void)
1250 {
1251
1252         trap_by_rdmsr = 0;
1253
1254         /*
1255          * Cyrix 486-class CPU does not support rdmsr instruction.
1256          * The rdmsr instruction generates invalid opcode fault, and exception
1257          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1258          * bluetrap6() set the magic number to trap_by_rdmsr.
1259          */
1260         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1261             GSEL(GCODE_SEL, SEL_KPL));
1262
1263         /*
1264          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1265          * In this case, rdmsr generates general protection fault, and
1266          * exception will be trapped by bluetrap13().
1267          */
1268         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1269             GSEL(GCODE_SEL, SEL_KPL));
1270
1271         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1272
1273         if (trap_by_rdmsr == 0xa8c1d)
1274                 return IDENTBLUE_CYRIX486;
1275         else if (trap_by_rdmsr == 0xa89c4)
1276                 return IDENTBLUE_CYRIXM2;
1277         return IDENTBLUE_IBMCPU;
1278 }
1279
1280
1281 /*
1282  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1283  *
1284  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1285  * +-------+-------+---------------+
1286  * |  SID  |  RID  |   Device ID   |
1287  * |    (DIR 1)    |    (DIR 0)    |
1288  * +-------+-------+---------------+
1289  */
1290 static void
1291 identifycyrix(void)
1292 {
1293         register_t saveintr;
1294         int     ccr2_test = 0, dir_test = 0;
1295         u_char  ccr2, ccr3;
1296
1297         saveintr = intr_disable();
1298
1299         ccr2 = read_cyrix_reg(CCR2);
1300         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1301         read_cyrix_reg(CCR2);
1302         if (read_cyrix_reg(CCR2) != ccr2)
1303                 ccr2_test = 1;
1304         write_cyrix_reg(CCR2, ccr2);
1305
1306         ccr3 = read_cyrix_reg(CCR3);
1307         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1308         read_cyrix_reg(CCR3);
1309         if (read_cyrix_reg(CCR3) != ccr3)
1310                 dir_test = 1;                                   /* CPU supports DIRs. */
1311         write_cyrix_reg(CCR3, ccr3);
1312
1313         if (dir_test) {
1314                 /* Device ID registers are available. */
1315                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1316                 cyrix_did += read_cyrix_reg(DIR0);
1317         } else if (ccr2_test)
1318                 cyrix_did = 0x0010;             /* 486S A-step */
1319         else
1320                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1321
1322         intr_restore(saveintr);
1323 }
1324 #endif
1325
1326 /* Update TSC freq with the value indicated by the caller. */
1327 static void
1328 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1329 {
1330
1331         /* If there was an error during the transition, don't do anything. */
1332         if (status != 0)
1333                 return;
1334
1335         /* Total setting for this level gives the new frequency in MHz. */
1336         hw_clockrate = level->total_set.freq;
1337 }
1338
1339 static void
1340 hook_tsc_freq(void *arg __unused)
1341 {
1342
1343         if (tsc_is_invariant)
1344                 return;
1345
1346         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1347             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1348 }
1349
1350 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1351
1352 static const struct {
1353         const char *    vm_bname;
1354         int             vm_guest;
1355 } vm_bnames[] = {
1356         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1357         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1358         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1359         { "Xen",        VM_GUEST_XEN },         /* Xen */
1360         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1361         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1362 };
1363
1364 static const struct {
1365         const char *    vm_pname;
1366         int             vm_guest;
1367 } vm_pnames[] = {
1368         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1369         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1370         { "VirtualBox",                 VM_GUEST_VBOX },
1371         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1372         { "KVM",                        VM_GUEST_KVM },
1373 };
1374
1375 static struct {
1376         const char      *vm_cpuid;
1377         int             vm_guest;
1378 } vm_cpuids[] = {
1379         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1380         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1381         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1382         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1383         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1384         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1385 };
1386
1387 static void
1388 identify_hypervisor_cpuid_base(void)
1389 {
1390         u_int leaf, regs[4];
1391         int i;
1392
1393         /*
1394          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1395          * http://lkml.org/lkml/2008/10/1/246
1396          *
1397          * KB1009458: Mechanisms to determine if software is running in
1398          * a VMware virtual machine
1399          * http://kb.vmware.com/kb/1009458
1400          *
1401          * Search for a hypervisor that we recognize. If we cannot find
1402          * a specific hypervisor, return the first information about the
1403          * hypervisor that we found, as others may be able to use.
1404          */
1405         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1406                 do_cpuid(leaf, regs);
1407
1408                 /*
1409                  * KVM from Linux kernels prior to commit
1410                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1411                  * to 0 rather than a valid hv_high value.  Check for
1412                  * the KVM signature bytes and fixup %eax to the
1413                  * highest supported leaf in that case.
1414                  */
1415                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1416                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1417                         regs[0] = leaf + 1;
1418
1419                 if (regs[0] >= leaf) {
1420                         for (i = 0; i < nitems(vm_cpuids); i++)
1421                                 if (strncmp((const char *)&regs[1],
1422                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1423                                         vm_guest = vm_cpuids[i].vm_guest;
1424                                         break;
1425                                 }
1426
1427                         /*
1428                          * If this is the first entry or we found a
1429                          * specific hypervisor, record the base, high value,
1430                          * and vendor identifier.
1431                          */
1432                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1433                                 hv_base = leaf;
1434                                 hv_high = regs[0];
1435                                 ((u_int *)&hv_vendor)[0] = regs[1];
1436                                 ((u_int *)&hv_vendor)[1] = regs[2];
1437                                 ((u_int *)&hv_vendor)[2] = regs[3];
1438                                 hv_vendor[12] = '\0';
1439
1440                                 /*
1441                                  * If we found a specific hypervisor, then
1442                                  * we are finished.
1443                                  */
1444                                 if (vm_guest != VM_GUEST_VM)
1445                                         return;
1446                         }
1447                 }
1448         }
1449 }
1450
1451 void
1452 identify_hypervisor(void)
1453 {
1454         u_int regs[4];
1455         char *p;
1456         int i;
1457
1458         /*
1459          * If CPUID2_HV is set, we are running in a hypervisor environment.
1460          */
1461         if (cpu_feature2 & CPUID2_HV) {
1462                 vm_guest = VM_GUEST_VM;
1463                 identify_hypervisor_cpuid_base();
1464
1465                 /* If we have a definitive vendor, we can return now. */
1466                 if (*hv_vendor != '\0')
1467                         return;
1468         }
1469
1470         /*
1471          * Examine SMBIOS strings for older hypervisors.
1472          */
1473         p = kern_getenv("smbios.system.serial");
1474         if (p != NULL) {
1475                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1476                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1477                         if (regs[1] == VMW_HVMAGIC) {
1478                                 vm_guest = VM_GUEST_VMWARE;
1479                                 freeenv(p);
1480                                 return;
1481                         }
1482                 }
1483                 freeenv(p);
1484         }
1485
1486         /*
1487          * XXX: Some of these entries may not be needed since they were
1488          * added to FreeBSD before the checks above.
1489          */
1490         p = kern_getenv("smbios.bios.vendor");
1491         if (p != NULL) {
1492                 for (i = 0; i < nitems(vm_bnames); i++)
1493                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1494                                 vm_guest = vm_bnames[i].vm_guest;
1495                                 /* If we have a specific match, return */
1496                                 if (vm_guest != VM_GUEST_VM) {
1497                                         freeenv(p);
1498                                         return;
1499                                 }
1500                                 /*
1501                                  * We are done with bnames, but there might be
1502                                  * a more specific match in the pnames
1503                                  */
1504                                 break;
1505                         }
1506                 freeenv(p);
1507         }
1508         p = kern_getenv("smbios.system.product");
1509         if (p != NULL) {
1510                 for (i = 0; i < nitems(vm_pnames); i++)
1511                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1512                                 vm_guest = vm_pnames[i].vm_guest;
1513                                 freeenv(p);
1514                                 return;
1515                         }
1516                 freeenv(p);
1517         }
1518 }
1519
1520 bool
1521 fix_cpuid(void)
1522 {
1523         uint64_t msr;
1524
1525         /*
1526          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1527          * get the largest standard CPUID function number again if it is set
1528          * from BIOS.  It is necessary for probing correct CPU topology later
1529          * and for the correct operation of the AVX-aware userspace.
1530          */
1531         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1532             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1533             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1534             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1535             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1536                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1537                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1538                         msr &= ~IA32_MISC_EN_LIMCPUID;
1539                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1540                         return (true);
1541                 }
1542         }
1543
1544         /*
1545          * Re-enable AMD Topology Extension that could be disabled by BIOS
1546          * on some notebook processors.  Without the extension it's really
1547          * hard to determine the correct CPU cache topology.
1548          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1549          * Models 60h-6Fh Processors, Publication # 50742.
1550          */
1551         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1552             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1553                 msr = rdmsr(MSR_EXTFEATURES);
1554                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1555                         msr |= (uint64_t)1 << 54;
1556                         wrmsr(MSR_EXTFEATURES, msr);
1557                         return (true);
1558                 }
1559         }
1560         return (false);
1561 }
1562
1563 void
1564 identify_cpu1(void)
1565 {
1566         u_int regs[4];
1567
1568         do_cpuid(0, regs);
1569         cpu_high = regs[0];
1570         ((u_int *)&cpu_vendor)[0] = regs[1];
1571         ((u_int *)&cpu_vendor)[1] = regs[3];
1572         ((u_int *)&cpu_vendor)[2] = regs[2];
1573         cpu_vendor[12] = '\0';
1574
1575         do_cpuid(1, regs);
1576         cpu_id = regs[0];
1577         cpu_procinfo = regs[1];
1578         cpu_feature = regs[3];
1579         cpu_feature2 = regs[2];
1580 }
1581
1582 void
1583 identify_cpu2(void)
1584 {
1585         u_int regs[4], cpu_stdext_disable;
1586
1587         if (cpu_high >= 6) {
1588                 cpuid_count(6, 0, regs);
1589                 cpu_power_eax = regs[0];
1590                 cpu_power_ebx = regs[1];
1591                 cpu_power_ecx = regs[2];
1592                 cpu_power_edx = regs[3];
1593         }
1594
1595         if (cpu_high >= 7) {
1596                 cpuid_count(7, 0, regs);
1597                 cpu_stdext_feature = regs[1];
1598
1599                 /*
1600                  * Some hypervisors failed to filter out unsupported
1601                  * extended features.  Allow to disable the
1602                  * extensions, activation of which requires setting a
1603                  * bit in CR4, and which VM monitors do not support.
1604                  */
1605                 cpu_stdext_disable = 0;
1606                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1607                 cpu_stdext_feature &= ~cpu_stdext_disable;
1608
1609                 cpu_stdext_feature2 = regs[2];
1610                 cpu_stdext_feature3 = regs[3];
1611
1612                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1613                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1614         }
1615 }
1616
1617 void
1618 identify_cpu_fixup_bsp(void)
1619 {
1620         u_int regs[4];
1621
1622         cpu_vendor_id = find_cpu_vendor_id();
1623
1624         if (fix_cpuid()) {
1625                 do_cpuid(0, regs);
1626                 cpu_high = regs[0];
1627         }
1628 }
1629
1630 /*
1631  * Final stage of CPU identification.
1632  */
1633 void
1634 finishidentcpu(void)
1635 {
1636         u_int regs[4];
1637 #ifdef __i386__
1638         u_char ccr3;
1639 #endif
1640
1641         identify_cpu_fixup_bsp();
1642
1643         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1644                 do_cpuid(5, regs);
1645                 cpu_mon_mwait_flags = regs[2];
1646                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1647                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1648         }
1649
1650         identify_cpu2();
1651
1652 #ifdef __i386__
1653         if (cpu_high > 0 &&
1654             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1655              cpu_vendor_id == CPU_VENDOR_AMD ||
1656              cpu_vendor_id == CPU_VENDOR_HYGON ||
1657              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1658              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1659              cpu_vendor_id == CPU_VENDOR_NSC)) {
1660                 do_cpuid(0x80000000, regs);
1661                 if (regs[0] >= 0x80000000)
1662                         cpu_exthigh = regs[0];
1663         }
1664 #else
1665         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1666             cpu_vendor_id == CPU_VENDOR_AMD ||
1667             cpu_vendor_id == CPU_VENDOR_HYGON ||
1668             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1669                 do_cpuid(0x80000000, regs);
1670                 cpu_exthigh = regs[0];
1671         }
1672 #endif
1673         if (cpu_exthigh >= 0x80000001) {
1674                 do_cpuid(0x80000001, regs);
1675                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1676                 amd_feature2 = regs[2];
1677         }
1678         if (cpu_exthigh >= 0x80000007) {
1679                 do_cpuid(0x80000007, regs);
1680                 amd_rascap = regs[1];
1681                 amd_pminfo = regs[3];
1682         }
1683         if (cpu_exthigh >= 0x80000008) {
1684                 do_cpuid(0x80000008, regs);
1685                 cpu_maxphyaddr = regs[0] & 0xff;
1686                 amd_extended_feature_extensions = regs[1];
1687                 cpu_procinfo2 = regs[2];
1688         } else {
1689                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1690         }
1691
1692 #ifdef __i386__
1693         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1694                 if (cpu == CPU_486) {
1695                         /*
1696                          * These conditions are equivalent to:
1697                          *     - CPU does not support cpuid instruction.
1698                          *     - Cyrix/IBM CPU is detected.
1699                          */
1700                         if (identblue() == IDENTBLUE_IBMCPU) {
1701                                 strcpy(cpu_vendor, "IBM");
1702                                 cpu_vendor_id = CPU_VENDOR_IBM;
1703                                 cpu = CPU_BLUE;
1704                                 return;
1705                         }
1706                 }
1707                 switch (cpu_id & 0xf00) {
1708                 case 0x600:
1709                         /*
1710                          * Cyrix's datasheet does not describe DIRs.
1711                          * Therefor, I assume it does not have them
1712                          * and use the result of the cpuid instruction.
1713                          * XXX they seem to have it for now at least. -Peter
1714                          */
1715                         identifycyrix();
1716                         cpu = CPU_M2;
1717                         break;
1718                 default:
1719                         identifycyrix();
1720                         /*
1721                          * This routine contains a trick.
1722                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1723                          */
1724                         switch (cyrix_did & 0x00f0) {
1725                         case 0x00:
1726                         case 0xf0:
1727                                 cpu = CPU_486DLC;
1728                                 break;
1729                         case 0x10:
1730                                 cpu = CPU_CY486DX;
1731                                 break;
1732                         case 0x20:
1733                                 if ((cyrix_did & 0x000f) < 8)
1734                                         cpu = CPU_M1;
1735                                 else
1736                                         cpu = CPU_M1SC;
1737                                 break;
1738                         case 0x30:
1739                                 cpu = CPU_M1;
1740                                 break;
1741                         case 0x40:
1742                                 /* MediaGX CPU */
1743                                 cpu = CPU_M1SC;
1744                                 break;
1745                         default:
1746                                 /* M2 and later CPUs are treated as M2. */
1747                                 cpu = CPU_M2;
1748
1749                                 /*
1750                                  * enable cpuid instruction.
1751                                  */
1752                                 ccr3 = read_cyrix_reg(CCR3);
1753                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1754                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1755                                 write_cyrix_reg(CCR3, ccr3);
1756
1757                                 do_cpuid(0, regs);
1758                                 cpu_high = regs[0];     /* eax */
1759                                 do_cpuid(1, regs);
1760                                 cpu_id = regs[0];       /* eax */
1761                                 cpu_feature = regs[3];  /* edx */
1762                                 break;
1763                         }
1764                 }
1765         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1766                 /*
1767                  * There are BlueLightning CPUs that do not change
1768                  * undefined flags by dividing 5 by 2.  In this case,
1769                  * the CPU identification routine in locore.s leaves
1770                  * cpu_vendor null string and puts CPU_486 into the
1771                  * cpu.
1772                  */
1773                 if (identblue() == IDENTBLUE_IBMCPU) {
1774                         strcpy(cpu_vendor, "IBM");
1775                         cpu_vendor_id = CPU_VENDOR_IBM;
1776                         cpu = CPU_BLUE;
1777                         return;
1778                 }
1779         }
1780 #endif
1781 }
1782
1783 int
1784 pti_get_default(void)
1785 {
1786
1787         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1788             strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1789                 return (0);
1790         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1791                 return (0);
1792         return (1);
1793 }
1794
1795 static u_int
1796 find_cpu_vendor_id(void)
1797 {
1798         int     i;
1799
1800         for (i = 0; i < nitems(cpu_vendors); i++)
1801                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1802                         return (cpu_vendors[i].vendor_id);
1803         return (0);
1804 }
1805
1806 static void
1807 print_AMD_assoc(int i)
1808 {
1809         if (i == 255)
1810                 printf(", fully associative\n");
1811         else
1812                 printf(", %d-way associative\n", i);
1813 }
1814
1815 static void
1816 print_AMD_l2_assoc(int i)
1817 {
1818         switch (i & 0x0f) {
1819         case 0: printf(", disabled/not present\n"); break;
1820         case 1: printf(", direct mapped\n"); break;
1821         case 2: printf(", 2-way associative\n"); break;
1822         case 4: printf(", 4-way associative\n"); break;
1823         case 6: printf(", 8-way associative\n"); break;
1824         case 8: printf(", 16-way associative\n"); break;
1825         case 15: printf(", fully associative\n"); break;
1826         default: printf(", reserved configuration\n"); break;
1827         }
1828 }
1829
1830 static void
1831 print_AMD_info(void)
1832 {
1833 #ifdef __i386__
1834         uint64_t amd_whcr;
1835 #endif
1836         u_int regs[4];
1837
1838         if (cpu_exthigh >= 0x80000005) {
1839                 do_cpuid(0x80000005, regs);
1840                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1841                 print_AMD_assoc(regs[0] >> 24);
1842
1843                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1844                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1845
1846                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1847                 print_AMD_assoc(regs[1] >> 24);
1848
1849                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1850                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1851
1852                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1853                 printf(", %d bytes/line", regs[2] & 0xff);
1854                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1855                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1856
1857                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1858                 printf(", %d bytes/line", regs[3] & 0xff);
1859                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1860                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1861         }
1862
1863         if (cpu_exthigh >= 0x80000006) {
1864                 do_cpuid(0x80000006, regs);
1865                 if ((regs[0] >> 16) != 0) {
1866                         printf("L2 2MB data TLB: %d entries",
1867                             (regs[0] >> 16) & 0xfff);
1868                         print_AMD_l2_assoc(regs[0] >> 28);
1869                         printf("L2 2MB instruction TLB: %d entries",
1870                             regs[0] & 0xfff);
1871                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1872                 } else {
1873                         printf("L2 2MB unified TLB: %d entries",
1874                             regs[0] & 0xfff);
1875                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1876                 }
1877                 if ((regs[1] >> 16) != 0) {
1878                         printf("L2 4KB data TLB: %d entries",
1879                             (regs[1] >> 16) & 0xfff);
1880                         print_AMD_l2_assoc(regs[1] >> 28);
1881
1882                         printf("L2 4KB instruction TLB: %d entries",
1883                             (regs[1] >> 16) & 0xfff);
1884                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1885                 } else {
1886                         printf("L2 4KB unified TLB: %d entries",
1887                             (regs[1] >> 16) & 0xfff);
1888                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1889                 }
1890                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1891                 printf(", %d bytes/line", regs[2] & 0xff);
1892                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1893                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1894         }
1895
1896 #ifdef __i386__
1897         if (((cpu_id & 0xf00) == 0x500)
1898             && (((cpu_id & 0x0f0) > 0x80)
1899                 || (((cpu_id & 0x0f0) == 0x80)
1900                     && (cpu_id & 0x00f) > 0x07))) {
1901                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1902                 amd_whcr = rdmsr(0xc0000082);
1903                 if (!(amd_whcr & (0x3ff << 22))) {
1904                         printf("Write Allocate Disable\n");
1905                 } else {
1906                         printf("Write Allocate Enable Limit: %dM bytes\n",
1907                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1908                         printf("Write Allocate 15-16M bytes: %s\n",
1909                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1910                 }
1911         } else if (((cpu_id & 0xf00) == 0x500)
1912                    && ((cpu_id & 0x0f0) > 0x50)) {
1913                 /* K6, K6-2(old core) */
1914                 amd_whcr = rdmsr(0xc0000082);
1915                 if (!(amd_whcr & (0x7f << 1))) {
1916                         printf("Write Allocate Disable\n");
1917                 } else {
1918                         printf("Write Allocate Enable Limit: %dM bytes\n",
1919                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1920                         printf("Write Allocate 15-16M bytes: %s\n",
1921                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1922                         printf("Hardware Write Allocate Control: %s\n",
1923                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1924                 }
1925         }
1926 #endif
1927         /*
1928          * Opteron Rev E shows a bug as in very rare occasions a read memory
1929          * barrier is not performed as expected if it is followed by a
1930          * non-atomic read-modify-write instruction.
1931          * As long as that bug pops up very rarely (intensive machine usage
1932          * on other operating systems generally generates one unexplainable
1933          * crash any 2 months) and as long as a model specific fix would be
1934          * impractical at this stage, print out a warning string if the broken
1935          * model and family are identified.
1936          */
1937         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1938             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1939                 printf("WARNING: This architecture revision has known SMP "
1940                     "hardware bugs which may cause random instability\n");
1941 }
1942
1943 static void
1944 print_INTEL_info(void)
1945 {
1946         u_int regs[4];
1947         u_int rounds, regnum;
1948         u_int nwaycode, nway;
1949
1950         if (cpu_high >= 2) {
1951                 rounds = 0;
1952                 do {
1953                         do_cpuid(0x2, regs);
1954                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1955                                 break;  /* we have a buggy CPU */
1956
1957                         for (regnum = 0; regnum <= 3; ++regnum) {
1958                                 if (regs[regnum] & (1<<31))
1959                                         continue;
1960                                 if (regnum != 0)
1961                                         print_INTEL_TLB(regs[regnum] & 0xff);
1962                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1963                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1964                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1965                         }
1966                 } while (--rounds > 0);
1967         }
1968
1969         if (cpu_exthigh >= 0x80000006) {
1970                 do_cpuid(0x80000006, regs);
1971                 nwaycode = (regs[2] >> 12) & 0x0f;
1972                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1973                         nway = 1 << (nwaycode / 2);
1974                 else
1975                         nway = 0;
1976                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1977                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1978         }
1979 }
1980
1981 static void
1982 print_INTEL_TLB(u_int data)
1983 {
1984         switch (data) {
1985         case 0x0:
1986         case 0x40:
1987         default:
1988                 break;
1989         case 0x1:
1990                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1991                 break;
1992         case 0x2:
1993                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1994                 break;
1995         case 0x3:
1996                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1997                 break;
1998         case 0x4:
1999                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
2000                 break;
2001         case 0x6:
2002                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2003                 break;
2004         case 0x8:
2005                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2006                 break;
2007         case 0x9:
2008                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2009                 break;
2010         case 0xa:
2011                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2012                 break;
2013         case 0xb:
2014                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2015                 break;
2016         case 0xc:
2017                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2018                 break;
2019         case 0xd:
2020                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2021                 break;
2022         case 0xe:
2023                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2024                 break;
2025         case 0x1d:
2026                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2027                 break;
2028         case 0x21:
2029                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2030                 break;
2031         case 0x22:
2032                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2033                 break;
2034         case 0x23:
2035                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2036                 break;
2037         case 0x24:
2038                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2039                 break;
2040         case 0x25:
2041                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2042                 break;
2043         case 0x29:
2044                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2045                 break;
2046         case 0x2c:
2047                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2048                 break;
2049         case 0x30:
2050                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2051                 break;
2052         case 0x39: /* De-listed in SDM rev. 54 */
2053                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2054                 break;
2055         case 0x3b: /* De-listed in SDM rev. 54 */
2056                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2057                 break;
2058         case 0x3c: /* De-listed in SDM rev. 54 */
2059                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2060                 break;
2061         case 0x41:
2062                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2063                 break;
2064         case 0x42:
2065                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2066                 break;
2067         case 0x43:
2068                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2069                 break;
2070         case 0x44:
2071                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2072                 break;
2073         case 0x45:
2074                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2075                 break;
2076         case 0x46:
2077                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2078                 break;
2079         case 0x47:
2080                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2081                 break;
2082         case 0x48:
2083                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2084                 break;
2085         case 0x49:
2086                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2087                     CPUID_TO_MODEL(cpu_id) == 0x6)
2088                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2089                 else
2090                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2091                 break;
2092         case 0x4a:
2093                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2094                 break;
2095         case 0x4b:
2096                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2097                 break;
2098         case 0x4c:
2099                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2100                 break;
2101         case 0x4d:
2102                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2103                 break;
2104         case 0x4e:
2105                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2106                 break;
2107         case 0x4f:
2108                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2109                 break;
2110         case 0x50:
2111                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2112                 break;
2113         case 0x51:
2114                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2115                 break;
2116         case 0x52:
2117                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2118                 break;
2119         case 0x55:
2120                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2121                 break;
2122         case 0x56:
2123                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2124                 break;
2125         case 0x57:
2126                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2127                 break;
2128         case 0x59:
2129                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2130                 break;
2131         case 0x5a:
2132                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2133                 break;
2134         case 0x5b:
2135                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2136                 break;
2137         case 0x5c:
2138                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2139                 break;
2140         case 0x5d:
2141                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2142                 break;
2143         case 0x60:
2144                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2145                 break;
2146         case 0x61:
2147                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2148                 break;
2149         case 0x63:
2150                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2151                 break;
2152         case 0x64:
2153                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2154                 break;
2155         case 0x66:
2156                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2157                 break;
2158         case 0x67:
2159                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2160                 break;
2161         case 0x68:
2162                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2163                 break;
2164         case 0x6a:
2165                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2166                 break;
2167         case 0x6b:
2168                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2169                 break;
2170         case 0x6c:
2171                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2172                 break;
2173         case 0x6d:
2174                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2175                 break;
2176         case 0x70:
2177                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2178                 break;
2179         case 0x71:
2180                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2181                 break;
2182         case 0x72:
2183                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2184                 break;
2185         case 0x76:
2186                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2187                 break;
2188         case 0x78:
2189                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2190                 break;
2191         case 0x79:
2192                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2193                 break;
2194         case 0x7a:
2195                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2196                 break;
2197         case 0x7b:
2198                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2199                 break;
2200         case 0x7c:
2201                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2202                 break;
2203         case 0x7d:
2204                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2205                 break;
2206         case 0x7f:
2207                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2208                 break;
2209         case 0x80:
2210                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2211                 break;
2212         case 0x82:
2213                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2214                 break;
2215         case 0x83:
2216                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2217                 break;
2218         case 0x84:
2219                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2220                 break;
2221         case 0x85:
2222                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2223                 break;
2224         case 0x86:
2225                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2226                 break;
2227         case 0x87:
2228                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2229                 break;
2230         case 0xa0:
2231                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2232                 break;
2233         case 0xb0:
2234                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2235                 break;
2236         case 0xb1:
2237                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2238                 break;
2239         case 0xb2:
2240                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2241                 break;
2242         case 0xb3:
2243                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2244                 break;
2245         case 0xb4:
2246                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2247                 break;
2248         case 0xb5:
2249                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2250                 break;
2251         case 0xb6:
2252                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2253                 break;
2254         case 0xba:
2255                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2256                 break;
2257         case 0xc0:
2258                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2259                 break;
2260         case 0xc1:
2261                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2262                 break;
2263         case 0xc2:
2264                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2265                 break;
2266         case 0xc3:
2267                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2268                 break;
2269         case 0xc4:
2270                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2271                 break;
2272         case 0xca:
2273                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2274                 break;
2275         case 0xd0:
2276                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2277                 break;
2278         case 0xd1:
2279                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2280                 break;
2281         case 0xd2:
2282                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2283                 break;
2284         case 0xd6:
2285                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2286                 break;
2287         case 0xd7:
2288                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2289                 break;
2290         case 0xd8:
2291                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2292                 break;
2293         case 0xdc:
2294                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2295                 break;
2296         case 0xdd:
2297                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2298                 break;
2299         case 0xde:
2300                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2301                 break;
2302         case 0xe2:
2303                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2304                 break;
2305         case 0xe3:
2306                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2307                 break;
2308         case 0xe4:
2309                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2310                 break;
2311         case 0xea:
2312                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2313                 break;
2314         case 0xeb:
2315                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2316                 break;
2317         case 0xec:
2318                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2319                 break;
2320         case 0xf0:
2321                 printf("64-Byte prefetching\n");
2322                 break;
2323         case 0xf1:
2324                 printf("128-Byte prefetching\n");
2325                 break;
2326         }
2327 }
2328
2329 static void
2330 print_svm_info(void)
2331 {
2332         u_int features, regs[4];
2333         uint64_t msr;
2334         int comma;
2335
2336         printf("\n  SVM: ");
2337         do_cpuid(0x8000000A, regs);
2338         features = regs[3];
2339
2340         msr = rdmsr(MSR_VM_CR);
2341         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2342                 printf("(disabled in BIOS) ");
2343
2344         if (!bootverbose) {
2345                 comma = 0;
2346                 if (features & (1 << 0)) {
2347                         printf("%sNP", comma ? "," : "");
2348                         comma = 1;
2349                 }
2350                 if (features & (1 << 3)) {
2351                         printf("%sNRIP", comma ? "," : "");
2352                         comma = 1;
2353                 }
2354                 if (features & (1 << 5)) {
2355                         printf("%sVClean", comma ? "," : "");
2356                         comma = 1;
2357                 }
2358                 if (features & (1 << 6)) {
2359                         printf("%sAFlush", comma ? "," : "");
2360                         comma = 1;
2361                 }
2362                 if (features & (1 << 7)) {
2363                         printf("%sDAssist", comma ? "," : "");
2364                         comma = 1;
2365                 }
2366                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2367                 return;
2368         }
2369
2370         printf("Features=0x%b", features,
2371                "\020"
2372                "\001NP"                 /* Nested paging */
2373                "\002LbrVirt"            /* LBR virtualization */
2374                "\003SVML"               /* SVM lock */
2375                "\004NRIPS"              /* NRIP save */
2376                "\005TscRateMsr"         /* MSR based TSC rate control */
2377                "\006VmcbClean"          /* VMCB clean bits */
2378                "\007FlushByAsid"        /* Flush by ASID */
2379                "\010DecodeAssist"       /* Decode assist */
2380                "\011<b8>"
2381                "\012<b9>"
2382                "\013PauseFilter"        /* PAUSE intercept filter */
2383                "\014EncryptedMcodePatch"
2384                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2385                "\016AVIC"               /* virtual interrupt controller */
2386                "\017<b14>"
2387                "\020V_VMSAVE_VMLOAD"
2388                "\021vGIF"
2389                "\022GMET"               /* Guest Mode Execute Trap */
2390                "\023<b18>"
2391                "\024<b19>"
2392                "\025GuesSpecCtl"        /* Guest Spec_ctl */
2393                "\026<b21>"
2394                "\027<b22>"
2395                "\030<b23>"
2396                "\031<b24>"
2397                "\032<b25>"
2398                "\033<b26>"
2399                "\034<b27>"
2400                "\035<b28>"
2401                "\036<b29>"
2402                "\037<b30>"
2403                "\040<b31>"
2404                );
2405         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2406 }
2407
2408 #ifdef __i386__
2409 static void
2410 print_transmeta_info(void)
2411 {
2412         u_int regs[4], nreg = 0;
2413
2414         do_cpuid(0x80860000, regs);
2415         nreg = regs[0];
2416         if (nreg >= 0x80860001) {
2417                 do_cpuid(0x80860001, regs);
2418                 printf("  Processor revision %u.%u.%u.%u\n",
2419                        (regs[1] >> 24) & 0xff,
2420                        (regs[1] >> 16) & 0xff,
2421                        (regs[1] >> 8) & 0xff,
2422                        regs[1] & 0xff);
2423         }
2424         if (nreg >= 0x80860002) {
2425                 do_cpuid(0x80860002, regs);
2426                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2427                        (regs[1] >> 24) & 0xff,
2428                        (regs[1] >> 16) & 0xff,
2429                        (regs[1] >> 8) & 0xff,
2430                        regs[1] & 0xff,
2431                        regs[2]);
2432         }
2433         if (nreg >= 0x80860006) {
2434                 char info[65];
2435                 do_cpuid(0x80860003, (u_int*) &info[0]);
2436                 do_cpuid(0x80860004, (u_int*) &info[16]);
2437                 do_cpuid(0x80860005, (u_int*) &info[32]);
2438                 do_cpuid(0x80860006, (u_int*) &info[48]);
2439                 info[64] = 0;
2440                 printf("  %s\n", info);
2441         }
2442 }
2443 #endif
2444
2445 static void
2446 print_via_padlock_info(void)
2447 {
2448         u_int regs[4];
2449
2450         do_cpuid(0xc0000001, regs);
2451         printf("\n  VIA Padlock Features=0x%b", regs[3],
2452         "\020"
2453         "\003RNG"               /* RNG */
2454         "\007AES"               /* ACE */
2455         "\011AES-CTR"           /* ACE2 */
2456         "\013SHA1,SHA256"       /* PHE */
2457         "\015RSA"               /* PMM */
2458         );
2459 }
2460
2461 static uint32_t
2462 vmx_settable(uint64_t basic, int msr, int true_msr)
2463 {
2464         uint64_t val;
2465
2466         if (basic & (1ULL << 55))
2467                 val = rdmsr(true_msr);
2468         else
2469                 val = rdmsr(msr);
2470
2471         /* Just report the controls that can be set to 1. */
2472         return (val >> 32);
2473 }
2474
2475 static void
2476 print_vmx_info(void)
2477 {
2478         uint64_t basic, msr;
2479         uint32_t entry, exit, mask, pin, proc, proc2;
2480         int comma;
2481
2482         printf("\n  VT-x: ");
2483         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2484         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2485                 printf("(disabled in BIOS) ");
2486         basic = rdmsr(MSR_VMX_BASIC);
2487         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2488             MSR_VMX_TRUE_PINBASED_CTLS);
2489         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2490             MSR_VMX_TRUE_PROCBASED_CTLS);
2491         if (proc & PROCBASED_SECONDARY_CONTROLS)
2492                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2493                     MSR_VMX_PROCBASED_CTLS2);
2494         else
2495                 proc2 = 0;
2496         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2497         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2498
2499         if (!bootverbose) {
2500                 comma = 0;
2501                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2502                     entry & VM_ENTRY_LOAD_PAT) {
2503                         printf("%sPAT", comma ? "," : "");
2504                         comma = 1;
2505                 }
2506                 if (proc & PROCBASED_HLT_EXITING) {
2507                         printf("%sHLT", comma ? "," : "");
2508                         comma = 1;
2509                 }
2510                 if (proc & PROCBASED_MTF) {
2511                         printf("%sMTF", comma ? "," : "");
2512                         comma = 1;
2513                 }
2514                 if (proc & PROCBASED_PAUSE_EXITING) {
2515                         printf("%sPAUSE", comma ? "," : "");
2516                         comma = 1;
2517                 }
2518                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2519                         printf("%sEPT", comma ? "," : "");
2520                         comma = 1;
2521                 }
2522                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2523                         printf("%sUG", comma ? "," : "");
2524                         comma = 1;
2525                 }
2526                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2527                         printf("%sVPID", comma ? "," : "");
2528                         comma = 1;
2529                 }
2530                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2531                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2532                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2533                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2534                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2535                         printf("%sVID", comma ? "," : "");
2536                         comma = 1;
2537                         if (pin & PINBASED_POSTED_INTERRUPT)
2538                                 printf(",PostIntr");
2539                 }
2540                 return;
2541         }
2542
2543         mask = basic >> 32;
2544         printf("Basic Features=0x%b", mask,
2545         "\020"
2546         "\02132PA"              /* 32-bit physical addresses */
2547         "\022SMM"               /* SMM dual-monitor */
2548         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2549         "\030TRUE"              /* TRUE_CTLS MSRs */
2550         );
2551         printf("\n        Pin-Based Controls=0x%b", pin,
2552         "\020"
2553         "\001ExtINT"            /* External-interrupt exiting */
2554         "\004NMI"               /* NMI exiting */
2555         "\006VNMI"              /* Virtual NMIs */
2556         "\007PreTmr"            /* Activate VMX-preemption timer */
2557         "\010PostIntr"          /* Process posted interrupts */
2558         );
2559         printf("\n        Primary Processor Controls=0x%b", proc,
2560         "\020"
2561         "\003INTWIN"            /* Interrupt-window exiting */
2562         "\004TSCOff"            /* Use TSC offsetting */
2563         "\010HLT"               /* HLT exiting */
2564         "\012INVLPG"            /* INVLPG exiting */
2565         "\013MWAIT"             /* MWAIT exiting */
2566         "\014RDPMC"             /* RDPMC exiting */
2567         "\015RDTSC"             /* RDTSC exiting */
2568         "\020CR3-LD"            /* CR3-load exiting */
2569         "\021CR3-ST"            /* CR3-store exiting */
2570         "\024CR8-LD"            /* CR8-load exiting */
2571         "\025CR8-ST"            /* CR8-store exiting */
2572         "\026TPR"               /* Use TPR shadow */
2573         "\027NMIWIN"            /* NMI-window exiting */
2574         "\030MOV-DR"            /* MOV-DR exiting */
2575         "\031IO"                /* Unconditional I/O exiting */
2576         "\032IOmap"             /* Use I/O bitmaps */
2577         "\034MTF"               /* Monitor trap flag */
2578         "\035MSRmap"            /* Use MSR bitmaps */
2579         "\036MONITOR"           /* MONITOR exiting */
2580         "\037PAUSE"             /* PAUSE exiting */
2581         );
2582         if (proc & PROCBASED_SECONDARY_CONTROLS)
2583                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2584                 "\020"
2585                 "\001APIC"              /* Virtualize APIC accesses */
2586                 "\002EPT"               /* Enable EPT */
2587                 "\003DT"                /* Descriptor-table exiting */
2588                 "\004RDTSCP"            /* Enable RDTSCP */
2589                 "\005x2APIC"            /* Virtualize x2APIC mode */
2590                 "\006VPID"              /* Enable VPID */
2591                 "\007WBINVD"            /* WBINVD exiting */
2592                 "\010UG"                /* Unrestricted guest */
2593                 "\011APIC-reg"          /* APIC-register virtualization */
2594                 "\012VID"               /* Virtual-interrupt delivery */
2595                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2596                 "\014RDRAND"            /* RDRAND exiting */
2597                 "\015INVPCID"           /* Enable INVPCID */
2598                 "\016VMFUNC"            /* Enable VM functions */
2599                 "\017VMCS"              /* VMCS shadowing */
2600                 "\020EPT#VE"            /* EPT-violation #VE */
2601                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2602                 );
2603         printf("\n        Exit Controls=0x%b", mask,
2604         "\020"
2605         "\003DR"                /* Save debug controls */
2606                                 /* Ignore Host address-space size */
2607         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2608         "\020AckInt"            /* Acknowledge interrupt on exit */
2609         "\023PAT-SV"            /* Save MSR_PAT */
2610         "\024PAT-LD"            /* Load MSR_PAT */
2611         "\025EFER-SV"           /* Save MSR_EFER */
2612         "\026EFER-LD"           /* Load MSR_EFER */
2613         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2614         );
2615         printf("\n        Entry Controls=0x%b", mask,
2616         "\020"
2617         "\003DR"                /* Save debug controls */
2618                                 /* Ignore IA-32e mode guest */
2619                                 /* Ignore Entry to SMM */
2620                                 /* Ignore Deactivate dual-monitor treatment */
2621         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2622         "\017PAT"               /* Load MSR_PAT */
2623         "\020EFER"              /* Load MSR_EFER */
2624         );
2625         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2626             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2627                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2628                 mask = msr;
2629                 printf("\n        EPT Features=0x%b", mask,
2630                 "\020"
2631                 "\001XO"                /* Execute-only translations */
2632                 "\007PW4"               /* Page-walk length of 4 */
2633                 "\011UC"                /* EPT paging-structure mem can be UC */
2634                 "\017WB"                /* EPT paging-structure mem can be WB */
2635                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2636                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2637                 "\025INVEPT"            /* INVEPT is supported */
2638                 "\026AD"                /* Accessed and dirty flags for EPT */
2639                 "\032single"            /* INVEPT single-context type */
2640                 "\033all"               /* INVEPT all-context type */
2641                 );
2642                 mask = msr >> 32;
2643                 printf("\n        VPID Features=0x%b", mask,
2644                 "\020"
2645                 "\001INVVPID"           /* INVVPID is supported */
2646                 "\011individual"        /* INVVPID individual-address type */
2647                 "\012single"            /* INVVPID single-context type */
2648                 "\013all"               /* INVVPID all-context type */
2649                  /* INVVPID single-context-retaining-globals type */
2650                 "\014single-globals"
2651                 );
2652         }
2653 }
2654
2655 static void
2656 print_hypervisor_info(void)
2657 {
2658
2659         if (*hv_vendor != '\0')
2660                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2661 }
2662
2663 /*
2664  * Returns the maximum physical address that can be used with the
2665  * current system.
2666  */
2667 vm_paddr_t
2668 cpu_getmaxphyaddr(void)
2669 {
2670
2671 #if defined(__i386__)
2672         if (!pae_mode)
2673                 return (0xffffffff);
2674 #endif
2675         return ((1ULL << cpu_maxphyaddr) - 1);
2676 }