sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 122 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %ebx */
 123 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %ecx */
 124 u_int   cpu_power_edx;          /* 06H: Power management leaf, %edx */
 125 char machine[] = MACHINE;
 126
 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 128     &via_feature_rng, 0,
 129     "VIA RNG feature available in CPU");
 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 131     &via_feature_xcrypt, 0,
 132     "VIA xcrypt feature available in CPU");
 133
 134 #ifdef __amd64__
 135 #ifdef SCTL_MASK32
 136 extern int adaptive_machine_arch;
 137 #endif
 138
 139 static int
 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 141 {
 142 #ifdef SCTL_MASK32
 143         static const char machine32[] = "i386";
 144 #endif
 145         int error;
 146
 147 #ifdef SCTL_MASK32
 148         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 149                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 150         else
 151 #endif
 152                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 153         return (error);
 154
 155 }
 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 157     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 158 #else
 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 160     machine, 0, "Machine class");
 161 #endif
 162
 163 static char cpu_model[128];
 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 165     cpu_model, 0, "Machine model");
 166
 167 static int hw_clockrate;
 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 169     &hw_clockrate, 0, "CPU instruction clock rate");
 170
 171 u_int hv_base;
 172 u_int hv_high;
 173 char hv_vendor[16];
 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 175     0, "Hypervisor vendor");
 176
 177 static eventhandler_tag tsc_post_tag;
 178
 179 static char cpu_brand[48];
 180
 181 #ifdef __i386__
 182 #define MAX_BRAND_INDEX 8
 183
 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 185         NULL,                   /* No brand */
 186         "Intel Celeron",
 187         "Intel Pentium III",
 188         "Intel Pentium III Xeon",
 189         NULL,
 190         NULL,
 191         NULL,
 192         NULL,
 193         "Intel Pentium 4"
 194 };
 195
 196 static struct {
 197         char    *cpu_name;
 198         int     cpu_class;
 199 } cpus[] = {
 200         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 201         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 202         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 203         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 204         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 205         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 206         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 207         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 208         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 209         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 210         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 211         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 212         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 213         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 214         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 215         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 216         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 217 };
 218 #endif
 219
 220 static struct {
 221         char    *vendor;
 222         u_int   vendor_id;
 223 } cpu_vendors[] = {
 224         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 225         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 226         { HYGON_VENDOR_ID,      CPU_VENDOR_HYGON },     /* HygonGenuine*/
 227         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 228 #ifdef __i386__
 229         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 230         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 231         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 232         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 233         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 234         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 235         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 236 #if 0
 237         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 238         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 239 #endif
 240 #endif
 241 };
 242
 243 void
 244 printcpuinfo(void)
 245 {
 246         u_int regs[4], i;
 247         char *brand;
 248
 249         printf("CPU: ");
 250 #ifdef __i386__
 251         cpu_class = cpus[cpu].cpu_class;
 252         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 253 #else
 254         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 255 #endif
 256
 257         /* Check for extended CPUID information and a processor name. */
 258         if (cpu_exthigh >= 0x80000004) {
 259                 brand = cpu_brand;
 260                 for (i = 0x80000002; i < 0x80000005; i++) {
 261                         do_cpuid(i, regs);
 262                         memcpy(brand, regs, sizeof(regs));
 263                         brand += sizeof(regs);
 264                 }
 265         }
 266
 267         switch (cpu_vendor_id) {
 268         case CPU_VENDOR_INTEL:
 269 #ifdef __i386__
 270                 if ((cpu_id & 0xf00) > 0x300) {
 271                         u_int brand_index;
 272
 273                         cpu_model[0] = '\0';
 274
 275                         switch (cpu_id & 0x3000) {
 276                         case 0x1000:
 277                                 strcpy(cpu_model, "Overdrive ");
 278                                 break;
 279                         case 0x2000:
 280                                 strcpy(cpu_model, "Dual ");
 281                                 break;
 282                         }
 283
 284                         switch (cpu_id & 0xf00) {
 285                         case 0x400:
 286                                 strcat(cpu_model, "i486 ");
 287                                 /* Check the particular flavor of 486 */
 288                                 switch (cpu_id & 0xf0) {
 289                                 case 0x00:
 290                                 case 0x10:
 291                                         strcat(cpu_model, "DX");
 292                                         break;
 293                                 case 0x20:
 294                                         strcat(cpu_model, "SX");
 295                                         break;
 296                                 case 0x30:
 297                                         strcat(cpu_model, "DX2");
 298                                         break;
 299                                 case 0x40:
 300                                         strcat(cpu_model, "SL");
 301                                         break;
 302                                 case 0x50:
 303                                         strcat(cpu_model, "SX2");
 304                                         break;
 305                                 case 0x70:
 306                                         strcat(cpu_model,
 307                                             "DX2 Write-Back Enhanced");
 308                                         break;
 309                                 case 0x80:
 310                                         strcat(cpu_model, "DX4");
 311                                         break;
 312                                 }
 313                                 break;
 314                         case 0x500:
 315                                 /* Check the particular flavor of 586 */
 316                                 strcat(cpu_model, "Pentium");
 317                                 switch (cpu_id & 0xf0) {
 318                                 case 0x00:
 319                                         strcat(cpu_model, " A-step");
 320                                         break;
 321                                 case 0x10:
 322                                         strcat(cpu_model, "/P5");
 323                                         break;
 324                                 case 0x20:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x30:
 328                                         strcat(cpu_model, "/P24T");
 329                                         break;
 330                                 case 0x40:
 331                                         strcat(cpu_model, "/P55C");
 332                                         break;
 333                                 case 0x70:
 334                                         strcat(cpu_model, "/P54C");
 335                                         break;
 336                                 case 0x80:
 337                                         strcat(cpu_model, "/P55C (quarter-micron)");
 338                                         break;
 339                                 default:
 340                                         /* nothing */
 341                                         break;
 342                                 }
 343 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 344                                 /*
 345                                  * XXX - If/when Intel fixes the bug, this
 346                                  * should also check the version of the
 347                                  * CPU, not just that it's a Pentium.
 348                                  */
 349                                 has_f00f_bug = 1;
 350 #endif
 351                                 break;
 352                         case 0x600:
 353                                 /* Check the particular flavor of 686 */
 354                                 switch (cpu_id & 0xf0) {
 355                                 case 0x00:
 356                                         strcat(cpu_model, "Pentium Pro A-step");
 357                                         break;
 358                                 case 0x10:
 359                                         strcat(cpu_model, "Pentium Pro");
 360                                         break;
 361                                 case 0x30:
 362                                 case 0x50:
 363                                 case 0x60:
 364                                         strcat(cpu_model,
 365                                 "Pentium II/Pentium II Xeon/Celeron");
 366                                         cpu = CPU_PII;
 367                                         break;
 368                                 case 0x70:
 369                                 case 0x80:
 370                                 case 0xa0:
 371                                 case 0xb0:
 372                                         strcat(cpu_model,
 373                                         "Pentium III/Pentium III Xeon/Celeron");
 374                                         cpu = CPU_PIII;
 375                                         break;
 376                                 default:
 377                                         strcat(cpu_model, "Unknown 80686");
 378                                         break;
 379                                 }
 380                                 break;
 381                         case 0xf00:
 382                                 strcat(cpu_model, "Pentium 4");
 383                                 cpu = CPU_P4;
 384                                 break;
 385                         default:
 386                                 strcat(cpu_model, "unknown");
 387                                 break;
 388                         }
 389
 390                         /*
 391                          * If we didn't get a brand name from the extended
 392                          * CPUID, try to look it up in the brand table.
 393                          */
 394                         if (cpu_high > 0 && *cpu_brand == '\0') {
 395                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 396                                 if (brand_index <= MAX_BRAND_INDEX &&
 397                                     cpu_brandtable[brand_index] != NULL)
 398                                         strcpy(cpu_brand,
 399                                             cpu_brandtable[brand_index]);
 400                         }
 401                 }
 402 #else
 403                 /* Please make up your mind folks! */
 404                 strcat(cpu_model, "EM64T");
 405 #endif
 406                 break;
 407         case CPU_VENDOR_AMD:
 408                 /*
 409                  * Values taken from AMD Processor Recognition
 410                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 411                  * (also describes ``Features'' encodings.
 412                  */
 413                 strcpy(cpu_model, "AMD ");
 414 #ifdef __i386__
 415                 switch (cpu_id & 0xFF0) {
 416                 case 0x410:
 417                         strcat(cpu_model, "Standard Am486DX");
 418                         break;
 419                 case 0x430:
 420                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 421                         break;
 422                 case 0x470:
 423                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 424                         break;
 425                 case 0x480:
 426                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 427                         break;
 428                 case 0x490:
 429                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 430                         break;
 431                 case 0x4E0:
 432                         strcat(cpu_model, "Am5x86 Write-Through");
 433                         break;
 434                 case 0x4F0:
 435                         strcat(cpu_model, "Am5x86 Write-Back");
 436                         break;
 437                 case 0x500:
 438                         strcat(cpu_model, "K5 model 0");
 439                         break;
 440                 case 0x510:
 441                         strcat(cpu_model, "K5 model 1");
 442                         break;
 443                 case 0x520:
 444                         strcat(cpu_model, "K5 PR166 (model 2)");
 445                         break;
 446                 case 0x530:
 447                         strcat(cpu_model, "K5 PR200 (model 3)");
 448                         break;
 449                 case 0x560:
 450                         strcat(cpu_model, "K6");
 451                         break;
 452                 case 0x570:
 453                         strcat(cpu_model, "K6 266 (model 1)");
 454                         break;
 455                 case 0x580:
 456                         strcat(cpu_model, "K6-2");
 457                         break;
 458                 case 0x590:
 459                         strcat(cpu_model, "K6-III");
 460                         break;
 461                 case 0x5a0:
 462                         strcat(cpu_model, "Geode LX");
 463                         break;
 464                 default:
 465                         strcat(cpu_model, "Unknown");
 466                         break;
 467                 }
 468 #else
 469                 if ((cpu_id & 0xf00) == 0xf00)
 470                         strcat(cpu_model, "AMD64 Processor");
 471                 else
 472                         strcat(cpu_model, "Unknown");
 473 #endif
 474                 break;
 475 #ifdef __i386__
 476         case CPU_VENDOR_CYRIX:
 477                 strcpy(cpu_model, "Cyrix ");
 478                 switch (cpu_id & 0xff0) {
 479                 case 0x440:
 480                         strcat(cpu_model, "MediaGX");
 481                         break;
 482                 case 0x520:
 483                         strcat(cpu_model, "6x86");
 484                         break;
 485                 case 0x540:
 486                         cpu_class = CPUCLASS_586;
 487                         strcat(cpu_model, "GXm");
 488                         break;
 489                 case 0x600:
 490                         strcat(cpu_model, "6x86MX");
 491                         break;
 492                 default:
 493                         /*
 494                          * Even though CPU supports the cpuid
 495                          * instruction, it can be disabled.
 496                          * Therefore, this routine supports all Cyrix
 497                          * CPUs.
 498                          */
 499                         switch (cyrix_did & 0xf0) {
 500                         case 0x00:
 501                                 switch (cyrix_did & 0x0f) {
 502                                 case 0x00:
 503                                         strcat(cpu_model, "486SLC");
 504                                         break;
 505                                 case 0x01:
 506                                         strcat(cpu_model, "486DLC");
 507                                         break;
 508                                 case 0x02:
 509                                         strcat(cpu_model, "486SLC2");
 510                                         break;
 511                                 case 0x03:
 512                                         strcat(cpu_model, "486DLC2");
 513                                         break;
 514                                 case 0x04:
 515                                         strcat(cpu_model, "486SRx");
 516                                         break;
 517                                 case 0x05:
 518                                         strcat(cpu_model, "486DRx");
 519                                         break;
 520                                 case 0x06:
 521                                         strcat(cpu_model, "486SRx2");
 522                                         break;
 523                                 case 0x07:
 524                                         strcat(cpu_model, "486DRx2");
 525                                         break;
 526                                 case 0x08:
 527                                         strcat(cpu_model, "486SRu");
 528                                         break;
 529                                 case 0x09:
 530                                         strcat(cpu_model, "486DRu");
 531                                         break;
 532                                 case 0x0a:
 533                                         strcat(cpu_model, "486SRu2");
 534                                         break;
 535                                 case 0x0b:
 536                                         strcat(cpu_model, "486DRu2");
 537                                         break;
 538                                 default:
 539                                         strcat(cpu_model, "Unknown");
 540                                         break;
 541                                 }
 542                                 break;
 543                         case 0x10:
 544                                 switch (cyrix_did & 0x0f) {
 545                                 case 0x00:
 546                                         strcat(cpu_model, "486S");
 547                                         break;
 548                                 case 0x01:
 549                                         strcat(cpu_model, "486S2");
 550                                         break;
 551                                 case 0x02:
 552                                         strcat(cpu_model, "486Se");
 553                                         break;
 554                                 case 0x03:
 555                                         strcat(cpu_model, "486S2e");
 556                                         break;
 557                                 case 0x0a:
 558                                         strcat(cpu_model, "486DX");
 559                                         break;
 560                                 case 0x0b:
 561                                         strcat(cpu_model, "486DX2");
 562                                         break;
 563                                 case 0x0f:
 564                                         strcat(cpu_model, "486DX4");
 565                                         break;
 566                                 default:
 567                                         strcat(cpu_model, "Unknown");
 568                                         break;
 569                                 }
 570                                 break;
 571                         case 0x20:
 572                                 if ((cyrix_did & 0x0f) < 8)
 573                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 574                                 else
 575                                         strcat(cpu_model, "5x86");
 576                                 break;
 577                         case 0x30:
 578                                 strcat(cpu_model, "6x86");
 579                                 break;
 580                         case 0x40:
 581                                 if ((cyrix_did & 0xf000) == 0x3000) {
 582                                         cpu_class = CPUCLASS_586;
 583                                         strcat(cpu_model, "GXm");
 584                                 } else
 585                                         strcat(cpu_model, "MediaGX");
 586                                 break;
 587                         case 0x50:
 588                                 strcat(cpu_model, "6x86MX");
 589                                 break;
 590                         case 0xf0:
 591                                 switch (cyrix_did & 0x0f) {
 592                                 case 0x0d:
 593                                         strcat(cpu_model, "Overdrive CPU");
 594                                         break;
 595                                 case 0x0e:
 596                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 597                                         break;
 598                                 case 0x0f:
 599                                         strcat(cpu_model, "486SLC/DLC");
 600                                         break;
 601                                 default:
 602                                         strcat(cpu_model, "Unknown");
 603                                         break;
 604                                 }
 605                                 break;
 606                         default:
 607                                 strcat(cpu_model, "Unknown");
 608                                 break;
 609                         }
 610                         break;
 611                 }
 612                 break;
 613         case CPU_VENDOR_RISE:
 614                 strcpy(cpu_model, "Rise ");
 615                 switch (cpu_id & 0xff0) {
 616                 case 0x500:     /* 6401 and 6441 (Kirin) */
 617                 case 0x520:     /* 6510 (Lynx) */
 618                         strcat(cpu_model, "mP6");
 619                         break;
 620                 default:
 621                         strcat(cpu_model, "Unknown");
 622                 }
 623                 break;
 624 #endif
 625         case CPU_VENDOR_CENTAUR:
 626 #ifdef __i386__
 627                 switch (cpu_id & 0xff0) {
 628                 case 0x540:
 629                         strcpy(cpu_model, "IDT WinChip C6");
 630                         break;
 631                 case 0x580:
 632                         strcpy(cpu_model, "IDT WinChip 2");
 633                         break;
 634                 case 0x590:
 635                         strcpy(cpu_model, "IDT WinChip 3");
 636                         break;
 637                 case 0x660:
 638                         strcpy(cpu_model, "VIA C3 Samuel");
 639                         break;
 640                 case 0x670:
 641                         if (cpu_id & 0x8)
 642                                 strcpy(cpu_model, "VIA C3 Ezra");
 643                         else
 644                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 645                         break;
 646                 case 0x680:
 647                         strcpy(cpu_model, "VIA C3 Ezra-T");
 648                         break;
 649                 case 0x690:
 650                         strcpy(cpu_model, "VIA C3 Nehemiah");
 651                         break;
 652                 case 0x6a0:
 653                 case 0x6d0:
 654                         strcpy(cpu_model, "VIA C7 Esther");
 655                         break;
 656                 case 0x6f0:
 657                         strcpy(cpu_model, "VIA Nano");
 658                         break;
 659                 default:
 660                         strcpy(cpu_model, "VIA/IDT Unknown");
 661                 }
 662 #else
 663                 strcpy(cpu_model, "VIA ");
 664                 if ((cpu_id & 0xff0) == 0x6f0)
 665                         strcat(cpu_model, "Nano Processor");
 666                 else
 667                         strcat(cpu_model, "Unknown");
 668 #endif
 669                 break;
 670 #ifdef __i386__
 671         case CPU_VENDOR_IBM:
 672                 strcpy(cpu_model, "Blue Lightning CPU");
 673                 break;
 674         case CPU_VENDOR_NSC:
 675                 switch (cpu_id & 0xff0) {
 676                 case 0x540:
 677                         strcpy(cpu_model, "Geode SC1100");
 678                         cpu = CPU_GEODE1100;
 679                         break;
 680                 default:
 681                         strcpy(cpu_model, "Geode/NSC unknown");
 682                         break;
 683                 }
 684                 break;
 685 #endif
 686         case CPU_VENDOR_HYGON:
 687                 strcpy(cpu_model, "Hygon ");
 688 #ifdef __i386__
 689                 strcat(cpu_model, "Unknown");
 690 #else
 691                 if ((cpu_id & 0xf00) == 0xf00)
 692                         strcat(cpu_model, "AMD64 Processor");
 693                 else
 694                         strcat(cpu_model, "Unknown");
 695 #endif
 696                 break;
 697
 698         default:
 699                 strcat(cpu_model, "Unknown");
 700                 break;
 701         }
 702
 703         /*
 704          * Replace cpu_model with cpu_brand minus leading spaces if
 705          * we have one.
 706          */
 707         brand = cpu_brand;
 708         while (*brand == ' ')
 709                 ++brand;
 710         if (*brand != '\0')
 711                 strcpy(cpu_model, brand);
 712
 713         printf("%s (", cpu_model);
 714         if (tsc_freq != 0) {
 715                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 716                 printf("%jd.%02d-MHz ",
 717                     (intmax_t)(tsc_freq + 4999) / 1000000,
 718                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 719         }
 720 #ifdef __i386__
 721         switch(cpu_class) {
 722         case CPUCLASS_286:
 723                 printf("286");
 724                 break;
 725         case CPUCLASS_386:
 726                 printf("386");
 727                 break;
 728 #if defined(I486_CPU)
 729         case CPUCLASS_486:
 730                 printf("486");
 731                 break;
 732 #endif
 733 #if defined(I586_CPU)
 734         case CPUCLASS_586:
 735                 printf("586");
 736                 break;
 737 #endif
 738 #if defined(I686_CPU)
 739         case CPUCLASS_686:
 740                 printf("686");
 741                 break;
 742 #endif
 743         default:
 744                 printf("Unknown");      /* will panic below... */
 745         }
 746 #else
 747         printf("K8");
 748 #endif
 749         printf("-class CPU)\n");
 750         if (*cpu_vendor)
 751                 printf("  Origin=\"%s\"", cpu_vendor);
 752         if (cpu_id)
 753                 printf("  Id=0x%x", cpu_id);
 754
 755         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 756             cpu_vendor_id == CPU_VENDOR_AMD ||
 757             cpu_vendor_id == CPU_VENDOR_HYGON ||
 758             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 759 #ifdef __i386__
 760             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 761             cpu_vendor_id == CPU_VENDOR_RISE ||
 762             cpu_vendor_id == CPU_VENDOR_NSC ||
 763             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 764 #endif
 765             0) {
 766                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 767                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 768                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 769 #ifdef __i386__
 770                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 771                         printf("\n  DIR=0x%04x", cyrix_did);
 772 #endif
 773
 774                 /*
 775                  * AMD CPUID Specification
 776                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 777                  *
 778                  * Intel Processor Identification and CPUID Instruction
 779                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 780                  */
 781                 if (cpu_high > 0) {
 782
 783                         /*
 784                          * Here we should probably set up flags indicating
 785                          * whether or not various features are available.
 786                          * The interesting ones are probably VME, PSE, PAE,
 787                          * and PGE.  The code already assumes without bothering
 788                          * to check that all CPUs >= Pentium have a TSC and
 789                          * MSRs.
 790                          */
 791                         printf("\n  Features=0x%b", cpu_feature,
 792                         "\020"
 793                         "\001FPU"       /* Integral FPU */
 794                         "\002VME"       /* Extended VM86 mode support */
 795                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 796                         "\004PSE"       /* 4MByte page tables */
 797                         "\005TSC"       /* Timestamp counter */
 798                         "\006MSR"       /* Machine specific registers */
 799                         "\007PAE"       /* Physical address extension */
 800                         "\010MCE"       /* Machine Check support */
 801                         "\011CX8"       /* CMPEXCH8 instruction */
 802                         "\012APIC"      /* SMP local APIC */
 803                         "\013oldMTRR"   /* Previous implementation of MTRR */
 804                         "\014SEP"       /* Fast System Call */
 805                         "\015MTRR"      /* Memory Type Range Registers */
 806                         "\016PGE"       /* PG_G (global bit) support */
 807                         "\017MCA"       /* Machine Check Architecture */
 808                         "\020CMOV"      /* CMOV instruction */
 809                         "\021PAT"       /* Page attributes table */
 810                         "\022PSE36"     /* 36 bit address space support */
 811                         "\023PN"        /* Processor Serial number */
 812                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 813                         "\025<b20>"
 814                         "\026DTS"       /* Debug Trace Store */
 815                         "\027ACPI"      /* ACPI support */
 816                         "\030MMX"       /* MMX instructions */
 817                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 818                         "\032SSE"       /* Streaming SIMD Extensions */
 819                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 820                         "\034SS"        /* Self snoop */
 821                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 822                         "\036TM"        /* Thermal Monitor clock slowdown */
 823                         "\037IA64"      /* CPU can execute IA64 instructions */
 824                         "\040PBE"       /* Pending Break Enable */
 825                         );
 826
 827                         if (cpu_feature2 != 0) {
 828                                 printf("\n  Features2=0x%b", cpu_feature2,
 829                                 "\020"
 830                                 "\001SSE3"      /* SSE3 */
 831                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 832                                 "\003DTES64"    /* 64-bit Debug Trace */
 833                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 834                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 835                                 "\006VMX"       /* Virtual Machine Extensions */
 836                                 "\007SMX"       /* Safer Mode Extensions */
 837                                 "\010EST"       /* Enhanced SpeedStep */
 838                                 "\011TM2"       /* Thermal Monitor 2 */
 839                                 "\012SSSE3"     /* SSSE3 */
 840                                 "\013CNXT-ID"   /* L1 context ID available */
 841                                 "\014SDBG"      /* IA32 silicon debug */
 842                                 "\015FMA"       /* Fused Multiply Add */
 843                                 "\016CX16"      /* CMPXCHG16B Instruction */
 844                                 "\017xTPR"      /* Send Task Priority Messages*/
 845                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 846                                 "\021<b16>"
 847                                 "\022PCID"      /* Process-context Identifiers*/
 848                                 "\023DCA"       /* Direct Cache Access */
 849                                 "\024SSE4.1"    /* SSE 4.1 */
 850                                 "\025SSE4.2"    /* SSE 4.2 */
 851                                 "\026x2APIC"    /* xAPIC Extensions */
 852                                 "\027MOVBE"     /* MOVBE Instruction */
 853                                 "\030POPCNT"    /* POPCNT Instruction */
 854                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 855                                 "\032AESNI"     /* AES Crypto */
 856                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 857                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 858                                 "\035AVX"       /* Advanced Vector Extensions */
 859                                 "\036F16C"      /* Half-precision conversions */
 860                                 "\037RDRAND"    /* RDRAND Instruction */
 861                                 "\040HV"        /* Hypervisor */
 862                                 );
 863                         }
 864
 865                         if (amd_feature != 0) {
 866                                 printf("\n  AMD Features=0x%b", amd_feature,
 867                                 "\020"          /* in hex */
 868                                 "\001<s0>"      /* Same */
 869                                 "\002<s1>"      /* Same */
 870                                 "\003<s2>"      /* Same */
 871                                 "\004<s3>"      /* Same */
 872                                 "\005<s4>"      /* Same */
 873                                 "\006<s5>"      /* Same */
 874                                 "\007<s6>"      /* Same */
 875                                 "\010<s7>"      /* Same */
 876                                 "\011<s8>"      /* Same */
 877                                 "\012<s9>"      /* Same */
 878                                 "\013<b10>"     /* Undefined */
 879                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 880                                 "\015<s12>"     /* Same */
 881                                 "\016<s13>"     /* Same */
 882                                 "\017<s14>"     /* Same */
 883                                 "\020<s15>"     /* Same */
 884                                 "\021<s16>"     /* Same */
 885                                 "\022<s17>"     /* Same */
 886                                 "\023<b18>"     /* Reserved, unknown */
 887                                 "\024MP"        /* Multiprocessor Capable */
 888                                 "\025NX"        /* Has EFER.NXE, NX */
 889                                 "\026<b21>"     /* Undefined */
 890                                 "\027MMX+"      /* AMD MMX Extensions */
 891                                 "\030<s23>"     /* Same */
 892                                 "\031<s24>"     /* Same */
 893                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 894                                 "\033Page1GB"   /* 1-GB large page support */
 895                                 "\034RDTSCP"    /* RDTSCP */
 896                                 "\035<b28>"     /* Undefined */
 897                                 "\036LM"        /* 64 bit long mode */
 898                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 899                                 "\0403DNow!"    /* AMD 3DNow! */
 900                                 );
 901                         }
 902
 903                         if (amd_feature2 != 0) {
 904                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 905                                 "\020"
 906                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 907                                 "\002CMP"       /* CMP legacy */
 908                                 "\003SVM"       /* Secure Virtual Mode */
 909                                 "\004ExtAPIC"   /* Extended APIC register */
 910                                 "\005CR8"       /* CR8 in legacy mode */
 911                                 "\006ABM"       /* LZCNT instruction */
 912                                 "\007SSE4A"     /* SSE4A */
 913                                 "\010MAS"       /* Misaligned SSE mode */
 914                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 915                                 "\012OSVW"      /* OS visible workaround */
 916                                 "\013IBS"       /* Instruction based sampling */
 917                                 "\014XOP"       /* XOP extended instructions */
 918                                 "\015SKINIT"    /* SKINIT/STGI */
 919                                 "\016WDT"       /* Watchdog timer */
 920                                 "\017<b14>"
 921                                 "\020LWP"       /* Lightweight Profiling */
 922                                 "\021FMA4"      /* 4-operand FMA instructions */
 923                                 "\022TCE"       /* Translation Cache Extension */
 924                                 "\023<b18>"
 925                                 "\024NodeId"    /* NodeId MSR support */
 926                                 "\025<b20>"
 927                                 "\026TBM"       /* Trailing Bit Manipulation */
 928                                 "\027Topology"  /* Topology Extensions */
 929                                 "\030PCXC"      /* Core perf count */
 930                                 "\031PNXC"      /* NB perf count */
 931                                 "\032<b25>"
 932                                 "\033DBE"       /* Data Breakpoint extension */
 933                                 "\034PTSC"      /* Performance TSC */
 934                                 "\035PL2I"      /* L2I perf count */
 935                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 936                                 "\037ADMSKX"    /* Address mask extension */
 937                                 "\040<b31>"
 938                                 );
 939                         }
 940
 941                         if (cpu_stdext_feature != 0) {
 942                                 printf("\n  Structured Extended Features=0x%b",
 943                                     cpu_stdext_feature,
 944                                        "\020"
 945                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 946                                        "\001FSGSBASE"
 947                                        "\002TSCADJ"
 948                                        "\003SGX"
 949                                        /* Bit Manipulation Instructions */
 950                                        "\004BMI1"
 951                                        /* Hardware Lock Elision */
 952                                        "\005HLE"
 953                                        /* Advanced Vector Instructions 2 */
 954                                        "\006AVX2"
 955                                        /* FDP_EXCPTN_ONLY */
 956                                        "\007FDPEXC"
 957                                        /* Supervisor Mode Execution Prot. */
 958                                        "\010SMEP"
 959                                        /* Bit Manipulation Instructions */
 960                                        "\011BMI2"
 961                                        "\012ERMS"
 962                                        /* Invalidate Processor Context ID */
 963                                        "\013INVPCID"
 964                                        /* Restricted Transactional Memory */
 965                                        "\014RTM"
 966                                        "\015PQM"
 967                                        "\016NFPUSG"
 968                                        /* Intel Memory Protection Extensions */
 969                                        "\017MPX"
 970                                        "\020PQE"
 971                                        /* AVX512 Foundation */
 972                                        "\021AVX512F"
 973                                        "\022AVX512DQ"
 974                                        /* Enhanced NRBG */
 975                                        "\023RDSEED"
 976                                        /* ADCX + ADOX */
 977                                        "\024ADX"
 978                                        /* Supervisor Mode Access Prevention */
 979                                        "\025SMAP"
 980                                        "\026AVX512IFMA"
 981                                        /* Formerly PCOMMIT */
 982                                        "\027<b22>"
 983                                        "\030CLFLUSHOPT"
 984                                        "\031CLWB"
 985                                        "\032PROCTRACE"
 986                                        "\033AVX512PF"
 987                                        "\034AVX512ER"
 988                                        "\035AVX512CD"
 989                                        "\036SHA"
 990                                        "\037AVX512BW"
 991                                        "\040AVX512VL"
 992                                        );
 993                         }
 994
 995                         if (cpu_stdext_feature2 != 0) {
 996                                 printf("\n  Structured Extended Features2=0x%b",
 997                                     cpu_stdext_feature2,
 998                                        "\020"
 999                                        "\001PREFETCHWT1"
1000                                        "\002AVX512VBMI"
1001                                        "\003UMIP"
1002                                        "\004PKU"
1003                                        "\005OSPKE"
1004                                        "\006WAITPKG"
1005                                        "\007AVX512VBMI2"
1006                                        "\011GFNI"
1007                                        "\012VAES"
1008                                        "\013VPCLMULQDQ"
1009                                        "\014AVX512VNNI"
1010                                        "\015AVX512BITALG"
1011                                        "\016TME"
1012                                        "\017AVX512VPOPCNTDQ"
1013                                        "\021LA57"
1014                                        "\027RDPID"
1015                                        "\032CLDEMOTE"
1016                                        "\034MOVDIRI"
1017                                        "\035MOVDIR64B"
1018                                        "\036ENQCMD"
1019                                        "\037SGXLC"
1020                                        );
1021                         }
1022
1023                         if (cpu_stdext_feature3 != 0) {
1024                                 printf("\n  Structured Extended Features3=0x%b",
1025                                     cpu_stdext_feature3,
1026                                        "\020"
1027                                        "\003AVX512_4VNNIW"
1028                                        "\004AVX512_4FMAPS"
1029                                        "\005FSRM"
1030                                        "\011AVX512VP2INTERSECT"
1031                                        "\013MD_CLEAR"
1032                                        "\016TSXFA"
1033                                        "\023PCONFIG"
1034                                        "\025IBT"
1035                                        "\033IBPB"
1036                                        "\034STIBP"
1037                                        "\035L1DFL"
1038                                        "\036ARCH_CAP"
1039                                        "\037CORE_CAP"
1040                                        "\040SSBD"
1041                                        );
1042                         }
1043
1044                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1045                                 cpuid_count(0xd, 0x1, regs);
1046                                 if (regs[0] != 0) {
1047                                         printf("\n  XSAVE Features=0x%b",
1048                                             regs[0],
1049                                             "\020"
1050                                             "\001XSAVEOPT"
1051                                             "\002XSAVEC"
1052                                             "\003XINUSE"
1053                                             "\004XSAVES");
1054                                 }
1055                         }
1056
1057                         if (cpu_ia32_arch_caps != 0) {
1058                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1059                                     (u_int)cpu_ia32_arch_caps,
1060                                        "\020"
1061                                        "\001RDCL_NO"
1062                                        "\002IBRS_ALL"
1063                                        "\003RSBA"
1064                                        "\004SKIP_L1DFL_VME"
1065                                        "\005SSB_NO"
1066                                        "\006MDS_NO"
1067                                        "\010TSX_CTRL"
1068                                        "\011TAA_NO"
1069                                        );
1070                         }
1071
1072                         if (amd_extended_feature_extensions != 0) {
1073                                 u_int amd_fe_masked;
1074
1075                                 amd_fe_masked = amd_extended_feature_extensions;
1076                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1077                                         amd_fe_masked &=
1078                                             ~(AMDFEID_IBRS_ALWAYSON |
1079                                                 AMDFEID_PREFER_IBRS);
1080                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1081                                         amd_fe_masked &=
1082                                             ~AMDFEID_STIBP_ALWAYSON;
1083
1084                                 printf("\n  "
1085                                     "AMD Extended Feature Extensions ID EBX="
1086                                     "0x%b", amd_fe_masked,
1087                                     "\020"
1088                                     "\001CLZERO"
1089                                     "\002IRPerf"
1090                                     "\003XSaveErPtr"
1091                                     "\005RDPRU"
1092                                     "\011MCOMMIT"
1093                                     "\012WBNOINVD"
1094                                     "\015IBPB"
1095                                     "\017IBRS"
1096                                     "\020STIBP"
1097                                     "\021IBRS_ALWAYSON"
1098                                     "\022STIBP_ALWAYSON"
1099                                     "\023PREFER_IBRS"
1100                                     "\030PPIN"
1101                                     "\031SSBD"
1102                                     "\032VIRT_SSBD"
1103                                     "\033SSB_NO"
1104                                     );
1105                         }
1106
1107                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1108                                 print_via_padlock_info();
1109
1110                         if (cpu_feature2 & CPUID2_VMX)
1111                                 print_vmx_info();
1112
1113                         if (amd_feature2 & AMDID2_SVM)
1114                                 print_svm_info();
1115
1116                         if ((cpu_feature & CPUID_HTT) &&
1117                             (cpu_vendor_id == CPU_VENDOR_AMD ||
1118                              cpu_vendor_id == CPU_VENDOR_HYGON))
1119                                 cpu_feature &= ~CPUID_HTT;
1120
1121                         /*
1122                          * If this CPU supports P-state invariant TSC then
1123                          * mention the capability.
1124                          */
1125                         if (tsc_is_invariant) {
1126                                 printf("\n  TSC: P-state invariant");
1127                                 if (tsc_perf_stat)
1128                                         printf(", performance statistics");
1129                         }
1130                 }
1131 #ifdef __i386__
1132         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1133                 printf("  DIR=0x%04x", cyrix_did);
1134                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1135                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1136 #ifndef CYRIX_CACHE_REALLY_WORKS
1137                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1138                         printf("\n  CPU cache: write-through mode");
1139 #endif
1140 #endif
1141         }
1142
1143         /* Avoid ugly blank lines: only print newline when we have to. */
1144         if (*cpu_vendor || cpu_id)
1145                 printf("\n");
1146
1147         if (bootverbose) {
1148                 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1149                     cpu_vendor_id == CPU_VENDOR_HYGON)
1150                         print_AMD_info();
1151                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1152                         print_INTEL_info();
1153 #ifdef __i386__
1154                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1155                         print_transmeta_info();
1156 #endif
1157         }
1158
1159         print_hypervisor_info();
1160 }
1161
1162 #ifdef __i386__
1163 void
1164 panicifcpuunsupported(void)
1165 {
1166
1167 #if !defined(lint)
1168 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1169 #error This kernel is not configured for one of the supported CPUs
1170 #endif
1171 #else /* lint */
1172 #endif /* lint */
1173         /*
1174          * Now that we have told the user what they have,
1175          * let them know if that machine type isn't configured.
1176          */
1177         switch (cpu_class) {
1178         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1179         case CPUCLASS_386:
1180 #if !defined(I486_CPU)
1181         case CPUCLASS_486:
1182 #endif
1183 #if !defined(I586_CPU)
1184         case CPUCLASS_586:
1185 #endif
1186 #if !defined(I686_CPU)
1187         case CPUCLASS_686:
1188 #endif
1189                 panic("CPU class not configured");
1190         default:
1191                 break;
1192         }
1193 }
1194
1195 static  volatile u_int trap_by_rdmsr;
1196
1197 /*
1198  * Special exception 6 handler.
1199  * The rdmsr instruction generates invalid opcodes fault on 486-class
1200  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1201  * function identblue() when this handler is called.  Stacked eip should
1202  * be advanced.
1203  */
1204 inthand_t       bluetrap6;
1205 #ifdef __GNUCLIKE_ASM
1206 __asm
1207 ("                                                                      \n\
1208         .text                                                           \n\
1209         .p2align 2,0x90                                                 \n\
1210         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1211 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1212         ss                                                              \n\
1213         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1214         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1215         iret                                                            \n\
1216 ");
1217 #endif
1218
1219 /*
1220  * Special exception 13 handler.
1221  * Accessing non-existent MSR generates general protection fault.
1222  */
1223 inthand_t       bluetrap13;
1224 #ifdef __GNUCLIKE_ASM
1225 __asm
1226 ("                                                                      \n\
1227         .text                                                           \n\
1228         .p2align 2,0x90                                                 \n\
1229         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1230 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1231         ss                                                              \n\
1232         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1233         popl    %eax            /* discard error code */                \n\
1234         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1235         iret                                                            \n\
1236 ");
1237 #endif
1238
1239 /*
1240  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1241  * support cpuid instruction.  This function should be called after
1242  * loading interrupt descriptor table register.
1243  *
1244  * I don't like this method that handles fault, but I couldn't get
1245  * information for any other methods.  Does blue giant know?
1246  */
1247 static int
1248 identblue(void)
1249 {
1250
1251         trap_by_rdmsr = 0;
1252
1253         /*
1254          * Cyrix 486-class CPU does not support rdmsr instruction.
1255          * The rdmsr instruction generates invalid opcode fault, and exception
1256          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1257          * bluetrap6() set the magic number to trap_by_rdmsr.
1258          */
1259         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1260             GSEL(GCODE_SEL, SEL_KPL));
1261
1262         /*
1263          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1264          * In this case, rdmsr generates general protection fault, and
1265          * exception will be trapped by bluetrap13().
1266          */
1267         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1268             GSEL(GCODE_SEL, SEL_KPL));
1269
1270         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1271
1272         if (trap_by_rdmsr == 0xa8c1d)
1273                 return IDENTBLUE_CYRIX486;
1274         else if (trap_by_rdmsr == 0xa89c4)
1275                 return IDENTBLUE_CYRIXM2;
1276         return IDENTBLUE_IBMCPU;
1277 }
1278
1279
1280 /*
1281  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1282  *
1283  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1284  * +-------+-------+---------------+
1285  * |  SID  |  RID  |   Device ID   |
1286  * |    (DIR 1)    |    (DIR 0)    |
1287  * +-------+-------+---------------+
1288  */
1289 static void
1290 identifycyrix(void)
1291 {
1292         register_t saveintr;
1293         int     ccr2_test = 0, dir_test = 0;
1294         u_char  ccr2, ccr3;
1295
1296         saveintr = intr_disable();
1297
1298         ccr2 = read_cyrix_reg(CCR2);
1299         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1300         read_cyrix_reg(CCR2);
1301         if (read_cyrix_reg(CCR2) != ccr2)
1302                 ccr2_test = 1;
1303         write_cyrix_reg(CCR2, ccr2);
1304
1305         ccr3 = read_cyrix_reg(CCR3);
1306         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1307         read_cyrix_reg(CCR3);
1308         if (read_cyrix_reg(CCR3) != ccr3)
1309                 dir_test = 1;                                   /* CPU supports DIRs. */
1310         write_cyrix_reg(CCR3, ccr3);
1311
1312         if (dir_test) {
1313                 /* Device ID registers are available. */
1314                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1315                 cyrix_did += read_cyrix_reg(DIR0);
1316         } else if (ccr2_test)
1317                 cyrix_did = 0x0010;             /* 486S A-step */
1318         else
1319                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1320
1321         intr_restore(saveintr);
1322 }
1323 #endif
1324
1325 /* Update TSC freq with the value indicated by the caller. */
1326 static void
1327 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1328 {
1329
1330         /* If there was an error during the transition, don't do anything. */
1331         if (status != 0)
1332                 return;
1333
1334         /* Total setting for this level gives the new frequency in MHz. */
1335         hw_clockrate = level->total_set.freq;
1336 }
1337
1338 static void
1339 hook_tsc_freq(void *arg __unused)
1340 {
1341
1342         if (tsc_is_invariant)
1343                 return;
1344
1345         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1346             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1347 }
1348
1349 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1350
1351 static const struct {
1352         const char *    vm_bname;
1353         int             vm_guest;
1354 } vm_bnames[] = {
1355         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1356         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1357         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1358         { "Xen",        VM_GUEST_XEN },         /* Xen */
1359         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1360         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1361 };
1362
1363 static const struct {
1364         const char *    vm_pname;
1365         int             vm_guest;
1366 } vm_pnames[] = {
1367         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1368         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1369         { "VirtualBox",                 VM_GUEST_VBOX },
1370         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1371         { "KVM",                        VM_GUEST_KVM },
1372 };
1373
1374 static struct {
1375         const char      *vm_cpuid;
1376         int             vm_guest;
1377 } vm_cpuids[] = {
1378         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1379         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1380         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1381         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1382         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1383         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1384 };
1385
1386 static void
1387 identify_hypervisor_cpuid_base(void)
1388 {
1389         u_int leaf, regs[4];
1390         int i;
1391
1392         /*
1393          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1394          * http://lkml.org/lkml/2008/10/1/246
1395          *
1396          * KB1009458: Mechanisms to determine if software is running in
1397          * a VMware virtual machine
1398          * http://kb.vmware.com/kb/1009458
1399          *
1400          * Search for a hypervisor that we recognize. If we cannot find
1401          * a specific hypervisor, return the first information about the
1402          * hypervisor that we found, as others may be able to use.
1403          */
1404         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1405                 do_cpuid(leaf, regs);
1406
1407                 /*
1408                  * KVM from Linux kernels prior to commit
1409                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1410                  * to 0 rather than a valid hv_high value.  Check for
1411                  * the KVM signature bytes and fixup %eax to the
1412                  * highest supported leaf in that case.
1413                  */
1414                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1415                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1416                         regs[0] = leaf + 1;
1417
1418                 if (regs[0] >= leaf) {
1419                         for (i = 0; i < nitems(vm_cpuids); i++)
1420                                 if (strncmp((const char *)&regs[1],
1421                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1422                                         vm_guest = vm_cpuids[i].vm_guest;
1423                                         break;
1424                                 }
1425
1426                         /*
1427                          * If this is the first entry or we found a
1428                          * specific hypervisor, record the base, high value,
1429                          * and vendor identifier.
1430                          */
1431                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1432                                 hv_base = leaf;
1433                                 hv_high = regs[0];
1434                                 ((u_int *)&hv_vendor)[0] = regs[1];
1435                                 ((u_int *)&hv_vendor)[1] = regs[2];
1436                                 ((u_int *)&hv_vendor)[2] = regs[3];
1437                                 hv_vendor[12] = '\0';
1438
1439                                 /*
1440                                  * If we found a specific hypervisor, then
1441                                  * we are finished.
1442                                  */
1443                                 if (vm_guest != VM_GUEST_VM)
1444                                         return;
1445                         }
1446                 }
1447         }
1448 }
1449
1450 void
1451 identify_hypervisor(void)
1452 {
1453         u_int regs[4];
1454         char *p;
1455         int i;
1456
1457         /*
1458          * If CPUID2_HV is set, we are running in a hypervisor environment.
1459          */
1460         if (cpu_feature2 & CPUID2_HV) {
1461                 vm_guest = VM_GUEST_VM;
1462                 identify_hypervisor_cpuid_base();
1463
1464                 /* If we have a definitive vendor, we can return now. */
1465                 if (*hv_vendor != '\0')
1466                         return;
1467         }
1468
1469         /*
1470          * Examine SMBIOS strings for older hypervisors.
1471          */
1472         p = kern_getenv("smbios.system.serial");
1473         if (p != NULL) {
1474                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1475                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1476                         if (regs[1] == VMW_HVMAGIC) {
1477                                 vm_guest = VM_GUEST_VMWARE;
1478                                 freeenv(p);
1479                                 return;
1480                         }
1481                 }
1482                 freeenv(p);
1483         }
1484
1485         /*
1486          * XXX: Some of these entries may not be needed since they were
1487          * added to FreeBSD before the checks above.
1488          */
1489         p = kern_getenv("smbios.bios.vendor");
1490         if (p != NULL) {
1491                 for (i = 0; i < nitems(vm_bnames); i++)
1492                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1493                                 vm_guest = vm_bnames[i].vm_guest;
1494                                 /* If we have a specific match, return */
1495                                 if (vm_guest != VM_GUEST_VM) {
1496                                         freeenv(p);
1497                                         return;
1498                                 }
1499                                 /*
1500                                  * We are done with bnames, but there might be
1501                                  * a more specific match in the pnames
1502                                  */
1503                                 break;
1504                         }
1505                 freeenv(p);
1506         }
1507         p = kern_getenv("smbios.system.product");
1508         if (p != NULL) {
1509                 for (i = 0; i < nitems(vm_pnames); i++)
1510                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1511                                 vm_guest = vm_pnames[i].vm_guest;
1512                                 freeenv(p);
1513                                 return;
1514                         }
1515                 freeenv(p);
1516         }
1517 }
1518
1519 bool
1520 fix_cpuid(void)
1521 {
1522         uint64_t msr;
1523
1524         /*
1525          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1526          * get the largest standard CPUID function number again if it is set
1527          * from BIOS.  It is necessary for probing correct CPU topology later
1528          * and for the correct operation of the AVX-aware userspace.
1529          */
1530         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1531             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1532             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1533             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1534             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1535                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1536                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1537                         msr &= ~IA32_MISC_EN_LIMCPUID;
1538                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1539                         return (true);
1540                 }
1541         }
1542
1543         /*
1544          * Re-enable AMD Topology Extension that could be disabled by BIOS
1545          * on some notebook processors.  Without the extension it's really
1546          * hard to determine the correct CPU cache topology.
1547          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1548          * Models 60h-6Fh Processors, Publication # 50742.
1549          */
1550         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1551             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1552                 msr = rdmsr(MSR_EXTFEATURES);
1553                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1554                         msr |= (uint64_t)1 << 54;
1555                         wrmsr(MSR_EXTFEATURES, msr);
1556                         return (true);
1557                 }
1558         }
1559         return (false);
1560 }
1561
1562 void
1563 identify_cpu1(void)
1564 {
1565         u_int regs[4];
1566
1567         do_cpuid(0, regs);
1568         cpu_high = regs[0];
1569         ((u_int *)&cpu_vendor)[0] = regs[1];
1570         ((u_int *)&cpu_vendor)[1] = regs[3];
1571         ((u_int *)&cpu_vendor)[2] = regs[2];
1572         cpu_vendor[12] = '\0';
1573
1574         do_cpuid(1, regs);
1575         cpu_id = regs[0];
1576         cpu_procinfo = regs[1];
1577         cpu_feature = regs[3];
1578         cpu_feature2 = regs[2];
1579 }
1580
1581 void
1582 identify_cpu2(void)
1583 {
1584         u_int regs[4], cpu_stdext_disable;
1585
1586         if (cpu_high >= 6) {
1587                 cpuid_count(6, 0, regs);
1588                 cpu_power_eax = regs[0];
1589                 cpu_power_ebx = regs[1];
1590                 cpu_power_ecx = regs[2];
1591                 cpu_power_edx = regs[3];
1592         }
1593
1594         if (cpu_high >= 7) {
1595                 cpuid_count(7, 0, regs);
1596                 cpu_stdext_feature = regs[1];
1597
1598                 /*
1599                  * Some hypervisors failed to filter out unsupported
1600                  * extended features.  Allow to disable the
1601                  * extensions, activation of which requires setting a
1602                  * bit in CR4, and which VM monitors do not support.
1603                  */
1604                 cpu_stdext_disable = 0;
1605                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1606                 cpu_stdext_feature &= ~cpu_stdext_disable;
1607
1608                 cpu_stdext_feature2 = regs[2];
1609                 cpu_stdext_feature3 = regs[3];
1610
1611                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1612                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1613         }
1614 }
1615
1616 void
1617 identify_cpu_fixup_bsp(void)
1618 {
1619         u_int regs[4];
1620
1621         cpu_vendor_id = find_cpu_vendor_id();
1622
1623         if (fix_cpuid()) {
1624                 do_cpuid(0, regs);
1625                 cpu_high = regs[0];
1626         }
1627 }
1628
1629 /*
1630  * Final stage of CPU identification.
1631  */
1632 void
1633 finishidentcpu(void)
1634 {
1635         u_int regs[4];
1636 #ifdef __i386__
1637         u_char ccr3;
1638 #endif
1639
1640         identify_cpu_fixup_bsp();
1641
1642         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1643                 do_cpuid(5, regs);
1644                 cpu_mon_mwait_flags = regs[2];
1645                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1646                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1647         }
1648
1649         identify_cpu2();
1650
1651 #ifdef __i386__
1652         if (cpu_high > 0 &&
1653             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1654              cpu_vendor_id == CPU_VENDOR_AMD ||
1655              cpu_vendor_id == CPU_VENDOR_HYGON ||
1656              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1657              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1658              cpu_vendor_id == CPU_VENDOR_NSC)) {
1659                 do_cpuid(0x80000000, regs);
1660                 if (regs[0] >= 0x80000000)
1661                         cpu_exthigh = regs[0];
1662         }
1663 #else
1664         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1665             cpu_vendor_id == CPU_VENDOR_AMD ||
1666             cpu_vendor_id == CPU_VENDOR_HYGON ||
1667             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1668                 do_cpuid(0x80000000, regs);
1669                 cpu_exthigh = regs[0];
1670         }
1671 #endif
1672         if (cpu_exthigh >= 0x80000001) {
1673                 do_cpuid(0x80000001, regs);
1674                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1675                 amd_feature2 = regs[2];
1676         }
1677         if (cpu_exthigh >= 0x80000007) {
1678                 do_cpuid(0x80000007, regs);
1679                 amd_rascap = regs[1];
1680                 amd_pminfo = regs[3];
1681         }
1682         if (cpu_exthigh >= 0x80000008) {
1683                 do_cpuid(0x80000008, regs);
1684                 cpu_maxphyaddr = regs[0] & 0xff;
1685                 amd_extended_feature_extensions = regs[1];
1686                 cpu_procinfo2 = regs[2];
1687         } else {
1688                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1689         }
1690
1691 #ifdef __i386__
1692         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1693                 if (cpu == CPU_486) {
1694                         /*
1695                          * These conditions are equivalent to:
1696                          *     - CPU does not support cpuid instruction.
1697                          *     - Cyrix/IBM CPU is detected.
1698                          */
1699                         if (identblue() == IDENTBLUE_IBMCPU) {
1700                                 strcpy(cpu_vendor, "IBM");
1701                                 cpu_vendor_id = CPU_VENDOR_IBM;
1702                                 cpu = CPU_BLUE;
1703                                 return;
1704                         }
1705                 }
1706                 switch (cpu_id & 0xf00) {
1707                 case 0x600:
1708                         /*
1709                          * Cyrix's datasheet does not describe DIRs.
1710                          * Therefor, I assume it does not have them
1711                          * and use the result of the cpuid instruction.
1712                          * XXX they seem to have it for now at least. -Peter
1713                          */
1714                         identifycyrix();
1715                         cpu = CPU_M2;
1716                         break;
1717                 default:
1718                         identifycyrix();
1719                         /*
1720                          * This routine contains a trick.
1721                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1722                          */
1723                         switch (cyrix_did & 0x00f0) {
1724                         case 0x00:
1725                         case 0xf0:
1726                                 cpu = CPU_486DLC;
1727                                 break;
1728                         case 0x10:
1729                                 cpu = CPU_CY486DX;
1730                                 break;
1731                         case 0x20:
1732                                 if ((cyrix_did & 0x000f) < 8)
1733                                         cpu = CPU_M1;
1734                                 else
1735                                         cpu = CPU_M1SC;
1736                                 break;
1737                         case 0x30:
1738                                 cpu = CPU_M1;
1739                                 break;
1740                         case 0x40:
1741                                 /* MediaGX CPU */
1742                                 cpu = CPU_M1SC;
1743                                 break;
1744                         default:
1745                                 /* M2 and later CPUs are treated as M2. */
1746                                 cpu = CPU_M2;
1747
1748                                 /*
1749                                  * enable cpuid instruction.
1750                                  */
1751                                 ccr3 = read_cyrix_reg(CCR3);
1752                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1753                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1754                                 write_cyrix_reg(CCR3, ccr3);
1755
1756                                 do_cpuid(0, regs);
1757                                 cpu_high = regs[0];     /* eax */
1758                                 do_cpuid(1, regs);
1759                                 cpu_id = regs[0];       /* eax */
1760                                 cpu_feature = regs[3];  /* edx */
1761                                 break;
1762                         }
1763                 }
1764         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1765                 /*
1766                  * There are BlueLightning CPUs that do not change
1767                  * undefined flags by dividing 5 by 2.  In this case,
1768                  * the CPU identification routine in locore.s leaves
1769                  * cpu_vendor null string and puts CPU_486 into the
1770                  * cpu.
1771                  */
1772                 if (identblue() == IDENTBLUE_IBMCPU) {
1773                         strcpy(cpu_vendor, "IBM");
1774                         cpu_vendor_id = CPU_VENDOR_IBM;
1775                         cpu = CPU_BLUE;
1776                         return;
1777                 }
1778         }
1779 #endif
1780 }
1781
1782 int
1783 pti_get_default(void)
1784 {
1785
1786         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1787             strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1788                 return (0);
1789         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1790                 return (0);
1791         return (1);
1792 }
1793
1794 static u_int
1795 find_cpu_vendor_id(void)
1796 {
1797         int     i;
1798
1799         for (i = 0; i < nitems(cpu_vendors); i++)
1800                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1801                         return (cpu_vendors[i].vendor_id);
1802         return (0);
1803 }
1804
1805 static void
1806 print_AMD_assoc(int i)
1807 {
1808         if (i == 255)
1809                 printf(", fully associative\n");
1810         else
1811                 printf(", %d-way associative\n", i);
1812 }
1813
1814 static void
1815 print_AMD_l2_assoc(int i)
1816 {
1817         switch (i & 0x0f) {
1818         case 0: printf(", disabled/not present\n"); break;
1819         case 1: printf(", direct mapped\n"); break;
1820         case 2: printf(", 2-way associative\n"); break;
1821         case 4: printf(", 4-way associative\n"); break;
1822         case 6: printf(", 8-way associative\n"); break;
1823         case 8: printf(", 16-way associative\n"); break;
1824         case 15: printf(", fully associative\n"); break;
1825         default: printf(", reserved configuration\n"); break;
1826         }
1827 }
1828
1829 static void
1830 print_AMD_info(void)
1831 {
1832 #ifdef __i386__
1833         uint64_t amd_whcr;
1834 #endif
1835         u_int regs[4];
1836
1837         if (cpu_exthigh >= 0x80000005) {
1838                 do_cpuid(0x80000005, regs);
1839                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1840                 print_AMD_assoc(regs[0] >> 24);
1841
1842                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1843                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1844
1845                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1846                 print_AMD_assoc(regs[1] >> 24);
1847
1848                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1849                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1850
1851                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1852                 printf(", %d bytes/line", regs[2] & 0xff);
1853                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1854                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1855
1856                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1857                 printf(", %d bytes/line", regs[3] & 0xff);
1858                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1859                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1860         }
1861
1862         if (cpu_exthigh >= 0x80000006) {
1863                 do_cpuid(0x80000006, regs);
1864                 if ((regs[0] >> 16) != 0) {
1865                         printf("L2 2MB data TLB: %d entries",
1866                             (regs[0] >> 16) & 0xfff);
1867                         print_AMD_l2_assoc(regs[0] >> 28);
1868                         printf("L2 2MB instruction TLB: %d entries",
1869                             regs[0] & 0xfff);
1870                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1871                 } else {
1872                         printf("L2 2MB unified TLB: %d entries",
1873                             regs[0] & 0xfff);
1874                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1875                 }
1876                 if ((regs[1] >> 16) != 0) {
1877                         printf("L2 4KB data TLB: %d entries",
1878                             (regs[1] >> 16) & 0xfff);
1879                         print_AMD_l2_assoc(regs[1] >> 28);
1880
1881                         printf("L2 4KB instruction TLB: %d entries",
1882                             (regs[1] >> 16) & 0xfff);
1883                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1884                 } else {
1885                         printf("L2 4KB unified TLB: %d entries",
1886                             (regs[1] >> 16) & 0xfff);
1887                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1888                 }
1889                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1890                 printf(", %d bytes/line", regs[2] & 0xff);
1891                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1892                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1893         }
1894
1895 #ifdef __i386__
1896         if (((cpu_id & 0xf00) == 0x500)
1897             && (((cpu_id & 0x0f0) > 0x80)
1898                 || (((cpu_id & 0x0f0) == 0x80)
1899                     && (cpu_id & 0x00f) > 0x07))) {
1900                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1901                 amd_whcr = rdmsr(0xc0000082);
1902                 if (!(amd_whcr & (0x3ff << 22))) {
1903                         printf("Write Allocate Disable\n");
1904                 } else {
1905                         printf("Write Allocate Enable Limit: %dM bytes\n",
1906                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1907                         printf("Write Allocate 15-16M bytes: %s\n",
1908                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1909                 }
1910         } else if (((cpu_id & 0xf00) == 0x500)
1911                    && ((cpu_id & 0x0f0) > 0x50)) {
1912                 /* K6, K6-2(old core) */
1913                 amd_whcr = rdmsr(0xc0000082);
1914                 if (!(amd_whcr & (0x7f << 1))) {
1915                         printf("Write Allocate Disable\n");
1916                 } else {
1917                         printf("Write Allocate Enable Limit: %dM bytes\n",
1918                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1919                         printf("Write Allocate 15-16M bytes: %s\n",
1920                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1921                         printf("Hardware Write Allocate Control: %s\n",
1922                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1923                 }
1924         }
1925 #endif
1926         /*
1927          * Opteron Rev E shows a bug as in very rare occasions a read memory
1928          * barrier is not performed as expected if it is followed by a
1929          * non-atomic read-modify-write instruction.
1930          * As long as that bug pops up very rarely (intensive machine usage
1931          * on other operating systems generally generates one unexplainable
1932          * crash any 2 months) and as long as a model specific fix would be
1933          * impractical at this stage, print out a warning string if the broken
1934          * model and family are identified.
1935          */
1936         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1937             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1938                 printf("WARNING: This architecture revision has known SMP "
1939                     "hardware bugs which may cause random instability\n");
1940 }
1941
1942 static void
1943 print_INTEL_info(void)
1944 {
1945         u_int regs[4];
1946         u_int rounds, regnum;
1947         u_int nwaycode, nway;
1948
1949         if (cpu_high >= 2) {
1950                 rounds = 0;
1951                 do {
1952                         do_cpuid(0x2, regs);
1953                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1954                                 break;  /* we have a buggy CPU */
1955
1956                         for (regnum = 0; regnum <= 3; ++regnum) {
1957                                 if (regs[regnum] & (1<<31))
1958                                         continue;
1959                                 if (regnum != 0)
1960                                         print_INTEL_TLB(regs[regnum] & 0xff);
1961                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1962                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1963                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1964                         }
1965                 } while (--rounds > 0);
1966         }
1967
1968         if (cpu_exthigh >= 0x80000006) {
1969                 do_cpuid(0x80000006, regs);
1970                 nwaycode = (regs[2] >> 12) & 0x0f;
1971                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1972                         nway = 1 << (nwaycode / 2);
1973                 else
1974                         nway = 0;
1975                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1976                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1977         }
1978 }
1979
1980 static void
1981 print_INTEL_TLB(u_int data)
1982 {
1983         switch (data) {
1984         case 0x0:
1985         case 0x40:
1986         default:
1987                 break;
1988         case 0x1:
1989                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1990                 break;
1991         case 0x2:
1992                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1993                 break;
1994         case 0x3:
1995                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1996                 break;
1997         case 0x4:
1998                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1999                 break;
2000         case 0x6:
2001                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2002                 break;
2003         case 0x8:
2004                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2005                 break;
2006         case 0x9:
2007                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2008                 break;
2009         case 0xa:
2010                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2011                 break;
2012         case 0xb:
2013                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2014                 break;
2015         case 0xc:
2016                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2017                 break;
2018         case 0xd:
2019                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2020                 break;
2021         case 0xe:
2022                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2023                 break;
2024         case 0x1d:
2025                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2026                 break;
2027         case 0x21:
2028                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2029                 break;
2030         case 0x22:
2031                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2032                 break;
2033         case 0x23:
2034                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2035                 break;
2036         case 0x24:
2037                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2038                 break;
2039         case 0x25:
2040                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2041                 break;
2042         case 0x29:
2043                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2044                 break;
2045         case 0x2c:
2046                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2047                 break;
2048         case 0x30:
2049                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2050                 break;
2051         case 0x39: /* De-listed in SDM rev. 54 */
2052                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2053                 break;
2054         case 0x3b: /* De-listed in SDM rev. 54 */
2055                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2056                 break;
2057         case 0x3c: /* De-listed in SDM rev. 54 */
2058                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2059                 break;
2060         case 0x41:
2061                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2062                 break;
2063         case 0x42:
2064                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2065                 break;
2066         case 0x43:
2067                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2068                 break;
2069         case 0x44:
2070                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2071                 break;
2072         case 0x45:
2073                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2074                 break;
2075         case 0x46:
2076                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2077                 break;
2078         case 0x47:
2079                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2080                 break;
2081         case 0x48:
2082                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2083                 break;
2084         case 0x49:
2085                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2086                     CPUID_TO_MODEL(cpu_id) == 0x6)
2087                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2088                 else
2089                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2090                 break;
2091         case 0x4a:
2092                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2093                 break;
2094         case 0x4b:
2095                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2096                 break;
2097         case 0x4c:
2098                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2099                 break;
2100         case 0x4d:
2101                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2102                 break;
2103         case 0x4e:
2104                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2105                 break;
2106         case 0x4f:
2107                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2108                 break;
2109         case 0x50:
2110                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2111                 break;
2112         case 0x51:
2113                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2114                 break;
2115         case 0x52:
2116                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2117                 break;
2118         case 0x55:
2119                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2120                 break;
2121         case 0x56:
2122                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2123                 break;
2124         case 0x57:
2125                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2126                 break;
2127         case 0x59:
2128                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2129                 break;
2130         case 0x5a:
2131                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2132                 break;
2133         case 0x5b:
2134                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2135                 break;
2136         case 0x5c:
2137                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2138                 break;
2139         case 0x5d:
2140                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2141                 break;
2142         case 0x60:
2143                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2144                 break;
2145         case 0x61:
2146                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2147                 break;
2148         case 0x63:
2149                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2150                 break;
2151         case 0x64:
2152                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2153                 break;
2154         case 0x66:
2155                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2156                 break;
2157         case 0x67:
2158                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2159                 break;
2160         case 0x68:
2161                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2162                 break;
2163         case 0x6a:
2164                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2165                 break;
2166         case 0x6b:
2167                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2168                 break;
2169         case 0x6c:
2170                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2171                 break;
2172         case 0x6d:
2173                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2174                 break;
2175         case 0x70:
2176                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2177                 break;
2178         case 0x71:
2179                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2180                 break;
2181         case 0x72:
2182                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2183                 break;
2184         case 0x76:
2185                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2186                 break;
2187         case 0x78:
2188                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2189                 break;
2190         case 0x79:
2191                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2192                 break;
2193         case 0x7a:
2194                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2195                 break;
2196         case 0x7b:
2197                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2198                 break;
2199         case 0x7c:
2200                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2201                 break;
2202         case 0x7d:
2203                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2204                 break;
2205         case 0x7f:
2206                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2207                 break;
2208         case 0x80:
2209                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2210                 break;
2211         case 0x82:
2212                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2213                 break;
2214         case 0x83:
2215                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2216                 break;
2217         case 0x84:
2218                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2219                 break;
2220         case 0x85:
2221                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2222                 break;
2223         case 0x86:
2224                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2225                 break;
2226         case 0x87:
2227                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2228                 break;
2229         case 0xa0:
2230                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2231                 break;
2232         case 0xb0:
2233                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2234                 break;
2235         case 0xb1:
2236                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2237                 break;
2238         case 0xb2:
2239                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2240                 break;
2241         case 0xb3:
2242                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2243                 break;
2244         case 0xb4:
2245                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2246                 break;
2247         case 0xb5:
2248                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2249                 break;
2250         case 0xb6:
2251                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2252                 break;
2253         case 0xba:
2254                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2255                 break;
2256         case 0xc0:
2257                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2258                 break;
2259         case 0xc1:
2260                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2261                 break;
2262         case 0xc2:
2263                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2264                 break;
2265         case 0xc3:
2266                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2267                 break;
2268         case 0xc4:
2269                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2270                 break;
2271         case 0xca:
2272                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2273                 break;
2274         case 0xd0:
2275                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2276                 break;
2277         case 0xd1:
2278                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2279                 break;
2280         case 0xd2:
2281                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2282                 break;
2283         case 0xd6:
2284                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2285                 break;
2286         case 0xd7:
2287                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2288                 break;
2289         case 0xd8:
2290                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2291                 break;
2292         case 0xdc:
2293                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2294                 break;
2295         case 0xdd:
2296                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2297                 break;
2298         case 0xde:
2299                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2300                 break;
2301         case 0xe2:
2302                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2303                 break;
2304         case 0xe3:
2305                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2306                 break;
2307         case 0xe4:
2308                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2309                 break;
2310         case 0xea:
2311                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2312                 break;
2313         case 0xeb:
2314                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2315                 break;
2316         case 0xec:
2317                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2318                 break;
2319         case 0xf0:
2320                 printf("64-Byte prefetching\n");
2321                 break;
2322         case 0xf1:
2323                 printf("128-Byte prefetching\n");
2324                 break;
2325         }
2326 }
2327
2328 static void
2329 print_svm_info(void)
2330 {
2331         u_int features, regs[4];
2332         uint64_t msr;
2333         int comma;
2334
2335         printf("\n  SVM: ");
2336         do_cpuid(0x8000000A, regs);
2337         features = regs[3];
2338
2339         msr = rdmsr(MSR_VM_CR);
2340         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2341                 printf("(disabled in BIOS) ");
2342
2343         if (!bootverbose) {
2344                 comma = 0;
2345                 if (features & (1 << 0)) {
2346                         printf("%sNP", comma ? "," : "");
2347                         comma = 1;
2348                 }
2349                 if (features & (1 << 3)) {
2350                         printf("%sNRIP", comma ? "," : "");
2351                         comma = 1;
2352                 }
2353                 if (features & (1 << 5)) {
2354                         printf("%sVClean", comma ? "," : "");
2355                         comma = 1;
2356                 }
2357                 if (features & (1 << 6)) {
2358                         printf("%sAFlush", comma ? "," : "");
2359                         comma = 1;
2360                 }
2361                 if (features & (1 << 7)) {
2362                         printf("%sDAssist", comma ? "," : "");
2363                         comma = 1;
2364                 }
2365                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2366                 return;
2367         }
2368
2369         printf("Features=0x%b", features,
2370                "\020"
2371                "\001NP"                 /* Nested paging */
2372                "\002LbrVirt"            /* LBR virtualization */
2373                "\003SVML"               /* SVM lock */
2374                "\004NRIPS"              /* NRIP save */
2375                "\005TscRateMsr"         /* MSR based TSC rate control */
2376                "\006VmcbClean"          /* VMCB clean bits */
2377                "\007FlushByAsid"        /* Flush by ASID */
2378                "\010DecodeAssist"       /* Decode assist */
2379                "\011<b8>"
2380                "\012<b9>"
2381                "\013PauseFilter"        /* PAUSE intercept filter */
2382                "\014EncryptedMcodePatch"
2383                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2384                "\016AVIC"               /* virtual interrupt controller */
2385                "\017<b14>"
2386                "\020V_VMSAVE_VMLOAD"
2387                "\021vGIF"
2388                "\022GMET"               /* Guest Mode Execute Trap */
2389                "\023<b18>"
2390                "\024<b19>"
2391                "\025GuesSpecCtl"        /* Guest Spec_ctl */
2392                "\026<b21>"
2393                "\027<b22>"
2394                "\030<b23>"
2395                "\031<b24>"
2396                "\032<b25>"
2397                "\033<b26>"
2398                "\034<b27>"
2399                "\035<b28>"
2400                "\036<b29>"
2401                "\037<b30>"
2402                "\040<b31>"
2403                );
2404         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2405 }
2406
2407 #ifdef __i386__
2408 static void
2409 print_transmeta_info(void)
2410 {
2411         u_int regs[4], nreg = 0;
2412
2413         do_cpuid(0x80860000, regs);
2414         nreg = regs[0];
2415         if (nreg >= 0x80860001) {
2416                 do_cpuid(0x80860001, regs);
2417                 printf("  Processor revision %u.%u.%u.%u\n",
2418                        (regs[1] >> 24) & 0xff,
2419                        (regs[1] >> 16) & 0xff,
2420                        (regs[1] >> 8) & 0xff,
2421                        regs[1] & 0xff);
2422         }
2423         if (nreg >= 0x80860002) {
2424                 do_cpuid(0x80860002, regs);
2425                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2426                        (regs[1] >> 24) & 0xff,
2427                        (regs[1] >> 16) & 0xff,
2428                        (regs[1] >> 8) & 0xff,
2429                        regs[1] & 0xff,
2430                        regs[2]);
2431         }
2432         if (nreg >= 0x80860006) {
2433                 char info[65];
2434                 do_cpuid(0x80860003, (u_int*) &info[0]);
2435                 do_cpuid(0x80860004, (u_int*) &info[16]);
2436                 do_cpuid(0x80860005, (u_int*) &info[32]);
2437                 do_cpuid(0x80860006, (u_int*) &info[48]);
2438                 info[64] = 0;
2439                 printf("  %s\n", info);
2440         }
2441 }
2442 #endif
2443
2444 static void
2445 print_via_padlock_info(void)
2446 {
2447         u_int regs[4];
2448
2449         do_cpuid(0xc0000001, regs);
2450         printf("\n  VIA Padlock Features=0x%b", regs[3],
2451         "\020"
2452         "\003RNG"               /* RNG */
2453         "\007AES"               /* ACE */
2454         "\011AES-CTR"           /* ACE2 */
2455         "\013SHA1,SHA256"       /* PHE */
2456         "\015RSA"               /* PMM */
2457         );
2458 }
2459
2460 static uint32_t
2461 vmx_settable(uint64_t basic, int msr, int true_msr)
2462 {
2463         uint64_t val;
2464
2465         if (basic & (1ULL << 55))
2466                 val = rdmsr(true_msr);
2467         else
2468                 val = rdmsr(msr);
2469
2470         /* Just report the controls that can be set to 1. */
2471         return (val >> 32);
2472 }
2473
2474 static void
2475 print_vmx_info(void)
2476 {
2477         uint64_t basic, msr;
2478         uint32_t entry, exit, mask, pin, proc, proc2;
2479         int comma;
2480
2481         printf("\n  VT-x: ");
2482         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2483         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2484                 printf("(disabled in BIOS) ");
2485         basic = rdmsr(MSR_VMX_BASIC);
2486         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2487             MSR_VMX_TRUE_PINBASED_CTLS);
2488         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2489             MSR_VMX_TRUE_PROCBASED_CTLS);
2490         if (proc & PROCBASED_SECONDARY_CONTROLS)
2491                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2492                     MSR_VMX_PROCBASED_CTLS2);
2493         else
2494                 proc2 = 0;
2495         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2496         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2497
2498         if (!bootverbose) {
2499                 comma = 0;
2500                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2501                     entry & VM_ENTRY_LOAD_PAT) {
2502                         printf("%sPAT", comma ? "," : "");
2503                         comma = 1;
2504                 }
2505                 if (proc & PROCBASED_HLT_EXITING) {
2506                         printf("%sHLT", comma ? "," : "");
2507                         comma = 1;
2508                 }
2509                 if (proc & PROCBASED_MTF) {
2510                         printf("%sMTF", comma ? "," : "");
2511                         comma = 1;
2512                 }
2513                 if (proc & PROCBASED_PAUSE_EXITING) {
2514                         printf("%sPAUSE", comma ? "," : "");
2515                         comma = 1;
2516                 }
2517                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2518                         printf("%sEPT", comma ? "," : "");
2519                         comma = 1;
2520                 }
2521                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2522                         printf("%sUG", comma ? "," : "");
2523                         comma = 1;
2524                 }
2525                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2526                         printf("%sVPID", comma ? "," : "");
2527                         comma = 1;
2528                 }
2529                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2530                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2531                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2532                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2533                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2534                         printf("%sVID", comma ? "," : "");
2535                         comma = 1;
2536                         if (pin & PINBASED_POSTED_INTERRUPT)
2537                                 printf(",PostIntr");
2538                 }
2539                 return;
2540         }
2541
2542         mask = basic >> 32;
2543         printf("Basic Features=0x%b", mask,
2544         "\020"
2545         "\02132PA"              /* 32-bit physical addresses */
2546         "\022SMM"               /* SMM dual-monitor */
2547         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2548         "\030TRUE"              /* TRUE_CTLS MSRs */
2549         );
2550         printf("\n        Pin-Based Controls=0x%b", pin,
2551         "\020"
2552         "\001ExtINT"            /* External-interrupt exiting */
2553         "\004NMI"               /* NMI exiting */
2554         "\006VNMI"              /* Virtual NMIs */
2555         "\007PreTmr"            /* Activate VMX-preemption timer */
2556         "\010PostIntr"          /* Process posted interrupts */
2557         );
2558         printf("\n        Primary Processor Controls=0x%b", proc,
2559         "\020"
2560         "\003INTWIN"            /* Interrupt-window exiting */
2561         "\004TSCOff"            /* Use TSC offsetting */
2562         "\010HLT"               /* HLT exiting */
2563         "\012INVLPG"            /* INVLPG exiting */
2564         "\013MWAIT"             /* MWAIT exiting */
2565         "\014RDPMC"             /* RDPMC exiting */
2566         "\015RDTSC"             /* RDTSC exiting */
2567         "\020CR3-LD"            /* CR3-load exiting */
2568         "\021CR3-ST"            /* CR3-store exiting */
2569         "\024CR8-LD"            /* CR8-load exiting */
2570         "\025CR8-ST"            /* CR8-store exiting */
2571         "\026TPR"               /* Use TPR shadow */
2572         "\027NMIWIN"            /* NMI-window exiting */
2573         "\030MOV-DR"            /* MOV-DR exiting */
2574         "\031IO"                /* Unconditional I/O exiting */
2575         "\032IOmap"             /* Use I/O bitmaps */
2576         "\034MTF"               /* Monitor trap flag */
2577         "\035MSRmap"            /* Use MSR bitmaps */
2578         "\036MONITOR"           /* MONITOR exiting */
2579         "\037PAUSE"             /* PAUSE exiting */
2580         );
2581         if (proc & PROCBASED_SECONDARY_CONTROLS)
2582                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2583                 "\020"
2584                 "\001APIC"              /* Virtualize APIC accesses */
2585                 "\002EPT"               /* Enable EPT */
2586                 "\003DT"                /* Descriptor-table exiting */
2587                 "\004RDTSCP"            /* Enable RDTSCP */
2588                 "\005x2APIC"            /* Virtualize x2APIC mode */
2589                 "\006VPID"              /* Enable VPID */
2590                 "\007WBINVD"            /* WBINVD exiting */
2591                 "\010UG"                /* Unrestricted guest */
2592                 "\011APIC-reg"          /* APIC-register virtualization */
2593                 "\012VID"               /* Virtual-interrupt delivery */
2594                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2595                 "\014RDRAND"            /* RDRAND exiting */
2596                 "\015INVPCID"           /* Enable INVPCID */
2597                 "\016VMFUNC"            /* Enable VM functions */
2598                 "\017VMCS"              /* VMCS shadowing */
2599                 "\020EPT#VE"            /* EPT-violation #VE */
2600                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2601                 );
2602         printf("\n        Exit Controls=0x%b", mask,
2603         "\020"
2604         "\003DR"                /* Save debug controls */
2605                                 /* Ignore Host address-space size */
2606         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2607         "\020AckInt"            /* Acknowledge interrupt on exit */
2608         "\023PAT-SV"            /* Save MSR_PAT */
2609         "\024PAT-LD"            /* Load MSR_PAT */
2610         "\025EFER-SV"           /* Save MSR_EFER */
2611         "\026EFER-LD"           /* Load MSR_EFER */
2612         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2613         );
2614         printf("\n        Entry Controls=0x%b", mask,
2615         "\020"
2616         "\003DR"                /* Save debug controls */
2617                                 /* Ignore IA-32e mode guest */
2618                                 /* Ignore Entry to SMM */
2619                                 /* Ignore Deactivate dual-monitor treatment */
2620         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2621         "\017PAT"               /* Load MSR_PAT */
2622         "\020EFER"              /* Load MSR_EFER */
2623         );
2624         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2625             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2626                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2627                 mask = msr;
2628                 printf("\n        EPT Features=0x%b", mask,
2629                 "\020"
2630                 "\001XO"                /* Execute-only translations */
2631                 "\007PW4"               /* Page-walk length of 4 */
2632                 "\011UC"                /* EPT paging-structure mem can be UC */
2633                 "\017WB"                /* EPT paging-structure mem can be WB */
2634                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2635                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2636                 "\025INVEPT"            /* INVEPT is supported */
2637                 "\026AD"                /* Accessed and dirty flags for EPT */
2638                 "\032single"            /* INVEPT single-context type */
2639                 "\033all"               /* INVEPT all-context type */
2640                 );
2641                 mask = msr >> 32;
2642                 printf("\n        VPID Features=0x%b", mask,
2643                 "\020"
2644                 "\001INVVPID"           /* INVVPID is supported */
2645                 "\011individual"        /* INVVPID individual-address type */
2646                 "\012single"            /* INVVPID single-context type */
2647                 "\013all"               /* INVVPID all-context type */
2648                  /* INVVPID single-context-retaining-globals type */
2649                 "\014single-globals"
2650                 );
2651         }
2652 }
2653
2654 static void
2655 print_hypervisor_info(void)
2656 {
2657
2658         if (*hv_vendor != '\0')
2659                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2660 }
2661
2662 /*
2663  * Returns the maximum physical address that can be used with the
2664  * current system.
2665  */
2666 vm_paddr_t
2667 cpu_getmaxphyaddr(void)
2668 {
2669
2670 #if defined(__i386__)
2671         if (!pae_mode)
2672                 return (0xffffffff);
2673 #endif
2674         return ((1ULL << cpu_maxphyaddr) - 1);
2675 }