sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
  71 #define CPU_ENABLE_SSE
  72 #endif
  73
  74 #define IDENTBLUE_CYRIX486      0
  75 #define IDENTBLUE_IBMCPU        1
  76 #define IDENTBLUE_CYRIXM2       2
  77
  78 static void identifycyrix(void);
  79 static void print_transmeta_info(void);
  80 #endif
  81 static u_int find_cpu_vendor_id(void);
  82 static void print_AMD_info(void);
  83 static void print_INTEL_info(void);
  84 static void print_INTEL_TLB(u_int data);
  85 static void print_hypervisor_info(void);
  86 static void print_svm_info(void);
  87 static void print_via_padlock_info(void);
  88 static void print_vmx_info(void);
  89
  90 #ifdef __i386__
  91 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  92 int     cpu_class;
  93 #endif
  94 u_int   cpu_feature;            /* Feature flags */
  95 u_int   cpu_feature2;           /* Feature flags */
  96 u_int   amd_feature;            /* AMD feature flags */
  97 u_int   amd_feature2;           /* AMD feature flags */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   via_feature_rng;        /* VIA RNG features */
 100 u_int   via_feature_xcrypt;     /* VIA ACE features */
 101 u_int   cpu_high;               /* Highest arg to CPUID */
 102 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 103 u_int   cpu_id;                 /* Stepping ID */
 104 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 105 u_int   cpu_procinfo2;          /* Multicore info */
 106 char    cpu_vendor[20];         /* CPU Origin code */
 107 u_int   cpu_vendor_id;          /* CPU vendor ID */
 108 #if defined(__amd64__) || defined(CPU_ENABLE_SSE)
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 #endif
 112 u_int   cpu_clflush_line_size = 32;
 113 u_int   cpu_stdext_feature;
 114 u_int   cpu_stdext_feature2;
 115 u_int   cpu_max_ext_state_size;
 116 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 117 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 118 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 120 char machine[] = MACHINE;
 121
 122 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 123     &via_feature_rng, 0,
 124     "VIA RNG feature available in CPU");
 125 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 126     &via_feature_xcrypt, 0,
 127     "VIA xcrypt feature available in CPU");
 128
 129 #ifdef __amd64__
 130 #ifdef SCTL_MASK32
 131 extern int adaptive_machine_arch;
 132 #endif
 133
 134 static int
 135 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 136 {
 137 #ifdef SCTL_MASK32
 138         static const char machine32[] = "i386";
 139 #endif
 140         int error;
 141
 142 #ifdef SCTL_MASK32
 143         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 144                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 145         else
 146 #endif
 147                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 148         return (error);
 149
 150 }
 151 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 152     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 153 #else
 154 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 155     machine, 0, "Machine class");
 156 #endif
 157
 158 static char cpu_model[128];
 159 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 160     cpu_model, 0, "Machine model");
 161
 162 static int hw_clockrate;
 163 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 164     &hw_clockrate, 0, "CPU instruction clock rate");
 165
 166 u_int hv_high;
 167 char hv_vendor[16];
 168 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 169     0, "Hypervisor vendor");
 170
 171 static eventhandler_tag tsc_post_tag;
 172
 173 static char cpu_brand[48];
 174
 175 #ifdef __i386__
 176 #define MAX_BRAND_INDEX 8
 177
 178 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 179         NULL,                   /* No brand */
 180         "Intel Celeron",
 181         "Intel Pentium III",
 182         "Intel Pentium III Xeon",
 183         NULL,
 184         NULL,
 185         NULL,
 186         NULL,
 187         "Intel Pentium 4"
 188 };
 189
 190 static struct {
 191         char    *cpu_name;
 192         int     cpu_class;
 193 } cpus[] = {
 194         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 195         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 196         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 197         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 198         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 199         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 200         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 201         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 202         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 203         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 204         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 205         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 206         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 207         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 208         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 209         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 210         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 211 };
 212 #endif
 213
 214 static struct {
 215         char    *vendor;
 216         u_int   vendor_id;
 217 } cpu_vendors[] = {
 218         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 219         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 220         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 221 #ifdef __i386__
 222         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 223         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 224         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 225         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 226         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 227         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 228         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 229 #if 0
 230         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 231         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 232 #endif
 233 #endif
 234 };
 235
 236 void
 237 printcpuinfo(void)
 238 {
 239         u_int regs[4], i;
 240         char *brand;
 241
 242         printf("CPU: ");
 243 #ifdef __i386__
 244         cpu_class = cpus[cpu].cpu_class;
 245         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 246 #else
 247         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 248 #endif
 249
 250         /* Check for extended CPUID information and a processor name. */
 251         if (cpu_exthigh >= 0x80000004) {
 252                 brand = cpu_brand;
 253                 for (i = 0x80000002; i < 0x80000005; i++) {
 254                         do_cpuid(i, regs);
 255                         memcpy(brand, regs, sizeof(regs));
 256                         brand += sizeof(regs);
 257                 }
 258         }
 259
 260         switch (cpu_vendor_id) {
 261         case CPU_VENDOR_INTEL:
 262 #ifdef __i386__
 263                 if ((cpu_id & 0xf00) > 0x300) {
 264                         u_int brand_index;
 265
 266                         cpu_model[0] = '\0';
 267
 268                         switch (cpu_id & 0x3000) {
 269                         case 0x1000:
 270                                 strcpy(cpu_model, "Overdrive ");
 271                                 break;
 272                         case 0x2000:
 273                                 strcpy(cpu_model, "Dual ");
 274                                 break;
 275                         }
 276
 277                         switch (cpu_id & 0xf00) {
 278                         case 0x400:
 279                                 strcat(cpu_model, "i486 ");
 280                                 /* Check the particular flavor of 486 */
 281                                 switch (cpu_id & 0xf0) {
 282                                 case 0x00:
 283                                 case 0x10:
 284                                         strcat(cpu_model, "DX");
 285                                         break;
 286                                 case 0x20:
 287                                         strcat(cpu_model, "SX");
 288                                         break;
 289                                 case 0x30:
 290                                         strcat(cpu_model, "DX2");
 291                                         break;
 292                                 case 0x40:
 293                                         strcat(cpu_model, "SL");
 294                                         break;
 295                                 case 0x50:
 296                                         strcat(cpu_model, "SX2");
 297                                         break;
 298                                 case 0x70:
 299                                         strcat(cpu_model,
 300                                             "DX2 Write-Back Enhanced");
 301                                         break;
 302                                 case 0x80:
 303                                         strcat(cpu_model, "DX4");
 304                                         break;
 305                                 }
 306                                 break;
 307                         case 0x500:
 308                                 /* Check the particular flavor of 586 */
 309                                 strcat(cpu_model, "Pentium");
 310                                 switch (cpu_id & 0xf0) {
 311                                 case 0x00:
 312                                         strcat(cpu_model, " A-step");
 313                                         break;
 314                                 case 0x10:
 315                                         strcat(cpu_model, "/P5");
 316                                         break;
 317                                 case 0x20:
 318                                         strcat(cpu_model, "/P54C");
 319                                         break;
 320                                 case 0x30:
 321                                         strcat(cpu_model, "/P24T");
 322                                         break;
 323                                 case 0x40:
 324                                         strcat(cpu_model, "/P55C");
 325                                         break;
 326                                 case 0x70:
 327                                         strcat(cpu_model, "/P54C");
 328                                         break;
 329                                 case 0x80:
 330                                         strcat(cpu_model, "/P55C (quarter-micron)");
 331                                         break;
 332                                 default:
 333                                         /* nothing */
 334                                         break;
 335                                 }
 336 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 337                                 /*
 338                                  * XXX - If/when Intel fixes the bug, this
 339                                  * should also check the version of the
 340                                  * CPU, not just that it's a Pentium.
 341                                  */
 342                                 has_f00f_bug = 1;
 343 #endif
 344                                 break;
 345                         case 0x600:
 346                                 /* Check the particular flavor of 686 */
 347                                 switch (cpu_id & 0xf0) {
 348                                 case 0x00:
 349                                         strcat(cpu_model, "Pentium Pro A-step");
 350                                         break;
 351                                 case 0x10:
 352                                         strcat(cpu_model, "Pentium Pro");
 353                                         break;
 354                                 case 0x30:
 355                                 case 0x50:
 356                                 case 0x60:
 357                                         strcat(cpu_model,
 358                                 "Pentium II/Pentium II Xeon/Celeron");
 359                                         cpu = CPU_PII;
 360                                         break;
 361                                 case 0x70:
 362                                 case 0x80:
 363                                 case 0xa0:
 364                                 case 0xb0:
 365                                         strcat(cpu_model,
 366                                         "Pentium III/Pentium III Xeon/Celeron");
 367                                         cpu = CPU_PIII;
 368                                         break;
 369                                 default:
 370                                         strcat(cpu_model, "Unknown 80686");
 371                                         break;
 372                                 }
 373                                 break;
 374                         case 0xf00:
 375                                 strcat(cpu_model, "Pentium 4");
 376                                 cpu = CPU_P4;
 377                                 break;
 378                         default:
 379                                 strcat(cpu_model, "unknown");
 380                                 break;
 381                         }
 382
 383                         /*
 384                          * If we didn't get a brand name from the extended
 385                          * CPUID, try to look it up in the brand table.
 386                          */
 387                         if (cpu_high > 0 && *cpu_brand == '\0') {
 388                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 389                                 if (brand_index <= MAX_BRAND_INDEX &&
 390                                     cpu_brandtable[brand_index] != NULL)
 391                                         strcpy(cpu_brand,
 392                                             cpu_brandtable[brand_index]);
 393                         }
 394                 }
 395 #else
 396                 /* Please make up your mind folks! */
 397                 strcat(cpu_model, "EM64T");
 398 #endif
 399                 break;
 400         case CPU_VENDOR_AMD:
 401                 /*
 402                  * Values taken from AMD Processor Recognition
 403                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 404                  * (also describes ``Features'' encodings.
 405                  */
 406                 strcpy(cpu_model, "AMD ");
 407 #ifdef __i386__
 408                 switch (cpu_id & 0xFF0) {
 409                 case 0x410:
 410                         strcat(cpu_model, "Standard Am486DX");
 411                         break;
 412                 case 0x430:
 413                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 414                         break;
 415                 case 0x470:
 416                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 417                         break;
 418                 case 0x480:
 419                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 420                         break;
 421                 case 0x490:
 422                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 423                         break;
 424                 case 0x4E0:
 425                         strcat(cpu_model, "Am5x86 Write-Through");
 426                         break;
 427                 case 0x4F0:
 428                         strcat(cpu_model, "Am5x86 Write-Back");
 429                         break;
 430                 case 0x500:
 431                         strcat(cpu_model, "K5 model 0");
 432                         break;
 433                 case 0x510:
 434                         strcat(cpu_model, "K5 model 1");
 435                         break;
 436                 case 0x520:
 437                         strcat(cpu_model, "K5 PR166 (model 2)");
 438                         break;
 439                 case 0x530:
 440                         strcat(cpu_model, "K5 PR200 (model 3)");
 441                         break;
 442                 case 0x560:
 443                         strcat(cpu_model, "K6");
 444                         break;
 445                 case 0x570:
 446                         strcat(cpu_model, "K6 266 (model 1)");
 447                         break;
 448                 case 0x580:
 449                         strcat(cpu_model, "K6-2");
 450                         break;
 451                 case 0x590:
 452                         strcat(cpu_model, "K6-III");
 453                         break;
 454                 case 0x5a0:
 455                         strcat(cpu_model, "Geode LX");
 456                         break;
 457                 default:
 458                         strcat(cpu_model, "Unknown");
 459                         break;
 460                 }
 461 #else
 462                 if ((cpu_id & 0xf00) == 0xf00)
 463                         strcat(cpu_model, "AMD64 Processor");
 464                 else
 465                         strcat(cpu_model, "Unknown");
 466 #endif
 467                 break;
 468 #ifdef __i386__
 469         case CPU_VENDOR_CYRIX:
 470                 strcpy(cpu_model, "Cyrix ");
 471                 switch (cpu_id & 0xff0) {
 472                 case 0x440:
 473                         strcat(cpu_model, "MediaGX");
 474                         break;
 475                 case 0x520:
 476                         strcat(cpu_model, "6x86");
 477                         break;
 478                 case 0x540:
 479                         cpu_class = CPUCLASS_586;
 480                         strcat(cpu_model, "GXm");
 481                         break;
 482                 case 0x600:
 483                         strcat(cpu_model, "6x86MX");
 484                         break;
 485                 default:
 486                         /*
 487                          * Even though CPU supports the cpuid
 488                          * instruction, it can be disabled.
 489                          * Therefore, this routine supports all Cyrix
 490                          * CPUs.
 491                          */
 492                         switch (cyrix_did & 0xf0) {
 493                         case 0x00:
 494                                 switch (cyrix_did & 0x0f) {
 495                                 case 0x00:
 496                                         strcat(cpu_model, "486SLC");
 497                                         break;
 498                                 case 0x01:
 499                                         strcat(cpu_model, "486DLC");
 500                                         break;
 501                                 case 0x02:
 502                                         strcat(cpu_model, "486SLC2");
 503                                         break;
 504                                 case 0x03:
 505                                         strcat(cpu_model, "486DLC2");
 506                                         break;
 507                                 case 0x04:
 508                                         strcat(cpu_model, "486SRx");
 509                                         break;
 510                                 case 0x05:
 511                                         strcat(cpu_model, "486DRx");
 512                                         break;
 513                                 case 0x06:
 514                                         strcat(cpu_model, "486SRx2");
 515                                         break;
 516                                 case 0x07:
 517                                         strcat(cpu_model, "486DRx2");
 518                                         break;
 519                                 case 0x08:
 520                                         strcat(cpu_model, "486SRu");
 521                                         break;
 522                                 case 0x09:
 523                                         strcat(cpu_model, "486DRu");
 524                                         break;
 525                                 case 0x0a:
 526                                         strcat(cpu_model, "486SRu2");
 527                                         break;
 528                                 case 0x0b:
 529                                         strcat(cpu_model, "486DRu2");
 530                                         break;
 531                                 default:
 532                                         strcat(cpu_model, "Unknown");
 533                                         break;
 534                                 }
 535                                 break;
 536                         case 0x10:
 537                                 switch (cyrix_did & 0x0f) {
 538                                 case 0x00:
 539                                         strcat(cpu_model, "486S");
 540                                         break;
 541                                 case 0x01:
 542                                         strcat(cpu_model, "486S2");
 543                                         break;
 544                                 case 0x02:
 545                                         strcat(cpu_model, "486Se");
 546                                         break;
 547                                 case 0x03:
 548                                         strcat(cpu_model, "486S2e");
 549                                         break;
 550                                 case 0x0a:
 551                                         strcat(cpu_model, "486DX");
 552                                         break;
 553                                 case 0x0b:
 554                                         strcat(cpu_model, "486DX2");
 555                                         break;
 556                                 case 0x0f:
 557                                         strcat(cpu_model, "486DX4");
 558                                         break;
 559                                 default:
 560                                         strcat(cpu_model, "Unknown");
 561                                         break;
 562                                 }
 563                                 break;
 564                         case 0x20:
 565                                 if ((cyrix_did & 0x0f) < 8)
 566                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 567                                 else
 568                                         strcat(cpu_model, "5x86");
 569                                 break;
 570                         case 0x30:
 571                                 strcat(cpu_model, "6x86");
 572                                 break;
 573                         case 0x40:
 574                                 if ((cyrix_did & 0xf000) == 0x3000) {
 575                                         cpu_class = CPUCLASS_586;
 576                                         strcat(cpu_model, "GXm");
 577                                 } else
 578                                         strcat(cpu_model, "MediaGX");
 579                                 break;
 580                         case 0x50:
 581                                 strcat(cpu_model, "6x86MX");
 582                                 break;
 583                         case 0xf0:
 584                                 switch (cyrix_did & 0x0f) {
 585                                 case 0x0d:
 586                                         strcat(cpu_model, "Overdrive CPU");
 587                                         break;
 588                                 case 0x0e:
 589                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 590                                         break;
 591                                 case 0x0f:
 592                                         strcat(cpu_model, "486SLC/DLC");
 593                                         break;
 594                                 default:
 595                                         strcat(cpu_model, "Unknown");
 596                                         break;
 597                                 }
 598                                 break;
 599                         default:
 600                                 strcat(cpu_model, "Unknown");
 601                                 break;
 602                         }
 603                         break;
 604                 }
 605                 break;
 606         case CPU_VENDOR_RISE:
 607                 strcpy(cpu_model, "Rise ");
 608                 switch (cpu_id & 0xff0) {
 609                 case 0x500:     /* 6401 and 6441 (Kirin) */
 610                 case 0x520:     /* 6510 (Lynx) */
 611                         strcat(cpu_model, "mP6");
 612                         break;
 613                 default:
 614                         strcat(cpu_model, "Unknown");
 615                 }
 616                 break;
 617 #endif
 618         case CPU_VENDOR_CENTAUR:
 619 #ifdef __i386__
 620                 switch (cpu_id & 0xff0) {
 621                 case 0x540:
 622                         strcpy(cpu_model, "IDT WinChip C6");
 623                         break;
 624                 case 0x580:
 625                         strcpy(cpu_model, "IDT WinChip 2");
 626                         break;
 627                 case 0x590:
 628                         strcpy(cpu_model, "IDT WinChip 3");
 629                         break;
 630                 case 0x660:
 631                         strcpy(cpu_model, "VIA C3 Samuel");
 632                         break;
 633                 case 0x670:
 634                         if (cpu_id & 0x8)
 635                                 strcpy(cpu_model, "VIA C3 Ezra");
 636                         else
 637                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 638                         break;
 639                 case 0x680:
 640                         strcpy(cpu_model, "VIA C3 Ezra-T");
 641                         break;
 642                 case 0x690:
 643                         strcpy(cpu_model, "VIA C3 Nehemiah");
 644                         break;
 645                 case 0x6a0:
 646                 case 0x6d0:
 647                         strcpy(cpu_model, "VIA C7 Esther");
 648                         break;
 649                 case 0x6f0:
 650                         strcpy(cpu_model, "VIA Nano");
 651                         break;
 652                 default:
 653                         strcpy(cpu_model, "VIA/IDT Unknown");
 654                 }
 655 #else
 656                 strcpy(cpu_model, "VIA ");
 657                 if ((cpu_id & 0xff0) == 0x6f0)
 658                         strcat(cpu_model, "Nano Processor");
 659                 else
 660                         strcat(cpu_model, "Unknown");
 661 #endif
 662                 break;
 663 #ifdef __i386__
 664         case CPU_VENDOR_IBM:
 665                 strcpy(cpu_model, "Blue Lightning CPU");
 666                 break;
 667         case CPU_VENDOR_NSC:
 668                 switch (cpu_id & 0xff0) {
 669                 case 0x540:
 670                         strcpy(cpu_model, "Geode SC1100");
 671                         cpu = CPU_GEODE1100;
 672                         break;
 673                 default:
 674                         strcpy(cpu_model, "Geode/NSC unknown");
 675                         break;
 676                 }
 677                 break;
 678 #endif
 679         default:
 680                 strcat(cpu_model, "Unknown");
 681                 break;
 682         }
 683
 684         /*
 685          * Replace cpu_model with cpu_brand minus leading spaces if
 686          * we have one.
 687          */
 688         brand = cpu_brand;
 689         while (*brand == ' ')
 690                 ++brand;
 691         if (*brand != '\0')
 692                 strcpy(cpu_model, brand);
 693
 694         printf("%s (", cpu_model);
 695         if (tsc_freq != 0) {
 696                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 697                 printf("%jd.%02d-MHz ",
 698                     (intmax_t)(tsc_freq + 4999) / 1000000,
 699                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 700         }
 701 #ifdef __i386__
 702         switch(cpu_class) {
 703         case CPUCLASS_286:
 704                 printf("286");
 705                 break;
 706         case CPUCLASS_386:
 707                 printf("386");
 708                 break;
 709 #if defined(I486_CPU)
 710         case CPUCLASS_486:
 711                 printf("486");
 712                 break;
 713 #endif
 714 #if defined(I586_CPU)
 715         case CPUCLASS_586:
 716                 printf("586");
 717                 break;
 718 #endif
 719 #if defined(I686_CPU)
 720         case CPUCLASS_686:
 721                 printf("686");
 722                 break;
 723 #endif
 724         default:
 725                 printf("Unknown");      /* will panic below... */
 726         }
 727 #else
 728         printf("K8");
 729 #endif
 730         printf("-class CPU)\n");
 731         if (*cpu_vendor)
 732                 printf("  Origin=\"%s\"", cpu_vendor);
 733         if (cpu_id)
 734                 printf("  Id=0x%x", cpu_id);
 735
 736         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 737             cpu_vendor_id == CPU_VENDOR_AMD ||
 738             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 739 #ifdef __i386__
 740             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 741             cpu_vendor_id == CPU_VENDOR_RISE ||
 742             cpu_vendor_id == CPU_VENDOR_NSC ||
 743             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 744 #endif
 745             0) {
 746                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 747                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 748                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 749 #ifdef __i386__
 750                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 751                         printf("\n  DIR=0x%04x", cyrix_did);
 752 #endif
 753
 754                 /*
 755                  * AMD CPUID Specification
 756                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 757                  *
 758                  * Intel Processor Identification and CPUID Instruction
 759                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 760                  */
 761                 if (cpu_high > 0) {
 762
 763                         /*
 764                          * Here we should probably set up flags indicating
 765                          * whether or not various features are available.
 766                          * The interesting ones are probably VME, PSE, PAE,
 767                          * and PGE.  The code already assumes without bothering
 768                          * to check that all CPUs >= Pentium have a TSC and
 769                          * MSRs.
 770                          */
 771                         printf("\n  Features=0x%b", cpu_feature,
 772                         "\020"
 773                         "\001FPU"       /* Integral FPU */
 774                         "\002VME"       /* Extended VM86 mode support */
 775                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 776                         "\004PSE"       /* 4MByte page tables */
 777                         "\005TSC"       /* Timestamp counter */
 778                         "\006MSR"       /* Machine specific registers */
 779                         "\007PAE"       /* Physical address extension */
 780                         "\010MCE"       /* Machine Check support */
 781                         "\011CX8"       /* CMPEXCH8 instruction */
 782                         "\012APIC"      /* SMP local APIC */
 783                         "\013oldMTRR"   /* Previous implementation of MTRR */
 784                         "\014SEP"       /* Fast System Call */
 785                         "\015MTRR"      /* Memory Type Range Registers */
 786                         "\016PGE"       /* PG_G (global bit) support */
 787                         "\017MCA"       /* Machine Check Architecture */
 788                         "\020CMOV"      /* CMOV instruction */
 789                         "\021PAT"       /* Page attributes table */
 790                         "\022PSE36"     /* 36 bit address space support */
 791                         "\023PN"        /* Processor Serial number */
 792                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 793                         "\025<b20>"
 794                         "\026DTS"       /* Debug Trace Store */
 795                         "\027ACPI"      /* ACPI support */
 796                         "\030MMX"       /* MMX instructions */
 797                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 798                         "\032SSE"       /* Streaming SIMD Extensions */
 799                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 800                         "\034SS"        /* Self snoop */
 801                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 802                         "\036TM"        /* Thermal Monitor clock slowdown */
 803                         "\037IA64"      /* CPU can execute IA64 instructions */
 804                         "\040PBE"       /* Pending Break Enable */
 805                         );
 806
 807                         if (cpu_feature2 != 0) {
 808                                 printf("\n  Features2=0x%b", cpu_feature2,
 809                                 "\020"
 810                                 "\001SSE3"      /* SSE3 */
 811                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 812                                 "\003DTES64"    /* 64-bit Debug Trace */
 813                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 814                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 815                                 "\006VMX"       /* Virtual Machine Extensions */
 816                                 "\007SMX"       /* Safer Mode Extensions */
 817                                 "\010EST"       /* Enhanced SpeedStep */
 818                                 "\011TM2"       /* Thermal Monitor 2 */
 819                                 "\012SSSE3"     /* SSSE3 */
 820                                 "\013CNXT-ID"   /* L1 context ID available */
 821                                 "\014SDBG"      /* IA32 silicon debug */
 822                                 "\015FMA"       /* Fused Multiply Add */
 823                                 "\016CX16"      /* CMPXCHG16B Instruction */
 824                                 "\017xTPR"      /* Send Task Priority Messages*/
 825                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 826                                 "\021<b16>"
 827                                 "\022PCID"      /* Process-context Identifiers*/
 828                                 "\023DCA"       /* Direct Cache Access */
 829                                 "\024SSE4.1"    /* SSE 4.1 */
 830                                 "\025SSE4.2"    /* SSE 4.2 */
 831                                 "\026x2APIC"    /* xAPIC Extensions */
 832                                 "\027MOVBE"     /* MOVBE Instruction */
 833                                 "\030POPCNT"    /* POPCNT Instruction */
 834                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 835                                 "\032AESNI"     /* AES Crypto */
 836                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 837                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 838                                 "\035AVX"       /* Advanced Vector Extensions */
 839                                 "\036F16C"      /* Half-precision conversions */
 840                                 "\037RDRAND"    /* RDRAND Instruction */
 841                                 "\040HV"        /* Hypervisor */
 842                                 );
 843                         }
 844
 845                         if (amd_feature != 0) {
 846                                 printf("\n  AMD Features=0x%b", amd_feature,
 847                                 "\020"          /* in hex */
 848                                 "\001<s0>"      /* Same */
 849                                 "\002<s1>"      /* Same */
 850                                 "\003<s2>"      /* Same */
 851                                 "\004<s3>"      /* Same */
 852                                 "\005<s4>"      /* Same */
 853                                 "\006<s5>"      /* Same */
 854                                 "\007<s6>"      /* Same */
 855                                 "\010<s7>"      /* Same */
 856                                 "\011<s8>"      /* Same */
 857                                 "\012<s9>"      /* Same */
 858                                 "\013<b10>"     /* Undefined */
 859                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 860                                 "\015<s12>"     /* Same */
 861                                 "\016<s13>"     /* Same */
 862                                 "\017<s14>"     /* Same */
 863                                 "\020<s15>"     /* Same */
 864                                 "\021<s16>"     /* Same */
 865                                 "\022<s17>"     /* Same */
 866                                 "\023<b18>"     /* Reserved, unknown */
 867                                 "\024MP"        /* Multiprocessor Capable */
 868                                 "\025NX"        /* Has EFER.NXE, NX */
 869                                 "\026<b21>"     /* Undefined */
 870                                 "\027MMX+"      /* AMD MMX Extensions */
 871                                 "\030<s23>"     /* Same */
 872                                 "\031<s24>"     /* Same */
 873                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 874                                 "\033Page1GB"   /* 1-GB large page support */
 875                                 "\034RDTSCP"    /* RDTSCP */
 876                                 "\035<b28>"     /* Undefined */
 877                                 "\036LM"        /* 64 bit long mode */
 878                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 879                                 "\0403DNow!"    /* AMD 3DNow! */
 880                                 );
 881                         }
 882
 883                         if (amd_feature2 != 0) {
 884                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 885                                 "\020"
 886                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 887                                 "\002CMP"       /* CMP legacy */
 888                                 "\003SVM"       /* Secure Virtual Mode */
 889                                 "\004ExtAPIC"   /* Extended APIC register */
 890                                 "\005CR8"       /* CR8 in legacy mode */
 891                                 "\006ABM"       /* LZCNT instruction */
 892                                 "\007SSE4A"     /* SSE4A */
 893                                 "\010MAS"       /* Misaligned SSE mode */
 894                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 895                                 "\012OSVW"      /* OS visible workaround */
 896                                 "\013IBS"       /* Instruction based sampling */
 897                                 "\014XOP"       /* XOP extended instructions */
 898                                 "\015SKINIT"    /* SKINIT/STGI */
 899                                 "\016WDT"       /* Watchdog timer */
 900                                 "\017<b14>"
 901                                 "\020LWP"       /* Lightweight Profiling */
 902                                 "\021FMA4"      /* 4-operand FMA instructions */
 903                                 "\022TCE"       /* Translation Cache Extension */
 904                                 "\023<b18>"
 905                                 "\024NodeId"    /* NodeId MSR support */
 906                                 "\025<b20>"
 907                                 "\026TBM"       /* Trailing Bit Manipulation */
 908                                 "\027Topology"  /* Topology Extensions */
 909                                 "\030PCXC"      /* Core perf count */
 910                                 "\031PNXC"      /* NB perf count */
 911                                 "\032<b25>"
 912                                 "\033DBE"       /* Data Breakpoint extension */
 913                                 "\034PTSC"      /* Performance TSC */
 914                                 "\035PL2I"      /* L2I perf count */
 915                                 "\036<b29>"
 916                                 "\037<b30>"
 917                                 "\040<b31>"
 918                                 );
 919                         }
 920
 921                         if (cpu_stdext_feature != 0) {
 922                                 printf("\n  Structured Extended Features=0x%b",
 923                                     cpu_stdext_feature,
 924                                        "\020"
 925                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 926                                        "\001FSGSBASE"
 927                                        "\002TSCADJ"
 928                                        "\003SGX"
 929                                        /* Bit Manipulation Instructions */
 930                                        "\004BMI1"
 931                                        /* Hardware Lock Elision */
 932                                        "\005HLE"
 933                                        /* Advanced Vector Instructions 2 */
 934                                        "\006AVX2"
 935                                        /* FDP_EXCPTN_ONLY */
 936                                        "\007FDPEXC"
 937                                        /* Supervisor Mode Execution Prot. */
 938                                        "\010SMEP"
 939                                        /* Bit Manipulation Instructions */
 940                                        "\011BMI2"
 941                                        "\012ERMS"
 942                                        /* Invalidate Processor Context ID */
 943                                        "\013INVPCID"
 944                                        /* Restricted Transactional Memory */
 945                                        "\014RTM"
 946                                        "\015PQM"
 947                                        "\016NFPUSG"
 948                                        /* Intel Memory Protection Extensions */
 949                                        "\017MPX"
 950                                        "\020PQE"
 951                                        /* AVX512 Foundation */
 952                                        "\021AVX512F"
 953                                        "\022AVX512DQ"
 954                                        /* Enhanced NRBG */
 955                                        "\023RDSEED"
 956                                        /* ADCX + ADOX */
 957                                        "\024ADX"
 958                                        /* Supervisor Mode Access Prevention */
 959                                        "\025SMAP"
 960                                        "\026AVX512IFMA"
 961                                        "\027PCOMMIT"
 962                                        "\030CLFLUSHOPT"
 963                                        "\031CLWB"
 964                                        "\032PROCTRACE"
 965                                        "\033AVX512PF"
 966                                        "\034AVX512ER"
 967                                        "\035AVX512CD"
 968                                        "\036SHA"
 969                                        "\037AVX512BW"
 970                                        );
 971                         }
 972
 973                         if (cpu_stdext_feature2 != 0) {
 974                                 printf("\n  Structured Extended Features2=0x%b",
 975                                     cpu_stdext_feature2,
 976                                        "\020"
 977                                        "\001PREFETCHWT1"
 978                                        "\002AVX512VBMI"
 979                                        "\003UMIP"
 980                                        "\004PKU"
 981                                        "\005OSPKE"
 982                                        "\027RDPID"
 983                                        "\037SGXLC"
 984                                        );
 985                         }
 986
 987                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 988                                 cpuid_count(0xd, 0x1, regs);
 989                                 if (regs[0] != 0) {
 990                                         printf("\n  XSAVE Features=0x%b",
 991                                             regs[0],
 992                                             "\020"
 993                                             "\001XSAVEOPT"
 994                                             "\002XSAVEC"
 995                                             "\003XINUSE"
 996                                             "\004XSAVES");
 997                                 }
 998                         }
 999
1000                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1001                                 print_via_padlock_info();
1002
1003                         if (cpu_feature2 & CPUID2_VMX)
1004                                 print_vmx_info();
1005
1006                         if (amd_feature2 & AMDID2_SVM)
1007                                 print_svm_info();
1008
1009                         if ((cpu_feature & CPUID_HTT) &&
1010                             cpu_vendor_id == CPU_VENDOR_AMD)
1011                                 cpu_feature &= ~CPUID_HTT;
1012
1013                         /*
1014                          * If this CPU supports P-state invariant TSC then
1015                          * mention the capability.
1016                          */
1017                         if (tsc_is_invariant) {
1018                                 printf("\n  TSC: P-state invariant");
1019                                 if (tsc_perf_stat)
1020                                         printf(", performance statistics");
1021                         }
1022                 }
1023 #ifdef __i386__
1024         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1025                 printf("  DIR=0x%04x", cyrix_did);
1026                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1027                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1028 #ifndef CYRIX_CACHE_REALLY_WORKS
1029                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1030                         printf("\n  CPU cache: write-through mode");
1031 #endif
1032 #endif
1033         }
1034
1035         /* Avoid ugly blank lines: only print newline when we have to. */
1036         if (*cpu_vendor || cpu_id)
1037                 printf("\n");
1038
1039         if (bootverbose) {
1040                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1041                         print_AMD_info();
1042                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1043                         print_INTEL_info();
1044 #ifdef __i386__
1045                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1046                         print_transmeta_info();
1047 #endif
1048         }
1049
1050         print_hypervisor_info();
1051 }
1052
1053 #ifdef __i386__
1054 void
1055 panicifcpuunsupported(void)
1056 {
1057
1058 #if !defined(lint)
1059 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1060 #error This kernel is not configured for one of the supported CPUs
1061 #endif
1062 #else /* lint */
1063 #endif /* lint */
1064         /*
1065          * Now that we have told the user what they have,
1066          * let them know if that machine type isn't configured.
1067          */
1068         switch (cpu_class) {
1069         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1070         case CPUCLASS_386:
1071 #if !defined(I486_CPU)
1072         case CPUCLASS_486:
1073 #endif
1074 #if !defined(I586_CPU)
1075         case CPUCLASS_586:
1076 #endif
1077 #if !defined(I686_CPU)
1078         case CPUCLASS_686:
1079 #endif
1080                 panic("CPU class not configured");
1081         default:
1082                 break;
1083         }
1084 }
1085
1086 static  volatile u_int trap_by_rdmsr;
1087
1088 /*
1089  * Special exception 6 handler.
1090  * The rdmsr instruction generates invalid opcodes fault on 486-class
1091  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1092  * function identblue() when this handler is called.  Stacked eip should
1093  * be advanced.
1094  */
1095 inthand_t       bluetrap6;
1096 #ifdef __GNUCLIKE_ASM
1097 __asm
1098 ("                                                                      \n\
1099         .text                                                           \n\
1100         .p2align 2,0x90                                                 \n\
1101         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1102 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1103         ss                                                              \n\
1104         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1105         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1106         iret                                                            \n\
1107 ");
1108 #endif
1109
1110 /*
1111  * Special exception 13 handler.
1112  * Accessing non-existent MSR generates general protection fault.
1113  */
1114 inthand_t       bluetrap13;
1115 #ifdef __GNUCLIKE_ASM
1116 __asm
1117 ("                                                                      \n\
1118         .text                                                           \n\
1119         .p2align 2,0x90                                                 \n\
1120         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1121 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1122         ss                                                              \n\
1123         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1124         popl    %eax            /* discard error code */                \n\
1125         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1126         iret                                                            \n\
1127 ");
1128 #endif
1129
1130 /*
1131  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1132  * support cpuid instruction.  This function should be called after
1133  * loading interrupt descriptor table register.
1134  *
1135  * I don't like this method that handles fault, but I couldn't get
1136  * information for any other methods.  Does blue giant know?
1137  */
1138 static int
1139 identblue(void)
1140 {
1141
1142         trap_by_rdmsr = 0;
1143
1144         /*
1145          * Cyrix 486-class CPU does not support rdmsr instruction.
1146          * The rdmsr instruction generates invalid opcode fault, and exception
1147          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1148          * bluetrap6() set the magic number to trap_by_rdmsr.
1149          */
1150         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1151             GSEL(GCODE_SEL, SEL_KPL));
1152
1153         /*
1154          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1155          * In this case, rdmsr generates general protection fault, and
1156          * exception will be trapped by bluetrap13().
1157          */
1158         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1159             GSEL(GCODE_SEL, SEL_KPL));
1160
1161         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1162
1163         if (trap_by_rdmsr == 0xa8c1d)
1164                 return IDENTBLUE_CYRIX486;
1165         else if (trap_by_rdmsr == 0xa89c4)
1166                 return IDENTBLUE_CYRIXM2;
1167         return IDENTBLUE_IBMCPU;
1168 }
1169
1170
1171 /*
1172  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1173  *
1174  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1175  * +-------+-------+---------------+
1176  * |  SID  |  RID  |   Device ID   |
1177  * |    (DIR 1)    |    (DIR 0)    |
1178  * +-------+-------+---------------+
1179  */
1180 static void
1181 identifycyrix(void)
1182 {
1183         register_t saveintr;
1184         int     ccr2_test = 0, dir_test = 0;
1185         u_char  ccr2, ccr3;
1186
1187         saveintr = intr_disable();
1188
1189         ccr2 = read_cyrix_reg(CCR2);
1190         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1191         read_cyrix_reg(CCR2);
1192         if (read_cyrix_reg(CCR2) != ccr2)
1193                 ccr2_test = 1;
1194         write_cyrix_reg(CCR2, ccr2);
1195
1196         ccr3 = read_cyrix_reg(CCR3);
1197         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1198         read_cyrix_reg(CCR3);
1199         if (read_cyrix_reg(CCR3) != ccr3)
1200                 dir_test = 1;                                   /* CPU supports DIRs. */
1201         write_cyrix_reg(CCR3, ccr3);
1202
1203         if (dir_test) {
1204                 /* Device ID registers are available. */
1205                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1206                 cyrix_did += read_cyrix_reg(DIR0);
1207         } else if (ccr2_test)
1208                 cyrix_did = 0x0010;             /* 486S A-step */
1209         else
1210                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1211
1212         intr_restore(saveintr);
1213 }
1214 #endif
1215
1216 /* Update TSC freq with the value indicated by the caller. */
1217 static void
1218 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1219 {
1220
1221         /* If there was an error during the transition, don't do anything. */
1222         if (status != 0)
1223                 return;
1224
1225         /* Total setting for this level gives the new frequency in MHz. */
1226         hw_clockrate = level->total_set.freq;
1227 }
1228
1229 static void
1230 hook_tsc_freq(void *arg __unused)
1231 {
1232
1233         if (tsc_is_invariant)
1234                 return;
1235
1236         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1237             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1238 }
1239
1240 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1241
1242 static const char *const vm_bnames[] = {
1243         "QEMU",                         /* QEMU */
1244         "Plex86",                       /* Plex86 */
1245         "Bochs",                        /* Bochs */
1246         "Xen",                          /* Xen */
1247         "BHYVE",                        /* bhyve */
1248         "Seabios",                      /* KVM */
1249         NULL
1250 };
1251
1252 static const char *const vm_pnames[] = {
1253         "VMware Virtual Platform",      /* VMWare VM */
1254         "Virtual Machine",              /* Microsoft VirtualPC */
1255         "VirtualBox",                   /* Sun xVM VirtualBox */
1256         "Parallels Virtual Platform",   /* Parallels VM */
1257         "KVM",                          /* KVM */
1258         NULL
1259 };
1260
1261 static void
1262 identify_hypervisor(void)
1263 {
1264         u_int regs[4];
1265         char *p;
1266         int i;
1267
1268         /*
1269          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1270          * http://lkml.org/lkml/2008/10/1/246
1271          *
1272          * KB1009458: Mechanisms to determine if software is running in
1273          * a VMware virtual machine
1274          * http://kb.vmware.com/kb/1009458
1275          */
1276         if (cpu_feature2 & CPUID2_HV) {
1277                 vm_guest = VM_GUEST_VM;
1278                 do_cpuid(0x40000000, regs);
1279                 if (regs[0] >= 0x40000000) {
1280                         hv_high = regs[0];
1281                         ((u_int *)&hv_vendor)[0] = regs[1];
1282                         ((u_int *)&hv_vendor)[1] = regs[2];
1283                         ((u_int *)&hv_vendor)[2] = regs[3];
1284                         hv_vendor[12] = '\0';
1285                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1286                                 vm_guest = VM_GUEST_VMWARE;
1287                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1288                                 vm_guest = VM_GUEST_HV;
1289                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1290                                 vm_guest = VM_GUEST_KVM;
1291                 }
1292                 return;
1293         }
1294
1295         /*
1296          * Examine SMBIOS strings for older hypervisors.
1297          */
1298         p = kern_getenv("smbios.system.serial");
1299         if (p != NULL) {
1300                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1301                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1302                         if (regs[1] == VMW_HVMAGIC) {
1303                                 vm_guest = VM_GUEST_VMWARE;
1304                                 freeenv(p);
1305                                 return;
1306                         }
1307                 }
1308                 freeenv(p);
1309         }
1310
1311         /*
1312          * XXX: Some of these entries may not be needed since they were
1313          * added to FreeBSD before the checks above.
1314          */
1315         p = kern_getenv("smbios.bios.vendor");
1316         if (p != NULL) {
1317                 for (i = 0; vm_bnames[i] != NULL; i++)
1318                         if (strcmp(p, vm_bnames[i]) == 0) {
1319                                 vm_guest = VM_GUEST_VM;
1320                                 freeenv(p);
1321                                 return;
1322                         }
1323                 freeenv(p);
1324         }
1325         p = kern_getenv("smbios.system.product");
1326         if (p != NULL) {
1327                 for (i = 0; vm_pnames[i] != NULL; i++)
1328                         if (strcmp(p, vm_pnames[i]) == 0) {
1329                                 vm_guest = VM_GUEST_VM;
1330                                 freeenv(p);
1331                                 return;
1332                         }
1333                 freeenv(p);
1334         }
1335 }
1336
1337 bool
1338 fix_cpuid(void)
1339 {
1340         uint64_t msr;
1341
1342         /*
1343          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1344          * get the largest standard CPUID function number again if it is set
1345          * from BIOS.  It is necessary for probing correct CPU topology later
1346          * and for the correct operation of the AVX-aware userspace.
1347          */
1348         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1349             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1350             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1351             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1352             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1353                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1354                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1355                         msr &= ~IA32_MISC_EN_LIMCPUID;
1356                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1357                         return (true);
1358                 }
1359         }
1360
1361         /*
1362          * Re-enable AMD Topology Extension that could be disabled by BIOS
1363          * on some notebook processors.  Without the extension it's really
1364          * hard to determine the correct CPU cache topology.
1365          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1366          * Models 60h-6Fh Processors, Publication # 50742.
1367          */
1368         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1369                 msr = rdmsr(MSR_EXTFEATURES);
1370                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1371                         msr |= (uint64_t)1 << 54;
1372                         wrmsr(MSR_EXTFEATURES, msr);
1373                         return (true);
1374                 }
1375         }
1376         return (false);
1377 }
1378
1379 /*
1380  * Final stage of CPU identification.
1381  */
1382 #ifdef __i386__
1383 void
1384 finishidentcpu(void)
1385 #else
1386 void
1387 identify_cpu(void)
1388 #endif
1389 {
1390         u_int regs[4], cpu_stdext_disable;
1391 #ifdef __i386__
1392         u_char ccr3;
1393 #endif
1394
1395 #ifdef __amd64__
1396         do_cpuid(0, regs);
1397         cpu_high = regs[0];
1398         ((u_int *)&cpu_vendor)[0] = regs[1];
1399         ((u_int *)&cpu_vendor)[1] = regs[3];
1400         ((u_int *)&cpu_vendor)[2] = regs[2];
1401         cpu_vendor[12] = '\0';
1402
1403         do_cpuid(1, regs);
1404         cpu_id = regs[0];
1405         cpu_procinfo = regs[1];
1406         cpu_feature = regs[3];
1407         cpu_feature2 = regs[2];
1408 #endif
1409
1410         identify_hypervisor();
1411         cpu_vendor_id = find_cpu_vendor_id();
1412
1413         if (fix_cpuid()) {
1414                 do_cpuid(0, regs);
1415                 cpu_high = regs[0];
1416         }
1417
1418         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1419                 do_cpuid(5, regs);
1420                 cpu_mon_mwait_flags = regs[2];
1421                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1422                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1423         }
1424
1425         if (cpu_high >= 7) {
1426                 cpuid_count(7, 0, regs);
1427                 cpu_stdext_feature = regs[1];
1428
1429                 /*
1430                  * Some hypervisors fail to filter out unsupported
1431                  * extended features.  For now, disable the
1432                  * extensions, activation of which requires setting a
1433                  * bit in CR4, and which VM monitors do not support.
1434                  */
1435                 if (cpu_feature2 & CPUID2_HV) {
1436                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1437                             CPUID_STDEXT_SMEP;
1438                 } else
1439                         cpu_stdext_disable = 0;
1440                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1441                 cpu_stdext_feature &= ~cpu_stdext_disable;
1442                 cpu_stdext_feature2 = regs[2];
1443         }
1444
1445 #ifdef __i386__
1446         if (cpu_high > 0 &&
1447             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1448              cpu_vendor_id == CPU_VENDOR_AMD ||
1449              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1450              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1451              cpu_vendor_id == CPU_VENDOR_NSC)) {
1452                 do_cpuid(0x80000000, regs);
1453                 if (regs[0] >= 0x80000000)
1454                         cpu_exthigh = regs[0];
1455         }
1456 #else
1457         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1458             cpu_vendor_id == CPU_VENDOR_AMD ||
1459             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1460                 do_cpuid(0x80000000, regs);
1461                 cpu_exthigh = regs[0];
1462         }
1463 #endif
1464         if (cpu_exthigh >= 0x80000001) {
1465                 do_cpuid(0x80000001, regs);
1466                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1467                 amd_feature2 = regs[2];
1468         }
1469         if (cpu_exthigh >= 0x80000007) {
1470                 do_cpuid(0x80000007, regs);
1471                 amd_pminfo = regs[3];
1472         }
1473         if (cpu_exthigh >= 0x80000008) {
1474                 do_cpuid(0x80000008, regs);
1475                 cpu_maxphyaddr = regs[0] & 0xff;
1476                 cpu_procinfo2 = regs[2];
1477         } else {
1478                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1479         }
1480
1481 #ifdef __i386__
1482         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1483                 if (cpu == CPU_486) {
1484                         /*
1485                          * These conditions are equivalent to:
1486                          *     - CPU does not support cpuid instruction.
1487                          *     - Cyrix/IBM CPU is detected.
1488                          */
1489                         if (identblue() == IDENTBLUE_IBMCPU) {
1490                                 strcpy(cpu_vendor, "IBM");
1491                                 cpu_vendor_id = CPU_VENDOR_IBM;
1492                                 cpu = CPU_BLUE;
1493                                 return;
1494                         }
1495                 }
1496                 switch (cpu_id & 0xf00) {
1497                 case 0x600:
1498                         /*
1499                          * Cyrix's datasheet does not describe DIRs.
1500                          * Therefor, I assume it does not have them
1501                          * and use the result of the cpuid instruction.
1502                          * XXX they seem to have it for now at least. -Peter
1503                          */
1504                         identifycyrix();
1505                         cpu = CPU_M2;
1506                         break;
1507                 default:
1508                         identifycyrix();
1509                         /*
1510                          * This routine contains a trick.
1511                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1512                          */
1513                         switch (cyrix_did & 0x00f0) {
1514                         case 0x00:
1515                         case 0xf0:
1516                                 cpu = CPU_486DLC;
1517                                 break;
1518                         case 0x10:
1519                                 cpu = CPU_CY486DX;
1520                                 break;
1521                         case 0x20:
1522                                 if ((cyrix_did & 0x000f) < 8)
1523                                         cpu = CPU_M1;
1524                                 else
1525                                         cpu = CPU_M1SC;
1526                                 break;
1527                         case 0x30:
1528                                 cpu = CPU_M1;
1529                                 break;
1530                         case 0x40:
1531                                 /* MediaGX CPU */
1532                                 cpu = CPU_M1SC;
1533                                 break;
1534                         default:
1535                                 /* M2 and later CPUs are treated as M2. */
1536                                 cpu = CPU_M2;
1537
1538                                 /*
1539                                  * enable cpuid instruction.
1540                                  */
1541                                 ccr3 = read_cyrix_reg(CCR3);
1542                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1543                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1544                                 write_cyrix_reg(CCR3, ccr3);
1545
1546                                 do_cpuid(0, regs);
1547                                 cpu_high = regs[0];     /* eax */
1548                                 do_cpuid(1, regs);
1549                                 cpu_id = regs[0];       /* eax */
1550                                 cpu_feature = regs[3];  /* edx */
1551                                 break;
1552                         }
1553                 }
1554         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1555                 /*
1556                  * There are BlueLightning CPUs that do not change
1557                  * undefined flags by dividing 5 by 2.  In this case,
1558                  * the CPU identification routine in locore.s leaves
1559                  * cpu_vendor null string and puts CPU_486 into the
1560                  * cpu.
1561                  */
1562                 if (identblue() == IDENTBLUE_IBMCPU) {
1563                         strcpy(cpu_vendor, "IBM");
1564                         cpu_vendor_id = CPU_VENDOR_IBM;
1565                         cpu = CPU_BLUE;
1566                         return;
1567                 }
1568         }
1569 #endif
1570 }
1571
1572 static u_int
1573 find_cpu_vendor_id(void)
1574 {
1575         int     i;
1576
1577         for (i = 0; i < nitems(cpu_vendors); i++)
1578                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1579                         return (cpu_vendors[i].vendor_id);
1580         return (0);
1581 }
1582
1583 static void
1584 print_AMD_assoc(int i)
1585 {
1586         if (i == 255)
1587                 printf(", fully associative\n");
1588         else
1589                 printf(", %d-way associative\n", i);
1590 }
1591
1592 static void
1593 print_AMD_l2_assoc(int i)
1594 {
1595         switch (i & 0x0f) {
1596         case 0: printf(", disabled/not present\n"); break;
1597         case 1: printf(", direct mapped\n"); break;
1598         case 2: printf(", 2-way associative\n"); break;
1599         case 4: printf(", 4-way associative\n"); break;
1600         case 6: printf(", 8-way associative\n"); break;
1601         case 8: printf(", 16-way associative\n"); break;
1602         case 15: printf(", fully associative\n"); break;
1603         default: printf(", reserved configuration\n"); break;
1604         }
1605 }
1606
1607 static void
1608 print_AMD_info(void)
1609 {
1610 #ifdef __i386__
1611         uint64_t amd_whcr;
1612 #endif
1613         u_int regs[4];
1614
1615         if (cpu_exthigh >= 0x80000005) {
1616                 do_cpuid(0x80000005, regs);
1617                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1618                 print_AMD_assoc(regs[0] >> 24);
1619
1620                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1621                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1622
1623                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1624                 print_AMD_assoc(regs[1] >> 24);
1625
1626                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1627                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1628
1629                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1630                 printf(", %d bytes/line", regs[2] & 0xff);
1631                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1632                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1633
1634                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1635                 printf(", %d bytes/line", regs[3] & 0xff);
1636                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1637                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1638         }
1639
1640         if (cpu_exthigh >= 0x80000006) {
1641                 do_cpuid(0x80000006, regs);
1642                 if ((regs[0] >> 16) != 0) {
1643                         printf("L2 2MB data TLB: %d entries",
1644                             (regs[0] >> 16) & 0xfff);
1645                         print_AMD_l2_assoc(regs[0] >> 28);
1646                         printf("L2 2MB instruction TLB: %d entries",
1647                             regs[0] & 0xfff);
1648                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1649                 } else {
1650                         printf("L2 2MB unified TLB: %d entries",
1651                             regs[0] & 0xfff);
1652                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1653                 }
1654                 if ((regs[1] >> 16) != 0) {
1655                         printf("L2 4KB data TLB: %d entries",
1656                             (regs[1] >> 16) & 0xfff);
1657                         print_AMD_l2_assoc(regs[1] >> 28);
1658
1659                         printf("L2 4KB instruction TLB: %d entries",
1660                             (regs[1] >> 16) & 0xfff);
1661                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1662                 } else {
1663                         printf("L2 4KB unified TLB: %d entries",
1664                             (regs[1] >> 16) & 0xfff);
1665                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1666                 }
1667                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1668                 printf(", %d bytes/line", regs[2] & 0xff);
1669                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1670                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1671         }
1672
1673 #ifdef __i386__
1674         if (((cpu_id & 0xf00) == 0x500)
1675             && (((cpu_id & 0x0f0) > 0x80)
1676                 || (((cpu_id & 0x0f0) == 0x80)
1677                     && (cpu_id & 0x00f) > 0x07))) {
1678                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1679                 amd_whcr = rdmsr(0xc0000082);
1680                 if (!(amd_whcr & (0x3ff << 22))) {
1681                         printf("Write Allocate Disable\n");
1682                 } else {
1683                         printf("Write Allocate Enable Limit: %dM bytes\n",
1684                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1685                         printf("Write Allocate 15-16M bytes: %s\n",
1686                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1687                 }
1688         } else if (((cpu_id & 0xf00) == 0x500)
1689                    && ((cpu_id & 0x0f0) > 0x50)) {
1690                 /* K6, K6-2(old core) */
1691                 amd_whcr = rdmsr(0xc0000082);
1692                 if (!(amd_whcr & (0x7f << 1))) {
1693                         printf("Write Allocate Disable\n");
1694                 } else {
1695                         printf("Write Allocate Enable Limit: %dM bytes\n",
1696                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1697                         printf("Write Allocate 15-16M bytes: %s\n",
1698                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1699                         printf("Hardware Write Allocate Control: %s\n",
1700                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1701                 }
1702         }
1703 #endif
1704         /*
1705          * Opteron Rev E shows a bug as in very rare occasions a read memory
1706          * barrier is not performed as expected if it is followed by a
1707          * non-atomic read-modify-write instruction.
1708          * As long as that bug pops up very rarely (intensive machine usage
1709          * on other operating systems generally generates one unexplainable
1710          * crash any 2 months) and as long as a model specific fix would be
1711          * impractical at this stage, print out a warning string if the broken
1712          * model and family are identified.
1713          */
1714         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1715             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1716                 printf("WARNING: This architecture revision has known SMP "
1717                     "hardware bugs which may cause random instability\n");
1718 }
1719
1720 static void
1721 print_INTEL_info(void)
1722 {
1723         u_int regs[4];
1724         u_int rounds, regnum;
1725         u_int nwaycode, nway;
1726
1727         if (cpu_high >= 2) {
1728                 rounds = 0;
1729                 do {
1730                         do_cpuid(0x2, regs);
1731                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1732                                 break;  /* we have a buggy CPU */
1733
1734                         for (regnum = 0; regnum <= 3; ++regnum) {
1735                                 if (regs[regnum] & (1<<31))
1736                                         continue;
1737                                 if (regnum != 0)
1738                                         print_INTEL_TLB(regs[regnum] & 0xff);
1739                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1740                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1741                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1742                         }
1743                 } while (--rounds > 0);
1744         }
1745
1746         if (cpu_exthigh >= 0x80000006) {
1747                 do_cpuid(0x80000006, regs);
1748                 nwaycode = (regs[2] >> 12) & 0x0f;
1749                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1750                         nway = 1 << (nwaycode / 2);
1751                 else
1752                         nway = 0;
1753                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1754                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1755         }
1756 }
1757
1758 static void
1759 print_INTEL_TLB(u_int data)
1760 {
1761         switch (data) {
1762         case 0x0:
1763         case 0x40:
1764         default:
1765                 break;
1766         case 0x1:
1767                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1768                 break;
1769         case 0x2:
1770                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1771                 break;
1772         case 0x3:
1773                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1774                 break;
1775         case 0x4:
1776                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1777                 break;
1778         case 0x6:
1779                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1780                 break;
1781         case 0x8:
1782                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1783                 break;
1784         case 0x9:
1785                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1786                 break;
1787         case 0xa:
1788                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1789                 break;
1790         case 0xb:
1791                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1792                 break;
1793         case 0xc:
1794                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1795                 break;
1796         case 0xd:
1797                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1798                 break;
1799         case 0xe:
1800                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1801                 break;
1802         case 0x1d:
1803                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1804                 break;
1805         case 0x21:
1806                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1807                 break;
1808         case 0x22:
1809                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1810                 break;
1811         case 0x23:
1812                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1813                 break;
1814         case 0x24:
1815                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1816                 break;
1817         case 0x25:
1818                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1819                 break;
1820         case 0x29:
1821                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1822                 break;
1823         case 0x2c:
1824                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1825                 break;
1826         case 0x30:
1827                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1828                 break;
1829         case 0x39: /* De-listed in SDM rev. 54 */
1830                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1831                 break;
1832         case 0x3b: /* De-listed in SDM rev. 54 */
1833                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1834                 break;
1835         case 0x3c: /* De-listed in SDM rev. 54 */
1836                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1837                 break;
1838         case 0x41:
1839                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1840                 break;
1841         case 0x42:
1842                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1843                 break;
1844         case 0x43:
1845                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1846                 break;
1847         case 0x44:
1848                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1849                 break;
1850         case 0x45:
1851                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1852                 break;
1853         case 0x46:
1854                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1855                 break;
1856         case 0x47:
1857                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1858                 break;
1859         case 0x48:
1860                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1861                 break;
1862         case 0x49:
1863                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1864                     CPUID_TO_MODEL(cpu_id) == 0x6)
1865                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1866                 else
1867                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1868                 break;
1869         case 0x4a:
1870                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1871                 break;
1872         case 0x4b:
1873                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1874                 break;
1875         case 0x4c:
1876                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1877                 break;
1878         case 0x4d:
1879                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1880                 break;
1881         case 0x4e:
1882                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1883                 break;
1884         case 0x4f:
1885                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1886                 break;
1887         case 0x50:
1888                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1889                 break;
1890         case 0x51:
1891                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1892                 break;
1893         case 0x52:
1894                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1895                 break;
1896         case 0x55:
1897                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1898                 break;
1899         case 0x56:
1900                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1901                 break;
1902         case 0x57:
1903                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1904                 break;
1905         case 0x59:
1906                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1907                 break;
1908         case 0x5a:
1909                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1910                 break;
1911         case 0x5b:
1912                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1913                 break;
1914         case 0x5c:
1915                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1916                 break;
1917         case 0x5d:
1918                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1919                 break;
1920         case 0x60:
1921                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1922                 break;
1923         case 0x61:
1924                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1925                 break;
1926         case 0x63:
1927                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1928                 break;
1929         case 0x64:
1930                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1931                 break;
1932         case 0x66:
1933                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1934                 break;
1935         case 0x67:
1936                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1937                 break;
1938         case 0x68:
1939                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1940                 break;
1941         case 0x6a:
1942                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1943                 break;
1944         case 0x6b:
1945                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1946                 break;
1947         case 0x6c:
1948                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1949                 break;
1950         case 0x6d:
1951                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1952                 break;
1953         case 0x70:
1954                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1955                 break;
1956         case 0x71:
1957                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1958                 break;
1959         case 0x72:
1960                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1961                 break;
1962         case 0x76:
1963                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1964                 break;
1965         case 0x78:
1966                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1967                 break;
1968         case 0x79:
1969                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1970                 break;
1971         case 0x7a:
1972                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1973                 break;
1974         case 0x7b:
1975                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1976                 break;
1977         case 0x7c:
1978                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1979                 break;
1980         case 0x7d:
1981                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1982                 break;
1983         case 0x7f:
1984                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1985                 break;
1986         case 0x80:
1987                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1988                 break;
1989         case 0x82:
1990                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1991                 break;
1992         case 0x83:
1993                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1994                 break;
1995         case 0x84:
1996                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1997                 break;
1998         case 0x85:
1999                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2000                 break;
2001         case 0x86:
2002                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2003                 break;
2004         case 0x87:
2005                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2006                 break;
2007         case 0xa0:
2008                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2009                 break;
2010         case 0xb0:
2011                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2012                 break;
2013         case 0xb1:
2014                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2015                 break;
2016         case 0xb2:
2017                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2018                 break;
2019         case 0xb3:
2020                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2021                 break;
2022         case 0xb4:
2023                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2024                 break;
2025         case 0xb5:
2026                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2027                 break;
2028         case 0xb6:
2029                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2030                 break;
2031         case 0xba:
2032                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2033                 break;
2034         case 0xc0:
2035                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2036                 break;
2037         case 0xc1:
2038                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2039                 break;
2040         case 0xc2:
2041                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2042                 break;
2043         case 0xc3:
2044                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2045                 break;
2046         case 0xc4:
2047                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2048                 break;
2049         case 0xca:
2050                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2051                 break;
2052         case 0xd0:
2053                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2054                 break;
2055         case 0xd1:
2056                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2057                 break;
2058         case 0xd2:
2059                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2060                 break;
2061         case 0xd6:
2062                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2063                 break;
2064         case 0xd7:
2065                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2066                 break;
2067         case 0xd8:
2068                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2069                 break;
2070         case 0xdc:
2071                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2072                 break;
2073         case 0xdd:
2074                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2075                 break;
2076         case 0xde:
2077                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2078                 break;
2079         case 0xe2:
2080                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2081                 break;
2082         case 0xe3:
2083                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2084                 break;
2085         case 0xe4:
2086                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2087                 break;
2088         case 0xea:
2089                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2090                 break;
2091         case 0xeb:
2092                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2093                 break;
2094         case 0xec:
2095                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2096                 break;
2097         case 0xf0:
2098                 printf("64-Byte prefetching\n");
2099                 break;
2100         case 0xf1:
2101                 printf("128-Byte prefetching\n");
2102                 break;
2103         }
2104 }
2105
2106 static void
2107 print_svm_info(void)
2108 {
2109         u_int features, regs[4];
2110         uint64_t msr;
2111         int comma;
2112
2113         printf("\n  SVM: ");
2114         do_cpuid(0x8000000A, regs);
2115         features = regs[3];
2116
2117         msr = rdmsr(MSR_VM_CR);
2118         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2119                 printf("(disabled in BIOS) ");
2120
2121         if (!bootverbose) {
2122                 comma = 0;
2123                 if (features & (1 << 0)) {
2124                         printf("%sNP", comma ? "," : "");
2125                         comma = 1;
2126                 }
2127                 if (features & (1 << 3)) {
2128                         printf("%sNRIP", comma ? "," : "");
2129                         comma = 1;
2130                 }
2131                 if (features & (1 << 5)) {
2132                         printf("%sVClean", comma ? "," : "");
2133                         comma = 1;
2134                 }
2135                 if (features & (1 << 6)) {
2136                         printf("%sAFlush", comma ? "," : "");
2137                         comma = 1;
2138                 }
2139                 if (features & (1 << 7)) {
2140                         printf("%sDAssist", comma ? "," : "");
2141                         comma = 1;
2142                 }
2143                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2144                 return;
2145         }
2146
2147         printf("Features=0x%b", features,
2148                "\020"
2149                "\001NP"                 /* Nested paging */
2150                "\002LbrVirt"            /* LBR virtualization */
2151                "\003SVML"               /* SVM lock */
2152                "\004NRIPS"              /* NRIP save */
2153                "\005TscRateMsr"         /* MSR based TSC rate control */
2154                "\006VmcbClean"          /* VMCB clean bits */
2155                "\007FlushByAsid"        /* Flush by ASID */
2156                "\010DecodeAssist"       /* Decode assist */
2157                "\011<b8>"
2158                "\012<b9>"
2159                "\013PauseFilter"        /* PAUSE intercept filter */
2160                "\014<b11>"
2161                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2162                "\016AVIC"               /* virtual interrupt controller */
2163                 );
2164         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2165 }
2166
2167 #ifdef __i386__
2168 static void
2169 print_transmeta_info(void)
2170 {
2171         u_int regs[4], nreg = 0;
2172
2173         do_cpuid(0x80860000, regs);
2174         nreg = regs[0];
2175         if (nreg >= 0x80860001) {
2176                 do_cpuid(0x80860001, regs);
2177                 printf("  Processor revision %u.%u.%u.%u\n",
2178                        (regs[1] >> 24) & 0xff,
2179                        (regs[1] >> 16) & 0xff,
2180                        (regs[1] >> 8) & 0xff,
2181                        regs[1] & 0xff);
2182         }
2183         if (nreg >= 0x80860002) {
2184                 do_cpuid(0x80860002, regs);
2185                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2186                        (regs[1] >> 24) & 0xff,
2187                        (regs[1] >> 16) & 0xff,
2188                        (regs[1] >> 8) & 0xff,
2189                        regs[1] & 0xff,
2190                        regs[2]);
2191         }
2192         if (nreg >= 0x80860006) {
2193                 char info[65];
2194                 do_cpuid(0x80860003, (u_int*) &info[0]);
2195                 do_cpuid(0x80860004, (u_int*) &info[16]);
2196                 do_cpuid(0x80860005, (u_int*) &info[32]);
2197                 do_cpuid(0x80860006, (u_int*) &info[48]);
2198                 info[64] = 0;
2199                 printf("  %s\n", info);
2200         }
2201 }
2202 #endif
2203
2204 static void
2205 print_via_padlock_info(void)
2206 {
2207         u_int regs[4];
2208
2209         do_cpuid(0xc0000001, regs);
2210         printf("\n  VIA Padlock Features=0x%b", regs[3],
2211         "\020"
2212         "\003RNG"               /* RNG */
2213         "\007AES"               /* ACE */
2214         "\011AES-CTR"           /* ACE2 */
2215         "\013SHA1,SHA256"       /* PHE */
2216         "\015RSA"               /* PMM */
2217         );
2218 }
2219
2220 static uint32_t
2221 vmx_settable(uint64_t basic, int msr, int true_msr)
2222 {
2223         uint64_t val;
2224
2225         if (basic & (1ULL << 55))
2226                 val = rdmsr(true_msr);
2227         else
2228                 val = rdmsr(msr);
2229
2230         /* Just report the controls that can be set to 1. */
2231         return (val >> 32);
2232 }
2233
2234 static void
2235 print_vmx_info(void)
2236 {
2237         uint64_t basic, msr;
2238         uint32_t entry, exit, mask, pin, proc, proc2;
2239         int comma;
2240
2241         printf("\n  VT-x: ");
2242         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2243         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2244                 printf("(disabled in BIOS) ");
2245         basic = rdmsr(MSR_VMX_BASIC);
2246         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2247             MSR_VMX_TRUE_PINBASED_CTLS);
2248         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2249             MSR_VMX_TRUE_PROCBASED_CTLS);
2250         if (proc & PROCBASED_SECONDARY_CONTROLS)
2251                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2252                     MSR_VMX_PROCBASED_CTLS2);
2253         else
2254                 proc2 = 0;
2255         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2256         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2257
2258         if (!bootverbose) {
2259                 comma = 0;
2260                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2261                     entry & VM_ENTRY_LOAD_PAT) {
2262                         printf("%sPAT", comma ? "," : "");
2263                         comma = 1;
2264                 }
2265                 if (proc & PROCBASED_HLT_EXITING) {
2266                         printf("%sHLT", comma ? "," : "");
2267                         comma = 1;
2268                 }
2269                 if (proc & PROCBASED_MTF) {
2270                         printf("%sMTF", comma ? "," : "");
2271                         comma = 1;
2272                 }
2273                 if (proc & PROCBASED_PAUSE_EXITING) {
2274                         printf("%sPAUSE", comma ? "," : "");
2275                         comma = 1;
2276                 }
2277                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2278                         printf("%sEPT", comma ? "," : "");
2279                         comma = 1;
2280                 }
2281                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2282                         printf("%sUG", comma ? "," : "");
2283                         comma = 1;
2284                 }
2285                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2286                         printf("%sVPID", comma ? "," : "");
2287                         comma = 1;
2288                 }
2289                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2290                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2291                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2292                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2293                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2294                         printf("%sVID", comma ? "," : "");
2295                         comma = 1;
2296                         if (pin & PINBASED_POSTED_INTERRUPT)
2297                                 printf(",PostIntr");
2298                 }
2299                 return;
2300         }
2301
2302         mask = basic >> 32;
2303         printf("Basic Features=0x%b", mask,
2304         "\020"
2305         "\02132PA"              /* 32-bit physical addresses */
2306         "\022SMM"               /* SMM dual-monitor */
2307         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2308         "\030TRUE"              /* TRUE_CTLS MSRs */
2309         );
2310         printf("\n        Pin-Based Controls=0x%b", pin,
2311         "\020"
2312         "\001ExtINT"            /* External-interrupt exiting */
2313         "\004NMI"               /* NMI exiting */
2314         "\006VNMI"              /* Virtual NMIs */
2315         "\007PreTmr"            /* Activate VMX-preemption timer */
2316         "\010PostIntr"          /* Process posted interrupts */
2317         );
2318         printf("\n        Primary Processor Controls=0x%b", proc,
2319         "\020"
2320         "\003INTWIN"            /* Interrupt-window exiting */
2321         "\004TSCOff"            /* Use TSC offsetting */
2322         "\010HLT"               /* HLT exiting */
2323         "\012INVLPG"            /* INVLPG exiting */
2324         "\013MWAIT"             /* MWAIT exiting */
2325         "\014RDPMC"             /* RDPMC exiting */
2326         "\015RDTSC"             /* RDTSC exiting */
2327         "\020CR3-LD"            /* CR3-load exiting */
2328         "\021CR3-ST"            /* CR3-store exiting */
2329         "\024CR8-LD"            /* CR8-load exiting */
2330         "\025CR8-ST"            /* CR8-store exiting */
2331         "\026TPR"               /* Use TPR shadow */
2332         "\027NMIWIN"            /* NMI-window exiting */
2333         "\030MOV-DR"            /* MOV-DR exiting */
2334         "\031IO"                /* Unconditional I/O exiting */
2335         "\032IOmap"             /* Use I/O bitmaps */
2336         "\034MTF"               /* Monitor trap flag */
2337         "\035MSRmap"            /* Use MSR bitmaps */
2338         "\036MONITOR"           /* MONITOR exiting */
2339         "\037PAUSE"             /* PAUSE exiting */
2340         );
2341         if (proc & PROCBASED_SECONDARY_CONTROLS)
2342                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2343                 "\020"
2344                 "\001APIC"              /* Virtualize APIC accesses */
2345                 "\002EPT"               /* Enable EPT */
2346                 "\003DT"                /* Descriptor-table exiting */
2347                 "\004RDTSCP"            /* Enable RDTSCP */
2348                 "\005x2APIC"            /* Virtualize x2APIC mode */
2349                 "\006VPID"              /* Enable VPID */
2350                 "\007WBINVD"            /* WBINVD exiting */
2351                 "\010UG"                /* Unrestricted guest */
2352                 "\011APIC-reg"          /* APIC-register virtualization */
2353                 "\012VID"               /* Virtual-interrupt delivery */
2354                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2355                 "\014RDRAND"            /* RDRAND exiting */
2356                 "\015INVPCID"           /* Enable INVPCID */
2357                 "\016VMFUNC"            /* Enable VM functions */
2358                 "\017VMCS"              /* VMCS shadowing */
2359                 "\020EPT#VE"            /* EPT-violation #VE */
2360                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2361                 );
2362         printf("\n        Exit Controls=0x%b", mask,
2363         "\020"
2364         "\003DR"                /* Save debug controls */
2365                                 /* Ignore Host address-space size */
2366         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2367         "\020AckInt"            /* Acknowledge interrupt on exit */
2368         "\023PAT-SV"            /* Save MSR_PAT */
2369         "\024PAT-LD"            /* Load MSR_PAT */
2370         "\025EFER-SV"           /* Save MSR_EFER */
2371         "\026EFER-LD"           /* Load MSR_EFER */
2372         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2373         );
2374         printf("\n        Entry Controls=0x%b", mask,
2375         "\020"
2376         "\003DR"                /* Save debug controls */
2377                                 /* Ignore IA-32e mode guest */
2378                                 /* Ignore Entry to SMM */
2379                                 /* Ignore Deactivate dual-monitor treatment */
2380         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2381         "\017PAT"               /* Load MSR_PAT */
2382         "\020EFER"              /* Load MSR_EFER */
2383         );
2384         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2385             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2386                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2387                 mask = msr;
2388                 printf("\n        EPT Features=0x%b", mask,
2389                 "\020"
2390                 "\001XO"                /* Execute-only translations */
2391                 "\007PW4"               /* Page-walk length of 4 */
2392                 "\011UC"                /* EPT paging-structure mem can be UC */
2393                 "\017WB"                /* EPT paging-structure mem can be WB */
2394                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2395                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2396                 "\025INVEPT"            /* INVEPT is supported */
2397                 "\026AD"                /* Accessed and dirty flags for EPT */
2398                 "\032single"            /* INVEPT single-context type */
2399                 "\033all"               /* INVEPT all-context type */
2400                 );
2401                 mask = msr >> 32;
2402                 printf("\n        VPID Features=0x%b", mask,
2403                 "\020"
2404                 "\001INVVPID"           /* INVVPID is supported */
2405                 "\011individual"        /* INVVPID individual-address type */
2406                 "\012single"            /* INVVPID single-context type */
2407                 "\013all"               /* INVVPID all-context type */
2408                  /* INVVPID single-context-retaining-globals type */
2409                 "\014single-globals"
2410                 );
2411         }
2412 }
2413
2414 static void
2415 print_hypervisor_info(void)
2416 {
2417
2418         if (*hv_vendor)
2419                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2420 }