sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   via_feature_rng;        /* VIA RNG features */
  97 u_int   via_feature_xcrypt;     /* VIA ACE features */
  98 u_int   cpu_high;               /* Highest arg to CPUID */
  99 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 100 u_int   cpu_id;                 /* Stepping ID */
 101 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 102 u_int   cpu_procinfo2;          /* Multicore info */
 103 char    cpu_vendor[20];         /* CPU Origin code */
 104 u_int   cpu_vendor_id;          /* CPU vendor ID */
 105 u_int   cpu_fxsr;               /* SSE enabled */
 106 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 107 u_int   cpu_clflush_line_size = 32;
 108 u_int   cpu_stdext_feature;
 109 u_int   cpu_stdext_feature2;
 110 u_int   cpu_max_ext_state_size;
 111 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 112 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 113 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 114 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 115 char machine[] = MACHINE;
 116
 117 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 118     &via_feature_rng, 0,
 119     "VIA RNG feature available in CPU");
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 121     &via_feature_xcrypt, 0,
 122     "VIA xcrypt feature available in CPU");
 123
 124 #ifdef __amd64__
 125 #ifdef SCTL_MASK32
 126 extern int adaptive_machine_arch;
 127 #endif
 128
 129 static int
 130 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 131 {
 132 #ifdef SCTL_MASK32
 133         static const char machine32[] = "i386";
 134 #endif
 135         int error;
 136
 137 #ifdef SCTL_MASK32
 138         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 139                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 140         else
 141 #endif
 142                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 143         return (error);
 144
 145 }
 146 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 147     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 148 #else
 149 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 150     machine, 0, "Machine class");
 151 #endif
 152
 153 static char cpu_model[128];
 154 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 155     cpu_model, 0, "Machine model");
 156
 157 static int hw_clockrate;
 158 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 159     &hw_clockrate, 0, "CPU instruction clock rate");
 160
 161 u_int hv_high;
 162 char hv_vendor[16];
 163 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 164     0, "Hypervisor vendor");
 165
 166 static eventhandler_tag tsc_post_tag;
 167
 168 static char cpu_brand[48];
 169
 170 #ifdef __i386__
 171 #define MAX_BRAND_INDEX 8
 172
 173 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 174         NULL,                   /* No brand */
 175         "Intel Celeron",
 176         "Intel Pentium III",
 177         "Intel Pentium III Xeon",
 178         NULL,
 179         NULL,
 180         NULL,
 181         NULL,
 182         "Intel Pentium 4"
 183 };
 184
 185 static struct {
 186         char    *cpu_name;
 187         int     cpu_class;
 188 } cpus[] = {
 189         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 190         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 191         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 192         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 193         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 194         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 195         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 196         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 197         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 198         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 199         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 200         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 201         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 202         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 203         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 204         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 205         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 206 };
 207 #endif
 208
 209 static struct {
 210         char    *vendor;
 211         u_int   vendor_id;
 212 } cpu_vendors[] = {
 213         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 214         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 215         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 216 #ifdef __i386__
 217         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 218         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 219         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 220         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 221         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 222         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 223         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 224 #if 0
 225         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 226         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 227 #endif
 228 #endif
 229 };
 230
 231 void
 232 printcpuinfo(void)
 233 {
 234         u_int regs[4], i;
 235         char *brand;
 236
 237         printf("CPU: ");
 238 #ifdef __i386__
 239         cpu_class = cpus[cpu].cpu_class;
 240         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 241 #else
 242         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 243 #endif
 244
 245         /* Check for extended CPUID information and a processor name. */
 246         if (cpu_exthigh >= 0x80000004) {
 247                 brand = cpu_brand;
 248                 for (i = 0x80000002; i < 0x80000005; i++) {
 249                         do_cpuid(i, regs);
 250                         memcpy(brand, regs, sizeof(regs));
 251                         brand += sizeof(regs);
 252                 }
 253         }
 254
 255         switch (cpu_vendor_id) {
 256         case CPU_VENDOR_INTEL:
 257 #ifdef __i386__
 258                 if ((cpu_id & 0xf00) > 0x300) {
 259                         u_int brand_index;
 260
 261                         cpu_model[0] = '\0';
 262
 263                         switch (cpu_id & 0x3000) {
 264                         case 0x1000:
 265                                 strcpy(cpu_model, "Overdrive ");
 266                                 break;
 267                         case 0x2000:
 268                                 strcpy(cpu_model, "Dual ");
 269                                 break;
 270                         }
 271
 272                         switch (cpu_id & 0xf00) {
 273                         case 0x400:
 274                                 strcat(cpu_model, "i486 ");
 275                                 /* Check the particular flavor of 486 */
 276                                 switch (cpu_id & 0xf0) {
 277                                 case 0x00:
 278                                 case 0x10:
 279                                         strcat(cpu_model, "DX");
 280                                         break;
 281                                 case 0x20:
 282                                         strcat(cpu_model, "SX");
 283                                         break;
 284                                 case 0x30:
 285                                         strcat(cpu_model, "DX2");
 286                                         break;
 287                                 case 0x40:
 288                                         strcat(cpu_model, "SL");
 289                                         break;
 290                                 case 0x50:
 291                                         strcat(cpu_model, "SX2");
 292                                         break;
 293                                 case 0x70:
 294                                         strcat(cpu_model,
 295                                             "DX2 Write-Back Enhanced");
 296                                         break;
 297                                 case 0x80:
 298                                         strcat(cpu_model, "DX4");
 299                                         break;
 300                                 }
 301                                 break;
 302                         case 0x500:
 303                                 /* Check the particular flavor of 586 */
 304                                 strcat(cpu_model, "Pentium");
 305                                 switch (cpu_id & 0xf0) {
 306                                 case 0x00:
 307                                         strcat(cpu_model, " A-step");
 308                                         break;
 309                                 case 0x10:
 310                                         strcat(cpu_model, "/P5");
 311                                         break;
 312                                 case 0x20:
 313                                         strcat(cpu_model, "/P54C");
 314                                         break;
 315                                 case 0x30:
 316                                         strcat(cpu_model, "/P24T");
 317                                         break;
 318                                 case 0x40:
 319                                         strcat(cpu_model, "/P55C");
 320                                         break;
 321                                 case 0x70:
 322                                         strcat(cpu_model, "/P54C");
 323                                         break;
 324                                 case 0x80:
 325                                         strcat(cpu_model, "/P55C (quarter-micron)");
 326                                         break;
 327                                 default:
 328                                         /* nothing */
 329                                         break;
 330                                 }
 331 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 332                                 /*
 333                                  * XXX - If/when Intel fixes the bug, this
 334                                  * should also check the version of the
 335                                  * CPU, not just that it's a Pentium.
 336                                  */
 337                                 has_f00f_bug = 1;
 338 #endif
 339                                 break;
 340                         case 0x600:
 341                                 /* Check the particular flavor of 686 */
 342                                 switch (cpu_id & 0xf0) {
 343                                 case 0x00:
 344                                         strcat(cpu_model, "Pentium Pro A-step");
 345                                         break;
 346                                 case 0x10:
 347                                         strcat(cpu_model, "Pentium Pro");
 348                                         break;
 349                                 case 0x30:
 350                                 case 0x50:
 351                                 case 0x60:
 352                                         strcat(cpu_model,
 353                                 "Pentium II/Pentium II Xeon/Celeron");
 354                                         cpu = CPU_PII;
 355                                         break;
 356                                 case 0x70:
 357                                 case 0x80:
 358                                 case 0xa0:
 359                                 case 0xb0:
 360                                         strcat(cpu_model,
 361                                         "Pentium III/Pentium III Xeon/Celeron");
 362                                         cpu = CPU_PIII;
 363                                         break;
 364                                 default:
 365                                         strcat(cpu_model, "Unknown 80686");
 366                                         break;
 367                                 }
 368                                 break;
 369                         case 0xf00:
 370                                 strcat(cpu_model, "Pentium 4");
 371                                 cpu = CPU_P4;
 372                                 break;
 373                         default:
 374                                 strcat(cpu_model, "unknown");
 375                                 break;
 376                         }
 377
 378                         /*
 379                          * If we didn't get a brand name from the extended
 380                          * CPUID, try to look it up in the brand table.
 381                          */
 382                         if (cpu_high > 0 && *cpu_brand == '\0') {
 383                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 384                                 if (brand_index <= MAX_BRAND_INDEX &&
 385                                     cpu_brandtable[brand_index] != NULL)
 386                                         strcpy(cpu_brand,
 387                                             cpu_brandtable[brand_index]);
 388                         }
 389                 }
 390 #else
 391                 /* Please make up your mind folks! */
 392                 strcat(cpu_model, "EM64T");
 393 #endif
 394                 break;
 395         case CPU_VENDOR_AMD:
 396                 /*
 397                  * Values taken from AMD Processor Recognition
 398                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 399                  * (also describes ``Features'' encodings.
 400                  */
 401                 strcpy(cpu_model, "AMD ");
 402 #ifdef __i386__
 403                 switch (cpu_id & 0xFF0) {
 404                 case 0x410:
 405                         strcat(cpu_model, "Standard Am486DX");
 406                         break;
 407                 case 0x430:
 408                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 409                         break;
 410                 case 0x470:
 411                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 412                         break;
 413                 case 0x480:
 414                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 415                         break;
 416                 case 0x490:
 417                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 418                         break;
 419                 case 0x4E0:
 420                         strcat(cpu_model, "Am5x86 Write-Through");
 421                         break;
 422                 case 0x4F0:
 423                         strcat(cpu_model, "Am5x86 Write-Back");
 424                         break;
 425                 case 0x500:
 426                         strcat(cpu_model, "K5 model 0");
 427                         break;
 428                 case 0x510:
 429                         strcat(cpu_model, "K5 model 1");
 430                         break;
 431                 case 0x520:
 432                         strcat(cpu_model, "K5 PR166 (model 2)");
 433                         break;
 434                 case 0x530:
 435                         strcat(cpu_model, "K5 PR200 (model 3)");
 436                         break;
 437                 case 0x560:
 438                         strcat(cpu_model, "K6");
 439                         break;
 440                 case 0x570:
 441                         strcat(cpu_model, "K6 266 (model 1)");
 442                         break;
 443                 case 0x580:
 444                         strcat(cpu_model, "K6-2");
 445                         break;
 446                 case 0x590:
 447                         strcat(cpu_model, "K6-III");
 448                         break;
 449                 case 0x5a0:
 450                         strcat(cpu_model, "Geode LX");
 451                         break;
 452                 default:
 453                         strcat(cpu_model, "Unknown");
 454                         break;
 455                 }
 456 #else
 457                 if ((cpu_id & 0xf00) == 0xf00)
 458                         strcat(cpu_model, "AMD64 Processor");
 459                 else
 460                         strcat(cpu_model, "Unknown");
 461 #endif
 462                 break;
 463 #ifdef __i386__
 464         case CPU_VENDOR_CYRIX:
 465                 strcpy(cpu_model, "Cyrix ");
 466                 switch (cpu_id & 0xff0) {
 467                 case 0x440:
 468                         strcat(cpu_model, "MediaGX");
 469                         break;
 470                 case 0x520:
 471                         strcat(cpu_model, "6x86");
 472                         break;
 473                 case 0x540:
 474                         cpu_class = CPUCLASS_586;
 475                         strcat(cpu_model, "GXm");
 476                         break;
 477                 case 0x600:
 478                         strcat(cpu_model, "6x86MX");
 479                         break;
 480                 default:
 481                         /*
 482                          * Even though CPU supports the cpuid
 483                          * instruction, it can be disabled.
 484                          * Therefore, this routine supports all Cyrix
 485                          * CPUs.
 486                          */
 487                         switch (cyrix_did & 0xf0) {
 488                         case 0x00:
 489                                 switch (cyrix_did & 0x0f) {
 490                                 case 0x00:
 491                                         strcat(cpu_model, "486SLC");
 492                                         break;
 493                                 case 0x01:
 494                                         strcat(cpu_model, "486DLC");
 495                                         break;
 496                                 case 0x02:
 497                                         strcat(cpu_model, "486SLC2");
 498                                         break;
 499                                 case 0x03:
 500                                         strcat(cpu_model, "486DLC2");
 501                                         break;
 502                                 case 0x04:
 503                                         strcat(cpu_model, "486SRx");
 504                                         break;
 505                                 case 0x05:
 506                                         strcat(cpu_model, "486DRx");
 507                                         break;
 508                                 case 0x06:
 509                                         strcat(cpu_model, "486SRx2");
 510                                         break;
 511                                 case 0x07:
 512                                         strcat(cpu_model, "486DRx2");
 513                                         break;
 514                                 case 0x08:
 515                                         strcat(cpu_model, "486SRu");
 516                                         break;
 517                                 case 0x09:
 518                                         strcat(cpu_model, "486DRu");
 519                                         break;
 520                                 case 0x0a:
 521                                         strcat(cpu_model, "486SRu2");
 522                                         break;
 523                                 case 0x0b:
 524                                         strcat(cpu_model, "486DRu2");
 525                                         break;
 526                                 default:
 527                                         strcat(cpu_model, "Unknown");
 528                                         break;
 529                                 }
 530                                 break;
 531                         case 0x10:
 532                                 switch (cyrix_did & 0x0f) {
 533                                 case 0x00:
 534                                         strcat(cpu_model, "486S");
 535                                         break;
 536                                 case 0x01:
 537                                         strcat(cpu_model, "486S2");
 538                                         break;
 539                                 case 0x02:
 540                                         strcat(cpu_model, "486Se");
 541                                         break;
 542                                 case 0x03:
 543                                         strcat(cpu_model, "486S2e");
 544                                         break;
 545                                 case 0x0a:
 546                                         strcat(cpu_model, "486DX");
 547                                         break;
 548                                 case 0x0b:
 549                                         strcat(cpu_model, "486DX2");
 550                                         break;
 551                                 case 0x0f:
 552                                         strcat(cpu_model, "486DX4");
 553                                         break;
 554                                 default:
 555                                         strcat(cpu_model, "Unknown");
 556                                         break;
 557                                 }
 558                                 break;
 559                         case 0x20:
 560                                 if ((cyrix_did & 0x0f) < 8)
 561                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 562                                 else
 563                                         strcat(cpu_model, "5x86");
 564                                 break;
 565                         case 0x30:
 566                                 strcat(cpu_model, "6x86");
 567                                 break;
 568                         case 0x40:
 569                                 if ((cyrix_did & 0xf000) == 0x3000) {
 570                                         cpu_class = CPUCLASS_586;
 571                                         strcat(cpu_model, "GXm");
 572                                 } else
 573                                         strcat(cpu_model, "MediaGX");
 574                                 break;
 575                         case 0x50:
 576                                 strcat(cpu_model, "6x86MX");
 577                                 break;
 578                         case 0xf0:
 579                                 switch (cyrix_did & 0x0f) {
 580                                 case 0x0d:
 581                                         strcat(cpu_model, "Overdrive CPU");
 582                                         break;
 583                                 case 0x0e:
 584                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 585                                         break;
 586                                 case 0x0f:
 587                                         strcat(cpu_model, "486SLC/DLC");
 588                                         break;
 589                                 default:
 590                                         strcat(cpu_model, "Unknown");
 591                                         break;
 592                                 }
 593                                 break;
 594                         default:
 595                                 strcat(cpu_model, "Unknown");
 596                                 break;
 597                         }
 598                         break;
 599                 }
 600                 break;
 601         case CPU_VENDOR_RISE:
 602                 strcpy(cpu_model, "Rise ");
 603                 switch (cpu_id & 0xff0) {
 604                 case 0x500:     /* 6401 and 6441 (Kirin) */
 605                 case 0x520:     /* 6510 (Lynx) */
 606                         strcat(cpu_model, "mP6");
 607                         break;
 608                 default:
 609                         strcat(cpu_model, "Unknown");
 610                 }
 611                 break;
 612 #endif
 613         case CPU_VENDOR_CENTAUR:
 614 #ifdef __i386__
 615                 switch (cpu_id & 0xff0) {
 616                 case 0x540:
 617                         strcpy(cpu_model, "IDT WinChip C6");
 618                         break;
 619                 case 0x580:
 620                         strcpy(cpu_model, "IDT WinChip 2");
 621                         break;
 622                 case 0x590:
 623                         strcpy(cpu_model, "IDT WinChip 3");
 624                         break;
 625                 case 0x660:
 626                         strcpy(cpu_model, "VIA C3 Samuel");
 627                         break;
 628                 case 0x670:
 629                         if (cpu_id & 0x8)
 630                                 strcpy(cpu_model, "VIA C3 Ezra");
 631                         else
 632                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 633                         break;
 634                 case 0x680:
 635                         strcpy(cpu_model, "VIA C3 Ezra-T");
 636                         break;
 637                 case 0x690:
 638                         strcpy(cpu_model, "VIA C3 Nehemiah");
 639                         break;
 640                 case 0x6a0:
 641                 case 0x6d0:
 642                         strcpy(cpu_model, "VIA C7 Esther");
 643                         break;
 644                 case 0x6f0:
 645                         strcpy(cpu_model, "VIA Nano");
 646                         break;
 647                 default:
 648                         strcpy(cpu_model, "VIA/IDT Unknown");
 649                 }
 650 #else
 651                 strcpy(cpu_model, "VIA ");
 652                 if ((cpu_id & 0xff0) == 0x6f0)
 653                         strcat(cpu_model, "Nano Processor");
 654                 else
 655                         strcat(cpu_model, "Unknown");
 656 #endif
 657                 break;
 658 #ifdef __i386__
 659         case CPU_VENDOR_IBM:
 660                 strcpy(cpu_model, "Blue Lightning CPU");
 661                 break;
 662         case CPU_VENDOR_NSC:
 663                 switch (cpu_id & 0xff0) {
 664                 case 0x540:
 665                         strcpy(cpu_model, "Geode SC1100");
 666                         cpu = CPU_GEODE1100;
 667                         break;
 668                 default:
 669                         strcpy(cpu_model, "Geode/NSC unknown");
 670                         break;
 671                 }
 672                 break;
 673 #endif
 674         default:
 675                 strcat(cpu_model, "Unknown");
 676                 break;
 677         }
 678
 679         /*
 680          * Replace cpu_model with cpu_brand minus leading spaces if
 681          * we have one.
 682          */
 683         brand = cpu_brand;
 684         while (*brand == ' ')
 685                 ++brand;
 686         if (*brand != '\0')
 687                 strcpy(cpu_model, brand);
 688
 689         printf("%s (", cpu_model);
 690         if (tsc_freq != 0) {
 691                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 692                 printf("%jd.%02d-MHz ",
 693                     (intmax_t)(tsc_freq + 4999) / 1000000,
 694                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 695         }
 696 #ifdef __i386__
 697         switch(cpu_class) {
 698         case CPUCLASS_286:
 699                 printf("286");
 700                 break;
 701         case CPUCLASS_386:
 702                 printf("386");
 703                 break;
 704 #if defined(I486_CPU)
 705         case CPUCLASS_486:
 706                 printf("486");
 707                 break;
 708 #endif
 709 #if defined(I586_CPU)
 710         case CPUCLASS_586:
 711                 printf("586");
 712                 break;
 713 #endif
 714 #if defined(I686_CPU)
 715         case CPUCLASS_686:
 716                 printf("686");
 717                 break;
 718 #endif
 719         default:
 720                 printf("Unknown");      /* will panic below... */
 721         }
 722 #else
 723         printf("K8");
 724 #endif
 725         printf("-class CPU)\n");
 726         if (*cpu_vendor)
 727                 printf("  Origin=\"%s\"", cpu_vendor);
 728         if (cpu_id)
 729                 printf("  Id=0x%x", cpu_id);
 730
 731         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 732             cpu_vendor_id == CPU_VENDOR_AMD ||
 733             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 734 #ifdef __i386__
 735             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 736             cpu_vendor_id == CPU_VENDOR_RISE ||
 737             cpu_vendor_id == CPU_VENDOR_NSC ||
 738             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 739 #endif
 740             0) {
 741                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 742                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 743                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 744 #ifdef __i386__
 745                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 746                         printf("\n  DIR=0x%04x", cyrix_did);
 747 #endif
 748
 749                 /*
 750                  * AMD CPUID Specification
 751                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 752                  *
 753                  * Intel Processor Identification and CPUID Instruction
 754                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 755                  */
 756                 if (cpu_high > 0) {
 757
 758                         /*
 759                          * Here we should probably set up flags indicating
 760                          * whether or not various features are available.
 761                          * The interesting ones are probably VME, PSE, PAE,
 762                          * and PGE.  The code already assumes without bothering
 763                          * to check that all CPUs >= Pentium have a TSC and
 764                          * MSRs.
 765                          */
 766                         printf("\n  Features=0x%b", cpu_feature,
 767                         "\020"
 768                         "\001FPU"       /* Integral FPU */
 769                         "\002VME"       /* Extended VM86 mode support */
 770                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 771                         "\004PSE"       /* 4MByte page tables */
 772                         "\005TSC"       /* Timestamp counter */
 773                         "\006MSR"       /* Machine specific registers */
 774                         "\007PAE"       /* Physical address extension */
 775                         "\010MCE"       /* Machine Check support */
 776                         "\011CX8"       /* CMPEXCH8 instruction */
 777                         "\012APIC"      /* SMP local APIC */
 778                         "\013oldMTRR"   /* Previous implementation of MTRR */
 779                         "\014SEP"       /* Fast System Call */
 780                         "\015MTRR"      /* Memory Type Range Registers */
 781                         "\016PGE"       /* PG_G (global bit) support */
 782                         "\017MCA"       /* Machine Check Architecture */
 783                         "\020CMOV"      /* CMOV instruction */
 784                         "\021PAT"       /* Page attributes table */
 785                         "\022PSE36"     /* 36 bit address space support */
 786                         "\023PN"        /* Processor Serial number */
 787                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 788                         "\025<b20>"
 789                         "\026DTS"       /* Debug Trace Store */
 790                         "\027ACPI"      /* ACPI support */
 791                         "\030MMX"       /* MMX instructions */
 792                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 793                         "\032SSE"       /* Streaming SIMD Extensions */
 794                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 795                         "\034SS"        /* Self snoop */
 796                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 797                         "\036TM"        /* Thermal Monitor clock slowdown */
 798                         "\037IA64"      /* CPU can execute IA64 instructions */
 799                         "\040PBE"       /* Pending Break Enable */
 800                         );
 801
 802                         if (cpu_feature2 != 0) {
 803                                 printf("\n  Features2=0x%b", cpu_feature2,
 804                                 "\020"
 805                                 "\001SSE3"      /* SSE3 */
 806                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 807                                 "\003DTES64"    /* 64-bit Debug Trace */
 808                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 809                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 810                                 "\006VMX"       /* Virtual Machine Extensions */
 811                                 "\007SMX"       /* Safer Mode Extensions */
 812                                 "\010EST"       /* Enhanced SpeedStep */
 813                                 "\011TM2"       /* Thermal Monitor 2 */
 814                                 "\012SSSE3"     /* SSSE3 */
 815                                 "\013CNXT-ID"   /* L1 context ID available */
 816                                 "\014SDBG"      /* IA32 silicon debug */
 817                                 "\015FMA"       /* Fused Multiply Add */
 818                                 "\016CX16"      /* CMPXCHG16B Instruction */
 819                                 "\017xTPR"      /* Send Task Priority Messages*/
 820                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 821                                 "\021<b16>"
 822                                 "\022PCID"      /* Process-context Identifiers*/
 823                                 "\023DCA"       /* Direct Cache Access */
 824                                 "\024SSE4.1"    /* SSE 4.1 */
 825                                 "\025SSE4.2"    /* SSE 4.2 */
 826                                 "\026x2APIC"    /* xAPIC Extensions */
 827                                 "\027MOVBE"     /* MOVBE Instruction */
 828                                 "\030POPCNT"    /* POPCNT Instruction */
 829                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 830                                 "\032AESNI"     /* AES Crypto */
 831                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 832                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 833                                 "\035AVX"       /* Advanced Vector Extensions */
 834                                 "\036F16C"      /* Half-precision conversions */
 835                                 "\037RDRAND"    /* RDRAND Instruction */
 836                                 "\040HV"        /* Hypervisor */
 837                                 );
 838                         }
 839
 840                         if (amd_feature != 0) {
 841                                 printf("\n  AMD Features=0x%b", amd_feature,
 842                                 "\020"          /* in hex */
 843                                 "\001<s0>"      /* Same */
 844                                 "\002<s1>"      /* Same */
 845                                 "\003<s2>"      /* Same */
 846                                 "\004<s3>"      /* Same */
 847                                 "\005<s4>"      /* Same */
 848                                 "\006<s5>"      /* Same */
 849                                 "\007<s6>"      /* Same */
 850                                 "\010<s7>"      /* Same */
 851                                 "\011<s8>"      /* Same */
 852                                 "\012<s9>"      /* Same */
 853                                 "\013<b10>"     /* Undefined */
 854                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 855                                 "\015<s12>"     /* Same */
 856                                 "\016<s13>"     /* Same */
 857                                 "\017<s14>"     /* Same */
 858                                 "\020<s15>"     /* Same */
 859                                 "\021<s16>"     /* Same */
 860                                 "\022<s17>"     /* Same */
 861                                 "\023<b18>"     /* Reserved, unknown */
 862                                 "\024MP"        /* Multiprocessor Capable */
 863                                 "\025NX"        /* Has EFER.NXE, NX */
 864                                 "\026<b21>"     /* Undefined */
 865                                 "\027MMX+"      /* AMD MMX Extensions */
 866                                 "\030<s23>"     /* Same */
 867                                 "\031<s24>"     /* Same */
 868                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 869                                 "\033Page1GB"   /* 1-GB large page support */
 870                                 "\034RDTSCP"    /* RDTSCP */
 871                                 "\035<b28>"     /* Undefined */
 872                                 "\036LM"        /* 64 bit long mode */
 873                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 874                                 "\0403DNow!"    /* AMD 3DNow! */
 875                                 );
 876                         }
 877
 878                         if (amd_feature2 != 0) {
 879                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 880                                 "\020"
 881                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 882                                 "\002CMP"       /* CMP legacy */
 883                                 "\003SVM"       /* Secure Virtual Mode */
 884                                 "\004ExtAPIC"   /* Extended APIC register */
 885                                 "\005CR8"       /* CR8 in legacy mode */
 886                                 "\006ABM"       /* LZCNT instruction */
 887                                 "\007SSE4A"     /* SSE4A */
 888                                 "\010MAS"       /* Misaligned SSE mode */
 889                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 890                                 "\012OSVW"      /* OS visible workaround */
 891                                 "\013IBS"       /* Instruction based sampling */
 892                                 "\014XOP"       /* XOP extended instructions */
 893                                 "\015SKINIT"    /* SKINIT/STGI */
 894                                 "\016WDT"       /* Watchdog timer */
 895                                 "\017<b14>"
 896                                 "\020LWP"       /* Lightweight Profiling */
 897                                 "\021FMA4"      /* 4-operand FMA instructions */
 898                                 "\022TCE"       /* Translation Cache Extension */
 899                                 "\023<b18>"
 900                                 "\024NodeId"    /* NodeId MSR support */
 901                                 "\025<b20>"
 902                                 "\026TBM"       /* Trailing Bit Manipulation */
 903                                 "\027Topology"  /* Topology Extensions */
 904                                 "\030PCXC"      /* Core perf count */
 905                                 "\031PNXC"      /* NB perf count */
 906                                 "\032<b25>"
 907                                 "\033DBE"       /* Data Breakpoint extension */
 908                                 "\034PTSC"      /* Performance TSC */
 909                                 "\035PL2I"      /* L2I perf count */
 910                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 911                                 "\037<b30>"
 912                                 "\040<b31>"
 913                                 );
 914                         }
 915
 916                         if (cpu_stdext_feature != 0) {
 917                                 printf("\n  Structured Extended Features=0x%b",
 918                                     cpu_stdext_feature,
 919                                        "\020"
 920                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 921                                        "\001FSGSBASE"
 922                                        "\002TSCADJ"
 923                                        "\003SGX"
 924                                        /* Bit Manipulation Instructions */
 925                                        "\004BMI1"
 926                                        /* Hardware Lock Elision */
 927                                        "\005HLE"
 928                                        /* Advanced Vector Instructions 2 */
 929                                        "\006AVX2"
 930                                        /* FDP_EXCPTN_ONLY */
 931                                        "\007FDPEXC"
 932                                        /* Supervisor Mode Execution Prot. */
 933                                        "\010SMEP"
 934                                        /* Bit Manipulation Instructions */
 935                                        "\011BMI2"
 936                                        "\012ERMS"
 937                                        /* Invalidate Processor Context ID */
 938                                        "\013INVPCID"
 939                                        /* Restricted Transactional Memory */
 940                                        "\014RTM"
 941                                        "\015PQM"
 942                                        "\016NFPUSG"
 943                                        /* Intel Memory Protection Extensions */
 944                                        "\017MPX"
 945                                        "\020PQE"
 946                                        /* AVX512 Foundation */
 947                                        "\021AVX512F"
 948                                        "\022AVX512DQ"
 949                                        /* Enhanced NRBG */
 950                                        "\023RDSEED"
 951                                        /* ADCX + ADOX */
 952                                        "\024ADX"
 953                                        /* Supervisor Mode Access Prevention */
 954                                        "\025SMAP"
 955                                        "\026AVX512IFMA"
 956                                        "\027PCOMMIT"
 957                                        "\030CLFLUSHOPT"
 958                                        "\031CLWB"
 959                                        "\032PROCTRACE"
 960                                        "\033AVX512PF"
 961                                        "\034AVX512ER"
 962                                        "\035AVX512CD"
 963                                        "\036SHA"
 964                                        "\037AVX512BW"
 965                                        );
 966                         }
 967
 968                         if (cpu_stdext_feature2 != 0) {
 969                                 printf("\n  Structured Extended Features2=0x%b",
 970                                     cpu_stdext_feature2,
 971                                        "\020"
 972                                        "\001PREFETCHWT1"
 973                                        "\002AVX512VBMI"
 974                                        "\003UMIP"
 975                                        "\004PKU"
 976                                        "\005OSPKE"
 977                                        "\027RDPID"
 978                                        "\037SGXLC"
 979                                        );
 980                         }
 981
 982                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 983                                 cpuid_count(0xd, 0x1, regs);
 984                                 if (regs[0] != 0) {
 985                                         printf("\n  XSAVE Features=0x%b",
 986                                             regs[0],
 987                                             "\020"
 988                                             "\001XSAVEOPT"
 989                                             "\002XSAVEC"
 990                                             "\003XINUSE"
 991                                             "\004XSAVES");
 992                                 }
 993                         }
 994
 995                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 996                                 print_via_padlock_info();
 997
 998                         if (cpu_feature2 & CPUID2_VMX)
 999                                 print_vmx_info();
1000
1001                         if (amd_feature2 & AMDID2_SVM)
1002                                 print_svm_info();
1003
1004                         if ((cpu_feature & CPUID_HTT) &&
1005                             cpu_vendor_id == CPU_VENDOR_AMD)
1006                                 cpu_feature &= ~CPUID_HTT;
1007
1008                         /*
1009                          * If this CPU supports P-state invariant TSC then
1010                          * mention the capability.
1011                          */
1012                         if (tsc_is_invariant) {
1013                                 printf("\n  TSC: P-state invariant");
1014                                 if (tsc_perf_stat)
1015                                         printf(", performance statistics");
1016                         }
1017                 }
1018 #ifdef __i386__
1019         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1020                 printf("  DIR=0x%04x", cyrix_did);
1021                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1022                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1023 #ifndef CYRIX_CACHE_REALLY_WORKS
1024                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1025                         printf("\n  CPU cache: write-through mode");
1026 #endif
1027 #endif
1028         }
1029
1030         /* Avoid ugly blank lines: only print newline when we have to. */
1031         if (*cpu_vendor || cpu_id)
1032                 printf("\n");
1033
1034         if (bootverbose) {
1035                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1036                         print_AMD_info();
1037                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1038                         print_INTEL_info();
1039 #ifdef __i386__
1040                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1041                         print_transmeta_info();
1042 #endif
1043         }
1044
1045         print_hypervisor_info();
1046 }
1047
1048 #ifdef __i386__
1049 void
1050 panicifcpuunsupported(void)
1051 {
1052
1053 #if !defined(lint)
1054 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1055 #error This kernel is not configured for one of the supported CPUs
1056 #endif
1057 #else /* lint */
1058 #endif /* lint */
1059         /*
1060          * Now that we have told the user what they have,
1061          * let them know if that machine type isn't configured.
1062          */
1063         switch (cpu_class) {
1064         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1065         case CPUCLASS_386:
1066 #if !defined(I486_CPU)
1067         case CPUCLASS_486:
1068 #endif
1069 #if !defined(I586_CPU)
1070         case CPUCLASS_586:
1071 #endif
1072 #if !defined(I686_CPU)
1073         case CPUCLASS_686:
1074 #endif
1075                 panic("CPU class not configured");
1076         default:
1077                 break;
1078         }
1079 }
1080
1081 static  volatile u_int trap_by_rdmsr;
1082
1083 /*
1084  * Special exception 6 handler.
1085  * The rdmsr instruction generates invalid opcodes fault on 486-class
1086  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1087  * function identblue() when this handler is called.  Stacked eip should
1088  * be advanced.
1089  */
1090 inthand_t       bluetrap6;
1091 #ifdef __GNUCLIKE_ASM
1092 __asm
1093 ("                                                                      \n\
1094         .text                                                           \n\
1095         .p2align 2,0x90                                                 \n\
1096         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1097 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1098         ss                                                              \n\
1099         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1100         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1101         iret                                                            \n\
1102 ");
1103 #endif
1104
1105 /*
1106  * Special exception 13 handler.
1107  * Accessing non-existent MSR generates general protection fault.
1108  */
1109 inthand_t       bluetrap13;
1110 #ifdef __GNUCLIKE_ASM
1111 __asm
1112 ("                                                                      \n\
1113         .text                                                           \n\
1114         .p2align 2,0x90                                                 \n\
1115         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1116 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1117         ss                                                              \n\
1118         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1119         popl    %eax            /* discard error code */                \n\
1120         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1121         iret                                                            \n\
1122 ");
1123 #endif
1124
1125 /*
1126  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1127  * support cpuid instruction.  This function should be called after
1128  * loading interrupt descriptor table register.
1129  *
1130  * I don't like this method that handles fault, but I couldn't get
1131  * information for any other methods.  Does blue giant know?
1132  */
1133 static int
1134 identblue(void)
1135 {
1136
1137         trap_by_rdmsr = 0;
1138
1139         /*
1140          * Cyrix 486-class CPU does not support rdmsr instruction.
1141          * The rdmsr instruction generates invalid opcode fault, and exception
1142          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1143          * bluetrap6() set the magic number to trap_by_rdmsr.
1144          */
1145         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1146             GSEL(GCODE_SEL, SEL_KPL));
1147
1148         /*
1149          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1150          * In this case, rdmsr generates general protection fault, and
1151          * exception will be trapped by bluetrap13().
1152          */
1153         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1154             GSEL(GCODE_SEL, SEL_KPL));
1155
1156         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1157
1158         if (trap_by_rdmsr == 0xa8c1d)
1159                 return IDENTBLUE_CYRIX486;
1160         else if (trap_by_rdmsr == 0xa89c4)
1161                 return IDENTBLUE_CYRIXM2;
1162         return IDENTBLUE_IBMCPU;
1163 }
1164
1165
1166 /*
1167  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1168  *
1169  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1170  * +-------+-------+---------------+
1171  * |  SID  |  RID  |   Device ID   |
1172  * |    (DIR 1)    |    (DIR 0)    |
1173  * +-------+-------+---------------+
1174  */
1175 static void
1176 identifycyrix(void)
1177 {
1178         register_t saveintr;
1179         int     ccr2_test = 0, dir_test = 0;
1180         u_char  ccr2, ccr3;
1181
1182         saveintr = intr_disable();
1183
1184         ccr2 = read_cyrix_reg(CCR2);
1185         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1186         read_cyrix_reg(CCR2);
1187         if (read_cyrix_reg(CCR2) != ccr2)
1188                 ccr2_test = 1;
1189         write_cyrix_reg(CCR2, ccr2);
1190
1191         ccr3 = read_cyrix_reg(CCR3);
1192         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1193         read_cyrix_reg(CCR3);
1194         if (read_cyrix_reg(CCR3) != ccr3)
1195                 dir_test = 1;                                   /* CPU supports DIRs. */
1196         write_cyrix_reg(CCR3, ccr3);
1197
1198         if (dir_test) {
1199                 /* Device ID registers are available. */
1200                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1201                 cyrix_did += read_cyrix_reg(DIR0);
1202         } else if (ccr2_test)
1203                 cyrix_did = 0x0010;             /* 486S A-step */
1204         else
1205                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1206
1207         intr_restore(saveintr);
1208 }
1209 #endif
1210
1211 /* Update TSC freq with the value indicated by the caller. */
1212 static void
1213 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1214 {
1215
1216         /* If there was an error during the transition, don't do anything. */
1217         if (status != 0)
1218                 return;
1219
1220         /* Total setting for this level gives the new frequency in MHz. */
1221         hw_clockrate = level->total_set.freq;
1222 }
1223
1224 static void
1225 hook_tsc_freq(void *arg __unused)
1226 {
1227
1228         if (tsc_is_invariant)
1229                 return;
1230
1231         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1232             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1233 }
1234
1235 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1236
1237 static const char *const vm_bnames[] = {
1238         "QEMU",                         /* QEMU */
1239         "Plex86",                       /* Plex86 */
1240         "Bochs",                        /* Bochs */
1241         "Xen",                          /* Xen */
1242         "BHYVE",                        /* bhyve */
1243         "Seabios",                      /* KVM */
1244         NULL
1245 };
1246
1247 static const char *const vm_pnames[] = {
1248         "VMware Virtual Platform",      /* VMWare VM */
1249         "Virtual Machine",              /* Microsoft VirtualPC */
1250         "VirtualBox",                   /* Sun xVM VirtualBox */
1251         "Parallels Virtual Platform",   /* Parallels VM */
1252         "KVM",                          /* KVM */
1253         NULL
1254 };
1255
1256 void
1257 identify_hypervisor(void)
1258 {
1259         u_int regs[4];
1260         char *p;
1261         int i;
1262
1263         /*
1264          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1265          * http://lkml.org/lkml/2008/10/1/246
1266          *
1267          * KB1009458: Mechanisms to determine if software is running in
1268          * a VMware virtual machine
1269          * http://kb.vmware.com/kb/1009458
1270          */
1271         if (cpu_feature2 & CPUID2_HV) {
1272                 vm_guest = VM_GUEST_VM;
1273                 do_cpuid(0x40000000, regs);
1274                 if (regs[0] >= 0x40000000) {
1275                         hv_high = regs[0];
1276                         ((u_int *)&hv_vendor)[0] = regs[1];
1277                         ((u_int *)&hv_vendor)[1] = regs[2];
1278                         ((u_int *)&hv_vendor)[2] = regs[3];
1279                         hv_vendor[12] = '\0';
1280                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1281                                 vm_guest = VM_GUEST_VMWARE;
1282                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1283                                 vm_guest = VM_GUEST_HV;
1284                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1285                                 vm_guest = VM_GUEST_KVM;
1286                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1287                                 vm_guest = VM_GUEST_BHYVE;
1288                 }
1289                 return;
1290         }
1291
1292         /*
1293          * Examine SMBIOS strings for older hypervisors.
1294          */
1295         p = kern_getenv("smbios.system.serial");
1296         if (p != NULL) {
1297                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1298                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1299                         if (regs[1] == VMW_HVMAGIC) {
1300                                 vm_guest = VM_GUEST_VMWARE;
1301                                 freeenv(p);
1302                                 return;
1303                         }
1304                 }
1305                 freeenv(p);
1306         }
1307
1308         /*
1309          * XXX: Some of these entries may not be needed since they were
1310          * added to FreeBSD before the checks above.
1311          */
1312         p = kern_getenv("smbios.bios.vendor");
1313         if (p != NULL) {
1314                 for (i = 0; vm_bnames[i] != NULL; i++)
1315                         if (strcmp(p, vm_bnames[i]) == 0) {
1316                                 vm_guest = VM_GUEST_VM;
1317                                 freeenv(p);
1318                                 return;
1319                         }
1320                 freeenv(p);
1321         }
1322         p = kern_getenv("smbios.system.product");
1323         if (p != NULL) {
1324                 for (i = 0; vm_pnames[i] != NULL; i++)
1325                         if (strcmp(p, vm_pnames[i]) == 0) {
1326                                 vm_guest = VM_GUEST_VM;
1327                                 freeenv(p);
1328                                 return;
1329                         }
1330                 freeenv(p);
1331         }
1332 }
1333
1334 bool
1335 fix_cpuid(void)
1336 {
1337         uint64_t msr;
1338
1339         /*
1340          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1341          * get the largest standard CPUID function number again if it is set
1342          * from BIOS.  It is necessary for probing correct CPU topology later
1343          * and for the correct operation of the AVX-aware userspace.
1344          */
1345         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1346             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1347             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1348             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1349             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1350                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1351                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1352                         msr &= ~IA32_MISC_EN_LIMCPUID;
1353                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1354                         return (true);
1355                 }
1356         }
1357
1358         /*
1359          * Re-enable AMD Topology Extension that could be disabled by BIOS
1360          * on some notebook processors.  Without the extension it's really
1361          * hard to determine the correct CPU cache topology.
1362          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1363          * Models 60h-6Fh Processors, Publication # 50742.
1364          */
1365         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1366                 msr = rdmsr(MSR_EXTFEATURES);
1367                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1368                         msr |= (uint64_t)1 << 54;
1369                         wrmsr(MSR_EXTFEATURES, msr);
1370                         return (true);
1371                 }
1372         }
1373         return (false);
1374 }
1375
1376 #ifdef __amd64__
1377 void
1378 identify_cpu(void)
1379 {
1380         u_int regs[4];
1381
1382         do_cpuid(0, regs);
1383         cpu_high = regs[0];
1384         ((u_int *)&cpu_vendor)[0] = regs[1];
1385         ((u_int *)&cpu_vendor)[1] = regs[3];
1386         ((u_int *)&cpu_vendor)[2] = regs[2];
1387         cpu_vendor[12] = '\0';
1388
1389         do_cpuid(1, regs);
1390         cpu_id = regs[0];
1391         cpu_procinfo = regs[1];
1392         cpu_feature = regs[3];
1393         cpu_feature2 = regs[2];
1394 }
1395 #endif
1396
1397 /*
1398  * Final stage of CPU identification.
1399  */
1400 void
1401 finishidentcpu(void)
1402 {
1403         u_int regs[4], cpu_stdext_disable;
1404 #ifdef __i386__
1405         u_char ccr3;
1406 #endif
1407
1408         cpu_vendor_id = find_cpu_vendor_id();
1409
1410         if (fix_cpuid()) {
1411                 do_cpuid(0, regs);
1412                 cpu_high = regs[0];
1413         }
1414
1415         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1416                 do_cpuid(5, regs);
1417                 cpu_mon_mwait_flags = regs[2];
1418                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1419                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1420         }
1421
1422         if (cpu_high >= 7) {
1423                 cpuid_count(7, 0, regs);
1424                 cpu_stdext_feature = regs[1];
1425
1426                 /*
1427                  * Some hypervisors failed to filter out unsupported
1428                  * extended features.  Allow to disable the
1429                  * extensions, activation of which requires setting a
1430                  * bit in CR4, and which VM monitors do not support.
1431                  */
1432                 cpu_stdext_disable = 0;
1433                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1434                 cpu_stdext_feature &= ~cpu_stdext_disable;
1435
1436                 cpu_stdext_feature2 = regs[2];
1437         }
1438
1439 #ifdef __i386__
1440         if (cpu_high > 0 &&
1441             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1442              cpu_vendor_id == CPU_VENDOR_AMD ||
1443              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1444              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1445              cpu_vendor_id == CPU_VENDOR_NSC)) {
1446                 do_cpuid(0x80000000, regs);
1447                 if (regs[0] >= 0x80000000)
1448                         cpu_exthigh = regs[0];
1449         }
1450 #else
1451         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1452             cpu_vendor_id == CPU_VENDOR_AMD ||
1453             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1454                 do_cpuid(0x80000000, regs);
1455                 cpu_exthigh = regs[0];
1456         }
1457 #endif
1458         if (cpu_exthigh >= 0x80000001) {
1459                 do_cpuid(0x80000001, regs);
1460                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1461                 amd_feature2 = regs[2];
1462         }
1463         if (cpu_exthigh >= 0x80000007) {
1464                 do_cpuid(0x80000007, regs);
1465                 amd_rascap = regs[1];
1466                 amd_pminfo = regs[3];
1467         }
1468         if (cpu_exthigh >= 0x80000008) {
1469                 do_cpuid(0x80000008, regs);
1470                 cpu_maxphyaddr = regs[0] & 0xff;
1471                 cpu_procinfo2 = regs[2];
1472         } else {
1473                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1474         }
1475
1476 #ifdef __i386__
1477         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1478                 if (cpu == CPU_486) {
1479                         /*
1480                          * These conditions are equivalent to:
1481                          *     - CPU does not support cpuid instruction.
1482                          *     - Cyrix/IBM CPU is detected.
1483                          */
1484                         if (identblue() == IDENTBLUE_IBMCPU) {
1485                                 strcpy(cpu_vendor, "IBM");
1486                                 cpu_vendor_id = CPU_VENDOR_IBM;
1487                                 cpu = CPU_BLUE;
1488                                 return;
1489                         }
1490                 }
1491                 switch (cpu_id & 0xf00) {
1492                 case 0x600:
1493                         /*
1494                          * Cyrix's datasheet does not describe DIRs.
1495                          * Therefor, I assume it does not have them
1496                          * and use the result of the cpuid instruction.
1497                          * XXX they seem to have it for now at least. -Peter
1498                          */
1499                         identifycyrix();
1500                         cpu = CPU_M2;
1501                         break;
1502                 default:
1503                         identifycyrix();
1504                         /*
1505                          * This routine contains a trick.
1506                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1507                          */
1508                         switch (cyrix_did & 0x00f0) {
1509                         case 0x00:
1510                         case 0xf0:
1511                                 cpu = CPU_486DLC;
1512                                 break;
1513                         case 0x10:
1514                                 cpu = CPU_CY486DX;
1515                                 break;
1516                         case 0x20:
1517                                 if ((cyrix_did & 0x000f) < 8)
1518                                         cpu = CPU_M1;
1519                                 else
1520                                         cpu = CPU_M1SC;
1521                                 break;
1522                         case 0x30:
1523                                 cpu = CPU_M1;
1524                                 break;
1525                         case 0x40:
1526                                 /* MediaGX CPU */
1527                                 cpu = CPU_M1SC;
1528                                 break;
1529                         default:
1530                                 /* M2 and later CPUs are treated as M2. */
1531                                 cpu = CPU_M2;
1532
1533                                 /*
1534                                  * enable cpuid instruction.
1535                                  */
1536                                 ccr3 = read_cyrix_reg(CCR3);
1537                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1538                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1539                                 write_cyrix_reg(CCR3, ccr3);
1540
1541                                 do_cpuid(0, regs);
1542                                 cpu_high = regs[0];     /* eax */
1543                                 do_cpuid(1, regs);
1544                                 cpu_id = regs[0];       /* eax */
1545                                 cpu_feature = regs[3];  /* edx */
1546                                 break;
1547                         }
1548                 }
1549         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1550                 /*
1551                  * There are BlueLightning CPUs that do not change
1552                  * undefined flags by dividing 5 by 2.  In this case,
1553                  * the CPU identification routine in locore.s leaves
1554                  * cpu_vendor null string and puts CPU_486 into the
1555                  * cpu.
1556                  */
1557                 if (identblue() == IDENTBLUE_IBMCPU) {
1558                         strcpy(cpu_vendor, "IBM");
1559                         cpu_vendor_id = CPU_VENDOR_IBM;
1560                         cpu = CPU_BLUE;
1561                         return;
1562                 }
1563         }
1564 #endif
1565 }
1566
1567 static u_int
1568 find_cpu_vendor_id(void)
1569 {
1570         int     i;
1571
1572         for (i = 0; i < nitems(cpu_vendors); i++)
1573                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1574                         return (cpu_vendors[i].vendor_id);
1575         return (0);
1576 }
1577
1578 static void
1579 print_AMD_assoc(int i)
1580 {
1581         if (i == 255)
1582                 printf(", fully associative\n");
1583         else
1584                 printf(", %d-way associative\n", i);
1585 }
1586
1587 static void
1588 print_AMD_l2_assoc(int i)
1589 {
1590         switch (i & 0x0f) {
1591         case 0: printf(", disabled/not present\n"); break;
1592         case 1: printf(", direct mapped\n"); break;
1593         case 2: printf(", 2-way associative\n"); break;
1594         case 4: printf(", 4-way associative\n"); break;
1595         case 6: printf(", 8-way associative\n"); break;
1596         case 8: printf(", 16-way associative\n"); break;
1597         case 15: printf(", fully associative\n"); break;
1598         default: printf(", reserved configuration\n"); break;
1599         }
1600 }
1601
1602 static void
1603 print_AMD_info(void)
1604 {
1605 #ifdef __i386__
1606         uint64_t amd_whcr;
1607 #endif
1608         u_int regs[4];
1609
1610         if (cpu_exthigh >= 0x80000005) {
1611                 do_cpuid(0x80000005, regs);
1612                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1613                 print_AMD_assoc(regs[0] >> 24);
1614
1615                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1616                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1617
1618                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1619                 print_AMD_assoc(regs[1] >> 24);
1620
1621                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1622                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1623
1624                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1625                 printf(", %d bytes/line", regs[2] & 0xff);
1626                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1627                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1628
1629                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1630                 printf(", %d bytes/line", regs[3] & 0xff);
1631                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1632                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1633         }
1634
1635         if (cpu_exthigh >= 0x80000006) {
1636                 do_cpuid(0x80000006, regs);
1637                 if ((regs[0] >> 16) != 0) {
1638                         printf("L2 2MB data TLB: %d entries",
1639                             (regs[0] >> 16) & 0xfff);
1640                         print_AMD_l2_assoc(regs[0] >> 28);
1641                         printf("L2 2MB instruction TLB: %d entries",
1642                             regs[0] & 0xfff);
1643                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1644                 } else {
1645                         printf("L2 2MB unified TLB: %d entries",
1646                             regs[0] & 0xfff);
1647                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1648                 }
1649                 if ((regs[1] >> 16) != 0) {
1650                         printf("L2 4KB data TLB: %d entries",
1651                             (regs[1] >> 16) & 0xfff);
1652                         print_AMD_l2_assoc(regs[1] >> 28);
1653
1654                         printf("L2 4KB instruction TLB: %d entries",
1655                             (regs[1] >> 16) & 0xfff);
1656                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1657                 } else {
1658                         printf("L2 4KB unified TLB: %d entries",
1659                             (regs[1] >> 16) & 0xfff);
1660                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1661                 }
1662                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1663                 printf(", %d bytes/line", regs[2] & 0xff);
1664                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1665                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1666         }
1667
1668 #ifdef __i386__
1669         if (((cpu_id & 0xf00) == 0x500)
1670             && (((cpu_id & 0x0f0) > 0x80)
1671                 || (((cpu_id & 0x0f0) == 0x80)
1672                     && (cpu_id & 0x00f) > 0x07))) {
1673                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1674                 amd_whcr = rdmsr(0xc0000082);
1675                 if (!(amd_whcr & (0x3ff << 22))) {
1676                         printf("Write Allocate Disable\n");
1677                 } else {
1678                         printf("Write Allocate Enable Limit: %dM bytes\n",
1679                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1680                         printf("Write Allocate 15-16M bytes: %s\n",
1681                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1682                 }
1683         } else if (((cpu_id & 0xf00) == 0x500)
1684                    && ((cpu_id & 0x0f0) > 0x50)) {
1685                 /* K6, K6-2(old core) */
1686                 amd_whcr = rdmsr(0xc0000082);
1687                 if (!(amd_whcr & (0x7f << 1))) {
1688                         printf("Write Allocate Disable\n");
1689                 } else {
1690                         printf("Write Allocate Enable Limit: %dM bytes\n",
1691                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1692                         printf("Write Allocate 15-16M bytes: %s\n",
1693                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1694                         printf("Hardware Write Allocate Control: %s\n",
1695                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1696                 }
1697         }
1698 #endif
1699         /*
1700          * Opteron Rev E shows a bug as in very rare occasions a read memory
1701          * barrier is not performed as expected if it is followed by a
1702          * non-atomic read-modify-write instruction.
1703          * As long as that bug pops up very rarely (intensive machine usage
1704          * on other operating systems generally generates one unexplainable
1705          * crash any 2 months) and as long as a model specific fix would be
1706          * impractical at this stage, print out a warning string if the broken
1707          * model and family are identified.
1708          */
1709         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1710             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1711                 printf("WARNING: This architecture revision has known SMP "
1712                     "hardware bugs which may cause random instability\n");
1713 }
1714
1715 static void
1716 print_INTEL_info(void)
1717 {
1718         u_int regs[4];
1719         u_int rounds, regnum;
1720         u_int nwaycode, nway;
1721
1722         if (cpu_high >= 2) {
1723                 rounds = 0;
1724                 do {
1725                         do_cpuid(0x2, regs);
1726                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1727                                 break;  /* we have a buggy CPU */
1728
1729                         for (regnum = 0; regnum <= 3; ++regnum) {
1730                                 if (regs[regnum] & (1<<31))
1731                                         continue;
1732                                 if (regnum != 0)
1733                                         print_INTEL_TLB(regs[regnum] & 0xff);
1734                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1735                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1736                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1737                         }
1738                 } while (--rounds > 0);
1739         }
1740
1741         if (cpu_exthigh >= 0x80000006) {
1742                 do_cpuid(0x80000006, regs);
1743                 nwaycode = (regs[2] >> 12) & 0x0f;
1744                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1745                         nway = 1 << (nwaycode / 2);
1746                 else
1747                         nway = 0;
1748                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1749                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1750         }
1751 }
1752
1753 static void
1754 print_INTEL_TLB(u_int data)
1755 {
1756         switch (data) {
1757         case 0x0:
1758         case 0x40:
1759         default:
1760                 break;
1761         case 0x1:
1762                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1763                 break;
1764         case 0x2:
1765                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1766                 break;
1767         case 0x3:
1768                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1769                 break;
1770         case 0x4:
1771                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1772                 break;
1773         case 0x6:
1774                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1775                 break;
1776         case 0x8:
1777                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1778                 break;
1779         case 0x9:
1780                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1781                 break;
1782         case 0xa:
1783                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1784                 break;
1785         case 0xb:
1786                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1787                 break;
1788         case 0xc:
1789                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1790                 break;
1791         case 0xd:
1792                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1793                 break;
1794         case 0xe:
1795                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1796                 break;
1797         case 0x1d:
1798                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1799                 break;
1800         case 0x21:
1801                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1802                 break;
1803         case 0x22:
1804                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1805                 break;
1806         case 0x23:
1807                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1808                 break;
1809         case 0x24:
1810                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1811                 break;
1812         case 0x25:
1813                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1814                 break;
1815         case 0x29:
1816                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1817                 break;
1818         case 0x2c:
1819                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1820                 break;
1821         case 0x30:
1822                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1823                 break;
1824         case 0x39: /* De-listed in SDM rev. 54 */
1825                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1826                 break;
1827         case 0x3b: /* De-listed in SDM rev. 54 */
1828                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1829                 break;
1830         case 0x3c: /* De-listed in SDM rev. 54 */
1831                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1832                 break;
1833         case 0x41:
1834                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1835                 break;
1836         case 0x42:
1837                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1838                 break;
1839         case 0x43:
1840                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1841                 break;
1842         case 0x44:
1843                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1844                 break;
1845         case 0x45:
1846                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1847                 break;
1848         case 0x46:
1849                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1850                 break;
1851         case 0x47:
1852                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1853                 break;
1854         case 0x48:
1855                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1856                 break;
1857         case 0x49:
1858                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1859                     CPUID_TO_MODEL(cpu_id) == 0x6)
1860                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1861                 else
1862                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1863                 break;
1864         case 0x4a:
1865                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1866                 break;
1867         case 0x4b:
1868                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1869                 break;
1870         case 0x4c:
1871                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1872                 break;
1873         case 0x4d:
1874                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1875                 break;
1876         case 0x4e:
1877                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1878                 break;
1879         case 0x4f:
1880                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1881                 break;
1882         case 0x50:
1883                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1884                 break;
1885         case 0x51:
1886                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1887                 break;
1888         case 0x52:
1889                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1890                 break;
1891         case 0x55:
1892                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1893                 break;
1894         case 0x56:
1895                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1896                 break;
1897         case 0x57:
1898                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1899                 break;
1900         case 0x59:
1901                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1902                 break;
1903         case 0x5a:
1904                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1905                 break;
1906         case 0x5b:
1907                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1908                 break;
1909         case 0x5c:
1910                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1911                 break;
1912         case 0x5d:
1913                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1914                 break;
1915         case 0x60:
1916                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1917                 break;
1918         case 0x61:
1919                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1920                 break;
1921         case 0x63:
1922                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1923                 break;
1924         case 0x64:
1925                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1926                 break;
1927         case 0x66:
1928                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1929                 break;
1930         case 0x67:
1931                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1932                 break;
1933         case 0x68:
1934                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1935                 break;
1936         case 0x6a:
1937                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1938                 break;
1939         case 0x6b:
1940                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1941                 break;
1942         case 0x6c:
1943                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1944                 break;
1945         case 0x6d:
1946                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1947                 break;
1948         case 0x70:
1949                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1950                 break;
1951         case 0x71:
1952                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1953                 break;
1954         case 0x72:
1955                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1956                 break;
1957         case 0x76:
1958                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1959                 break;
1960         case 0x78:
1961                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1962                 break;
1963         case 0x79:
1964                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1965                 break;
1966         case 0x7a:
1967                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1968                 break;
1969         case 0x7b:
1970                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1971                 break;
1972         case 0x7c:
1973                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1974                 break;
1975         case 0x7d:
1976                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1977                 break;
1978         case 0x7f:
1979                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1980                 break;
1981         case 0x80:
1982                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1983                 break;
1984         case 0x82:
1985                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1986                 break;
1987         case 0x83:
1988                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1989                 break;
1990         case 0x84:
1991                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1992                 break;
1993         case 0x85:
1994                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1995                 break;
1996         case 0x86:
1997                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1998                 break;
1999         case 0x87:
2000                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2001                 break;
2002         case 0xa0:
2003                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2004                 break;
2005         case 0xb0:
2006                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2007                 break;
2008         case 0xb1:
2009                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2010                 break;
2011         case 0xb2:
2012                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2013                 break;
2014         case 0xb3:
2015                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2016                 break;
2017         case 0xb4:
2018                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2019                 break;
2020         case 0xb5:
2021                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2022                 break;
2023         case 0xb6:
2024                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2025                 break;
2026         case 0xba:
2027                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2028                 break;
2029         case 0xc0:
2030                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2031                 break;
2032         case 0xc1:
2033                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2034                 break;
2035         case 0xc2:
2036                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2037                 break;
2038         case 0xc3:
2039                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2040                 break;
2041         case 0xc4:
2042                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2043                 break;
2044         case 0xca:
2045                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2046                 break;
2047         case 0xd0:
2048                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2049                 break;
2050         case 0xd1:
2051                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2052                 break;
2053         case 0xd2:
2054                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2055                 break;
2056         case 0xd6:
2057                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2058                 break;
2059         case 0xd7:
2060                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2061                 break;
2062         case 0xd8:
2063                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2064                 break;
2065         case 0xdc:
2066                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2067                 break;
2068         case 0xdd:
2069                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2070                 break;
2071         case 0xde:
2072                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2073                 break;
2074         case 0xe2:
2075                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2076                 break;
2077         case 0xe3:
2078                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2079                 break;
2080         case 0xe4:
2081                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2082                 break;
2083         case 0xea:
2084                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2085                 break;
2086         case 0xeb:
2087                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2088                 break;
2089         case 0xec:
2090                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2091                 break;
2092         case 0xf0:
2093                 printf("64-Byte prefetching\n");
2094                 break;
2095         case 0xf1:
2096                 printf("128-Byte prefetching\n");
2097                 break;
2098         }
2099 }
2100
2101 static void
2102 print_svm_info(void)
2103 {
2104         u_int features, regs[4];
2105         uint64_t msr;
2106         int comma;
2107
2108         printf("\n  SVM: ");
2109         do_cpuid(0x8000000A, regs);
2110         features = regs[3];
2111
2112         msr = rdmsr(MSR_VM_CR);
2113         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2114                 printf("(disabled in BIOS) ");
2115
2116         if (!bootverbose) {
2117                 comma = 0;
2118                 if (features & (1 << 0)) {
2119                         printf("%sNP", comma ? "," : "");
2120                         comma = 1;
2121                 }
2122                 if (features & (1 << 3)) {
2123                         printf("%sNRIP", comma ? "," : "");
2124                         comma = 1;
2125                 }
2126                 if (features & (1 << 5)) {
2127                         printf("%sVClean", comma ? "," : "");
2128                         comma = 1;
2129                 }
2130                 if (features & (1 << 6)) {
2131                         printf("%sAFlush", comma ? "," : "");
2132                         comma = 1;
2133                 }
2134                 if (features & (1 << 7)) {
2135                         printf("%sDAssist", comma ? "," : "");
2136                         comma = 1;
2137                 }
2138                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2139                 return;
2140         }
2141
2142         printf("Features=0x%b", features,
2143                "\020"
2144                "\001NP"                 /* Nested paging */
2145                "\002LbrVirt"            /* LBR virtualization */
2146                "\003SVML"               /* SVM lock */
2147                "\004NRIPS"              /* NRIP save */
2148                "\005TscRateMsr"         /* MSR based TSC rate control */
2149                "\006VmcbClean"          /* VMCB clean bits */
2150                "\007FlushByAsid"        /* Flush by ASID */
2151                "\010DecodeAssist"       /* Decode assist */
2152                "\011<b8>"
2153                "\012<b9>"
2154                "\013PauseFilter"        /* PAUSE intercept filter */
2155                "\014<b11>"
2156                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2157                "\016AVIC"               /* virtual interrupt controller */
2158                 );
2159         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2160 }
2161
2162 #ifdef __i386__
2163 static void
2164 print_transmeta_info(void)
2165 {
2166         u_int regs[4], nreg = 0;
2167
2168         do_cpuid(0x80860000, regs);
2169         nreg = regs[0];
2170         if (nreg >= 0x80860001) {
2171                 do_cpuid(0x80860001, regs);
2172                 printf("  Processor revision %u.%u.%u.%u\n",
2173                        (regs[1] >> 24) & 0xff,
2174                        (regs[1] >> 16) & 0xff,
2175                        (regs[1] >> 8) & 0xff,
2176                        regs[1] & 0xff);
2177         }
2178         if (nreg >= 0x80860002) {
2179                 do_cpuid(0x80860002, regs);
2180                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2181                        (regs[1] >> 24) & 0xff,
2182                        (regs[1] >> 16) & 0xff,
2183                        (regs[1] >> 8) & 0xff,
2184                        regs[1] & 0xff,
2185                        regs[2]);
2186         }
2187         if (nreg >= 0x80860006) {
2188                 char info[65];
2189                 do_cpuid(0x80860003, (u_int*) &info[0]);
2190                 do_cpuid(0x80860004, (u_int*) &info[16]);
2191                 do_cpuid(0x80860005, (u_int*) &info[32]);
2192                 do_cpuid(0x80860006, (u_int*) &info[48]);
2193                 info[64] = 0;
2194                 printf("  %s\n", info);
2195         }
2196 }
2197 #endif
2198
2199 static void
2200 print_via_padlock_info(void)
2201 {
2202         u_int regs[4];
2203
2204         do_cpuid(0xc0000001, regs);
2205         printf("\n  VIA Padlock Features=0x%b", regs[3],
2206         "\020"
2207         "\003RNG"               /* RNG */
2208         "\007AES"               /* ACE */
2209         "\011AES-CTR"           /* ACE2 */
2210         "\013SHA1,SHA256"       /* PHE */
2211         "\015RSA"               /* PMM */
2212         );
2213 }
2214
2215 static uint32_t
2216 vmx_settable(uint64_t basic, int msr, int true_msr)
2217 {
2218         uint64_t val;
2219
2220         if (basic & (1ULL << 55))
2221                 val = rdmsr(true_msr);
2222         else
2223                 val = rdmsr(msr);
2224
2225         /* Just report the controls that can be set to 1. */
2226         return (val >> 32);
2227 }
2228
2229 static void
2230 print_vmx_info(void)
2231 {
2232         uint64_t basic, msr;
2233         uint32_t entry, exit, mask, pin, proc, proc2;
2234         int comma;
2235
2236         printf("\n  VT-x: ");
2237         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2238         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2239                 printf("(disabled in BIOS) ");
2240         basic = rdmsr(MSR_VMX_BASIC);
2241         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2242             MSR_VMX_TRUE_PINBASED_CTLS);
2243         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2244             MSR_VMX_TRUE_PROCBASED_CTLS);
2245         if (proc & PROCBASED_SECONDARY_CONTROLS)
2246                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2247                     MSR_VMX_PROCBASED_CTLS2);
2248         else
2249                 proc2 = 0;
2250         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2251         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2252
2253         if (!bootverbose) {
2254                 comma = 0;
2255                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2256                     entry & VM_ENTRY_LOAD_PAT) {
2257                         printf("%sPAT", comma ? "," : "");
2258                         comma = 1;
2259                 }
2260                 if (proc & PROCBASED_HLT_EXITING) {
2261                         printf("%sHLT", comma ? "," : "");
2262                         comma = 1;
2263                 }
2264                 if (proc & PROCBASED_MTF) {
2265                         printf("%sMTF", comma ? "," : "");
2266                         comma = 1;
2267                 }
2268                 if (proc & PROCBASED_PAUSE_EXITING) {
2269                         printf("%sPAUSE", comma ? "," : "");
2270                         comma = 1;
2271                 }
2272                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2273                         printf("%sEPT", comma ? "," : "");
2274                         comma = 1;
2275                 }
2276                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2277                         printf("%sUG", comma ? "," : "");
2278                         comma = 1;
2279                 }
2280                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2281                         printf("%sVPID", comma ? "," : "");
2282                         comma = 1;
2283                 }
2284                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2285                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2286                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2287                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2288                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2289                         printf("%sVID", comma ? "," : "");
2290                         comma = 1;
2291                         if (pin & PINBASED_POSTED_INTERRUPT)
2292                                 printf(",PostIntr");
2293                 }
2294                 return;
2295         }
2296
2297         mask = basic >> 32;
2298         printf("Basic Features=0x%b", mask,
2299         "\020"
2300         "\02132PA"              /* 32-bit physical addresses */
2301         "\022SMM"               /* SMM dual-monitor */
2302         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2303         "\030TRUE"              /* TRUE_CTLS MSRs */
2304         );
2305         printf("\n        Pin-Based Controls=0x%b", pin,
2306         "\020"
2307         "\001ExtINT"            /* External-interrupt exiting */
2308         "\004NMI"               /* NMI exiting */
2309         "\006VNMI"              /* Virtual NMIs */
2310         "\007PreTmr"            /* Activate VMX-preemption timer */
2311         "\010PostIntr"          /* Process posted interrupts */
2312         );
2313         printf("\n        Primary Processor Controls=0x%b", proc,
2314         "\020"
2315         "\003INTWIN"            /* Interrupt-window exiting */
2316         "\004TSCOff"            /* Use TSC offsetting */
2317         "\010HLT"               /* HLT exiting */
2318         "\012INVLPG"            /* INVLPG exiting */
2319         "\013MWAIT"             /* MWAIT exiting */
2320         "\014RDPMC"             /* RDPMC exiting */
2321         "\015RDTSC"             /* RDTSC exiting */
2322         "\020CR3-LD"            /* CR3-load exiting */
2323         "\021CR3-ST"            /* CR3-store exiting */
2324         "\024CR8-LD"            /* CR8-load exiting */
2325         "\025CR8-ST"            /* CR8-store exiting */
2326         "\026TPR"               /* Use TPR shadow */
2327         "\027NMIWIN"            /* NMI-window exiting */
2328         "\030MOV-DR"            /* MOV-DR exiting */
2329         "\031IO"                /* Unconditional I/O exiting */
2330         "\032IOmap"             /* Use I/O bitmaps */
2331         "\034MTF"               /* Monitor trap flag */
2332         "\035MSRmap"            /* Use MSR bitmaps */
2333         "\036MONITOR"           /* MONITOR exiting */
2334         "\037PAUSE"             /* PAUSE exiting */
2335         );
2336         if (proc & PROCBASED_SECONDARY_CONTROLS)
2337                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2338                 "\020"
2339                 "\001APIC"              /* Virtualize APIC accesses */
2340                 "\002EPT"               /* Enable EPT */
2341                 "\003DT"                /* Descriptor-table exiting */
2342                 "\004RDTSCP"            /* Enable RDTSCP */
2343                 "\005x2APIC"            /* Virtualize x2APIC mode */
2344                 "\006VPID"              /* Enable VPID */
2345                 "\007WBINVD"            /* WBINVD exiting */
2346                 "\010UG"                /* Unrestricted guest */
2347                 "\011APIC-reg"          /* APIC-register virtualization */
2348                 "\012VID"               /* Virtual-interrupt delivery */
2349                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2350                 "\014RDRAND"            /* RDRAND exiting */
2351                 "\015INVPCID"           /* Enable INVPCID */
2352                 "\016VMFUNC"            /* Enable VM functions */
2353                 "\017VMCS"              /* VMCS shadowing */
2354                 "\020EPT#VE"            /* EPT-violation #VE */
2355                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2356                 );
2357         printf("\n        Exit Controls=0x%b", mask,
2358         "\020"
2359         "\003DR"                /* Save debug controls */
2360                                 /* Ignore Host address-space size */
2361         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2362         "\020AckInt"            /* Acknowledge interrupt on exit */
2363         "\023PAT-SV"            /* Save MSR_PAT */
2364         "\024PAT-LD"            /* Load MSR_PAT */
2365         "\025EFER-SV"           /* Save MSR_EFER */
2366         "\026EFER-LD"           /* Load MSR_EFER */
2367         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2368         );
2369         printf("\n        Entry Controls=0x%b", mask,
2370         "\020"
2371         "\003DR"                /* Save debug controls */
2372                                 /* Ignore IA-32e mode guest */
2373                                 /* Ignore Entry to SMM */
2374                                 /* Ignore Deactivate dual-monitor treatment */
2375         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2376         "\017PAT"               /* Load MSR_PAT */
2377         "\020EFER"              /* Load MSR_EFER */
2378         );
2379         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2380             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2381                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2382                 mask = msr;
2383                 printf("\n        EPT Features=0x%b", mask,
2384                 "\020"
2385                 "\001XO"                /* Execute-only translations */
2386                 "\007PW4"               /* Page-walk length of 4 */
2387                 "\011UC"                /* EPT paging-structure mem can be UC */
2388                 "\017WB"                /* EPT paging-structure mem can be WB */
2389                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2390                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2391                 "\025INVEPT"            /* INVEPT is supported */
2392                 "\026AD"                /* Accessed and dirty flags for EPT */
2393                 "\032single"            /* INVEPT single-context type */
2394                 "\033all"               /* INVEPT all-context type */
2395                 );
2396                 mask = msr >> 32;
2397                 printf("\n        VPID Features=0x%b", mask,
2398                 "\020"
2399                 "\001INVVPID"           /* INVVPID is supported */
2400                 "\011individual"        /* INVVPID individual-address type */
2401                 "\012single"            /* INVVPID single-context type */
2402                 "\013all"               /* INVVPID all-context type */
2403                  /* INVVPID single-context-retaining-globals type */
2404                 "\014single-globals"
2405                 );
2406         }
2407 }
2408
2409 static void
2410 print_hypervisor_info(void)
2411 {
2412
2413         if (*hv_vendor)
2414                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2415 }