sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
  71 #define CPU_ENABLE_SSE
  72 #endif
  73
  74 #define IDENTBLUE_CYRIX486      0
  75 #define IDENTBLUE_IBMCPU        1
  76 #define IDENTBLUE_CYRIXM2       2
  77
  78 static void identifycyrix(void);
  79 static void print_transmeta_info(void);
  80 #endif
  81 static u_int find_cpu_vendor_id(void);
  82 static void print_AMD_info(void);
  83 static void print_INTEL_info(void);
  84 static void print_INTEL_TLB(u_int data);
  85 static void print_hypervisor_info(void);
  86 static void print_svm_info(void);
  87 static void print_via_padlock_info(void);
  88 static void print_vmx_info(void);
  89
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 u_int   cpu_feature;            /* Feature flags */
  93 u_int   cpu_feature2;           /* Feature flags */
  94 u_int   amd_feature;            /* AMD feature flags */
  95 u_int   amd_feature2;           /* AMD feature flags */
  96 u_int   amd_pminfo;             /* AMD advanced power management info */
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 #if defined(__amd64__) || defined(CPU_ENABLE_SSE)
 107 u_int   cpu_fxsr;               /* SSE enabled */
 108 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 109 #endif
 110 u_int   cpu_clflush_line_size = 32;
 111 u_int   cpu_stdext_feature;
 112 u_int   cpu_stdext_feature2;
 113 u_int   cpu_max_ext_state_size;
 114 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 115 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 116 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 117 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 118 char machine[] = MACHINE;
 119
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 121     &via_feature_rng, 0,
 122     "VIA RNG feature available in CPU");
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 124     &via_feature_xcrypt, 0,
 125     "VIA xcrypt feature available in CPU");
 126
 127 #ifdef __amd64__
 128 #ifdef SCTL_MASK32
 129 extern int adaptive_machine_arch;
 130 #endif
 131
 132 static int
 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 134 {
 135 #ifdef SCTL_MASK32
 136         static const char machine32[] = "i386";
 137 #endif
 138         int error;
 139
 140 #ifdef SCTL_MASK32
 141         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 142                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 143         else
 144 #endif
 145                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 146         return (error);
 147
 148 }
 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD,
 150     NULL, 0, sysctl_hw_machine, "A", "Machine class");
 151 #else
 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 153     machine, 0, "Machine class");
 154 #endif
 155
 156 static char cpu_model[128];
 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
 158     cpu_model, 0, "Machine model");
 159
 160 static int hw_clockrate;
 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 162     &hw_clockrate, 0, "CPU instruction clock rate");
 163
 164 u_int hv_high;
 165 char hv_vendor[16];
 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor, 0,
 167     "Hypervisor vendor");
 168
 169 static eventhandler_tag tsc_post_tag;
 170
 171 static char cpu_brand[48];
 172
 173 #ifdef __i386__
 174 #define MAX_BRAND_INDEX 8
 175
 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 177         NULL,                   /* No brand */
 178         "Intel Celeron",
 179         "Intel Pentium III",
 180         "Intel Pentium III Xeon",
 181         NULL,
 182         NULL,
 183         NULL,
 184         NULL,
 185         "Intel Pentium 4"
 186 };
 187 #endif
 188
 189 static struct {
 190         char    *cpu_name;
 191         int     cpu_class;
 192 } cpus[] = {
 193 #ifdef __i386__
 194         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 195         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 196         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 197         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 198         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 199         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 200         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 201         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 202         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 203         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 204         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 205         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 206         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 207         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 208         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 209         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 210         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 211 #else
 212         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
 213         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
 214 #endif
 215 };
 216
 217 static struct {
 218         char    *vendor;
 219         u_int   vendor_id;
 220 } cpu_vendors[] = {
 221         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 222         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 223         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 224 #ifdef __i386__
 225         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 226         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 227         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 228         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 229         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 230         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 231         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 232 #if 0
 233         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 234         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 235 #endif
 236 #endif
 237 };
 238
 239 void
 240 printcpuinfo(void)
 241 {
 242         u_int regs[4], i;
 243         char *brand;
 244
 245         cpu_class = cpus[cpu].cpu_class;
 246         printf("CPU: ");
 247         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 248
 249         /* Check for extended CPUID information and a processor name. */
 250         if (cpu_exthigh >= 0x80000004) {
 251                 brand = cpu_brand;
 252                 for (i = 0x80000002; i < 0x80000005; i++) {
 253                         do_cpuid(i, regs);
 254                         memcpy(brand, regs, sizeof(regs));
 255                         brand += sizeof(regs);
 256                 }
 257         }
 258
 259         switch (cpu_vendor_id) {
 260         case CPU_VENDOR_INTEL:
 261 #ifdef __i386__
 262                 if ((cpu_id & 0xf00) > 0x300) {
 263                         u_int brand_index;
 264
 265                         cpu_model[0] = '\0';
 266
 267                         switch (cpu_id & 0x3000) {
 268                         case 0x1000:
 269                                 strcpy(cpu_model, "Overdrive ");
 270                                 break;
 271                         case 0x2000:
 272                                 strcpy(cpu_model, "Dual ");
 273                                 break;
 274                         }
 275
 276                         switch (cpu_id & 0xf00) {
 277                         case 0x400:
 278                                 strcat(cpu_model, "i486 ");
 279                                 /* Check the particular flavor of 486 */
 280                                 switch (cpu_id & 0xf0) {
 281                                 case 0x00:
 282                                 case 0x10:
 283                                         strcat(cpu_model, "DX");
 284                                         break;
 285                                 case 0x20:
 286                                         strcat(cpu_model, "SX");
 287                                         break;
 288                                 case 0x30:
 289                                         strcat(cpu_model, "DX2");
 290                                         break;
 291                                 case 0x40:
 292                                         strcat(cpu_model, "SL");
 293                                         break;
 294                                 case 0x50:
 295                                         strcat(cpu_model, "SX2");
 296                                         break;
 297                                 case 0x70:
 298                                         strcat(cpu_model,
 299                                             "DX2 Write-Back Enhanced");
 300                                         break;
 301                                 case 0x80:
 302                                         strcat(cpu_model, "DX4");
 303                                         break;
 304                                 }
 305                                 break;
 306                         case 0x500:
 307                                 /* Check the particular flavor of 586 */
 308                                 strcat(cpu_model, "Pentium");
 309                                 switch (cpu_id & 0xf0) {
 310                                 case 0x00:
 311                                         strcat(cpu_model, " A-step");
 312                                         break;
 313                                 case 0x10:
 314                                         strcat(cpu_model, "/P5");
 315                                         break;
 316                                 case 0x20:
 317                                         strcat(cpu_model, "/P54C");
 318                                         break;
 319                                 case 0x30:
 320                                         strcat(cpu_model, "/P24T");
 321                                         break;
 322                                 case 0x40:
 323                                         strcat(cpu_model, "/P55C");
 324                                         break;
 325                                 case 0x70:
 326                                         strcat(cpu_model, "/P54C");
 327                                         break;
 328                                 case 0x80:
 329                                         strcat(cpu_model, "/P55C (quarter-micron)");
 330                                         break;
 331                                 default:
 332                                         /* nothing */
 333                                         break;
 334                                 }
 335 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 336                                 /*
 337                                  * XXX - If/when Intel fixes the bug, this
 338                                  * should also check the version of the
 339                                  * CPU, not just that it's a Pentium.
 340                                  */
 341                                 has_f00f_bug = 1;
 342 #endif
 343                                 break;
 344                         case 0x600:
 345                                 /* Check the particular flavor of 686 */
 346                                 switch (cpu_id & 0xf0) {
 347                                 case 0x00:
 348                                         strcat(cpu_model, "Pentium Pro A-step");
 349                                         break;
 350                                 case 0x10:
 351                                         strcat(cpu_model, "Pentium Pro");
 352                                         break;
 353                                 case 0x30:
 354                                 case 0x50:
 355                                 case 0x60:
 356                                         strcat(cpu_model,
 357                                 "Pentium II/Pentium II Xeon/Celeron");
 358                                         cpu = CPU_PII;
 359                                         break;
 360                                 case 0x70:
 361                                 case 0x80:
 362                                 case 0xa0:
 363                                 case 0xb0:
 364                                         strcat(cpu_model,
 365                                         "Pentium III/Pentium III Xeon/Celeron");
 366                                         cpu = CPU_PIII;
 367                                         break;
 368                                 default:
 369                                         strcat(cpu_model, "Unknown 80686");
 370                                         break;
 371                                 }
 372                                 break;
 373                         case 0xf00:
 374                                 strcat(cpu_model, "Pentium 4");
 375                                 cpu = CPU_P4;
 376                                 break;
 377                         default:
 378                                 strcat(cpu_model, "unknown");
 379                                 break;
 380                         }
 381
 382                         /*
 383                          * If we didn't get a brand name from the extended
 384                          * CPUID, try to look it up in the brand table.
 385                          */
 386                         if (cpu_high > 0 && *cpu_brand == '\0') {
 387                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 388                                 if (brand_index <= MAX_BRAND_INDEX &&
 389                                     cpu_brandtable[brand_index] != NULL)
 390                                         strcpy(cpu_brand,
 391                                             cpu_brandtable[brand_index]);
 392                         }
 393                 }
 394 #else
 395                 /* Please make up your mind folks! */
 396                 strcat(cpu_model, "EM64T");
 397 #endif
 398                 break;
 399         case CPU_VENDOR_AMD:
 400                 /*
 401                  * Values taken from AMD Processor Recognition
 402                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 403                  * (also describes ``Features'' encodings.
 404                  */
 405                 strcpy(cpu_model, "AMD ");
 406 #ifdef __i386__
 407                 switch (cpu_id & 0xFF0) {
 408                 case 0x410:
 409                         strcat(cpu_model, "Standard Am486DX");
 410                         break;
 411                 case 0x430:
 412                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 413                         break;
 414                 case 0x470:
 415                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 416                         break;
 417                 case 0x480:
 418                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 419                         break;
 420                 case 0x490:
 421                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 422                         break;
 423                 case 0x4E0:
 424                         strcat(cpu_model, "Am5x86 Write-Through");
 425                         break;
 426                 case 0x4F0:
 427                         strcat(cpu_model, "Am5x86 Write-Back");
 428                         break;
 429                 case 0x500:
 430                         strcat(cpu_model, "K5 model 0");
 431                         break;
 432                 case 0x510:
 433                         strcat(cpu_model, "K5 model 1");
 434                         break;
 435                 case 0x520:
 436                         strcat(cpu_model, "K5 PR166 (model 2)");
 437                         break;
 438                 case 0x530:
 439                         strcat(cpu_model, "K5 PR200 (model 3)");
 440                         break;
 441                 case 0x560:
 442                         strcat(cpu_model, "K6");
 443                         break;
 444                 case 0x570:
 445                         strcat(cpu_model, "K6 266 (model 1)");
 446                         break;
 447                 case 0x580:
 448                         strcat(cpu_model, "K6-2");
 449                         break;
 450                 case 0x590:
 451                         strcat(cpu_model, "K6-III");
 452                         break;
 453                 case 0x5a0:
 454                         strcat(cpu_model, "Geode LX");
 455                         break;
 456                 default:
 457                         strcat(cpu_model, "Unknown");
 458                         break;
 459                 }
 460 #else
 461                 if ((cpu_id & 0xf00) == 0xf00)
 462                         strcat(cpu_model, "AMD64 Processor");
 463                 else
 464                         strcat(cpu_model, "Unknown");
 465 #endif
 466                 break;
 467 #ifdef __i386__
 468         case CPU_VENDOR_CYRIX:
 469                 strcpy(cpu_model, "Cyrix ");
 470                 switch (cpu_id & 0xff0) {
 471                 case 0x440:
 472                         strcat(cpu_model, "MediaGX");
 473                         break;
 474                 case 0x520:
 475                         strcat(cpu_model, "6x86");
 476                         break;
 477                 case 0x540:
 478                         cpu_class = CPUCLASS_586;
 479                         strcat(cpu_model, "GXm");
 480                         break;
 481                 case 0x600:
 482                         strcat(cpu_model, "6x86MX");
 483                         break;
 484                 default:
 485                         /*
 486                          * Even though CPU supports the cpuid
 487                          * instruction, it can be disabled.
 488                          * Therefore, this routine supports all Cyrix
 489                          * CPUs.
 490                          */
 491                         switch (cyrix_did & 0xf0) {
 492                         case 0x00:
 493                                 switch (cyrix_did & 0x0f) {
 494                                 case 0x00:
 495                                         strcat(cpu_model, "486SLC");
 496                                         break;
 497                                 case 0x01:
 498                                         strcat(cpu_model, "486DLC");
 499                                         break;
 500                                 case 0x02:
 501                                         strcat(cpu_model, "486SLC2");
 502                                         break;
 503                                 case 0x03:
 504                                         strcat(cpu_model, "486DLC2");
 505                                         break;
 506                                 case 0x04:
 507                                         strcat(cpu_model, "486SRx");
 508                                         break;
 509                                 case 0x05:
 510                                         strcat(cpu_model, "486DRx");
 511                                         break;
 512                                 case 0x06:
 513                                         strcat(cpu_model, "486SRx2");
 514                                         break;
 515                                 case 0x07:
 516                                         strcat(cpu_model, "486DRx2");
 517                                         break;
 518                                 case 0x08:
 519                                         strcat(cpu_model, "486SRu");
 520                                         break;
 521                                 case 0x09:
 522                                         strcat(cpu_model, "486DRu");
 523                                         break;
 524                                 case 0x0a:
 525                                         strcat(cpu_model, "486SRu2");
 526                                         break;
 527                                 case 0x0b:
 528                                         strcat(cpu_model, "486DRu2");
 529                                         break;
 530                                 default:
 531                                         strcat(cpu_model, "Unknown");
 532                                         break;
 533                                 }
 534                                 break;
 535                         case 0x10:
 536                                 switch (cyrix_did & 0x0f) {
 537                                 case 0x00:
 538                                         strcat(cpu_model, "486S");
 539                                         break;
 540                                 case 0x01:
 541                                         strcat(cpu_model, "486S2");
 542                                         break;
 543                                 case 0x02:
 544                                         strcat(cpu_model, "486Se");
 545                                         break;
 546                                 case 0x03:
 547                                         strcat(cpu_model, "486S2e");
 548                                         break;
 549                                 case 0x0a:
 550                                         strcat(cpu_model, "486DX");
 551                                         break;
 552                                 case 0x0b:
 553                                         strcat(cpu_model, "486DX2");
 554                                         break;
 555                                 case 0x0f:
 556                                         strcat(cpu_model, "486DX4");
 557                                         break;
 558                                 default:
 559                                         strcat(cpu_model, "Unknown");
 560                                         break;
 561                                 }
 562                                 break;
 563                         case 0x20:
 564                                 if ((cyrix_did & 0x0f) < 8)
 565                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 566                                 else
 567                                         strcat(cpu_model, "5x86");
 568                                 break;
 569                         case 0x30:
 570                                 strcat(cpu_model, "6x86");
 571                                 break;
 572                         case 0x40:
 573                                 if ((cyrix_did & 0xf000) == 0x3000) {
 574                                         cpu_class = CPUCLASS_586;
 575                                         strcat(cpu_model, "GXm");
 576                                 } else
 577                                         strcat(cpu_model, "MediaGX");
 578                                 break;
 579                         case 0x50:
 580                                 strcat(cpu_model, "6x86MX");
 581                                 break;
 582                         case 0xf0:
 583                                 switch (cyrix_did & 0x0f) {
 584                                 case 0x0d:
 585                                         strcat(cpu_model, "Overdrive CPU");
 586                                         break;
 587                                 case 0x0e:
 588                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 589                                         break;
 590                                 case 0x0f:
 591                                         strcat(cpu_model, "486SLC/DLC");
 592                                         break;
 593                                 default:
 594                                         strcat(cpu_model, "Unknown");
 595                                         break;
 596                                 }
 597                                 break;
 598                         default:
 599                                 strcat(cpu_model, "Unknown");
 600                                 break;
 601                         }
 602                         break;
 603                 }
 604                 break;
 605         case CPU_VENDOR_RISE:
 606                 strcpy(cpu_model, "Rise ");
 607                 switch (cpu_id & 0xff0) {
 608                 case 0x500:     /* 6401 and 6441 (Kirin) */
 609                 case 0x520:     /* 6510 (Lynx) */
 610                         strcat(cpu_model, "mP6");
 611                         break;
 612                 default:
 613                         strcat(cpu_model, "Unknown");
 614                 }
 615                 break;
 616 #endif
 617         case CPU_VENDOR_CENTAUR:
 618 #ifdef __i386__
 619                 switch (cpu_id & 0xff0) {
 620                 case 0x540:
 621                         strcpy(cpu_model, "IDT WinChip C6");
 622                         break;
 623                 case 0x580:
 624                         strcpy(cpu_model, "IDT WinChip 2");
 625                         break;
 626                 case 0x590:
 627                         strcpy(cpu_model, "IDT WinChip 3");
 628                         break;
 629                 case 0x660:
 630                         strcpy(cpu_model, "VIA C3 Samuel");
 631                         break;
 632                 case 0x670:
 633                         if (cpu_id & 0x8)
 634                                 strcpy(cpu_model, "VIA C3 Ezra");
 635                         else
 636                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 637                         break;
 638                 case 0x680:
 639                         strcpy(cpu_model, "VIA C3 Ezra-T");
 640                         break;
 641                 case 0x690:
 642                         strcpy(cpu_model, "VIA C3 Nehemiah");
 643                         break;
 644                 case 0x6a0:
 645                 case 0x6d0:
 646                         strcpy(cpu_model, "VIA C7 Esther");
 647                         break;
 648                 case 0x6f0:
 649                         strcpy(cpu_model, "VIA Nano");
 650                         break;
 651                 default:
 652                         strcpy(cpu_model, "VIA/IDT Unknown");
 653                 }
 654 #else
 655                 strcpy(cpu_model, "VIA ");
 656                 if ((cpu_id & 0xff0) == 0x6f0)
 657                         strcat(cpu_model, "Nano Processor");
 658                 else
 659                         strcat(cpu_model, "Unknown");
 660 #endif
 661                 break;
 662 #ifdef __i386__
 663         case CPU_VENDOR_IBM:
 664                 strcpy(cpu_model, "Blue Lightning CPU");
 665                 break;
 666         case CPU_VENDOR_NSC:
 667                 switch (cpu_id & 0xff0) {
 668                 case 0x540:
 669                         strcpy(cpu_model, "Geode SC1100");
 670                         cpu = CPU_GEODE1100;
 671                         break;
 672                 default:
 673                         strcpy(cpu_model, "Geode/NSC unknown");
 674                         break;
 675                 }
 676                 break;
 677 #endif
 678         default:
 679                 strcat(cpu_model, "Unknown");
 680                 break;
 681         }
 682
 683         /*
 684          * Replace cpu_model with cpu_brand minus leading spaces if
 685          * we have one.
 686          */
 687         brand = cpu_brand;
 688         while (*brand == ' ')
 689                 ++brand;
 690         if (*brand != '\0')
 691                 strcpy(cpu_model, brand);
 692
 693         printf("%s (", cpu_model);
 694         if (tsc_freq != 0) {
 695                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 696                 printf("%jd.%02d-MHz ",
 697                     (intmax_t)(tsc_freq + 4999) / 1000000,
 698                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 699         }
 700         switch(cpu_class) {
 701 #ifdef __i386__
 702         case CPUCLASS_286:
 703                 printf("286");
 704                 break;
 705         case CPUCLASS_386:
 706                 printf("386");
 707                 break;
 708 #if defined(I486_CPU)
 709         case CPUCLASS_486:
 710                 printf("486");
 711                 break;
 712 #endif
 713 #if defined(I586_CPU)
 714         case CPUCLASS_586:
 715                 printf("586");
 716                 break;
 717 #endif
 718 #if defined(I686_CPU)
 719         case CPUCLASS_686:
 720                 printf("686");
 721                 break;
 722 #endif
 723 #else
 724         case CPUCLASS_K8:
 725                 printf("K8");
 726                 break;
 727 #endif
 728         default:
 729                 printf("Unknown");      /* will panic below... */
 730         }
 731         printf("-class CPU)\n");
 732         if (*cpu_vendor)
 733                 printf("  Origin=\"%s\"", cpu_vendor);
 734         if (cpu_id)
 735                 printf("  Id=0x%x", cpu_id);
 736
 737         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 738             cpu_vendor_id == CPU_VENDOR_AMD ||
 739             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 740 #ifdef __i386__
 741             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 742             cpu_vendor_id == CPU_VENDOR_RISE ||
 743             cpu_vendor_id == CPU_VENDOR_NSC ||
 744             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 745 #endif
 746             0) {
 747                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 748                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 749                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 750 #ifdef __i386__
 751                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 752                         printf("\n  DIR=0x%04x", cyrix_did);
 753 #endif
 754
 755                 /*
 756                  * AMD CPUID Specification
 757                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 758                  *
 759                  * Intel Processor Identification and CPUID Instruction
 760                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 761                  */
 762                 if (cpu_high > 0) {
 763
 764                         /*
 765                          * Here we should probably set up flags indicating
 766                          * whether or not various features are available.
 767                          * The interesting ones are probably VME, PSE, PAE,
 768                          * and PGE.  The code already assumes without bothering
 769                          * to check that all CPUs >= Pentium have a TSC and
 770                          * MSRs.
 771                          */
 772                         printf("\n  Features=0x%b", cpu_feature,
 773                         "\020"
 774                         "\001FPU"       /* Integral FPU */
 775                         "\002VME"       /* Extended VM86 mode support */
 776                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 777                         "\004PSE"       /* 4MByte page tables */
 778                         "\005TSC"       /* Timestamp counter */
 779                         "\006MSR"       /* Machine specific registers */
 780                         "\007PAE"       /* Physical address extension */
 781                         "\010MCE"       /* Machine Check support */
 782                         "\011CX8"       /* CMPEXCH8 instruction */
 783                         "\012APIC"      /* SMP local APIC */
 784                         "\013oldMTRR"   /* Previous implementation of MTRR */
 785                         "\014SEP"       /* Fast System Call */
 786                         "\015MTRR"      /* Memory Type Range Registers */
 787                         "\016PGE"       /* PG_G (global bit) support */
 788                         "\017MCA"       /* Machine Check Architecture */
 789                         "\020CMOV"      /* CMOV instruction */
 790                         "\021PAT"       /* Page attributes table */
 791                         "\022PSE36"     /* 36 bit address space support */
 792                         "\023PN"        /* Processor Serial number */
 793                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 794                         "\025<b20>"
 795                         "\026DTS"       /* Debug Trace Store */
 796                         "\027ACPI"      /* ACPI support */
 797                         "\030MMX"       /* MMX instructions */
 798                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 799                         "\032SSE"       /* Streaming SIMD Extensions */
 800                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 801                         "\034SS"        /* Self snoop */
 802                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 803                         "\036TM"        /* Thermal Monitor clock slowdown */
 804                         "\037IA64"      /* CPU can execute IA64 instructions */
 805                         "\040PBE"       /* Pending Break Enable */
 806                         );
 807
 808                         if (cpu_feature2 != 0) {
 809                                 printf("\n  Features2=0x%b", cpu_feature2,
 810                                 "\020"
 811                                 "\001SSE3"      /* SSE3 */
 812                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 813                                 "\003DTES64"    /* 64-bit Debug Trace */
 814                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 815                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 816                                 "\006VMX"       /* Virtual Machine Extensions */
 817                                 "\007SMX"       /* Safer Mode Extensions */
 818                                 "\010EST"       /* Enhanced SpeedStep */
 819                                 "\011TM2"       /* Thermal Monitor 2 */
 820                                 "\012SSSE3"     /* SSSE3 */
 821                                 "\013CNXT-ID"   /* L1 context ID available */
 822                                 "\014SDBG"      /* IA32 silicon debug */
 823                                 "\015FMA"       /* Fused Multiply Add */
 824                                 "\016CX16"      /* CMPXCHG16B Instruction */
 825                                 "\017xTPR"      /* Send Task Priority Messages*/
 826                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 827                                 "\021<b16>"
 828                                 "\022PCID"      /* Process-context Identifiers*/
 829                                 "\023DCA"       /* Direct Cache Access */
 830                                 "\024SSE4.1"    /* SSE 4.1 */
 831                                 "\025SSE4.2"    /* SSE 4.2 */
 832                                 "\026x2APIC"    /* xAPIC Extensions */
 833                                 "\027MOVBE"     /* MOVBE Instruction */
 834                                 "\030POPCNT"    /* POPCNT Instruction */
 835                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 836                                 "\032AESNI"     /* AES Crypto */
 837                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 838                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 839                                 "\035AVX"       /* Advanced Vector Extensions */
 840                                 "\036F16C"      /* Half-precision conversions */
 841                                 "\037RDRAND"    /* RDRAND Instruction */
 842                                 "\040HV"        /* Hypervisor */
 843                                 );
 844                         }
 845
 846                         if (amd_feature != 0) {
 847                                 printf("\n  AMD Features=0x%b", amd_feature,
 848                                 "\020"          /* in hex */
 849                                 "\001<s0>"      /* Same */
 850                                 "\002<s1>"      /* Same */
 851                                 "\003<s2>"      /* Same */
 852                                 "\004<s3>"      /* Same */
 853                                 "\005<s4>"      /* Same */
 854                                 "\006<s5>"      /* Same */
 855                                 "\007<s6>"      /* Same */
 856                                 "\010<s7>"      /* Same */
 857                                 "\011<s8>"      /* Same */
 858                                 "\012<s9>"      /* Same */
 859                                 "\013<b10>"     /* Undefined */
 860                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 861                                 "\015<s12>"     /* Same */
 862                                 "\016<s13>"     /* Same */
 863                                 "\017<s14>"     /* Same */
 864                                 "\020<s15>"     /* Same */
 865                                 "\021<s16>"     /* Same */
 866                                 "\022<s17>"     /* Same */
 867                                 "\023<b18>"     /* Reserved, unknown */
 868                                 "\024MP"        /* Multiprocessor Capable */
 869                                 "\025NX"        /* Has EFER.NXE, NX */
 870                                 "\026<b21>"     /* Undefined */
 871                                 "\027MMX+"      /* AMD MMX Extensions */
 872                                 "\030<s23>"     /* Same */
 873                                 "\031<s24>"     /* Same */
 874                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 875                                 "\033Page1GB"   /* 1-GB large page support */
 876                                 "\034RDTSCP"    /* RDTSCP */
 877                                 "\035<b28>"     /* Undefined */
 878                                 "\036LM"        /* 64 bit long mode */
 879                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 880                                 "\0403DNow!"    /* AMD 3DNow! */
 881                                 );
 882                         }
 883
 884                         if (amd_feature2 != 0) {
 885                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 886                                 "\020"
 887                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 888                                 "\002CMP"       /* CMP legacy */
 889                                 "\003SVM"       /* Secure Virtual Mode */
 890                                 "\004ExtAPIC"   /* Extended APIC register */
 891                                 "\005CR8"       /* CR8 in legacy mode */
 892                                 "\006ABM"       /* LZCNT instruction */
 893                                 "\007SSE4A"     /* SSE4A */
 894                                 "\010MAS"       /* Misaligned SSE mode */
 895                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 896                                 "\012OSVW"      /* OS visible workaround */
 897                                 "\013IBS"       /* Instruction based sampling */
 898                                 "\014XOP"       /* XOP extended instructions */
 899                                 "\015SKINIT"    /* SKINIT/STGI */
 900                                 "\016WDT"       /* Watchdog timer */
 901                                 "\017<b14>"
 902                                 "\020LWP"       /* Lightweight Profiling */
 903                                 "\021FMA4"      /* 4-operand FMA instructions */
 904                                 "\022TCE"       /* Translation Cache Extension */
 905                                 "\023<b18>"
 906                                 "\024NodeId"    /* NodeId MSR support */
 907                                 "\025<b20>"
 908                                 "\026TBM"       /* Trailing Bit Manipulation */
 909                                 "\027Topology"  /* Topology Extensions */
 910                                 "\030PCXC"      /* Core perf count */
 911                                 "\031PNXC"      /* NB perf count */
 912                                 "\032<b25>"
 913                                 "\033DBE"       /* Data Breakpoint extension */
 914                                 "\034PTSC"      /* Performance TSC */
 915                                 "\035PL2I"      /* L2I perf count */
 916                                 "\036<b29>"
 917                                 "\037<b30>"
 918                                 "\040<b31>"
 919                                 );
 920                         }
 921
 922                         if (cpu_stdext_feature != 0) {
 923                                 printf("\n  Structured Extended Features=0x%b",
 924                                     cpu_stdext_feature,
 925                                        "\020"
 926                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 927                                        "\001FSGSBASE"
 928                                        "\002TSCADJ"
 929                                        /* Bit Manipulation Instructions */
 930                                        "\004BMI1"
 931                                        /* Hardware Lock Elision */
 932                                        "\005HLE"
 933                                        /* Advanced Vector Instructions 2 */
 934                                        "\006AVX2"
 935                                        /* Supervisor Mode Execution Prot. */
 936                                        "\010SMEP"
 937                                        /* Bit Manipulation Instructions */
 938                                        "\011BMI2"
 939                                        "\012ERMS"
 940                                        /* Invalidate Processor Context ID */
 941                                        "\013INVPCID"
 942                                        /* Restricted Transactional Memory */
 943                                        "\014RTM"
 944                                        "\015PQM"
 945                                        "\016NFPUSG"
 946                                        "\020PQE"
 947                                        /* Intel Memory Protection Extensions */
 948                                        "\017MPX"
 949                                        /* AVX512 Foundation */
 950                                        "\021AVX512F"
 951                                        "\022AVX512DQ"
 952                                        /* Enhanced NRBG */
 953                                        "\023RDSEED"
 954                                        /* ADCX + ADOX */
 955                                        "\024ADX"
 956                                        /* Supervisor Mode Access Prevention */
 957                                        "\025SMAP"
 958                                        "\026AVX512IFMA"
 959                                        "\027PCOMMIT"
 960                                        "\030CLFLUSHOPT"
 961                                        "\031CLWB"
 962                                        "\032PROCTRACE"
 963                                        "\033AVX512PF"
 964                                        "\034AVX512ER"
 965                                        "\035AVX512CD"
 966                                        "\036SHA"
 967                                        "\037AVX512BW"
 968                                        );
 969                         }
 970
 971                         if (cpu_stdext_feature2 != 0) {
 972                                 printf("\n  Structured Extended Features2=0x%b",
 973                                     cpu_stdext_feature2,
 974                                        "\020"
 975                                        "\001PREFETCHWT1"
 976                                        "\002AVX512VBMI"
 977                                        "\004PKU"
 978                                        "\005OSPKE"
 979                                        );
 980                         }
 981
 982                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 983                                 cpuid_count(0xd, 0x1, regs);
 984                                 if (regs[0] != 0) {
 985                                         printf("\n  XSAVE Features=0x%b",
 986                                             regs[0],
 987                                             "\020"
 988                                             "\001XSAVEOPT"
 989                                             "\002XSAVEC"
 990                                             "\003XINUSE"
 991                                             "\004XSAVES");
 992                                 }
 993                         }
 994
 995                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
 996                                 print_via_padlock_info();
 997
 998                         if (cpu_feature2 & CPUID2_VMX)
 999                                 print_vmx_info();
1000
1001                         if (amd_feature2 & AMDID2_SVM)
1002                                 print_svm_info();
1003
1004                         if ((cpu_feature & CPUID_HTT) &&
1005                             cpu_vendor_id == CPU_VENDOR_AMD)
1006                                 cpu_feature &= ~CPUID_HTT;
1007
1008                         /*
1009                          * If this CPU supports P-state invariant TSC then
1010                          * mention the capability.
1011                          */
1012                         if (tsc_is_invariant) {
1013                                 printf("\n  TSC: P-state invariant");
1014                                 if (tsc_perf_stat)
1015                                         printf(", performance statistics");
1016                         }
1017                 }
1018 #ifdef __i386__
1019         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1020                 printf("  DIR=0x%04x", cyrix_did);
1021                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1022                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1023 #ifndef CYRIX_CACHE_REALLY_WORKS
1024                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1025                         printf("\n  CPU cache: write-through mode");
1026 #endif
1027 #endif
1028         }
1029
1030         /* Avoid ugly blank lines: only print newline when we have to. */
1031         if (*cpu_vendor || cpu_id)
1032                 printf("\n");
1033
1034         if (bootverbose) {
1035                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1036                         print_AMD_info();
1037                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1038                         print_INTEL_info();
1039 #ifdef __i386__
1040                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1041                         print_transmeta_info();
1042 #endif
1043         }
1044
1045         print_hypervisor_info();
1046 }
1047
1048 void
1049 panicifcpuunsupported(void)
1050 {
1051
1052 #ifdef __i386__
1053 #if !defined(lint)
1054 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1055 #error This kernel is not configured for one of the supported CPUs
1056 #endif
1057 #else /* lint */
1058 #endif /* lint */
1059 #else /* __amd64__ */
1060 #ifndef HAMMER
1061 #error "You need to specify a cpu type"
1062 #endif
1063 #endif
1064         /*
1065          * Now that we have told the user what they have,
1066          * let them know if that machine type isn't configured.
1067          */
1068         switch (cpu_class) {
1069 #ifdef __i386__
1070         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1071         case CPUCLASS_386:
1072 #if !defined(I486_CPU)
1073         case CPUCLASS_486:
1074 #endif
1075 #if !defined(I586_CPU)
1076         case CPUCLASS_586:
1077 #endif
1078 #if !defined(I686_CPU)
1079         case CPUCLASS_686:
1080 #endif
1081 #else /* __amd64__ */
1082         case CPUCLASS_X86:
1083 #ifndef HAMMER
1084         case CPUCLASS_K8:
1085 #endif
1086 #endif
1087                 panic("CPU class not configured");
1088         default:
1089                 break;
1090         }
1091 }
1092
1093 #ifdef __i386__
1094 static  volatile u_int trap_by_rdmsr;
1095
1096 /*
1097  * Special exception 6 handler.
1098  * The rdmsr instruction generates invalid opcodes fault on 486-class
1099  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1100  * function identblue() when this handler is called.  Stacked eip should
1101  * be advanced.
1102  */
1103 inthand_t       bluetrap6;
1104 #ifdef __GNUCLIKE_ASM
1105 __asm
1106 ("                                                                      \n\
1107         .text                                                           \n\
1108         .p2align 2,0x90                                                 \n\
1109         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1110 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1111         ss                                                              \n\
1112         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1113         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1114         iret                                                            \n\
1115 ");
1116 #endif
1117
1118 /*
1119  * Special exception 13 handler.
1120  * Accessing non-existent MSR generates general protection fault.
1121  */
1122 inthand_t       bluetrap13;
1123 #ifdef __GNUCLIKE_ASM
1124 __asm
1125 ("                                                                      \n\
1126         .text                                                           \n\
1127         .p2align 2,0x90                                                 \n\
1128         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1129 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1130         ss                                                              \n\
1131         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1132         popl    %eax            /* discard error code */                \n\
1133         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1134         iret                                                            \n\
1135 ");
1136 #endif
1137
1138 /*
1139  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1140  * support cpuid instruction.  This function should be called after
1141  * loading interrupt descriptor table register.
1142  *
1143  * I don't like this method that handles fault, but I couldn't get
1144  * information for any other methods.  Does blue giant know?
1145  */
1146 static int
1147 identblue(void)
1148 {
1149
1150         trap_by_rdmsr = 0;
1151
1152         /*
1153          * Cyrix 486-class CPU does not support rdmsr instruction.
1154          * The rdmsr instruction generates invalid opcode fault, and exception
1155          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1156          * bluetrap6() set the magic number to trap_by_rdmsr.
1157          */
1158         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1159             GSEL(GCODE_SEL, SEL_KPL));
1160
1161         /*
1162          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1163          * In this case, rdmsr generates general protection fault, and
1164          * exception will be trapped by bluetrap13().
1165          */
1166         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1167             GSEL(GCODE_SEL, SEL_KPL));
1168
1169         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1170
1171         if (trap_by_rdmsr == 0xa8c1d)
1172                 return IDENTBLUE_CYRIX486;
1173         else if (trap_by_rdmsr == 0xa89c4)
1174                 return IDENTBLUE_CYRIXM2;
1175         return IDENTBLUE_IBMCPU;
1176 }
1177
1178
1179 /*
1180  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1181  *
1182  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1183  * +-------+-------+---------------+
1184  * |  SID  |  RID  |   Device ID   |
1185  * |    (DIR 1)    |    (DIR 0)    |
1186  * +-------+-------+---------------+
1187  */
1188 static void
1189 identifycyrix(void)
1190 {
1191         register_t saveintr;
1192         int     ccr2_test = 0, dir_test = 0;
1193         u_char  ccr2, ccr3;
1194
1195         saveintr = intr_disable();
1196
1197         ccr2 = read_cyrix_reg(CCR2);
1198         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1199         read_cyrix_reg(CCR2);
1200         if (read_cyrix_reg(CCR2) != ccr2)
1201                 ccr2_test = 1;
1202         write_cyrix_reg(CCR2, ccr2);
1203
1204         ccr3 = read_cyrix_reg(CCR3);
1205         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1206         read_cyrix_reg(CCR3);
1207         if (read_cyrix_reg(CCR3) != ccr3)
1208                 dir_test = 1;                                   /* CPU supports DIRs. */
1209         write_cyrix_reg(CCR3, ccr3);
1210
1211         if (dir_test) {
1212                 /* Device ID registers are available. */
1213                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1214                 cyrix_did += read_cyrix_reg(DIR0);
1215         } else if (ccr2_test)
1216                 cyrix_did = 0x0010;             /* 486S A-step */
1217         else
1218                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1219
1220         intr_restore(saveintr);
1221 }
1222 #endif
1223
1224 /* Update TSC freq with the value indicated by the caller. */
1225 static void
1226 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1227 {
1228
1229         /* If there was an error during the transition, don't do anything. */
1230         if (status != 0)
1231                 return;
1232
1233         /* Total setting for this level gives the new frequency in MHz. */
1234         hw_clockrate = level->total_set.freq;
1235 }
1236
1237 static void
1238 hook_tsc_freq(void *arg __unused)
1239 {
1240
1241         if (tsc_is_invariant)
1242                 return;
1243
1244         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1245             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1246 }
1247
1248 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1249
1250 static const char *const vm_bnames[] = {
1251         "QEMU",                         /* QEMU */
1252         "Plex86",                       /* Plex86 */
1253         "Bochs",                        /* Bochs */
1254         "Xen",                          /* Xen */
1255         "BHYVE",                        /* bhyve */
1256         "Seabios",                      /* KVM */
1257         NULL
1258 };
1259
1260 static const char *const vm_pnames[] = {
1261         "VMware Virtual Platform",      /* VMWare VM */
1262         "Virtual Machine",              /* Microsoft VirtualPC */
1263         "VirtualBox",                   /* Sun xVM VirtualBox */
1264         "Parallels Virtual Platform",   /* Parallels VM */
1265         "KVM",                          /* KVM */
1266         NULL
1267 };
1268
1269 static void
1270 identify_hypervisor(void)
1271 {
1272         u_int regs[4];
1273         char *p;
1274         int i;
1275
1276         /*
1277          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1278          * http://lkml.org/lkml/2008/10/1/246
1279          *
1280          * KB1009458: Mechanisms to determine if software is running in
1281          * a VMware virtual machine
1282          * http://kb.vmware.com/kb/1009458
1283          */
1284         if (cpu_feature2 & CPUID2_HV) {
1285                 vm_guest = VM_GUEST_VM;
1286                 do_cpuid(0x40000000, regs);
1287                 if (regs[0] >= 0x40000000) {
1288                         hv_high = regs[0];
1289                         ((u_int *)&hv_vendor)[0] = regs[1];
1290                         ((u_int *)&hv_vendor)[1] = regs[2];
1291                         ((u_int *)&hv_vendor)[2] = regs[3];
1292                         hv_vendor[12] = '\0';
1293                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1294                                 vm_guest = VM_GUEST_VMWARE;
1295                 }
1296                 return;
1297         }
1298
1299         /*
1300          * Examine SMBIOS strings for older hypervisors.
1301          */
1302         p = kern_getenv("smbios.system.serial");
1303         if (p != NULL) {
1304                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1305                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1306                         if (regs[1] == VMW_HVMAGIC) {
1307                                 vm_guest = VM_GUEST_VMWARE;
1308                                 freeenv(p);
1309                                 return;
1310                         }
1311                 }
1312                 freeenv(p);
1313         }
1314
1315         /*
1316          * XXX: Some of these entries may not be needed since they were
1317          * added to FreeBSD before the checks above.
1318          */
1319         p = kern_getenv("smbios.bios.vendor");
1320         if (p != NULL) {
1321                 for (i = 0; vm_bnames[i] != NULL; i++)
1322                         if (strcmp(p, vm_bnames[i]) == 0) {
1323                                 vm_guest = VM_GUEST_VM;
1324                                 freeenv(p);
1325                                 return;
1326                         }
1327                 freeenv(p);
1328         }
1329         p = kern_getenv("smbios.system.product");
1330         if (p != NULL) {
1331                 for (i = 0; vm_pnames[i] != NULL; i++)
1332                         if (strcmp(p, vm_pnames[i]) == 0) {
1333                                 vm_guest = VM_GUEST_VM;
1334                                 freeenv(p);
1335                                 return;
1336                         }
1337                 freeenv(p);
1338         }
1339 }
1340
1341 /*
1342  * Clear "Limit CPUID Maxval" bit and return true if the caller should
1343  * get the largest standard CPUID function number again if it is set
1344  * from BIOS.  It is necessary for probing correct CPU topology later
1345  * and for the correct operation of the AVX-aware userspace.
1346  */
1347 bool
1348 intel_fix_cpuid(void)
1349 {
1350         uint64_t msr;
1351
1352         if (cpu_vendor_id != CPU_VENDOR_INTEL)
1353                 return (false);
1354         if ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1355             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1356             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1357             CPUID_TO_MODEL(cpu_id) >= 0xe)) {
1358                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1359                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1360                         msr &= ~IA32_MISC_EN_LIMCPUID;
1361                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1362                         return (true);
1363                 }
1364         }
1365         return (false);
1366 }
1367
1368 /*
1369  * Final stage of CPU identification.
1370  */
1371 #ifdef __i386__
1372 void
1373 finishidentcpu(void)
1374 #else
1375 void
1376 identify_cpu(void)
1377 #endif
1378 {
1379         u_int regs[4], cpu_stdext_disable;
1380 #ifdef __i386__
1381         u_char ccr3;
1382 #endif
1383
1384 #ifdef __amd64__
1385         do_cpuid(0, regs);
1386         cpu_high = regs[0];
1387         ((u_int *)&cpu_vendor)[0] = regs[1];
1388         ((u_int *)&cpu_vendor)[1] = regs[3];
1389         ((u_int *)&cpu_vendor)[2] = regs[2];
1390         cpu_vendor[12] = '\0';
1391
1392         do_cpuid(1, regs);
1393         cpu_id = regs[0];
1394         cpu_procinfo = regs[1];
1395         cpu_feature = regs[3];
1396         cpu_feature2 = regs[2];
1397 #endif
1398
1399         identify_hypervisor();
1400         cpu_vendor_id = find_cpu_vendor_id();
1401
1402         if (intel_fix_cpuid()) {
1403                 do_cpuid(0, regs);
1404                 cpu_high = regs[0];
1405         }
1406
1407         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1408                 do_cpuid(5, regs);
1409                 cpu_mon_mwait_flags = regs[2];
1410                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1411                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1412         }
1413
1414         if (cpu_high >= 7) {
1415                 cpuid_count(7, 0, regs);
1416                 cpu_stdext_feature = regs[1];
1417
1418                 /*
1419                  * Some hypervisors fail to filter out unsupported
1420                  * extended features.  For now, disable the
1421                  * extensions, activation of which requires setting a
1422                  * bit in CR4, and which VM monitors do not support.
1423                  */
1424                 if (cpu_feature2 & CPUID2_HV) {
1425                         cpu_stdext_disable = CPUID_STDEXT_FSGSBASE |
1426                             CPUID_STDEXT_SMEP;
1427                 } else
1428                         cpu_stdext_disable = 0;
1429                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1430                 cpu_stdext_feature &= ~cpu_stdext_disable;
1431                 cpu_stdext_feature2 = regs[2];
1432         }
1433
1434 #ifdef __i386__
1435         if (cpu_high > 0 &&
1436             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1437              cpu_vendor_id == CPU_VENDOR_AMD ||
1438              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1439              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1440              cpu_vendor_id == CPU_VENDOR_NSC)) {
1441                 do_cpuid(0x80000000, regs);
1442                 if (regs[0] >= 0x80000000)
1443                         cpu_exthigh = regs[0];
1444         }
1445 #else
1446         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1447             cpu_vendor_id == CPU_VENDOR_AMD ||
1448             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1449                 do_cpuid(0x80000000, regs);
1450                 cpu_exthigh = regs[0];
1451         }
1452 #endif
1453         if (cpu_exthigh >= 0x80000001) {
1454                 do_cpuid(0x80000001, regs);
1455                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1456                 amd_feature2 = regs[2];
1457         }
1458         if (cpu_exthigh >= 0x80000007) {
1459                 do_cpuid(0x80000007, regs);
1460                 amd_pminfo = regs[3];
1461         }
1462         if (cpu_exthigh >= 0x80000008) {
1463                 do_cpuid(0x80000008, regs);
1464                 cpu_maxphyaddr = regs[0] & 0xff;
1465                 cpu_procinfo2 = regs[2];
1466         } else {
1467                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1468         }
1469
1470 #ifdef __i386__
1471         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1472                 if (cpu == CPU_486) {
1473                         /*
1474                          * These conditions are equivalent to:
1475                          *     - CPU does not support cpuid instruction.
1476                          *     - Cyrix/IBM CPU is detected.
1477                          */
1478                         if (identblue() == IDENTBLUE_IBMCPU) {
1479                                 strcpy(cpu_vendor, "IBM");
1480                                 cpu_vendor_id = CPU_VENDOR_IBM;
1481                                 cpu = CPU_BLUE;
1482                                 return;
1483                         }
1484                 }
1485                 switch (cpu_id & 0xf00) {
1486                 case 0x600:
1487                         /*
1488                          * Cyrix's datasheet does not describe DIRs.
1489                          * Therefor, I assume it does not have them
1490                          * and use the result of the cpuid instruction.
1491                          * XXX they seem to have it for now at least. -Peter
1492                          */
1493                         identifycyrix();
1494                         cpu = CPU_M2;
1495                         break;
1496                 default:
1497                         identifycyrix();
1498                         /*
1499                          * This routine contains a trick.
1500                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1501                          */
1502                         switch (cyrix_did & 0x00f0) {
1503                         case 0x00:
1504                         case 0xf0:
1505                                 cpu = CPU_486DLC;
1506                                 break;
1507                         case 0x10:
1508                                 cpu = CPU_CY486DX;
1509                                 break;
1510                         case 0x20:
1511                                 if ((cyrix_did & 0x000f) < 8)
1512                                         cpu = CPU_M1;
1513                                 else
1514                                         cpu = CPU_M1SC;
1515                                 break;
1516                         case 0x30:
1517                                 cpu = CPU_M1;
1518                                 break;
1519                         case 0x40:
1520                                 /* MediaGX CPU */
1521                                 cpu = CPU_M1SC;
1522                                 break;
1523                         default:
1524                                 /* M2 and later CPUs are treated as M2. */
1525                                 cpu = CPU_M2;
1526
1527                                 /*
1528                                  * enable cpuid instruction.
1529                                  */
1530                                 ccr3 = read_cyrix_reg(CCR3);
1531                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1532                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1533                                 write_cyrix_reg(CCR3, ccr3);
1534
1535                                 do_cpuid(0, regs);
1536                                 cpu_high = regs[0];     /* eax */
1537                                 do_cpuid(1, regs);
1538                                 cpu_id = regs[0];       /* eax */
1539                                 cpu_feature = regs[3];  /* edx */
1540                                 break;
1541                         }
1542                 }
1543         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1544                 /*
1545                  * There are BlueLightning CPUs that do not change
1546                  * undefined flags by dividing 5 by 2.  In this case,
1547                  * the CPU identification routine in locore.s leaves
1548                  * cpu_vendor null string and puts CPU_486 into the
1549                  * cpu.
1550                  */
1551                 if (identblue() == IDENTBLUE_IBMCPU) {
1552                         strcpy(cpu_vendor, "IBM");
1553                         cpu_vendor_id = CPU_VENDOR_IBM;
1554                         cpu = CPU_BLUE;
1555                         return;
1556                 }
1557         }
1558 #else
1559         /* XXX */
1560         cpu = CPU_CLAWHAMMER;
1561 #endif
1562 }
1563
1564 static u_int
1565 find_cpu_vendor_id(void)
1566 {
1567         int     i;
1568
1569         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1570                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1571                         return (cpu_vendors[i].vendor_id);
1572         return (0);
1573 }
1574
1575 static void
1576 print_AMD_assoc(int i)
1577 {
1578         if (i == 255)
1579                 printf(", fully associative\n");
1580         else
1581                 printf(", %d-way associative\n", i);
1582 }
1583
1584 static void
1585 print_AMD_l2_assoc(int i)
1586 {
1587         switch (i & 0x0f) {
1588         case 0: printf(", disabled/not present\n"); break;
1589         case 1: printf(", direct mapped\n"); break;
1590         case 2: printf(", 2-way associative\n"); break;
1591         case 4: printf(", 4-way associative\n"); break;
1592         case 6: printf(", 8-way associative\n"); break;
1593         case 8: printf(", 16-way associative\n"); break;
1594         case 15: printf(", fully associative\n"); break;
1595         default: printf(", reserved configuration\n"); break;
1596         }
1597 }
1598
1599 static void
1600 print_AMD_info(void)
1601 {
1602 #ifdef __i386__
1603         uint64_t amd_whcr;
1604 #endif
1605         u_int regs[4];
1606
1607         if (cpu_exthigh >= 0x80000005) {
1608                 do_cpuid(0x80000005, regs);
1609                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1610                 print_AMD_assoc(regs[0] >> 24);
1611
1612                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1613                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1614
1615                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1616                 print_AMD_assoc(regs[1] >> 24);
1617
1618                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1619                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1620
1621                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1622                 printf(", %d bytes/line", regs[2] & 0xff);
1623                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1624                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1625
1626                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1627                 printf(", %d bytes/line", regs[3] & 0xff);
1628                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1629                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1630         }
1631
1632         if (cpu_exthigh >= 0x80000006) {
1633                 do_cpuid(0x80000006, regs);
1634                 if ((regs[0] >> 16) != 0) {
1635                         printf("L2 2MB data TLB: %d entries",
1636                             (regs[0] >> 16) & 0xfff);
1637                         print_AMD_l2_assoc(regs[0] >> 28);
1638                         printf("L2 2MB instruction TLB: %d entries",
1639                             regs[0] & 0xfff);
1640                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1641                 } else {
1642                         printf("L2 2MB unified TLB: %d entries",
1643                             regs[0] & 0xfff);
1644                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1645                 }
1646                 if ((regs[1] >> 16) != 0) {
1647                         printf("L2 4KB data TLB: %d entries",
1648                             (regs[1] >> 16) & 0xfff);
1649                         print_AMD_l2_assoc(regs[1] >> 28);
1650
1651                         printf("L2 4KB instruction TLB: %d entries",
1652                             (regs[1] >> 16) & 0xfff);
1653                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1654                 } else {
1655                         printf("L2 4KB unified TLB: %d entries",
1656                             (regs[1] >> 16) & 0xfff);
1657                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1658                 }
1659                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1660                 printf(", %d bytes/line", regs[2] & 0xff);
1661                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1662                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1663         }
1664
1665 #ifdef __i386__
1666         if (((cpu_id & 0xf00) == 0x500)
1667             && (((cpu_id & 0x0f0) > 0x80)
1668                 || (((cpu_id & 0x0f0) == 0x80)
1669                     && (cpu_id & 0x00f) > 0x07))) {
1670                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1671                 amd_whcr = rdmsr(0xc0000082);
1672                 if (!(amd_whcr & (0x3ff << 22))) {
1673                         printf("Write Allocate Disable\n");
1674                 } else {
1675                         printf("Write Allocate Enable Limit: %dM bytes\n",
1676                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1677                         printf("Write Allocate 15-16M bytes: %s\n",
1678                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1679                 }
1680         } else if (((cpu_id & 0xf00) == 0x500)
1681                    && ((cpu_id & 0x0f0) > 0x50)) {
1682                 /* K6, K6-2(old core) */
1683                 amd_whcr = rdmsr(0xc0000082);
1684                 if (!(amd_whcr & (0x7f << 1))) {
1685                         printf("Write Allocate Disable\n");
1686                 } else {
1687                         printf("Write Allocate Enable Limit: %dM bytes\n",
1688                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1689                         printf("Write Allocate 15-16M bytes: %s\n",
1690                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1691                         printf("Hardware Write Allocate Control: %s\n",
1692                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1693                 }
1694         }
1695 #endif
1696         /*
1697          * Opteron Rev E shows a bug as in very rare occasions a read memory
1698          * barrier is not performed as expected if it is followed by a
1699          * non-atomic read-modify-write instruction.
1700          * As long as that bug pops up very rarely (intensive machine usage
1701          * on other operating systems generally generates one unexplainable
1702          * crash any 2 months) and as long as a model specific fix would be
1703          * impratical at this stage, print out a warning string if the broken
1704          * model and family are identified.
1705          */
1706         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1707             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1708                 printf("WARNING: This architecture revision has known SMP "
1709                     "hardware bugs which may cause random instability\n");
1710 }
1711
1712 static void
1713 print_INTEL_info(void)
1714 {
1715         u_int regs[4];
1716         u_int rounds, regnum;
1717         u_int nwaycode, nway;
1718
1719         if (cpu_high >= 2) {
1720                 rounds = 0;
1721                 do {
1722                         do_cpuid(0x2, regs);
1723                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1724                                 break;  /* we have a buggy CPU */
1725
1726                         for (regnum = 0; regnum <= 3; ++regnum) {
1727                                 if (regs[regnum] & (1<<31))
1728                                         continue;
1729                                 if (regnum != 0)
1730                                         print_INTEL_TLB(regs[regnum] & 0xff);
1731                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1732                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1733                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1734                         }
1735                 } while (--rounds > 0);
1736         }
1737
1738         if (cpu_exthigh >= 0x80000006) {
1739                 do_cpuid(0x80000006, regs);
1740                 nwaycode = (regs[2] >> 12) & 0x0f;
1741                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1742                         nway = 1 << (nwaycode / 2);
1743                 else
1744                         nway = 0;
1745                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1746                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1747         }
1748 }
1749
1750 static void
1751 print_INTEL_TLB(u_int data)
1752 {
1753         switch (data) {
1754         case 0x0:
1755         case 0x40:
1756         default:
1757                 break;
1758         case 0x1:
1759                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1760                 break;
1761         case 0x2:
1762                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1763                 break;
1764         case 0x3:
1765                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1766                 break;
1767         case 0x4:
1768                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1769                 break;
1770         case 0x6:
1771                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1772                 break;
1773         case 0x8:
1774                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1775                 break;
1776         case 0x9:
1777                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1778                 break;
1779         case 0xa:
1780                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1781                 break;
1782         case 0xb:
1783                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1784                 break;
1785         case 0xc:
1786                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1787                 break;
1788         case 0xd:
1789                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1790                 break;
1791         case 0xe:
1792                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1793                 break;
1794         case 0x1d:
1795                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1796                 break;
1797         case 0x21:
1798                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1799                 break;
1800         case 0x22:
1801                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1802                 break;
1803         case 0x23:
1804                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1805                 break;
1806         case 0x24:
1807                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1808                 break;
1809         case 0x25:
1810                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1811                 break;
1812         case 0x29:
1813                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1814                 break;
1815         case 0x2c:
1816                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1817                 break;
1818         case 0x30:
1819                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1820                 break;
1821         case 0x39: /* De-listed in SDM rev. 54 */
1822                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1823                 break;
1824         case 0x3b: /* De-listed in SDM rev. 54 */
1825                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1826                 break;
1827         case 0x3c: /* De-listed in SDM rev. 54 */
1828                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1829                 break;
1830         case 0x41:
1831                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1832                 break;
1833         case 0x42:
1834                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1835                 break;
1836         case 0x43:
1837                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1838                 break;
1839         case 0x44:
1840                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1841                 break;
1842         case 0x45:
1843                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1844                 break;
1845         case 0x46:
1846                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1847                 break;
1848         case 0x47:
1849                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1850                 break;
1851         case 0x48:
1852                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1853                 break;
1854         case 0x49:
1855                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1856                     CPUID_TO_MODEL(cpu_id) == 0x6)
1857                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1858                 else
1859                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1860                 break;
1861         case 0x4a:
1862                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1863                 break;
1864         case 0x4b:
1865                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1866                 break;
1867         case 0x4c:
1868                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1869                 break;
1870         case 0x4d:
1871                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1872                 break;
1873         case 0x4e:
1874                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1875                 break;
1876         case 0x4f:
1877                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1878                 break;
1879         case 0x50:
1880                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1881                 break;
1882         case 0x51:
1883                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1884                 break;
1885         case 0x52:
1886                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1887                 break;
1888         case 0x55:
1889                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1890                 break;
1891         case 0x56:
1892                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1893                 break;
1894         case 0x57:
1895                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1896                 break;
1897         case 0x59:
1898                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1899                 break;
1900         case 0x5a:
1901                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1902                 break;
1903         case 0x5b:
1904                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1905                 break;
1906         case 0x5c:
1907                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1908                 break;
1909         case 0x5d:
1910                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1911                 break;
1912         case 0x60:
1913                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1914                 break;
1915         case 0x61:
1916                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1917                 break;
1918         case 0x63:
1919                 printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n");
1920                 break;
1921         case 0x66:
1922                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1923                 break;
1924         case 0x67:
1925                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1926                 break;
1927         case 0x68:
1928                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1929                 break;
1930         case 0x6a:
1931                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1932                 break;
1933         case 0x6b:
1934                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1935                 break;
1936         case 0x6c:
1937                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1938                 break;
1939         case 0x6d:
1940                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1941                 break;
1942         case 0x70:
1943                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1944                 break;
1945         case 0x71:
1946                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1947                 break;
1948         case 0x72:
1949                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1950                 break;
1951         case 0x76:
1952                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1953                 break;
1954         case 0x78:
1955                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1956                 break;
1957         case 0x79:
1958                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1959                 break;
1960         case 0x7a:
1961                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1962                 break;
1963         case 0x7b:
1964                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1965                 break;
1966         case 0x7c:
1967                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1968                 break;
1969         case 0x7d:
1970                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1971                 break;
1972         case 0x7f:
1973                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1974                 break;
1975         case 0x80:
1976                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1977                 break;
1978         case 0x82:
1979                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1980                 break;
1981         case 0x83:
1982                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
1983                 break;
1984         case 0x84:
1985                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
1986                 break;
1987         case 0x85:
1988                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
1989                 break;
1990         case 0x86:
1991                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
1992                 break;
1993         case 0x87:
1994                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
1995                 break;
1996         case 0xa0:
1997                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
1998                 break;
1999         case 0xb0:
2000                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2001                 break;
2002         case 0xb1:
2003                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2004                 break;
2005         case 0xb2:
2006                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2007                 break;
2008         case 0xb3:
2009                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2010                 break;
2011         case 0xb4:
2012                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2013                 break;
2014         case 0xb5:
2015                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2016                 break;
2017         case 0xb6:
2018                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2019                 break;
2020         case 0xba:
2021                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2022                 break;
2023         case 0xc0:
2024                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2025                 break;
2026         case 0xc1:
2027                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2028                 break;
2029         case 0xc2:
2030                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2031                 break;
2032         case 0xc3:
2033                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2034                 break;
2035         case 0xca:
2036                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2037                 break;
2038         case 0xd0:
2039                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2040                 break;
2041         case 0xd1:
2042                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2043                 break;
2044         case 0xd2:
2045                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2046                 break;
2047         case 0xd6:
2048                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2049                 break;
2050         case 0xd7:
2051                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2052                 break;
2053         case 0xd8:
2054                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2055                 break;
2056         case 0xdc:
2057                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2058                 break;
2059         case 0xdd:
2060                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2061                 break;
2062         case 0xde:
2063                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2064                 break;
2065         case 0xe2:
2066                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2067                 break;
2068         case 0xe3:
2069                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2070                 break;
2071         case 0xe4:
2072                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2073                 break;
2074         case 0xea:
2075                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2076                 break;
2077         case 0xeb:
2078                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2079                 break;
2080         case 0xec:
2081                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2082                 break;
2083         case 0xf0:
2084                 printf("64-Byte prefetching\n");
2085                 break;
2086         case 0xf1:
2087                 printf("128-Byte prefetching\n");
2088                 break;
2089         }
2090 }
2091
2092 static void
2093 print_svm_info(void)
2094 {
2095         u_int features, regs[4];
2096         uint64_t msr;
2097         int comma;
2098
2099         printf("\n  SVM: ");
2100         do_cpuid(0x8000000A, regs);
2101         features = regs[3];
2102
2103         msr = rdmsr(MSR_VM_CR);
2104         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2105                 printf("(disabled in BIOS) ");
2106
2107         if (!bootverbose) {
2108                 comma = 0;
2109                 if (features & (1 << 0)) {
2110                         printf("%sNP", comma ? "," : "");
2111                         comma = 1;
2112                 }
2113                 if (features & (1 << 3)) {
2114                         printf("%sNRIP", comma ? "," : "");
2115                         comma = 1;
2116                 }
2117                 if (features & (1 << 5)) {
2118                         printf("%sVClean", comma ? "," : "");
2119                         comma = 1;
2120                 }
2121                 if (features & (1 << 6)) {
2122                         printf("%sAFlush", comma ? "," : "");
2123                         comma = 1;
2124                 }
2125                 if (features & (1 << 7)) {
2126                         printf("%sDAssist", comma ? "," : "");
2127                         comma = 1;
2128                 }
2129                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2130                 return;
2131         }
2132
2133         printf("Features=0x%b", features,
2134                "\020"
2135                "\001NP"                 /* Nested paging */
2136                "\002LbrVirt"            /* LBR virtualization */
2137                "\003SVML"               /* SVM lock */
2138                "\004NRIPS"              /* NRIP save */
2139                "\005TscRateMsr"         /* MSR based TSC rate control */
2140                "\006VmcbClean"          /* VMCB clean bits */
2141                "\007FlushByAsid"        /* Flush by ASID */
2142                "\010DecodeAssist"       /* Decode assist */
2143                "\011<b8>"
2144                "\012<b9>"
2145                "\013PauseFilter"        /* PAUSE intercept filter */
2146                "\014<b11>"
2147                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2148                "\016AVIC"               /* virtual interrupt controller */
2149                 );
2150         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2151 }
2152
2153 #ifdef __i386__
2154 static void
2155 print_transmeta_info(void)
2156 {
2157         u_int regs[4], nreg = 0;
2158
2159         do_cpuid(0x80860000, regs);
2160         nreg = regs[0];
2161         if (nreg >= 0x80860001) {
2162                 do_cpuid(0x80860001, regs);
2163                 printf("  Processor revision %u.%u.%u.%u\n",
2164                        (regs[1] >> 24) & 0xff,
2165                        (regs[1] >> 16) & 0xff,
2166                        (regs[1] >> 8) & 0xff,
2167                        regs[1] & 0xff);
2168         }
2169         if (nreg >= 0x80860002) {
2170                 do_cpuid(0x80860002, regs);
2171                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2172                        (regs[1] >> 24) & 0xff,
2173                        (regs[1] >> 16) & 0xff,
2174                        (regs[1] >> 8) & 0xff,
2175                        regs[1] & 0xff,
2176                        regs[2]);
2177         }
2178         if (nreg >= 0x80860006) {
2179                 char info[65];
2180                 do_cpuid(0x80860003, (u_int*) &info[0]);
2181                 do_cpuid(0x80860004, (u_int*) &info[16]);
2182                 do_cpuid(0x80860005, (u_int*) &info[32]);
2183                 do_cpuid(0x80860006, (u_int*) &info[48]);
2184                 info[64] = 0;
2185                 printf("  %s\n", info);
2186         }
2187 }
2188 #endif
2189
2190 static void
2191 print_via_padlock_info(void)
2192 {
2193         u_int regs[4];
2194
2195         do_cpuid(0xc0000001, regs);
2196         printf("\n  VIA Padlock Features=0x%b", regs[3],
2197         "\020"
2198         "\003RNG"               /* RNG */
2199         "\007AES"               /* ACE */
2200         "\011AES-CTR"           /* ACE2 */
2201         "\013SHA1,SHA256"       /* PHE */
2202         "\015RSA"               /* PMM */
2203         );
2204 }
2205
2206 static uint32_t
2207 vmx_settable(uint64_t basic, int msr, int true_msr)
2208 {
2209         uint64_t val;
2210
2211         if (basic & (1ULL << 55))
2212                 val = rdmsr(true_msr);
2213         else
2214                 val = rdmsr(msr);
2215
2216         /* Just report the controls that can be set to 1. */
2217         return (val >> 32);
2218 }
2219
2220 static void
2221 print_vmx_info(void)
2222 {
2223         uint64_t basic, msr;
2224         uint32_t entry, exit, mask, pin, proc, proc2;
2225         int comma;
2226
2227         printf("\n  VT-x: ");
2228         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2229         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2230                 printf("(disabled in BIOS) ");
2231         basic = rdmsr(MSR_VMX_BASIC);
2232         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2233             MSR_VMX_TRUE_PINBASED_CTLS);
2234         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2235             MSR_VMX_TRUE_PROCBASED_CTLS);
2236         if (proc & PROCBASED_SECONDARY_CONTROLS)
2237                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2238                     MSR_VMX_PROCBASED_CTLS2);
2239         else
2240                 proc2 = 0;
2241         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2242         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2243
2244         if (!bootverbose) {
2245                 comma = 0;
2246                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2247                     entry & VM_ENTRY_LOAD_PAT) {
2248                         printf("%sPAT", comma ? "," : "");
2249                         comma = 1;
2250                 }
2251                 if (proc & PROCBASED_HLT_EXITING) {
2252                         printf("%sHLT", comma ? "," : "");
2253                         comma = 1;
2254                 }
2255                 if (proc & PROCBASED_MTF) {
2256                         printf("%sMTF", comma ? "," : "");
2257                         comma = 1;
2258                 }
2259                 if (proc & PROCBASED_PAUSE_EXITING) {
2260                         printf("%sPAUSE", comma ? "," : "");
2261                         comma = 1;
2262                 }
2263                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2264                         printf("%sEPT", comma ? "," : "");
2265                         comma = 1;
2266                 }
2267                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2268                         printf("%sUG", comma ? "," : "");
2269                         comma = 1;
2270                 }
2271                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2272                         printf("%sVPID", comma ? "," : "");
2273                         comma = 1;
2274                 }
2275                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2276                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2277                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2278                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2279                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2280                         printf("%sVID", comma ? "," : "");
2281                         comma = 1;
2282                         if (pin & PINBASED_POSTED_INTERRUPT)
2283                                 printf(",PostIntr");
2284                 }
2285                 return;
2286         }
2287
2288         mask = basic >> 32;
2289         printf("Basic Features=0x%b", mask,
2290         "\020"
2291         "\02132PA"              /* 32-bit physical addresses */
2292         "\022SMM"               /* SMM dual-monitor */
2293         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2294         "\030TRUE"              /* TRUE_CTLS MSRs */
2295         );
2296         printf("\n        Pin-Based Controls=0x%b", pin,
2297         "\020"
2298         "\001ExtINT"            /* External-interrupt exiting */
2299         "\004NMI"               /* NMI exiting */
2300         "\006VNMI"              /* Virtual NMIs */
2301         "\007PreTmr"            /* Activate VMX-preemption timer */
2302         "\010PostIntr"          /* Process posted interrupts */
2303         );
2304         printf("\n        Primary Processor Controls=0x%b", proc,
2305         "\020"
2306         "\003INTWIN"            /* Interrupt-window exiting */
2307         "\004TSCOff"            /* Use TSC offsetting */
2308         "\010HLT"               /* HLT exiting */
2309         "\012INVLPG"            /* INVLPG exiting */
2310         "\013MWAIT"             /* MWAIT exiting */
2311         "\014RDPMC"             /* RDPMC exiting */
2312         "\015RDTSC"             /* RDTSC exiting */
2313         "\020CR3-LD"            /* CR3-load exiting */
2314         "\021CR3-ST"            /* CR3-store exiting */
2315         "\024CR8-LD"            /* CR8-load exiting */
2316         "\025CR8-ST"            /* CR8-store exiting */
2317         "\026TPR"               /* Use TPR shadow */
2318         "\027NMIWIN"            /* NMI-window exiting */
2319         "\030MOV-DR"            /* MOV-DR exiting */
2320         "\031IO"                /* Unconditional I/O exiting */
2321         "\032IOmap"             /* Use I/O bitmaps */
2322         "\034MTF"               /* Monitor trap flag */
2323         "\035MSRmap"            /* Use MSR bitmaps */
2324         "\036MONITOR"           /* MONITOR exiting */
2325         "\037PAUSE"             /* PAUSE exiting */
2326         );
2327         if (proc & PROCBASED_SECONDARY_CONTROLS)
2328                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2329                 "\020"
2330                 "\001APIC"              /* Virtualize APIC accesses */
2331                 "\002EPT"               /* Enable EPT */
2332                 "\003DT"                /* Descriptor-table exiting */
2333                 "\004RDTSCP"            /* Enable RDTSCP */
2334                 "\005x2APIC"            /* Virtualize x2APIC mode */
2335                 "\006VPID"              /* Enable VPID */
2336                 "\007WBINVD"            /* WBINVD exiting */
2337                 "\010UG"                /* Unrestricted guest */
2338                 "\011APIC-reg"          /* APIC-register virtualization */
2339                 "\012VID"               /* Virtual-interrupt delivery */
2340                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2341                 "\014RDRAND"            /* RDRAND exiting */
2342                 "\015INVPCID"           /* Enable INVPCID */
2343                 "\016VMFUNC"            /* Enable VM functions */
2344                 "\017VMCS"              /* VMCS shadowing */
2345                 "\020EPT#VE"            /* EPT-violation #VE */
2346                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2347                 );
2348         printf("\n        Exit Controls=0x%b", mask,
2349         "\020"
2350         "\003DR"                /* Save debug controls */
2351                                 /* Ignore Host address-space size */
2352         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2353         "\020AckInt"            /* Acknowledge interrupt on exit */
2354         "\023PAT-SV"            /* Save MSR_PAT */
2355         "\024PAT-LD"            /* Load MSR_PAT */
2356         "\025EFER-SV"           /* Save MSR_EFER */
2357         "\026EFER-LD"           /* Load MSR_EFER */
2358         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2359         );
2360         printf("\n        Entry Controls=0x%b", mask,
2361         "\020"
2362         "\003DR"                /* Save debug controls */
2363                                 /* Ignore IA-32e mode guest */
2364                                 /* Ignore Entry to SMM */
2365                                 /* Ignore Deactivate dual-monitor treatment */
2366         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2367         "\017PAT"               /* Load MSR_PAT */
2368         "\020EFER"              /* Load MSR_EFER */
2369         );
2370         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2371             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2372                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2373                 mask = msr;
2374                 printf("\n        EPT Features=0x%b", mask,
2375                 "\020"
2376                 "\001XO"                /* Execute-only translations */
2377                 "\007PW4"               /* Page-walk length of 4 */
2378                 "\011UC"                /* EPT paging-structure mem can be UC */
2379                 "\017WB"                /* EPT paging-structure mem can be WB */
2380                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2381                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2382                 "\025INVEPT"            /* INVEPT is supported */
2383                 "\026AD"                /* Accessed and dirty flags for EPT */
2384                 "\032single"            /* INVEPT single-context type */
2385                 "\033all"               /* INVEPT all-context type */
2386                 );
2387                 mask = msr >> 32;
2388                 printf("\n        VPID Features=0x%b", mask,
2389                 "\020"
2390                 "\001INVVPID"           /* INVVPID is supported */
2391                 "\011individual"        /* INVVPID individual-address type */
2392                 "\012single"            /* INVVPID single-context type */
2393                 "\013all"               /* INVVPID all-context type */
2394                  /* INVVPID single-context-retaining-globals type */
2395                 "\014single-globals"
2396                 );
2397         }
2398 }
2399
2400 static void
2401 print_hypervisor_info(void)
2402 {
2403
2404         if (*hv_vendor)
2405                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2406 }