sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 char machine[] = MACHINE;
 122
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 124     &via_feature_rng, 0,
 125     "VIA RNG feature available in CPU");
 126 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 127     &via_feature_xcrypt, 0,
 128     "VIA xcrypt feature available in CPU");
 129
 130 #ifdef __amd64__
 131 #ifdef SCTL_MASK32
 132 extern int adaptive_machine_arch;
 133 #endif
 134
 135 static int
 136 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 137 {
 138 #ifdef SCTL_MASK32
 139         static const char machine32[] = "i386";
 140 #endif
 141         int error;
 142
 143 #ifdef SCTL_MASK32
 144         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 145                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 146         else
 147 #endif
 148                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 149         return (error);
 150
 151 }
 152 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 153     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 154 #else
 155 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 156     machine, 0, "Machine class");
 157 #endif
 158
 159 static char cpu_model[128];
 160 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 161     cpu_model, 0, "Machine model");
 162
 163 static int hw_clockrate;
 164 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 165     &hw_clockrate, 0, "CPU instruction clock rate");
 166
 167 u_int hv_base;
 168 u_int hv_high;
 169 char hv_vendor[16];
 170 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 171     0, "Hypervisor vendor");
 172
 173 static eventhandler_tag tsc_post_tag;
 174
 175 static char cpu_brand[48];
 176
 177 #ifdef __i386__
 178 #define MAX_BRAND_INDEX 8
 179
 180 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 181         NULL,                   /* No brand */
 182         "Intel Celeron",
 183         "Intel Pentium III",
 184         "Intel Pentium III Xeon",
 185         NULL,
 186         NULL,
 187         NULL,
 188         NULL,
 189         "Intel Pentium 4"
 190 };
 191
 192 static struct {
 193         char    *cpu_name;
 194         int     cpu_class;
 195 } cpus[] = {
 196         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 197         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 198         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 199         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 200         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 201         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 202         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 203         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 204         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 205         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 206         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 207         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 208         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 209         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 210         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 211         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 212         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 213 };
 214 #endif
 215
 216 static struct {
 217         char    *vendor;
 218         u_int   vendor_id;
 219 } cpu_vendors[] = {
 220         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 221         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 222         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 223 #ifdef __i386__
 224         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 225         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 226         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 227         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 228         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 229         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 230         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 231 #if 0
 232         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 233         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 234 #endif
 235 #endif
 236 };
 237
 238 void
 239 printcpuinfo(void)
 240 {
 241         u_int regs[4], i;
 242         char *brand;
 243
 244         printf("CPU: ");
 245 #ifdef __i386__
 246         cpu_class = cpus[cpu].cpu_class;
 247         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 248 #else
 249         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 250 #endif
 251
 252         /* Check for extended CPUID information and a processor name. */
 253         if (cpu_exthigh >= 0x80000004) {
 254                 brand = cpu_brand;
 255                 for (i = 0x80000002; i < 0x80000005; i++) {
 256                         do_cpuid(i, regs);
 257                         memcpy(brand, regs, sizeof(regs));
 258                         brand += sizeof(regs);
 259                 }
 260         }
 261
 262         switch (cpu_vendor_id) {
 263         case CPU_VENDOR_INTEL:
 264 #ifdef __i386__
 265                 if ((cpu_id & 0xf00) > 0x300) {
 266                         u_int brand_index;
 267
 268                         cpu_model[0] = '\0';
 269
 270                         switch (cpu_id & 0x3000) {
 271                         case 0x1000:
 272                                 strcpy(cpu_model, "Overdrive ");
 273                                 break;
 274                         case 0x2000:
 275                                 strcpy(cpu_model, "Dual ");
 276                                 break;
 277                         }
 278
 279                         switch (cpu_id & 0xf00) {
 280                         case 0x400:
 281                                 strcat(cpu_model, "i486 ");
 282                                 /* Check the particular flavor of 486 */
 283                                 switch (cpu_id & 0xf0) {
 284                                 case 0x00:
 285                                 case 0x10:
 286                                         strcat(cpu_model, "DX");
 287                                         break;
 288                                 case 0x20:
 289                                         strcat(cpu_model, "SX");
 290                                         break;
 291                                 case 0x30:
 292                                         strcat(cpu_model, "DX2");
 293                                         break;
 294                                 case 0x40:
 295                                         strcat(cpu_model, "SL");
 296                                         break;
 297                                 case 0x50:
 298                                         strcat(cpu_model, "SX2");
 299                                         break;
 300                                 case 0x70:
 301                                         strcat(cpu_model,
 302                                             "DX2 Write-Back Enhanced");
 303                                         break;
 304                                 case 0x80:
 305                                         strcat(cpu_model, "DX4");
 306                                         break;
 307                                 }
 308                                 break;
 309                         case 0x500:
 310                                 /* Check the particular flavor of 586 */
 311                                 strcat(cpu_model, "Pentium");
 312                                 switch (cpu_id & 0xf0) {
 313                                 case 0x00:
 314                                         strcat(cpu_model, " A-step");
 315                                         break;
 316                                 case 0x10:
 317                                         strcat(cpu_model, "/P5");
 318                                         break;
 319                                 case 0x20:
 320                                         strcat(cpu_model, "/P54C");
 321                                         break;
 322                                 case 0x30:
 323                                         strcat(cpu_model, "/P24T");
 324                                         break;
 325                                 case 0x40:
 326                                         strcat(cpu_model, "/P55C");
 327                                         break;
 328                                 case 0x70:
 329                                         strcat(cpu_model, "/P54C");
 330                                         break;
 331                                 case 0x80:
 332                                         strcat(cpu_model, "/P55C (quarter-micron)");
 333                                         break;
 334                                 default:
 335                                         /* nothing */
 336                                         break;
 337                                 }
 338 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 339                                 /*
 340                                  * XXX - If/when Intel fixes the bug, this
 341                                  * should also check the version of the
 342                                  * CPU, not just that it's a Pentium.
 343                                  */
 344                                 has_f00f_bug = 1;
 345 #endif
 346                                 break;
 347                         case 0x600:
 348                                 /* Check the particular flavor of 686 */
 349                                 switch (cpu_id & 0xf0) {
 350                                 case 0x00:
 351                                         strcat(cpu_model, "Pentium Pro A-step");
 352                                         break;
 353                                 case 0x10:
 354                                         strcat(cpu_model, "Pentium Pro");
 355                                         break;
 356                                 case 0x30:
 357                                 case 0x50:
 358                                 case 0x60:
 359                                         strcat(cpu_model,
 360                                 "Pentium II/Pentium II Xeon/Celeron");
 361                                         cpu = CPU_PII;
 362                                         break;
 363                                 case 0x70:
 364                                 case 0x80:
 365                                 case 0xa0:
 366                                 case 0xb0:
 367                                         strcat(cpu_model,
 368                                         "Pentium III/Pentium III Xeon/Celeron");
 369                                         cpu = CPU_PIII;
 370                                         break;
 371                                 default:
 372                                         strcat(cpu_model, "Unknown 80686");
 373                                         break;
 374                                 }
 375                                 break;
 376                         case 0xf00:
 377                                 strcat(cpu_model, "Pentium 4");
 378                                 cpu = CPU_P4;
 379                                 break;
 380                         default:
 381                                 strcat(cpu_model, "unknown");
 382                                 break;
 383                         }
 384
 385                         /*
 386                          * If we didn't get a brand name from the extended
 387                          * CPUID, try to look it up in the brand table.
 388                          */
 389                         if (cpu_high > 0 && *cpu_brand == '\0') {
 390                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 391                                 if (brand_index <= MAX_BRAND_INDEX &&
 392                                     cpu_brandtable[brand_index] != NULL)
 393                                         strcpy(cpu_brand,
 394                                             cpu_brandtable[brand_index]);
 395                         }
 396                 }
 397 #else
 398                 /* Please make up your mind folks! */
 399                 strcat(cpu_model, "EM64T");
 400 #endif
 401                 break;
 402         case CPU_VENDOR_AMD:
 403                 /*
 404                  * Values taken from AMD Processor Recognition
 405                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 406                  * (also describes ``Features'' encodings.
 407                  */
 408                 strcpy(cpu_model, "AMD ");
 409 #ifdef __i386__
 410                 switch (cpu_id & 0xFF0) {
 411                 case 0x410:
 412                         strcat(cpu_model, "Standard Am486DX");
 413                         break;
 414                 case 0x430:
 415                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 416                         break;
 417                 case 0x470:
 418                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 419                         break;
 420                 case 0x480:
 421                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 422                         break;
 423                 case 0x490:
 424                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 425                         break;
 426                 case 0x4E0:
 427                         strcat(cpu_model, "Am5x86 Write-Through");
 428                         break;
 429                 case 0x4F0:
 430                         strcat(cpu_model, "Am5x86 Write-Back");
 431                         break;
 432                 case 0x500:
 433                         strcat(cpu_model, "K5 model 0");
 434                         break;
 435                 case 0x510:
 436                         strcat(cpu_model, "K5 model 1");
 437                         break;
 438                 case 0x520:
 439                         strcat(cpu_model, "K5 PR166 (model 2)");
 440                         break;
 441                 case 0x530:
 442                         strcat(cpu_model, "K5 PR200 (model 3)");
 443                         break;
 444                 case 0x560:
 445                         strcat(cpu_model, "K6");
 446                         break;
 447                 case 0x570:
 448                         strcat(cpu_model, "K6 266 (model 1)");
 449                         break;
 450                 case 0x580:
 451                         strcat(cpu_model, "K6-2");
 452                         break;
 453                 case 0x590:
 454                         strcat(cpu_model, "K6-III");
 455                         break;
 456                 case 0x5a0:
 457                         strcat(cpu_model, "Geode LX");
 458                         break;
 459                 default:
 460                         strcat(cpu_model, "Unknown");
 461                         break;
 462                 }
 463 #else
 464                 if ((cpu_id & 0xf00) == 0xf00)
 465                         strcat(cpu_model, "AMD64 Processor");
 466                 else
 467                         strcat(cpu_model, "Unknown");
 468 #endif
 469                 break;
 470 #ifdef __i386__
 471         case CPU_VENDOR_CYRIX:
 472                 strcpy(cpu_model, "Cyrix ");
 473                 switch (cpu_id & 0xff0) {
 474                 case 0x440:
 475                         strcat(cpu_model, "MediaGX");
 476                         break;
 477                 case 0x520:
 478                         strcat(cpu_model, "6x86");
 479                         break;
 480                 case 0x540:
 481                         cpu_class = CPUCLASS_586;
 482                         strcat(cpu_model, "GXm");
 483                         break;
 484                 case 0x600:
 485                         strcat(cpu_model, "6x86MX");
 486                         break;
 487                 default:
 488                         /*
 489                          * Even though CPU supports the cpuid
 490                          * instruction, it can be disabled.
 491                          * Therefore, this routine supports all Cyrix
 492                          * CPUs.
 493                          */
 494                         switch (cyrix_did & 0xf0) {
 495                         case 0x00:
 496                                 switch (cyrix_did & 0x0f) {
 497                                 case 0x00:
 498                                         strcat(cpu_model, "486SLC");
 499                                         break;
 500                                 case 0x01:
 501                                         strcat(cpu_model, "486DLC");
 502                                         break;
 503                                 case 0x02:
 504                                         strcat(cpu_model, "486SLC2");
 505                                         break;
 506                                 case 0x03:
 507                                         strcat(cpu_model, "486DLC2");
 508                                         break;
 509                                 case 0x04:
 510                                         strcat(cpu_model, "486SRx");
 511                                         break;
 512                                 case 0x05:
 513                                         strcat(cpu_model, "486DRx");
 514                                         break;
 515                                 case 0x06:
 516                                         strcat(cpu_model, "486SRx2");
 517                                         break;
 518                                 case 0x07:
 519                                         strcat(cpu_model, "486DRx2");
 520                                         break;
 521                                 case 0x08:
 522                                         strcat(cpu_model, "486SRu");
 523                                         break;
 524                                 case 0x09:
 525                                         strcat(cpu_model, "486DRu");
 526                                         break;
 527                                 case 0x0a:
 528                                         strcat(cpu_model, "486SRu2");
 529                                         break;
 530                                 case 0x0b:
 531                                         strcat(cpu_model, "486DRu2");
 532                                         break;
 533                                 default:
 534                                         strcat(cpu_model, "Unknown");
 535                                         break;
 536                                 }
 537                                 break;
 538                         case 0x10:
 539                                 switch (cyrix_did & 0x0f) {
 540                                 case 0x00:
 541                                         strcat(cpu_model, "486S");
 542                                         break;
 543                                 case 0x01:
 544                                         strcat(cpu_model, "486S2");
 545                                         break;
 546                                 case 0x02:
 547                                         strcat(cpu_model, "486Se");
 548                                         break;
 549                                 case 0x03:
 550                                         strcat(cpu_model, "486S2e");
 551                                         break;
 552                                 case 0x0a:
 553                                         strcat(cpu_model, "486DX");
 554                                         break;
 555                                 case 0x0b:
 556                                         strcat(cpu_model, "486DX2");
 557                                         break;
 558                                 case 0x0f:
 559                                         strcat(cpu_model, "486DX4");
 560                                         break;
 561                                 default:
 562                                         strcat(cpu_model, "Unknown");
 563                                         break;
 564                                 }
 565                                 break;
 566                         case 0x20:
 567                                 if ((cyrix_did & 0x0f) < 8)
 568                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 569                                 else
 570                                         strcat(cpu_model, "5x86");
 571                                 break;
 572                         case 0x30:
 573                                 strcat(cpu_model, "6x86");
 574                                 break;
 575                         case 0x40:
 576                                 if ((cyrix_did & 0xf000) == 0x3000) {
 577                                         cpu_class = CPUCLASS_586;
 578                                         strcat(cpu_model, "GXm");
 579                                 } else
 580                                         strcat(cpu_model, "MediaGX");
 581                                 break;
 582                         case 0x50:
 583                                 strcat(cpu_model, "6x86MX");
 584                                 break;
 585                         case 0xf0:
 586                                 switch (cyrix_did & 0x0f) {
 587                                 case 0x0d:
 588                                         strcat(cpu_model, "Overdrive CPU");
 589                                         break;
 590                                 case 0x0e:
 591                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 592                                         break;
 593                                 case 0x0f:
 594                                         strcat(cpu_model, "486SLC/DLC");
 595                                         break;
 596                                 default:
 597                                         strcat(cpu_model, "Unknown");
 598                                         break;
 599                                 }
 600                                 break;
 601                         default:
 602                                 strcat(cpu_model, "Unknown");
 603                                 break;
 604                         }
 605                         break;
 606                 }
 607                 break;
 608         case CPU_VENDOR_RISE:
 609                 strcpy(cpu_model, "Rise ");
 610                 switch (cpu_id & 0xff0) {
 611                 case 0x500:     /* 6401 and 6441 (Kirin) */
 612                 case 0x520:     /* 6510 (Lynx) */
 613                         strcat(cpu_model, "mP6");
 614                         break;
 615                 default:
 616                         strcat(cpu_model, "Unknown");
 617                 }
 618                 break;
 619 #endif
 620         case CPU_VENDOR_CENTAUR:
 621 #ifdef __i386__
 622                 switch (cpu_id & 0xff0) {
 623                 case 0x540:
 624                         strcpy(cpu_model, "IDT WinChip C6");
 625                         break;
 626                 case 0x580:
 627                         strcpy(cpu_model, "IDT WinChip 2");
 628                         break;
 629                 case 0x590:
 630                         strcpy(cpu_model, "IDT WinChip 3");
 631                         break;
 632                 case 0x660:
 633                         strcpy(cpu_model, "VIA C3 Samuel");
 634                         break;
 635                 case 0x670:
 636                         if (cpu_id & 0x8)
 637                                 strcpy(cpu_model, "VIA C3 Ezra");
 638                         else
 639                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 640                         break;
 641                 case 0x680:
 642                         strcpy(cpu_model, "VIA C3 Ezra-T");
 643                         break;
 644                 case 0x690:
 645                         strcpy(cpu_model, "VIA C3 Nehemiah");
 646                         break;
 647                 case 0x6a0:
 648                 case 0x6d0:
 649                         strcpy(cpu_model, "VIA C7 Esther");
 650                         break;
 651                 case 0x6f0:
 652                         strcpy(cpu_model, "VIA Nano");
 653                         break;
 654                 default:
 655                         strcpy(cpu_model, "VIA/IDT Unknown");
 656                 }
 657 #else
 658                 strcpy(cpu_model, "VIA ");
 659                 if ((cpu_id & 0xff0) == 0x6f0)
 660                         strcat(cpu_model, "Nano Processor");
 661                 else
 662                         strcat(cpu_model, "Unknown");
 663 #endif
 664                 break;
 665 #ifdef __i386__
 666         case CPU_VENDOR_IBM:
 667                 strcpy(cpu_model, "Blue Lightning CPU");
 668                 break;
 669         case CPU_VENDOR_NSC:
 670                 switch (cpu_id & 0xff0) {
 671                 case 0x540:
 672                         strcpy(cpu_model, "Geode SC1100");
 673                         cpu = CPU_GEODE1100;
 674                         break;
 675                 default:
 676                         strcpy(cpu_model, "Geode/NSC unknown");
 677                         break;
 678                 }
 679                 break;
 680 #endif
 681         default:
 682                 strcat(cpu_model, "Unknown");
 683                 break;
 684         }
 685
 686         /*
 687          * Replace cpu_model with cpu_brand minus leading spaces if
 688          * we have one.
 689          */
 690         brand = cpu_brand;
 691         while (*brand == ' ')
 692                 ++brand;
 693         if (*brand != '\0')
 694                 strcpy(cpu_model, brand);
 695
 696         printf("%s (", cpu_model);
 697         if (tsc_freq != 0) {
 698                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 699                 printf("%jd.%02d-MHz ",
 700                     (intmax_t)(tsc_freq + 4999) / 1000000,
 701                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 702         }
 703 #ifdef __i386__
 704         switch(cpu_class) {
 705         case CPUCLASS_286:
 706                 printf("286");
 707                 break;
 708         case CPUCLASS_386:
 709                 printf("386");
 710                 break;
 711 #if defined(I486_CPU)
 712         case CPUCLASS_486:
 713                 printf("486");
 714                 break;
 715 #endif
 716 #if defined(I586_CPU)
 717         case CPUCLASS_586:
 718                 printf("586");
 719                 break;
 720 #endif
 721 #if defined(I686_CPU)
 722         case CPUCLASS_686:
 723                 printf("686");
 724                 break;
 725 #endif
 726         default:
 727                 printf("Unknown");      /* will panic below... */
 728         }
 729 #else
 730         printf("K8");
 731 #endif
 732         printf("-class CPU)\n");
 733         if (*cpu_vendor)
 734                 printf("  Origin=\"%s\"", cpu_vendor);
 735         if (cpu_id)
 736                 printf("  Id=0x%x", cpu_id);
 737
 738         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 739             cpu_vendor_id == CPU_VENDOR_AMD ||
 740             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 741 #ifdef __i386__
 742             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 743             cpu_vendor_id == CPU_VENDOR_RISE ||
 744             cpu_vendor_id == CPU_VENDOR_NSC ||
 745             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 746 #endif
 747             0) {
 748                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 749                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 750                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 751 #ifdef __i386__
 752                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 753                         printf("\n  DIR=0x%04x", cyrix_did);
 754 #endif
 755
 756                 /*
 757                  * AMD CPUID Specification
 758                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 759                  *
 760                  * Intel Processor Identification and CPUID Instruction
 761                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 762                  */
 763                 if (cpu_high > 0) {
 764
 765                         /*
 766                          * Here we should probably set up flags indicating
 767                          * whether or not various features are available.
 768                          * The interesting ones are probably VME, PSE, PAE,
 769                          * and PGE.  The code already assumes without bothering
 770                          * to check that all CPUs >= Pentium have a TSC and
 771                          * MSRs.
 772                          */
 773                         printf("\n  Features=0x%b", cpu_feature,
 774                         "\020"
 775                         "\001FPU"       /* Integral FPU */
 776                         "\002VME"       /* Extended VM86 mode support */
 777                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 778                         "\004PSE"       /* 4MByte page tables */
 779                         "\005TSC"       /* Timestamp counter */
 780                         "\006MSR"       /* Machine specific registers */
 781                         "\007PAE"       /* Physical address extension */
 782                         "\010MCE"       /* Machine Check support */
 783                         "\011CX8"       /* CMPEXCH8 instruction */
 784                         "\012APIC"      /* SMP local APIC */
 785                         "\013oldMTRR"   /* Previous implementation of MTRR */
 786                         "\014SEP"       /* Fast System Call */
 787                         "\015MTRR"      /* Memory Type Range Registers */
 788                         "\016PGE"       /* PG_G (global bit) support */
 789                         "\017MCA"       /* Machine Check Architecture */
 790                         "\020CMOV"      /* CMOV instruction */
 791                         "\021PAT"       /* Page attributes table */
 792                         "\022PSE36"     /* 36 bit address space support */
 793                         "\023PN"        /* Processor Serial number */
 794                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 795                         "\025<b20>"
 796                         "\026DTS"       /* Debug Trace Store */
 797                         "\027ACPI"      /* ACPI support */
 798                         "\030MMX"       /* MMX instructions */
 799                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 800                         "\032SSE"       /* Streaming SIMD Extensions */
 801                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 802                         "\034SS"        /* Self snoop */
 803                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 804                         "\036TM"        /* Thermal Monitor clock slowdown */
 805                         "\037IA64"      /* CPU can execute IA64 instructions */
 806                         "\040PBE"       /* Pending Break Enable */
 807                         );
 808
 809                         if (cpu_feature2 != 0) {
 810                                 printf("\n  Features2=0x%b", cpu_feature2,
 811                                 "\020"
 812                                 "\001SSE3"      /* SSE3 */
 813                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 814                                 "\003DTES64"    /* 64-bit Debug Trace */
 815                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 816                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 817                                 "\006VMX"       /* Virtual Machine Extensions */
 818                                 "\007SMX"       /* Safer Mode Extensions */
 819                                 "\010EST"       /* Enhanced SpeedStep */
 820                                 "\011TM2"       /* Thermal Monitor 2 */
 821                                 "\012SSSE3"     /* SSSE3 */
 822                                 "\013CNXT-ID"   /* L1 context ID available */
 823                                 "\014SDBG"      /* IA32 silicon debug */
 824                                 "\015FMA"       /* Fused Multiply Add */
 825                                 "\016CX16"      /* CMPXCHG16B Instruction */
 826                                 "\017xTPR"      /* Send Task Priority Messages*/
 827                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 828                                 "\021<b16>"
 829                                 "\022PCID"      /* Process-context Identifiers*/
 830                                 "\023DCA"       /* Direct Cache Access */
 831                                 "\024SSE4.1"    /* SSE 4.1 */
 832                                 "\025SSE4.2"    /* SSE 4.2 */
 833                                 "\026x2APIC"    /* xAPIC Extensions */
 834                                 "\027MOVBE"     /* MOVBE Instruction */
 835                                 "\030POPCNT"    /* POPCNT Instruction */
 836                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 837                                 "\032AESNI"     /* AES Crypto */
 838                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 839                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 840                                 "\035AVX"       /* Advanced Vector Extensions */
 841                                 "\036F16C"      /* Half-precision conversions */
 842                                 "\037RDRAND"    /* RDRAND Instruction */
 843                                 "\040HV"        /* Hypervisor */
 844                                 );
 845                         }
 846
 847                         if (amd_feature != 0) {
 848                                 printf("\n  AMD Features=0x%b", amd_feature,
 849                                 "\020"          /* in hex */
 850                                 "\001<s0>"      /* Same */
 851                                 "\002<s1>"      /* Same */
 852                                 "\003<s2>"      /* Same */
 853                                 "\004<s3>"      /* Same */
 854                                 "\005<s4>"      /* Same */
 855                                 "\006<s5>"      /* Same */
 856                                 "\007<s6>"      /* Same */
 857                                 "\010<s7>"      /* Same */
 858                                 "\011<s8>"      /* Same */
 859                                 "\012<s9>"      /* Same */
 860                                 "\013<b10>"     /* Undefined */
 861                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 862                                 "\015<s12>"     /* Same */
 863                                 "\016<s13>"     /* Same */
 864                                 "\017<s14>"     /* Same */
 865                                 "\020<s15>"     /* Same */
 866                                 "\021<s16>"     /* Same */
 867                                 "\022<s17>"     /* Same */
 868                                 "\023<b18>"     /* Reserved, unknown */
 869                                 "\024MP"        /* Multiprocessor Capable */
 870                                 "\025NX"        /* Has EFER.NXE, NX */
 871                                 "\026<b21>"     /* Undefined */
 872                                 "\027MMX+"      /* AMD MMX Extensions */
 873                                 "\030<s23>"     /* Same */
 874                                 "\031<s24>"     /* Same */
 875                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 876                                 "\033Page1GB"   /* 1-GB large page support */
 877                                 "\034RDTSCP"    /* RDTSCP */
 878                                 "\035<b28>"     /* Undefined */
 879                                 "\036LM"        /* 64 bit long mode */
 880                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 881                                 "\0403DNow!"    /* AMD 3DNow! */
 882                                 );
 883                         }
 884
 885                         if (amd_feature2 != 0) {
 886                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 887                                 "\020"
 888                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 889                                 "\002CMP"       /* CMP legacy */
 890                                 "\003SVM"       /* Secure Virtual Mode */
 891                                 "\004ExtAPIC"   /* Extended APIC register */
 892                                 "\005CR8"       /* CR8 in legacy mode */
 893                                 "\006ABM"       /* LZCNT instruction */
 894                                 "\007SSE4A"     /* SSE4A */
 895                                 "\010MAS"       /* Misaligned SSE mode */
 896                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 897                                 "\012OSVW"      /* OS visible workaround */
 898                                 "\013IBS"       /* Instruction based sampling */
 899                                 "\014XOP"       /* XOP extended instructions */
 900                                 "\015SKINIT"    /* SKINIT/STGI */
 901                                 "\016WDT"       /* Watchdog timer */
 902                                 "\017<b14>"
 903                                 "\020LWP"       /* Lightweight Profiling */
 904                                 "\021FMA4"      /* 4-operand FMA instructions */
 905                                 "\022TCE"       /* Translation Cache Extension */
 906                                 "\023<b18>"
 907                                 "\024NodeId"    /* NodeId MSR support */
 908                                 "\025<b20>"
 909                                 "\026TBM"       /* Trailing Bit Manipulation */
 910                                 "\027Topology"  /* Topology Extensions */
 911                                 "\030PCXC"      /* Core perf count */
 912                                 "\031PNXC"      /* NB perf count */
 913                                 "\032<b25>"
 914                                 "\033DBE"       /* Data Breakpoint extension */
 915                                 "\034PTSC"      /* Performance TSC */
 916                                 "\035PL2I"      /* L2I perf count */
 917                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 918                                 "\037<b30>"
 919                                 "\040<b31>"
 920                                 );
 921                         }
 922
 923                         if (cpu_stdext_feature != 0) {
 924                                 printf("\n  Structured Extended Features=0x%b",
 925                                     cpu_stdext_feature,
 926                                        "\020"
 927                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 928                                        "\001FSGSBASE"
 929                                        "\002TSCADJ"
 930                                        "\003SGX"
 931                                        /* Bit Manipulation Instructions */
 932                                        "\004BMI1"
 933                                        /* Hardware Lock Elision */
 934                                        "\005HLE"
 935                                        /* Advanced Vector Instructions 2 */
 936                                        "\006AVX2"
 937                                        /* FDP_EXCPTN_ONLY */
 938                                        "\007FDPEXC"
 939                                        /* Supervisor Mode Execution Prot. */
 940                                        "\010SMEP"
 941                                        /* Bit Manipulation Instructions */
 942                                        "\011BMI2"
 943                                        "\012ERMS"
 944                                        /* Invalidate Processor Context ID */
 945                                        "\013INVPCID"
 946                                        /* Restricted Transactional Memory */
 947                                        "\014RTM"
 948                                        "\015PQM"
 949                                        "\016NFPUSG"
 950                                        /* Intel Memory Protection Extensions */
 951                                        "\017MPX"
 952                                        "\020PQE"
 953                                        /* AVX512 Foundation */
 954                                        "\021AVX512F"
 955                                        "\022AVX512DQ"
 956                                        /* Enhanced NRBG */
 957                                        "\023RDSEED"
 958                                        /* ADCX + ADOX */
 959                                        "\024ADX"
 960                                        /* Supervisor Mode Access Prevention */
 961                                        "\025SMAP"
 962                                        "\026AVX512IFMA"
 963                                        "\027PCOMMIT"
 964                                        "\030CLFLUSHOPT"
 965                                        "\031CLWB"
 966                                        "\032PROCTRACE"
 967                                        "\033AVX512PF"
 968                                        "\034AVX512ER"
 969                                        "\035AVX512CD"
 970                                        "\036SHA"
 971                                        "\037AVX512BW"
 972                                        "\040AVX512VL"
 973                                        );
 974                         }
 975
 976                         if (cpu_stdext_feature2 != 0) {
 977                                 printf("\n  Structured Extended Features2=0x%b",
 978                                     cpu_stdext_feature2,
 979                                        "\020"
 980                                        "\001PREFETCHWT1"
 981                                        "\002AVX512VBMI"
 982                                        "\003UMIP"
 983                                        "\004PKU"
 984                                        "\005OSPKE"
 985                                        "\006WAITPKG"
 986                                        "\007AVX512VBMI2"
 987                                        "\011GFNI"
 988                                        "\012VAES"
 989                                        "\013VPCLMULQDQ"
 990                                        "\014AVX512VNNI"
 991                                        "\015AVX512BITALG"
 992                                        "\016AVX512VPOPCNTDQ"
 993                                        "\027RDPID"
 994                                        "\032CLDEMOTE"
 995                                        "\034MOVDIRI"
 996                                        "\035MOVDIRI64B"
 997                                        "\036ENQCMD"
 998                                        "\037SGXLC"
 999                                        );
1000                         }
1001
1002                         if (cpu_stdext_feature3 != 0) {
1003                                 printf("\n  Structured Extended Features3=0x%b",
1004                                     cpu_stdext_feature3,
1005                                        "\020"
1006                                        "\003AVX512_4VNNIW"
1007                                        "\004AVX512_4FMAPS"
1008                                        "\011AVX512VP2INTERSECT"
1009                                        "\013MD_CLEAR"
1010                                        "\016TSXFA"
1011                                        "\023PCONFIG"
1012                                        "\033IBPB"
1013                                        "\034STIBP"
1014                                        "\035L1DFL"
1015                                        "\036ARCH_CAP"
1016                                        "\037CORE_CAP"
1017                                        "\040SSBD"
1018                                        );
1019                         }
1020
1021                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1022                                 cpuid_count(0xd, 0x1, regs);
1023                                 if (regs[0] != 0) {
1024                                         printf("\n  XSAVE Features=0x%b",
1025                                             regs[0],
1026                                             "\020"
1027                                             "\001XSAVEOPT"
1028                                             "\002XSAVEC"
1029                                             "\003XINUSE"
1030                                             "\004XSAVES");
1031                                 }
1032                         }
1033
1034                         if (cpu_ia32_arch_caps != 0) {
1035                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1036                                     (u_int)cpu_ia32_arch_caps,
1037                                        "\020"
1038                                        "\001RDCL_NO"
1039                                        "\002IBRS_ALL"
1040                                        "\003RSBA"
1041                                        "\004SKIP_L1DFL_VME"
1042                                        "\005SSB_NO"
1043                                        );
1044                         }
1045
1046                         if (amd_extended_feature_extensions != 0) {
1047                                 u_int amd_fe_masked;
1048
1049                                 amd_fe_masked = amd_extended_feature_extensions;
1050                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1051                                         amd_fe_masked &=
1052                                             ~(AMDFEID_IBRS_ALWAYSON |
1053                                                 AMDFEID_PREFER_IBRS);
1054                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1055                                         amd_fe_masked &=
1056                                             ~AMDFEID_STIBP_ALWAYSON;
1057
1058                                 printf("\n  "
1059                                     "AMD Extended Feature Extensions ID EBX="
1060                                     "0x%b", amd_fe_masked,
1061                                     "\020"
1062                                     "\001CLZERO"
1063                                     "\002IRPerf"
1064                                     "\003XSaveErPtr"
1065                                     "\015IBPB"
1066                                     "\017IBRS"
1067                                     "\020STIBP"
1068                                     "\021IBRS_ALWAYSON"
1069                                     "\022STIBP_ALWAYSON"
1070                                     "\023PREFER_IBRS"
1071                                     "\031SSBD"
1072                                     "\032VIRT_SSBD"
1073                                     "\033SSB_NO"
1074                                     );
1075                         }
1076
1077                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1078                                 print_via_padlock_info();
1079
1080                         if (cpu_feature2 & CPUID2_VMX)
1081                                 print_vmx_info();
1082
1083                         if (amd_feature2 & AMDID2_SVM)
1084                                 print_svm_info();
1085
1086                         if ((cpu_feature & CPUID_HTT) &&
1087                             cpu_vendor_id == CPU_VENDOR_AMD)
1088                                 cpu_feature &= ~CPUID_HTT;
1089
1090                         /*
1091                          * If this CPU supports P-state invariant TSC then
1092                          * mention the capability.
1093                          */
1094                         if (tsc_is_invariant) {
1095                                 printf("\n  TSC: P-state invariant");
1096                                 if (tsc_perf_stat)
1097                                         printf(", performance statistics");
1098                         }
1099                 }
1100 #ifdef __i386__
1101         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1102                 printf("  DIR=0x%04x", cyrix_did);
1103                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1104                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1105 #ifndef CYRIX_CACHE_REALLY_WORKS
1106                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1107                         printf("\n  CPU cache: write-through mode");
1108 #endif
1109 #endif
1110         }
1111
1112         /* Avoid ugly blank lines: only print newline when we have to. */
1113         if (*cpu_vendor || cpu_id)
1114                 printf("\n");
1115
1116         if (bootverbose) {
1117                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1118                         print_AMD_info();
1119                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1120                         print_INTEL_info();
1121 #ifdef __i386__
1122                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1123                         print_transmeta_info();
1124 #endif
1125         }
1126
1127         print_hypervisor_info();
1128 }
1129
1130 #ifdef __i386__
1131 void
1132 panicifcpuunsupported(void)
1133 {
1134
1135 #if !defined(lint)
1136 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1137 #error This kernel is not configured for one of the supported CPUs
1138 #endif
1139 #else /* lint */
1140 #endif /* lint */
1141         /*
1142          * Now that we have told the user what they have,
1143          * let them know if that machine type isn't configured.
1144          */
1145         switch (cpu_class) {
1146         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1147         case CPUCLASS_386:
1148 #if !defined(I486_CPU)
1149         case CPUCLASS_486:
1150 #endif
1151 #if !defined(I586_CPU)
1152         case CPUCLASS_586:
1153 #endif
1154 #if !defined(I686_CPU)
1155         case CPUCLASS_686:
1156 #endif
1157                 panic("CPU class not configured");
1158         default:
1159                 break;
1160         }
1161 }
1162
1163 static  volatile u_int trap_by_rdmsr;
1164
1165 /*
1166  * Special exception 6 handler.
1167  * The rdmsr instruction generates invalid opcodes fault on 486-class
1168  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1169  * function identblue() when this handler is called.  Stacked eip should
1170  * be advanced.
1171  */
1172 inthand_t       bluetrap6;
1173 #ifdef __GNUCLIKE_ASM
1174 __asm
1175 ("                                                                      \n\
1176         .text                                                           \n\
1177         .p2align 2,0x90                                                 \n\
1178         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1179 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1180         ss                                                              \n\
1181         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1182         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1183         iret                                                            \n\
1184 ");
1185 #endif
1186
1187 /*
1188  * Special exception 13 handler.
1189  * Accessing non-existent MSR generates general protection fault.
1190  */
1191 inthand_t       bluetrap13;
1192 #ifdef __GNUCLIKE_ASM
1193 __asm
1194 ("                                                                      \n\
1195         .text                                                           \n\
1196         .p2align 2,0x90                                                 \n\
1197         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1198 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1199         ss                                                              \n\
1200         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1201         popl    %eax            /* discard error code */                \n\
1202         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1203         iret                                                            \n\
1204 ");
1205 #endif
1206
1207 /*
1208  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1209  * support cpuid instruction.  This function should be called after
1210  * loading interrupt descriptor table register.
1211  *
1212  * I don't like this method that handles fault, but I couldn't get
1213  * information for any other methods.  Does blue giant know?
1214  */
1215 static int
1216 identblue(void)
1217 {
1218
1219         trap_by_rdmsr = 0;
1220
1221         /*
1222          * Cyrix 486-class CPU does not support rdmsr instruction.
1223          * The rdmsr instruction generates invalid opcode fault, and exception
1224          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1225          * bluetrap6() set the magic number to trap_by_rdmsr.
1226          */
1227         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1228             GSEL(GCODE_SEL, SEL_KPL));
1229
1230         /*
1231          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1232          * In this case, rdmsr generates general protection fault, and
1233          * exception will be trapped by bluetrap13().
1234          */
1235         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1236             GSEL(GCODE_SEL, SEL_KPL));
1237
1238         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1239
1240         if (trap_by_rdmsr == 0xa8c1d)
1241                 return IDENTBLUE_CYRIX486;
1242         else if (trap_by_rdmsr == 0xa89c4)
1243                 return IDENTBLUE_CYRIXM2;
1244         return IDENTBLUE_IBMCPU;
1245 }
1246
1247
1248 /*
1249  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1250  *
1251  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1252  * +-------+-------+---------------+
1253  * |  SID  |  RID  |   Device ID   |
1254  * |    (DIR 1)    |    (DIR 0)    |
1255  * +-------+-------+---------------+
1256  */
1257 static void
1258 identifycyrix(void)
1259 {
1260         register_t saveintr;
1261         int     ccr2_test = 0, dir_test = 0;
1262         u_char  ccr2, ccr3;
1263
1264         saveintr = intr_disable();
1265
1266         ccr2 = read_cyrix_reg(CCR2);
1267         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1268         read_cyrix_reg(CCR2);
1269         if (read_cyrix_reg(CCR2) != ccr2)
1270                 ccr2_test = 1;
1271         write_cyrix_reg(CCR2, ccr2);
1272
1273         ccr3 = read_cyrix_reg(CCR3);
1274         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1275         read_cyrix_reg(CCR3);
1276         if (read_cyrix_reg(CCR3) != ccr3)
1277                 dir_test = 1;                                   /* CPU supports DIRs. */
1278         write_cyrix_reg(CCR3, ccr3);
1279
1280         if (dir_test) {
1281                 /* Device ID registers are available. */
1282                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1283                 cyrix_did += read_cyrix_reg(DIR0);
1284         } else if (ccr2_test)
1285                 cyrix_did = 0x0010;             /* 486S A-step */
1286         else
1287                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1288
1289         intr_restore(saveintr);
1290 }
1291 #endif
1292
1293 /* Update TSC freq with the value indicated by the caller. */
1294 static void
1295 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1296 {
1297
1298         /* If there was an error during the transition, don't do anything. */
1299         if (status != 0)
1300                 return;
1301
1302         /* Total setting for this level gives the new frequency in MHz. */
1303         hw_clockrate = level->total_set.freq;
1304 }
1305
1306 static void
1307 hook_tsc_freq(void *arg __unused)
1308 {
1309
1310         if (tsc_is_invariant)
1311                 return;
1312
1313         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1314             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1315 }
1316
1317 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1318
1319 static const struct {
1320         const char *    vm_bname;
1321         int             vm_guest;
1322 } vm_bnames[] = {
1323         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1324         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1325         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1326         { "Xen",        VM_GUEST_XEN },         /* Xen */
1327         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1328         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1329 };
1330
1331 static const struct {
1332         const char *    vm_pname;
1333         int             vm_guest;
1334 } vm_pnames[] = {
1335         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1336         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1337         { "VirtualBox",                 VM_GUEST_VBOX },
1338         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1339         { "KVM",                        VM_GUEST_KVM },
1340 };
1341
1342 static struct {
1343         const char      *vm_cpuid;
1344         int             vm_guest;
1345 } vm_cpuids[] = {
1346         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1347         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1348         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1349         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1350         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1351         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1352 };
1353
1354 static void
1355 identify_hypervisor_cpuid_base(void)
1356 {
1357         u_int leaf, regs[4];
1358         int i;
1359
1360         /*
1361          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1362          * http://lkml.org/lkml/2008/10/1/246
1363          *
1364          * KB1009458: Mechanisms to determine if software is running in
1365          * a VMware virtual machine
1366          * http://kb.vmware.com/kb/1009458
1367          *
1368          * Search for a hypervisor that we recognize. If we cannot find
1369          * a specific hypervisor, return the first information about the
1370          * hypervisor that we found, as others may be able to use.
1371          */
1372         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1373                 do_cpuid(leaf, regs);
1374
1375                 /*
1376                  * KVM from Linux kernels prior to commit
1377                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1378                  * to 0 rather than a valid hv_high value.  Check for
1379                  * the KVM signature bytes and fixup %eax to the
1380                  * highest supported leaf in that case.
1381                  */
1382                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1383                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1384                         regs[0] = leaf + 1;
1385
1386                 if (regs[0] >= leaf) {
1387                         for (i = 0; i < nitems(vm_cpuids); i++)
1388                                 if (strncmp((const char *)&regs[1],
1389                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1390                                         vm_guest = vm_cpuids[i].vm_guest;
1391                                         break;
1392                                 }
1393
1394                         /*
1395                          * If this is the first entry or we found a
1396                          * specific hypervisor, record the base, high value,
1397                          * and vendor identifier.
1398                          */
1399                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1400                                 hv_base = leaf;
1401                                 hv_high = regs[0];
1402                                 ((u_int *)&hv_vendor)[0] = regs[1];
1403                                 ((u_int *)&hv_vendor)[1] = regs[2];
1404                                 ((u_int *)&hv_vendor)[2] = regs[3];
1405                                 hv_vendor[12] = '\0';
1406
1407                                 /*
1408                                  * If we found a specific hypervisor, then
1409                                  * we are finished.
1410                                  */
1411                                 if (vm_guest != VM_GUEST_VM)
1412                                         return;
1413                         }
1414                 }
1415         }
1416 }
1417
1418 void
1419 identify_hypervisor(void)
1420 {
1421         u_int regs[4];
1422         char *p;
1423         int i;
1424
1425         /*
1426          * If CPUID2_HV is set, we are running in a hypervisor environment.
1427          */
1428         if (cpu_feature2 & CPUID2_HV) {
1429                 vm_guest = VM_GUEST_VM;
1430                 identify_hypervisor_cpuid_base();
1431
1432                 /* If we have a definitive vendor, we can return now. */
1433                 if (*hv_vendor != '\0')
1434                         return;
1435         }
1436
1437         /*
1438          * Examine SMBIOS strings for older hypervisors.
1439          */
1440         p = kern_getenv("smbios.system.serial");
1441         if (p != NULL) {
1442                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1443                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1444                         if (regs[1] == VMW_HVMAGIC) {
1445                                 vm_guest = VM_GUEST_VMWARE;
1446                                 freeenv(p);
1447                                 return;
1448                         }
1449                 }
1450                 freeenv(p);
1451         }
1452
1453         /*
1454          * XXX: Some of these entries may not be needed since they were
1455          * added to FreeBSD before the checks above.
1456          */
1457         p = kern_getenv("smbios.bios.vendor");
1458         if (p != NULL) {
1459                 for (i = 0; i < nitems(vm_bnames); i++)
1460                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1461                                 vm_guest = vm_bnames[i].vm_guest;
1462                                 /* If we have a specific match, return */
1463                                 if (vm_guest != VM_GUEST_VM) {
1464                                         freeenv(p);
1465                                         return;
1466                                 }
1467                                 /*
1468                                  * We are done with bnames, but there might be
1469                                  * a more specific match in the pnames
1470                                  */
1471                                 break;
1472                         }
1473                 freeenv(p);
1474         }
1475         p = kern_getenv("smbios.system.product");
1476         if (p != NULL) {
1477                 for (i = 0; i < nitems(vm_pnames); i++)
1478                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1479                                 vm_guest = vm_pnames[i].vm_guest;
1480                                 freeenv(p);
1481                                 return;
1482                         }
1483                 freeenv(p);
1484         }
1485 }
1486
1487 bool
1488 fix_cpuid(void)
1489 {
1490         uint64_t msr;
1491
1492         /*
1493          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1494          * get the largest standard CPUID function number again if it is set
1495          * from BIOS.  It is necessary for probing correct CPU topology later
1496          * and for the correct operation of the AVX-aware userspace.
1497          */
1498         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1499             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1500             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1501             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1502             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1503                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1504                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1505                         msr &= ~IA32_MISC_EN_LIMCPUID;
1506                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1507                         return (true);
1508                 }
1509         }
1510
1511         /*
1512          * Re-enable AMD Topology Extension that could be disabled by BIOS
1513          * on some notebook processors.  Without the extension it's really
1514          * hard to determine the correct CPU cache topology.
1515          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1516          * Models 60h-6Fh Processors, Publication # 50742.
1517          */
1518         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1519             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1520                 msr = rdmsr(MSR_EXTFEATURES);
1521                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1522                         msr |= (uint64_t)1 << 54;
1523                         wrmsr(MSR_EXTFEATURES, msr);
1524                         return (true);
1525                 }
1526         }
1527         return (false);
1528 }
1529
1530 void
1531 identify_cpu1(void)
1532 {
1533         u_int regs[4];
1534
1535         do_cpuid(0, regs);
1536         cpu_high = regs[0];
1537         ((u_int *)&cpu_vendor)[0] = regs[1];
1538         ((u_int *)&cpu_vendor)[1] = regs[3];
1539         ((u_int *)&cpu_vendor)[2] = regs[2];
1540         cpu_vendor[12] = '\0';
1541
1542         do_cpuid(1, regs);
1543         cpu_id = regs[0];
1544         cpu_procinfo = regs[1];
1545         cpu_feature = regs[3];
1546         cpu_feature2 = regs[2];
1547 }
1548
1549 void
1550 identify_cpu2(void)
1551 {
1552         u_int regs[4], cpu_stdext_disable;
1553
1554         if (cpu_high >= 7) {
1555                 cpuid_count(7, 0, regs);
1556                 cpu_stdext_feature = regs[1];
1557
1558                 /*
1559                  * Some hypervisors failed to filter out unsupported
1560                  * extended features.  Allow to disable the
1561                  * extensions, activation of which requires setting a
1562                  * bit in CR4, and which VM monitors do not support.
1563                  */
1564                 cpu_stdext_disable = 0;
1565                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1566                 cpu_stdext_feature &= ~cpu_stdext_disable;
1567
1568                 cpu_stdext_feature2 = regs[2];
1569                 cpu_stdext_feature3 = regs[3];
1570
1571                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1572                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1573         }
1574 }
1575
1576 void
1577 identify_cpu_fixup_bsp(void)
1578 {
1579         u_int regs[4];
1580
1581         cpu_vendor_id = find_cpu_vendor_id();
1582
1583         if (fix_cpuid()) {
1584                 do_cpuid(0, regs);
1585                 cpu_high = regs[0];
1586         }
1587 }
1588
1589 /*
1590  * Final stage of CPU identification.
1591  */
1592 void
1593 finishidentcpu(void)
1594 {
1595         u_int regs[4];
1596 #ifdef __i386__
1597         u_char ccr3;
1598 #endif
1599
1600         identify_cpu_fixup_bsp();
1601
1602         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1603                 do_cpuid(5, regs);
1604                 cpu_mon_mwait_flags = regs[2];
1605                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1606                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1607         }
1608
1609         identify_cpu2();
1610
1611 #ifdef __i386__
1612         if (cpu_high > 0 &&
1613             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1614              cpu_vendor_id == CPU_VENDOR_AMD ||
1615              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1616              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1617              cpu_vendor_id == CPU_VENDOR_NSC)) {
1618                 do_cpuid(0x80000000, regs);
1619                 if (regs[0] >= 0x80000000)
1620                         cpu_exthigh = regs[0];
1621         }
1622 #else
1623         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1624             cpu_vendor_id == CPU_VENDOR_AMD ||
1625             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1626                 do_cpuid(0x80000000, regs);
1627                 cpu_exthigh = regs[0];
1628         }
1629 #endif
1630         if (cpu_exthigh >= 0x80000001) {
1631                 do_cpuid(0x80000001, regs);
1632                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1633                 amd_feature2 = regs[2];
1634         }
1635         if (cpu_exthigh >= 0x80000007) {
1636                 do_cpuid(0x80000007, regs);
1637                 amd_rascap = regs[1];
1638                 amd_pminfo = regs[3];
1639         }
1640         if (cpu_exthigh >= 0x80000008) {
1641                 do_cpuid(0x80000008, regs);
1642                 cpu_maxphyaddr = regs[0] & 0xff;
1643                 amd_extended_feature_extensions = regs[1];
1644                 cpu_procinfo2 = regs[2];
1645         } else {
1646                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1647         }
1648
1649 #ifdef __i386__
1650         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1651                 if (cpu == CPU_486) {
1652                         /*
1653                          * These conditions are equivalent to:
1654                          *     - CPU does not support cpuid instruction.
1655                          *     - Cyrix/IBM CPU is detected.
1656                          */
1657                         if (identblue() == IDENTBLUE_IBMCPU) {
1658                                 strcpy(cpu_vendor, "IBM");
1659                                 cpu_vendor_id = CPU_VENDOR_IBM;
1660                                 cpu = CPU_BLUE;
1661                                 return;
1662                         }
1663                 }
1664                 switch (cpu_id & 0xf00) {
1665                 case 0x600:
1666                         /*
1667                          * Cyrix's datasheet does not describe DIRs.
1668                          * Therefor, I assume it does not have them
1669                          * and use the result of the cpuid instruction.
1670                          * XXX they seem to have it for now at least. -Peter
1671                          */
1672                         identifycyrix();
1673                         cpu = CPU_M2;
1674                         break;
1675                 default:
1676                         identifycyrix();
1677                         /*
1678                          * This routine contains a trick.
1679                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1680                          */
1681                         switch (cyrix_did & 0x00f0) {
1682                         case 0x00:
1683                         case 0xf0:
1684                                 cpu = CPU_486DLC;
1685                                 break;
1686                         case 0x10:
1687                                 cpu = CPU_CY486DX;
1688                                 break;
1689                         case 0x20:
1690                                 if ((cyrix_did & 0x000f) < 8)
1691                                         cpu = CPU_M1;
1692                                 else
1693                                         cpu = CPU_M1SC;
1694                                 break;
1695                         case 0x30:
1696                                 cpu = CPU_M1;
1697                                 break;
1698                         case 0x40:
1699                                 /* MediaGX CPU */
1700                                 cpu = CPU_M1SC;
1701                                 break;
1702                         default:
1703                                 /* M2 and later CPUs are treated as M2. */
1704                                 cpu = CPU_M2;
1705
1706                                 /*
1707                                  * enable cpuid instruction.
1708                                  */
1709                                 ccr3 = read_cyrix_reg(CCR3);
1710                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1711                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1712                                 write_cyrix_reg(CCR3, ccr3);
1713
1714                                 do_cpuid(0, regs);
1715                                 cpu_high = regs[0];     /* eax */
1716                                 do_cpuid(1, regs);
1717                                 cpu_id = regs[0];       /* eax */
1718                                 cpu_feature = regs[3];  /* edx */
1719                                 break;
1720                         }
1721                 }
1722         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1723                 /*
1724                  * There are BlueLightning CPUs that do not change
1725                  * undefined flags by dividing 5 by 2.  In this case,
1726                  * the CPU identification routine in locore.s leaves
1727                  * cpu_vendor null string and puts CPU_486 into the
1728                  * cpu.
1729                  */
1730                 if (identblue() == IDENTBLUE_IBMCPU) {
1731                         strcpy(cpu_vendor, "IBM");
1732                         cpu_vendor_id = CPU_VENDOR_IBM;
1733                         cpu = CPU_BLUE;
1734                         return;
1735                 }
1736         }
1737 #endif
1738 }
1739
1740 int
1741 pti_get_default(void)
1742 {
1743
1744         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1745                 return (0);
1746         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1747                 return (0);
1748         return (1);
1749 }
1750
1751 static u_int
1752 find_cpu_vendor_id(void)
1753 {
1754         int     i;
1755
1756         for (i = 0; i < nitems(cpu_vendors); i++)
1757                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1758                         return (cpu_vendors[i].vendor_id);
1759         return (0);
1760 }
1761
1762 static void
1763 print_AMD_assoc(int i)
1764 {
1765         if (i == 255)
1766                 printf(", fully associative\n");
1767         else
1768                 printf(", %d-way associative\n", i);
1769 }
1770
1771 static void
1772 print_AMD_l2_assoc(int i)
1773 {
1774         switch (i & 0x0f) {
1775         case 0: printf(", disabled/not present\n"); break;
1776         case 1: printf(", direct mapped\n"); break;
1777         case 2: printf(", 2-way associative\n"); break;
1778         case 4: printf(", 4-way associative\n"); break;
1779         case 6: printf(", 8-way associative\n"); break;
1780         case 8: printf(", 16-way associative\n"); break;
1781         case 15: printf(", fully associative\n"); break;
1782         default: printf(", reserved configuration\n"); break;
1783         }
1784 }
1785
1786 static void
1787 print_AMD_info(void)
1788 {
1789 #ifdef __i386__
1790         uint64_t amd_whcr;
1791 #endif
1792         u_int regs[4];
1793
1794         if (cpu_exthigh >= 0x80000005) {
1795                 do_cpuid(0x80000005, regs);
1796                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1797                 print_AMD_assoc(regs[0] >> 24);
1798
1799                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1800                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1801
1802                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1803                 print_AMD_assoc(regs[1] >> 24);
1804
1805                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1806                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1807
1808                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1809                 printf(", %d bytes/line", regs[2] & 0xff);
1810                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1811                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1812
1813                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1814                 printf(", %d bytes/line", regs[3] & 0xff);
1815                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1816                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1817         }
1818
1819         if (cpu_exthigh >= 0x80000006) {
1820                 do_cpuid(0x80000006, regs);
1821                 if ((regs[0] >> 16) != 0) {
1822                         printf("L2 2MB data TLB: %d entries",
1823                             (regs[0] >> 16) & 0xfff);
1824                         print_AMD_l2_assoc(regs[0] >> 28);
1825                         printf("L2 2MB instruction TLB: %d entries",
1826                             regs[0] & 0xfff);
1827                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1828                 } else {
1829                         printf("L2 2MB unified TLB: %d entries",
1830                             regs[0] & 0xfff);
1831                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1832                 }
1833                 if ((regs[1] >> 16) != 0) {
1834                         printf("L2 4KB data TLB: %d entries",
1835                             (regs[1] >> 16) & 0xfff);
1836                         print_AMD_l2_assoc(regs[1] >> 28);
1837
1838                         printf("L2 4KB instruction TLB: %d entries",
1839                             (regs[1] >> 16) & 0xfff);
1840                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1841                 } else {
1842                         printf("L2 4KB unified TLB: %d entries",
1843                             (regs[1] >> 16) & 0xfff);
1844                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1845                 }
1846                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1847                 printf(", %d bytes/line", regs[2] & 0xff);
1848                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1849                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1850         }
1851
1852 #ifdef __i386__
1853         if (((cpu_id & 0xf00) == 0x500)
1854             && (((cpu_id & 0x0f0) > 0x80)
1855                 || (((cpu_id & 0x0f0) == 0x80)
1856                     && (cpu_id & 0x00f) > 0x07))) {
1857                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1858                 amd_whcr = rdmsr(0xc0000082);
1859                 if (!(amd_whcr & (0x3ff << 22))) {
1860                         printf("Write Allocate Disable\n");
1861                 } else {
1862                         printf("Write Allocate Enable Limit: %dM bytes\n",
1863                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1864                         printf("Write Allocate 15-16M bytes: %s\n",
1865                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1866                 }
1867         } else if (((cpu_id & 0xf00) == 0x500)
1868                    && ((cpu_id & 0x0f0) > 0x50)) {
1869                 /* K6, K6-2(old core) */
1870                 amd_whcr = rdmsr(0xc0000082);
1871                 if (!(amd_whcr & (0x7f << 1))) {
1872                         printf("Write Allocate Disable\n");
1873                 } else {
1874                         printf("Write Allocate Enable Limit: %dM bytes\n",
1875                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1876                         printf("Write Allocate 15-16M bytes: %s\n",
1877                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1878                         printf("Hardware Write Allocate Control: %s\n",
1879                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1880                 }
1881         }
1882 #endif
1883         /*
1884          * Opteron Rev E shows a bug as in very rare occasions a read memory
1885          * barrier is not performed as expected if it is followed by a
1886          * non-atomic read-modify-write instruction.
1887          * As long as that bug pops up very rarely (intensive machine usage
1888          * on other operating systems generally generates one unexplainable
1889          * crash any 2 months) and as long as a model specific fix would be
1890          * impractical at this stage, print out a warning string if the broken
1891          * model and family are identified.
1892          */
1893         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1894             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1895                 printf("WARNING: This architecture revision has known SMP "
1896                     "hardware bugs which may cause random instability\n");
1897 }
1898
1899 static void
1900 print_INTEL_info(void)
1901 {
1902         u_int regs[4];
1903         u_int rounds, regnum;
1904         u_int nwaycode, nway;
1905
1906         if (cpu_high >= 2) {
1907                 rounds = 0;
1908                 do {
1909                         do_cpuid(0x2, regs);
1910                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1911                                 break;  /* we have a buggy CPU */
1912
1913                         for (regnum = 0; regnum <= 3; ++regnum) {
1914                                 if (regs[regnum] & (1<<31))
1915                                         continue;
1916                                 if (regnum != 0)
1917                                         print_INTEL_TLB(regs[regnum] & 0xff);
1918                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1919                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1920                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1921                         }
1922                 } while (--rounds > 0);
1923         }
1924
1925         if (cpu_exthigh >= 0x80000006) {
1926                 do_cpuid(0x80000006, regs);
1927                 nwaycode = (regs[2] >> 12) & 0x0f;
1928                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1929                         nway = 1 << (nwaycode / 2);
1930                 else
1931                         nway = 0;
1932                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1933                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1934         }
1935 }
1936
1937 static void
1938 print_INTEL_TLB(u_int data)
1939 {
1940         switch (data) {
1941         case 0x0:
1942         case 0x40:
1943         default:
1944                 break;
1945         case 0x1:
1946                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1947                 break;
1948         case 0x2:
1949                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1950                 break;
1951         case 0x3:
1952                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1953                 break;
1954         case 0x4:
1955                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1956                 break;
1957         case 0x6:
1958                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1959                 break;
1960         case 0x8:
1961                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1962                 break;
1963         case 0x9:
1964                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1965                 break;
1966         case 0xa:
1967                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1968                 break;
1969         case 0xb:
1970                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1971                 break;
1972         case 0xc:
1973                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1974                 break;
1975         case 0xd:
1976                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1977                 break;
1978         case 0xe:
1979                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1980                 break;
1981         case 0x1d:
1982                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1983                 break;
1984         case 0x21:
1985                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1986                 break;
1987         case 0x22:
1988                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1989                 break;
1990         case 0x23:
1991                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1992                 break;
1993         case 0x24:
1994                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1995                 break;
1996         case 0x25:
1997                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1998                 break;
1999         case 0x29:
2000                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2001                 break;
2002         case 0x2c:
2003                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2004                 break;
2005         case 0x30:
2006                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2007                 break;
2008         case 0x39: /* De-listed in SDM rev. 54 */
2009                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2010                 break;
2011         case 0x3b: /* De-listed in SDM rev. 54 */
2012                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2013                 break;
2014         case 0x3c: /* De-listed in SDM rev. 54 */
2015                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2016                 break;
2017         case 0x41:
2018                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2019                 break;
2020         case 0x42:
2021                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2022                 break;
2023         case 0x43:
2024                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2025                 break;
2026         case 0x44:
2027                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2028                 break;
2029         case 0x45:
2030                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2031                 break;
2032         case 0x46:
2033                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2034                 break;
2035         case 0x47:
2036                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2037                 break;
2038         case 0x48:
2039                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2040                 break;
2041         case 0x49:
2042                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2043                     CPUID_TO_MODEL(cpu_id) == 0x6)
2044                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2045                 else
2046                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2047                 break;
2048         case 0x4a:
2049                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2050                 break;
2051         case 0x4b:
2052                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2053                 break;
2054         case 0x4c:
2055                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2056                 break;
2057         case 0x4d:
2058                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2059                 break;
2060         case 0x4e:
2061                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2062                 break;
2063         case 0x4f:
2064                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2065                 break;
2066         case 0x50:
2067                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2068                 break;
2069         case 0x51:
2070                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2071                 break;
2072         case 0x52:
2073                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2074                 break;
2075         case 0x55:
2076                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2077                 break;
2078         case 0x56:
2079                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2080                 break;
2081         case 0x57:
2082                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2083                 break;
2084         case 0x59:
2085                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2086                 break;
2087         case 0x5a:
2088                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2089                 break;
2090         case 0x5b:
2091                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2092                 break;
2093         case 0x5c:
2094                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2095                 break;
2096         case 0x5d:
2097                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2098                 break;
2099         case 0x60:
2100                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2101                 break;
2102         case 0x61:
2103                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2104                 break;
2105         case 0x63:
2106                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2107                 break;
2108         case 0x64:
2109                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2110                 break;
2111         case 0x66:
2112                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2113                 break;
2114         case 0x67:
2115                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2116                 break;
2117         case 0x68:
2118                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2119                 break;
2120         case 0x6a:
2121                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2122                 break;
2123         case 0x6b:
2124                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2125                 break;
2126         case 0x6c:
2127                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2128                 break;
2129         case 0x6d:
2130                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2131                 break;
2132         case 0x70:
2133                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2134                 break;
2135         case 0x71:
2136                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2137                 break;
2138         case 0x72:
2139                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2140                 break;
2141         case 0x76:
2142                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2143                 break;
2144         case 0x78:
2145                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2146                 break;
2147         case 0x79:
2148                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2149                 break;
2150         case 0x7a:
2151                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2152                 break;
2153         case 0x7b:
2154                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2155                 break;
2156         case 0x7c:
2157                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2158                 break;
2159         case 0x7d:
2160                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2161                 break;
2162         case 0x7f:
2163                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2164                 break;
2165         case 0x80:
2166                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2167                 break;
2168         case 0x82:
2169                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2170                 break;
2171         case 0x83:
2172                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2173                 break;
2174         case 0x84:
2175                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2176                 break;
2177         case 0x85:
2178                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2179                 break;
2180         case 0x86:
2181                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2182                 break;
2183         case 0x87:
2184                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2185                 break;
2186         case 0xa0:
2187                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2188                 break;
2189         case 0xb0:
2190                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2191                 break;
2192         case 0xb1:
2193                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2194                 break;
2195         case 0xb2:
2196                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2197                 break;
2198         case 0xb3:
2199                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2200                 break;
2201         case 0xb4:
2202                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2203                 break;
2204         case 0xb5:
2205                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2206                 break;
2207         case 0xb6:
2208                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2209                 break;
2210         case 0xba:
2211                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2212                 break;
2213         case 0xc0:
2214                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2215                 break;
2216         case 0xc1:
2217                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2218                 break;
2219         case 0xc2:
2220                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2221                 break;
2222         case 0xc3:
2223                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2224                 break;
2225         case 0xc4:
2226                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2227                 break;
2228         case 0xca:
2229                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2230                 break;
2231         case 0xd0:
2232                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2233                 break;
2234         case 0xd1:
2235                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2236                 break;
2237         case 0xd2:
2238                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2239                 break;
2240         case 0xd6:
2241                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2242                 break;
2243         case 0xd7:
2244                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2245                 break;
2246         case 0xd8:
2247                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2248                 break;
2249         case 0xdc:
2250                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2251                 break;
2252         case 0xdd:
2253                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2254                 break;
2255         case 0xde:
2256                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2257                 break;
2258         case 0xe2:
2259                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2260                 break;
2261         case 0xe3:
2262                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2263                 break;
2264         case 0xe4:
2265                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2266                 break;
2267         case 0xea:
2268                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2269                 break;
2270         case 0xeb:
2271                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2272                 break;
2273         case 0xec:
2274                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2275                 break;
2276         case 0xf0:
2277                 printf("64-Byte prefetching\n");
2278                 break;
2279         case 0xf1:
2280                 printf("128-Byte prefetching\n");
2281                 break;
2282         }
2283 }
2284
2285 static void
2286 print_svm_info(void)
2287 {
2288         u_int features, regs[4];
2289         uint64_t msr;
2290         int comma;
2291
2292         printf("\n  SVM: ");
2293         do_cpuid(0x8000000A, regs);
2294         features = regs[3];
2295
2296         msr = rdmsr(MSR_VM_CR);
2297         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2298                 printf("(disabled in BIOS) ");
2299
2300         if (!bootverbose) {
2301                 comma = 0;
2302                 if (features & (1 << 0)) {
2303                         printf("%sNP", comma ? "," : "");
2304                         comma = 1;
2305                 }
2306                 if (features & (1 << 3)) {
2307                         printf("%sNRIP", comma ? "," : "");
2308                         comma = 1;
2309                 }
2310                 if (features & (1 << 5)) {
2311                         printf("%sVClean", comma ? "," : "");
2312                         comma = 1;
2313                 }
2314                 if (features & (1 << 6)) {
2315                         printf("%sAFlush", comma ? "," : "");
2316                         comma = 1;
2317                 }
2318                 if (features & (1 << 7)) {
2319                         printf("%sDAssist", comma ? "," : "");
2320                         comma = 1;
2321                 }
2322                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2323                 return;
2324         }
2325
2326         printf("Features=0x%b", features,
2327                "\020"
2328                "\001NP"                 /* Nested paging */
2329                "\002LbrVirt"            /* LBR virtualization */
2330                "\003SVML"               /* SVM lock */
2331                "\004NRIPS"              /* NRIP save */
2332                "\005TscRateMsr"         /* MSR based TSC rate control */
2333                "\006VmcbClean"          /* VMCB clean bits */
2334                "\007FlushByAsid"        /* Flush by ASID */
2335                "\010DecodeAssist"       /* Decode assist */
2336                "\011<b8>"
2337                "\012<b9>"
2338                "\013PauseFilter"        /* PAUSE intercept filter */
2339                "\014EncryptedMcodePatch"
2340                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2341                "\016AVIC"               /* virtual interrupt controller */
2342                "\017<b14>"
2343                "\020V_VMSAVE_VMLOAD"
2344                "\021vGIF"
2345                "\022<b17>"
2346                "\023<b18>"
2347                "\024<b19>"
2348                "\025<b20>"
2349                "\026<b21>"
2350                "\027<b22>"
2351                "\030<b23>"
2352                "\031<b24>"
2353                "\032<b25>"
2354                "\033<b26>"
2355                "\034<b27>"
2356                "\035<b28>"
2357                "\036<b29>"
2358                "\037<b30>"
2359                "\040<b31>"
2360                 );
2361         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2362 }
2363
2364 #ifdef __i386__
2365 static void
2366 print_transmeta_info(void)
2367 {
2368         u_int regs[4], nreg = 0;
2369
2370         do_cpuid(0x80860000, regs);
2371         nreg = regs[0];
2372         if (nreg >= 0x80860001) {
2373                 do_cpuid(0x80860001, regs);
2374                 printf("  Processor revision %u.%u.%u.%u\n",
2375                        (regs[1] >> 24) & 0xff,
2376                        (regs[1] >> 16) & 0xff,
2377                        (regs[1] >> 8) & 0xff,
2378                        regs[1] & 0xff);
2379         }
2380         if (nreg >= 0x80860002) {
2381                 do_cpuid(0x80860002, regs);
2382                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2383                        (regs[1] >> 24) & 0xff,
2384                        (regs[1] >> 16) & 0xff,
2385                        (regs[1] >> 8) & 0xff,
2386                        regs[1] & 0xff,
2387                        regs[2]);
2388         }
2389         if (nreg >= 0x80860006) {
2390                 char info[65];
2391                 do_cpuid(0x80860003, (u_int*) &info[0]);
2392                 do_cpuid(0x80860004, (u_int*) &info[16]);
2393                 do_cpuid(0x80860005, (u_int*) &info[32]);
2394                 do_cpuid(0x80860006, (u_int*) &info[48]);
2395                 info[64] = 0;
2396                 printf("  %s\n", info);
2397         }
2398 }
2399 #endif
2400
2401 static void
2402 print_via_padlock_info(void)
2403 {
2404         u_int regs[4];
2405
2406         do_cpuid(0xc0000001, regs);
2407         printf("\n  VIA Padlock Features=0x%b", regs[3],
2408         "\020"
2409         "\003RNG"               /* RNG */
2410         "\007AES"               /* ACE */
2411         "\011AES-CTR"           /* ACE2 */
2412         "\013SHA1,SHA256"       /* PHE */
2413         "\015RSA"               /* PMM */
2414         );
2415 }
2416
2417 static uint32_t
2418 vmx_settable(uint64_t basic, int msr, int true_msr)
2419 {
2420         uint64_t val;
2421
2422         if (basic & (1ULL << 55))
2423                 val = rdmsr(true_msr);
2424         else
2425                 val = rdmsr(msr);
2426
2427         /* Just report the controls that can be set to 1. */
2428         return (val >> 32);
2429 }
2430
2431 static void
2432 print_vmx_info(void)
2433 {
2434         uint64_t basic, msr;
2435         uint32_t entry, exit, mask, pin, proc, proc2;
2436         int comma;
2437
2438         printf("\n  VT-x: ");
2439         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2440         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2441                 printf("(disabled in BIOS) ");
2442         basic = rdmsr(MSR_VMX_BASIC);
2443         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2444             MSR_VMX_TRUE_PINBASED_CTLS);
2445         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2446             MSR_VMX_TRUE_PROCBASED_CTLS);
2447         if (proc & PROCBASED_SECONDARY_CONTROLS)
2448                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2449                     MSR_VMX_PROCBASED_CTLS2);
2450         else
2451                 proc2 = 0;
2452         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2453         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2454
2455         if (!bootverbose) {
2456                 comma = 0;
2457                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2458                     entry & VM_ENTRY_LOAD_PAT) {
2459                         printf("%sPAT", comma ? "," : "");
2460                         comma = 1;
2461                 }
2462                 if (proc & PROCBASED_HLT_EXITING) {
2463                         printf("%sHLT", comma ? "," : "");
2464                         comma = 1;
2465                 }
2466                 if (proc & PROCBASED_MTF) {
2467                         printf("%sMTF", comma ? "," : "");
2468                         comma = 1;
2469                 }
2470                 if (proc & PROCBASED_PAUSE_EXITING) {
2471                         printf("%sPAUSE", comma ? "," : "");
2472                         comma = 1;
2473                 }
2474                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2475                         printf("%sEPT", comma ? "," : "");
2476                         comma = 1;
2477                 }
2478                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2479                         printf("%sUG", comma ? "," : "");
2480                         comma = 1;
2481                 }
2482                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2483                         printf("%sVPID", comma ? "," : "");
2484                         comma = 1;
2485                 }
2486                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2487                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2488                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2489                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2490                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2491                         printf("%sVID", comma ? "," : "");
2492                         comma = 1;
2493                         if (pin & PINBASED_POSTED_INTERRUPT)
2494                                 printf(",PostIntr");
2495                 }
2496                 return;
2497         }
2498
2499         mask = basic >> 32;
2500         printf("Basic Features=0x%b", mask,
2501         "\020"
2502         "\02132PA"              /* 32-bit physical addresses */
2503         "\022SMM"               /* SMM dual-monitor */
2504         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2505         "\030TRUE"              /* TRUE_CTLS MSRs */
2506         );
2507         printf("\n        Pin-Based Controls=0x%b", pin,
2508         "\020"
2509         "\001ExtINT"            /* External-interrupt exiting */
2510         "\004NMI"               /* NMI exiting */
2511         "\006VNMI"              /* Virtual NMIs */
2512         "\007PreTmr"            /* Activate VMX-preemption timer */
2513         "\010PostIntr"          /* Process posted interrupts */
2514         );
2515         printf("\n        Primary Processor Controls=0x%b", proc,
2516         "\020"
2517         "\003INTWIN"            /* Interrupt-window exiting */
2518         "\004TSCOff"            /* Use TSC offsetting */
2519         "\010HLT"               /* HLT exiting */
2520         "\012INVLPG"            /* INVLPG exiting */
2521         "\013MWAIT"             /* MWAIT exiting */
2522         "\014RDPMC"             /* RDPMC exiting */
2523         "\015RDTSC"             /* RDTSC exiting */
2524         "\020CR3-LD"            /* CR3-load exiting */
2525         "\021CR3-ST"            /* CR3-store exiting */
2526         "\024CR8-LD"            /* CR8-load exiting */
2527         "\025CR8-ST"            /* CR8-store exiting */
2528         "\026TPR"               /* Use TPR shadow */
2529         "\027NMIWIN"            /* NMI-window exiting */
2530         "\030MOV-DR"            /* MOV-DR exiting */
2531         "\031IO"                /* Unconditional I/O exiting */
2532         "\032IOmap"             /* Use I/O bitmaps */
2533         "\034MTF"               /* Monitor trap flag */
2534         "\035MSRmap"            /* Use MSR bitmaps */
2535         "\036MONITOR"           /* MONITOR exiting */
2536         "\037PAUSE"             /* PAUSE exiting */
2537         );
2538         if (proc & PROCBASED_SECONDARY_CONTROLS)
2539                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2540                 "\020"
2541                 "\001APIC"              /* Virtualize APIC accesses */
2542                 "\002EPT"               /* Enable EPT */
2543                 "\003DT"                /* Descriptor-table exiting */
2544                 "\004RDTSCP"            /* Enable RDTSCP */
2545                 "\005x2APIC"            /* Virtualize x2APIC mode */
2546                 "\006VPID"              /* Enable VPID */
2547                 "\007WBINVD"            /* WBINVD exiting */
2548                 "\010UG"                /* Unrestricted guest */
2549                 "\011APIC-reg"          /* APIC-register virtualization */
2550                 "\012VID"               /* Virtual-interrupt delivery */
2551                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2552                 "\014RDRAND"            /* RDRAND exiting */
2553                 "\015INVPCID"           /* Enable INVPCID */
2554                 "\016VMFUNC"            /* Enable VM functions */
2555                 "\017VMCS"              /* VMCS shadowing */
2556                 "\020EPT#VE"            /* EPT-violation #VE */
2557                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2558                 );
2559         printf("\n        Exit Controls=0x%b", mask,
2560         "\020"
2561         "\003DR"                /* Save debug controls */
2562                                 /* Ignore Host address-space size */
2563         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2564         "\020AckInt"            /* Acknowledge interrupt on exit */
2565         "\023PAT-SV"            /* Save MSR_PAT */
2566         "\024PAT-LD"            /* Load MSR_PAT */
2567         "\025EFER-SV"           /* Save MSR_EFER */
2568         "\026EFER-LD"           /* Load MSR_EFER */
2569         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2570         );
2571         printf("\n        Entry Controls=0x%b", mask,
2572         "\020"
2573         "\003DR"                /* Save debug controls */
2574                                 /* Ignore IA-32e mode guest */
2575                                 /* Ignore Entry to SMM */
2576                                 /* Ignore Deactivate dual-monitor treatment */
2577         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2578         "\017PAT"               /* Load MSR_PAT */
2579         "\020EFER"              /* Load MSR_EFER */
2580         );
2581         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2582             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2583                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2584                 mask = msr;
2585                 printf("\n        EPT Features=0x%b", mask,
2586                 "\020"
2587                 "\001XO"                /* Execute-only translations */
2588                 "\007PW4"               /* Page-walk length of 4 */
2589                 "\011UC"                /* EPT paging-structure mem can be UC */
2590                 "\017WB"                /* EPT paging-structure mem can be WB */
2591                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2592                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2593                 "\025INVEPT"            /* INVEPT is supported */
2594                 "\026AD"                /* Accessed and dirty flags for EPT */
2595                 "\032single"            /* INVEPT single-context type */
2596                 "\033all"               /* INVEPT all-context type */
2597                 );
2598                 mask = msr >> 32;
2599                 printf("\n        VPID Features=0x%b", mask,
2600                 "\020"
2601                 "\001INVVPID"           /* INVVPID is supported */
2602                 "\011individual"        /* INVVPID individual-address type */
2603                 "\012single"            /* INVVPID single-context type */
2604                 "\013all"               /* INVVPID all-context type */
2605                  /* INVVPID single-context-retaining-globals type */
2606                 "\014single-globals"
2607                 );
2608         }
2609 }
2610
2611 static void
2612 print_hypervisor_info(void)
2613 {
2614
2615         if (*hv_vendor != '\0')
2616                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2617 }
2618
2619 /*
2620  * Returns the maximum physical address that can be used with the
2621  * current system.
2622  */
2623 vm_paddr_t
2624 cpu_getmaxphyaddr(void)
2625 {
2626
2627 #if defined(__i386__)
2628         if (!pae_mode)
2629                 return (0xffffffff);
2630 #endif
2631         return ((1ULL << cpu_maxphyaddr) - 1);
2632 }