2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
49 #include <sys/eventhandler.h>
50 #include <sys/limits.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/sysctl.h>
54 #include <sys/power.h>
59 #include <machine/asmacros.h>
60 #include <machine/clock.h>
61 #include <machine/cputypes.h>
62 #include <machine/frame.h>
63 #include <machine/intr_machdep.h>
64 #include <machine/md_var.h>
65 #include <machine/segments.h>
66 #include <machine/specialreg.h>
68 #include <amd64/vmm/intel/vmx_controls.h>
69 #include <x86/isa/icu.h>
70 #include <x86/vmware.h>
73 #define IDENTBLUE_CYRIX486 0
74 #define IDENTBLUE_IBMCPU 1
75 #define IDENTBLUE_CYRIXM2 2
77 static void identifycyrix(void);
78 static void print_transmeta_info(void);
80 static u_int find_cpu_vendor_id(void);
81 static void print_AMD_info(void);
82 static void print_INTEL_info(void);
83 static void print_INTEL_TLB(u_int data);
84 static void print_hypervisor_info(void);
85 static void print_svm_info(void);
86 static void print_via_padlock_info(void);
87 static void print_vmx_info(void);
90 int cpu; /* Are we 386, 386sx, 486, etc? */
93 u_int cpu_feature; /* Feature flags */
94 u_int cpu_feature2; /* Feature flags */
95 u_int amd_feature; /* AMD feature flags */
96 u_int amd_feature2; /* AMD feature flags */
97 u_int amd_rascap; /* AMD RAS capabilities */
98 u_int amd_pminfo; /* AMD advanced power management info */
99 u_int amd_extended_feature_extensions;
100 u_int via_feature_rng; /* VIA RNG features */
101 u_int via_feature_xcrypt; /* VIA ACE features */
102 u_int cpu_high; /* Highest arg to CPUID */
103 u_int cpu_exthigh; /* Highest arg to extended CPUID */
104 u_int cpu_id; /* Stepping ID */
105 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
106 u_int cpu_procinfo2; /* Multicore info */
107 char cpu_vendor[20]; /* CPU Origin code */
108 u_int cpu_vendor_id; /* CPU vendor ID */
109 u_int cpu_fxsr; /* SSE enabled */
110 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
111 u_int cpu_clflush_line_size = 32;
112 u_int cpu_stdext_feature; /* %ebx */
113 u_int cpu_stdext_feature2; /* %ecx */
114 u_int cpu_stdext_feature3; /* %edx */
115 uint64_t cpu_ia32_arch_caps;
116 u_int cpu_max_ext_state_size;
117 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
118 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
119 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
120 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
121 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
122 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
123 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
124 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
125 char machine[] = MACHINE;
127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
129 "VIA RNG feature available in CPU");
130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
131 &via_feature_xcrypt, 0,
132 "VIA xcrypt feature available in CPU");
136 extern int adaptive_machine_arch;
140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
143 static const char machine32[] = "i386";
148 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
149 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
152 error = SYSCTL_OUT(req, machine, sizeof(machine));
156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
157 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
160 machine, 0, "Machine class");
163 static char cpu_model[128];
164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
165 cpu_model, 0, "Machine model");
167 static int hw_clockrate;
168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
169 &hw_clockrate, 0, "CPU instruction clock rate");
174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
175 0, "Hypervisor vendor");
177 static eventhandler_tag tsc_post_tag;
179 static char cpu_brand[48];
182 #define MAX_BRAND_INDEX 8
184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
188 "Intel Pentium III Xeon",
200 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
201 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
202 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
203 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
204 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
205 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
206 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
207 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
208 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
209 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
210 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
211 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
212 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
213 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
214 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
215 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
216 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
224 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
225 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
226 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine*/
227 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
229 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
230 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
231 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
232 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
233 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
234 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
235 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
237 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
238 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
251 cpu_class = cpus[cpu].cpu_class;
252 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
254 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
257 /* Check for extended CPUID information and a processor name. */
258 if (cpu_exthigh >= 0x80000004) {
260 for (i = 0x80000002; i < 0x80000005; i++) {
262 memcpy(brand, regs, sizeof(regs));
263 brand += sizeof(regs);
267 switch (cpu_vendor_id) {
268 case CPU_VENDOR_INTEL:
270 if ((cpu_id & 0xf00) > 0x300) {
275 switch (cpu_id & 0x3000) {
277 strcpy(cpu_model, "Overdrive ");
280 strcpy(cpu_model, "Dual ");
284 switch (cpu_id & 0xf00) {
286 strcat(cpu_model, "i486 ");
287 /* Check the particular flavor of 486 */
288 switch (cpu_id & 0xf0) {
291 strcat(cpu_model, "DX");
294 strcat(cpu_model, "SX");
297 strcat(cpu_model, "DX2");
300 strcat(cpu_model, "SL");
303 strcat(cpu_model, "SX2");
307 "DX2 Write-Back Enhanced");
310 strcat(cpu_model, "DX4");
315 /* Check the particular flavor of 586 */
316 strcat(cpu_model, "Pentium");
317 switch (cpu_id & 0xf0) {
319 strcat(cpu_model, " A-step");
322 strcat(cpu_model, "/P5");
325 strcat(cpu_model, "/P54C");
328 strcat(cpu_model, "/P24T");
331 strcat(cpu_model, "/P55C");
334 strcat(cpu_model, "/P54C");
337 strcat(cpu_model, "/P55C (quarter-micron)");
343 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
345 * XXX - If/when Intel fixes the bug, this
346 * should also check the version of the
347 * CPU, not just that it's a Pentium.
353 /* Check the particular flavor of 686 */
354 switch (cpu_id & 0xf0) {
356 strcat(cpu_model, "Pentium Pro A-step");
359 strcat(cpu_model, "Pentium Pro");
365 "Pentium II/Pentium II Xeon/Celeron");
373 "Pentium III/Pentium III Xeon/Celeron");
377 strcat(cpu_model, "Unknown 80686");
382 strcat(cpu_model, "Pentium 4");
386 strcat(cpu_model, "unknown");
391 * If we didn't get a brand name from the extended
392 * CPUID, try to look it up in the brand table.
394 if (cpu_high > 0 && *cpu_brand == '\0') {
395 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
396 if (brand_index <= MAX_BRAND_INDEX &&
397 cpu_brandtable[brand_index] != NULL)
399 cpu_brandtable[brand_index]);
403 /* Please make up your mind folks! */
404 strcat(cpu_model, "EM64T");
409 * Values taken from AMD Processor Recognition
410 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
411 * (also describes ``Features'' encodings.
413 strcpy(cpu_model, "AMD ");
415 switch (cpu_id & 0xFF0) {
417 strcat(cpu_model, "Standard Am486DX");
420 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
423 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
426 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
429 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
432 strcat(cpu_model, "Am5x86 Write-Through");
435 strcat(cpu_model, "Am5x86 Write-Back");
438 strcat(cpu_model, "K5 model 0");
441 strcat(cpu_model, "K5 model 1");
444 strcat(cpu_model, "K5 PR166 (model 2)");
447 strcat(cpu_model, "K5 PR200 (model 3)");
450 strcat(cpu_model, "K6");
453 strcat(cpu_model, "K6 266 (model 1)");
456 strcat(cpu_model, "K6-2");
459 strcat(cpu_model, "K6-III");
462 strcat(cpu_model, "Geode LX");
465 strcat(cpu_model, "Unknown");
469 if ((cpu_id & 0xf00) == 0xf00)
470 strcat(cpu_model, "AMD64 Processor");
472 strcat(cpu_model, "Unknown");
476 case CPU_VENDOR_CYRIX:
477 strcpy(cpu_model, "Cyrix ");
478 switch (cpu_id & 0xff0) {
480 strcat(cpu_model, "MediaGX");
483 strcat(cpu_model, "6x86");
486 cpu_class = CPUCLASS_586;
487 strcat(cpu_model, "GXm");
490 strcat(cpu_model, "6x86MX");
494 * Even though CPU supports the cpuid
495 * instruction, it can be disabled.
496 * Therefore, this routine supports all Cyrix
499 switch (cyrix_did & 0xf0) {
501 switch (cyrix_did & 0x0f) {
503 strcat(cpu_model, "486SLC");
506 strcat(cpu_model, "486DLC");
509 strcat(cpu_model, "486SLC2");
512 strcat(cpu_model, "486DLC2");
515 strcat(cpu_model, "486SRx");
518 strcat(cpu_model, "486DRx");
521 strcat(cpu_model, "486SRx2");
524 strcat(cpu_model, "486DRx2");
527 strcat(cpu_model, "486SRu");
530 strcat(cpu_model, "486DRu");
533 strcat(cpu_model, "486SRu2");
536 strcat(cpu_model, "486DRu2");
539 strcat(cpu_model, "Unknown");
544 switch (cyrix_did & 0x0f) {
546 strcat(cpu_model, "486S");
549 strcat(cpu_model, "486S2");
552 strcat(cpu_model, "486Se");
555 strcat(cpu_model, "486S2e");
558 strcat(cpu_model, "486DX");
561 strcat(cpu_model, "486DX2");
564 strcat(cpu_model, "486DX4");
567 strcat(cpu_model, "Unknown");
572 if ((cyrix_did & 0x0f) < 8)
573 strcat(cpu_model, "6x86"); /* Where did you get it? */
575 strcat(cpu_model, "5x86");
578 strcat(cpu_model, "6x86");
581 if ((cyrix_did & 0xf000) == 0x3000) {
582 cpu_class = CPUCLASS_586;
583 strcat(cpu_model, "GXm");
585 strcat(cpu_model, "MediaGX");
588 strcat(cpu_model, "6x86MX");
591 switch (cyrix_did & 0x0f) {
593 strcat(cpu_model, "Overdrive CPU");
596 strcpy(cpu_model, "Texas Instruments 486SXL");
599 strcat(cpu_model, "486SLC/DLC");
602 strcat(cpu_model, "Unknown");
607 strcat(cpu_model, "Unknown");
613 case CPU_VENDOR_RISE:
614 strcpy(cpu_model, "Rise ");
615 switch (cpu_id & 0xff0) {
616 case 0x500: /* 6401 and 6441 (Kirin) */
617 case 0x520: /* 6510 (Lynx) */
618 strcat(cpu_model, "mP6");
621 strcat(cpu_model, "Unknown");
625 case CPU_VENDOR_CENTAUR:
627 switch (cpu_id & 0xff0) {
629 strcpy(cpu_model, "IDT WinChip C6");
632 strcpy(cpu_model, "IDT WinChip 2");
635 strcpy(cpu_model, "IDT WinChip 3");
638 strcpy(cpu_model, "VIA C3 Samuel");
642 strcpy(cpu_model, "VIA C3 Ezra");
644 strcpy(cpu_model, "VIA C3 Samuel 2");
647 strcpy(cpu_model, "VIA C3 Ezra-T");
650 strcpy(cpu_model, "VIA C3 Nehemiah");
654 strcpy(cpu_model, "VIA C7 Esther");
657 strcpy(cpu_model, "VIA Nano");
660 strcpy(cpu_model, "VIA/IDT Unknown");
663 strcpy(cpu_model, "VIA ");
664 if ((cpu_id & 0xff0) == 0x6f0)
665 strcat(cpu_model, "Nano Processor");
667 strcat(cpu_model, "Unknown");
672 strcpy(cpu_model, "Blue Lightning CPU");
675 switch (cpu_id & 0xff0) {
677 strcpy(cpu_model, "Geode SC1100");
681 strcpy(cpu_model, "Geode/NSC unknown");
686 case CPU_VENDOR_HYGON:
687 strcpy(cpu_model, "Hygon ");
689 strcat(cpu_model, "Unknown");
691 if ((cpu_id & 0xf00) == 0xf00)
692 strcat(cpu_model, "AMD64 Processor");
694 strcat(cpu_model, "Unknown");
699 strcat(cpu_model, "Unknown");
704 * Replace cpu_model with cpu_brand minus leading spaces if
708 while (*brand == ' ')
711 strcpy(cpu_model, brand);
713 printf("%s (", cpu_model);
715 hw_clockrate = (tsc_freq + 5000) / 1000000;
716 printf("%jd.%02d-MHz ",
717 (intmax_t)(tsc_freq + 4999) / 1000000,
718 (u_int)((tsc_freq + 4999) / 10000) % 100);
728 #if defined(I486_CPU)
733 #if defined(I586_CPU)
738 #if defined(I686_CPU)
744 printf("Unknown"); /* will panic below... */
749 printf("-class CPU)\n");
751 printf(" Origin=\"%s\"", cpu_vendor);
753 printf(" Id=0x%x", cpu_id);
755 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
756 cpu_vendor_id == CPU_VENDOR_AMD ||
757 cpu_vendor_id == CPU_VENDOR_HYGON ||
758 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
760 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
761 cpu_vendor_id == CPU_VENDOR_RISE ||
762 cpu_vendor_id == CPU_VENDOR_NSC ||
763 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
766 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
767 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
768 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
770 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
771 printf("\n DIR=0x%04x", cyrix_did);
775 * AMD CPUID Specification
776 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
778 * Intel Processor Identification and CPUID Instruction
779 * http://www.intel.com/assets/pdf/appnote/241618.pdf
783 * Here we should probably set up flags indicating
784 * whether or not various features are available.
785 * The interesting ones are probably VME, PSE, PAE,
786 * and PGE. The code already assumes without bothering
787 * to check that all CPUs >= Pentium have a TSC and
790 printf("\n Features=0x%b", cpu_feature,
792 "\001FPU" /* Integral FPU */
793 "\002VME" /* Extended VM86 mode support */
794 "\003DE" /* Debugging Extensions (CR4.DE) */
795 "\004PSE" /* 4MByte page tables */
796 "\005TSC" /* Timestamp counter */
797 "\006MSR" /* Machine specific registers */
798 "\007PAE" /* Physical address extension */
799 "\010MCE" /* Machine Check support */
800 "\011CX8" /* CMPEXCH8 instruction */
801 "\012APIC" /* SMP local APIC */
802 "\013oldMTRR" /* Previous implementation of MTRR */
803 "\014SEP" /* Fast System Call */
804 "\015MTRR" /* Memory Type Range Registers */
805 "\016PGE" /* PG_G (global bit) support */
806 "\017MCA" /* Machine Check Architecture */
807 "\020CMOV" /* CMOV instruction */
808 "\021PAT" /* Page attributes table */
809 "\022PSE36" /* 36 bit address space support */
810 "\023PN" /* Processor Serial number */
811 "\024CLFLUSH" /* Has the CLFLUSH instruction */
813 "\026DTS" /* Debug Trace Store */
814 "\027ACPI" /* ACPI support */
815 "\030MMX" /* MMX instructions */
816 "\031FXSR" /* FXSAVE/FXRSTOR */
817 "\032SSE" /* Streaming SIMD Extensions */
818 "\033SSE2" /* Streaming SIMD Extensions #2 */
819 "\034SS" /* Self snoop */
820 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
821 "\036TM" /* Thermal Monitor clock slowdown */
822 "\037IA64" /* CPU can execute IA64 instructions */
823 "\040PBE" /* Pending Break Enable */
826 if (cpu_feature2 != 0) {
827 printf("\n Features2=0x%b", cpu_feature2,
829 "\001SSE3" /* SSE3 */
830 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
831 "\003DTES64" /* 64-bit Debug Trace */
832 "\004MON" /* MONITOR/MWAIT Instructions */
833 "\005DS_CPL" /* CPL Qualified Debug Store */
834 "\006VMX" /* Virtual Machine Extensions */
835 "\007SMX" /* Safer Mode Extensions */
836 "\010EST" /* Enhanced SpeedStep */
837 "\011TM2" /* Thermal Monitor 2 */
838 "\012SSSE3" /* SSSE3 */
839 "\013CNXT-ID" /* L1 context ID available */
840 "\014SDBG" /* IA32 silicon debug */
841 "\015FMA" /* Fused Multiply Add */
842 "\016CX16" /* CMPXCHG16B Instruction */
843 "\017xTPR" /* Send Task Priority Messages*/
844 "\020PDCM" /* Perf/Debug Capability MSR */
846 "\022PCID" /* Process-context Identifiers*/
847 "\023DCA" /* Direct Cache Access */
848 "\024SSE4.1" /* SSE 4.1 */
849 "\025SSE4.2" /* SSE 4.2 */
850 "\026x2APIC" /* xAPIC Extensions */
851 "\027MOVBE" /* MOVBE Instruction */
852 "\030POPCNT" /* POPCNT Instruction */
853 "\031TSCDLT" /* TSC-Deadline Timer */
854 "\032AESNI" /* AES Crypto */
855 "\033XSAVE" /* XSAVE/XRSTOR States */
856 "\034OSXSAVE" /* OS-Enabled State Management*/
857 "\035AVX" /* Advanced Vector Extensions */
858 "\036F16C" /* Half-precision conversions */
859 "\037RDRAND" /* RDRAND Instruction */
860 "\040HV" /* Hypervisor */
864 if (amd_feature != 0) {
865 printf("\n AMD Features=0x%b", amd_feature,
867 "\001<s0>" /* Same */
868 "\002<s1>" /* Same */
869 "\003<s2>" /* Same */
870 "\004<s3>" /* Same */
871 "\005<s4>" /* Same */
872 "\006<s5>" /* Same */
873 "\007<s6>" /* Same */
874 "\010<s7>" /* Same */
875 "\011<s8>" /* Same */
876 "\012<s9>" /* Same */
877 "\013<b10>" /* Undefined */
878 "\014SYSCALL" /* Have SYSCALL/SYSRET */
879 "\015<s12>" /* Same */
880 "\016<s13>" /* Same */
881 "\017<s14>" /* Same */
882 "\020<s15>" /* Same */
883 "\021<s16>" /* Same */
884 "\022<s17>" /* Same */
885 "\023<b18>" /* Reserved, unknown */
886 "\024MP" /* Multiprocessor Capable */
887 "\025NX" /* Has EFER.NXE, NX */
888 "\026<b21>" /* Undefined */
889 "\027MMX+" /* AMD MMX Extensions */
890 "\030<s23>" /* Same */
891 "\031<s24>" /* Same */
892 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
893 "\033Page1GB" /* 1-GB large page support */
894 "\034RDTSCP" /* RDTSCP */
895 "\035<b28>" /* Undefined */
896 "\036LM" /* 64 bit long mode */
897 "\0373DNow!+" /* AMD 3DNow! Extensions */
898 "\0403DNow!" /* AMD 3DNow! */
902 if (amd_feature2 != 0) {
903 printf("\n AMD Features2=0x%b", amd_feature2,
905 "\001LAHF" /* LAHF/SAHF in long mode */
906 "\002CMP" /* CMP legacy */
907 "\003SVM" /* Secure Virtual Mode */
908 "\004ExtAPIC" /* Extended APIC register */
909 "\005CR8" /* CR8 in legacy mode */
910 "\006ABM" /* LZCNT instruction */
911 "\007SSE4A" /* SSE4A */
912 "\010MAS" /* Misaligned SSE mode */
913 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
914 "\012OSVW" /* OS visible workaround */
915 "\013IBS" /* Instruction based sampling */
916 "\014XOP" /* XOP extended instructions */
917 "\015SKINIT" /* SKINIT/STGI */
918 "\016WDT" /* Watchdog timer */
920 "\020LWP" /* Lightweight Profiling */
921 "\021FMA4" /* 4-operand FMA instructions */
922 "\022TCE" /* Translation Cache Extension */
924 "\024NodeId" /* NodeId MSR support */
926 "\026TBM" /* Trailing Bit Manipulation */
927 "\027Topology" /* Topology Extensions */
928 "\030PCXC" /* Core perf count */
929 "\031PNXC" /* NB perf count */
931 "\033DBE" /* Data Breakpoint extension */
932 "\034PTSC" /* Performance TSC */
933 "\035PL2I" /* L2I perf count */
934 "\036MWAITX" /* MONITORX/MWAITX instructions */
935 "\037ADMSKX" /* Address mask extension */
940 if (cpu_stdext_feature != 0) {
941 printf("\n Structured Extended Features=0x%b",
944 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
948 /* Bit Manipulation Instructions */
950 /* Hardware Lock Elision */
952 /* Advanced Vector Instructions 2 */
954 /* FDP_EXCPTN_ONLY */
956 /* Supervisor Mode Execution Prot. */
958 /* Bit Manipulation Instructions */
961 /* Invalidate Processor Context ID */
963 /* Restricted Transactional Memory */
967 /* Intel Memory Protection Extensions */
970 /* AVX512 Foundation */
977 /* Supervisor Mode Access Prevention */
980 /* Formerly PCOMMIT */
994 if (cpu_stdext_feature2 != 0) {
995 printf("\n Structured Extended Features2=0x%b",
1011 "\017AVX512VPOPCNTDQ"
1022 if (cpu_stdext_feature3 != 0) {
1023 printf("\n Structured Extended Features3=0x%b",
1024 cpu_stdext_feature3,
1029 "\011AVX512VP2INTERSECT"
1044 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1045 cpuid_count(0xd, 0x1, regs);
1047 printf("\n XSAVE Features=0x%b",
1057 if (cpu_ia32_arch_caps != 0) {
1058 printf("\n IA32_ARCH_CAPS=0x%b",
1059 (u_int)cpu_ia32_arch_caps,
1064 "\004SKIP_L1DFL_VME"
1072 if (amd_extended_feature_extensions != 0) {
1073 u_int amd_fe_masked;
1075 amd_fe_masked = amd_extended_feature_extensions;
1076 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1078 ~(AMDFEID_IBRS_ALWAYSON |
1079 AMDFEID_PREFER_IBRS);
1080 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1082 ~AMDFEID_STIBP_ALWAYSON;
1085 "AMD Extended Feature Extensions ID EBX="
1086 "0x%b", amd_fe_masked,
1098 "\022STIBP_ALWAYSON"
1107 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1108 print_via_padlock_info();
1110 if (cpu_feature2 & CPUID2_VMX)
1113 if (amd_feature2 & AMDID2_SVM)
1116 if ((cpu_feature & CPUID_HTT) &&
1117 (cpu_vendor_id == CPU_VENDOR_AMD ||
1118 cpu_vendor_id == CPU_VENDOR_HYGON))
1119 cpu_feature &= ~CPUID_HTT;
1122 * If this CPU supports P-state invariant TSC then
1123 * mention the capability.
1125 if (tsc_is_invariant) {
1126 printf("\n TSC: P-state invariant");
1128 printf(", performance statistics");
1132 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1133 printf(" DIR=0x%04x", cyrix_did);
1134 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1135 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1136 #ifndef CYRIX_CACHE_REALLY_WORKS
1137 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1138 printf("\n CPU cache: write-through mode");
1143 /* Avoid ugly blank lines: only print newline when we have to. */
1144 if (*cpu_vendor || cpu_id)
1148 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1149 cpu_vendor_id == CPU_VENDOR_HYGON)
1151 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1154 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1155 print_transmeta_info();
1159 print_hypervisor_info();
1164 panicifcpuunsupported(void)
1168 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1169 #error This kernel is not configured for one of the supported CPUs
1174 * Now that we have told the user what they have,
1175 * let them know if that machine type isn't configured.
1177 switch (cpu_class) {
1178 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1180 #if !defined(I486_CPU)
1183 #if !defined(I586_CPU)
1186 #if !defined(I686_CPU)
1189 panic("CPU class not configured");
1195 static volatile u_int trap_by_rdmsr;
1198 * Special exception 6 handler.
1199 * The rdmsr instruction generates invalid opcodes fault on 486-class
1200 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1201 * function identblue() when this handler is called. Stacked eip should
1204 inthand_t bluetrap6;
1205 #ifdef __GNUCLIKE_ASM
1210 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1211 " __XSTRING(CNAME(bluetrap6)) ": \n\
1213 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1214 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1220 * Special exception 13 handler.
1221 * Accessing non-existent MSR generates general protection fault.
1223 inthand_t bluetrap13;
1224 #ifdef __GNUCLIKE_ASM
1229 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1230 " __XSTRING(CNAME(bluetrap13)) ": \n\
1232 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1233 popl %eax /* discard error code */ \n\
1234 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1240 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1241 * support cpuid instruction. This function should be called after
1242 * loading interrupt descriptor table register.
1244 * I don't like this method that handles fault, but I couldn't get
1245 * information for any other methods. Does blue giant know?
1254 * Cyrix 486-class CPU does not support rdmsr instruction.
1255 * The rdmsr instruction generates invalid opcode fault, and exception
1256 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1257 * bluetrap6() set the magic number to trap_by_rdmsr.
1259 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1260 GSEL(GCODE_SEL, SEL_KPL));
1263 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1264 * In this case, rdmsr generates general protection fault, and
1265 * exception will be trapped by bluetrap13().
1267 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1268 GSEL(GCODE_SEL, SEL_KPL));
1270 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1272 if (trap_by_rdmsr == 0xa8c1d)
1273 return IDENTBLUE_CYRIX486;
1274 else if (trap_by_rdmsr == 0xa89c4)
1275 return IDENTBLUE_CYRIXM2;
1276 return IDENTBLUE_IBMCPU;
1280 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1282 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1283 * +-------+-------+---------------+
1284 * | SID | RID | Device ID |
1285 * | (DIR 1) | (DIR 0) |
1286 * +-------+-------+---------------+
1291 register_t saveintr;
1292 int ccr2_test = 0, dir_test = 0;
1295 saveintr = intr_disable();
1297 ccr2 = read_cyrix_reg(CCR2);
1298 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1299 read_cyrix_reg(CCR2);
1300 if (read_cyrix_reg(CCR2) != ccr2)
1302 write_cyrix_reg(CCR2, ccr2);
1304 ccr3 = read_cyrix_reg(CCR3);
1305 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1306 read_cyrix_reg(CCR3);
1307 if (read_cyrix_reg(CCR3) != ccr3)
1308 dir_test = 1; /* CPU supports DIRs. */
1309 write_cyrix_reg(CCR3, ccr3);
1312 /* Device ID registers are available. */
1313 cyrix_did = read_cyrix_reg(DIR1) << 8;
1314 cyrix_did += read_cyrix_reg(DIR0);
1315 } else if (ccr2_test)
1316 cyrix_did = 0x0010; /* 486S A-step */
1318 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1320 intr_restore(saveintr);
1324 /* Update TSC freq with the value indicated by the caller. */
1326 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1329 /* If there was an error during the transition, don't do anything. */
1333 /* Total setting for this level gives the new frequency in MHz. */
1334 hw_clockrate = level->total_set.freq;
1338 hook_tsc_freq(void *arg __unused)
1341 if (tsc_is_invariant)
1344 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1345 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1348 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1350 static const struct {
1351 const char * vm_bname;
1354 { "QEMU", VM_GUEST_VM }, /* QEMU */
1355 { "Plex86", VM_GUEST_VM }, /* Plex86 */
1356 { "Bochs", VM_GUEST_VM }, /* Bochs */
1357 { "Xen", VM_GUEST_XEN }, /* Xen */
1358 { "BHYVE", VM_GUEST_BHYVE }, /* bhyve */
1359 { "Seabios", VM_GUEST_KVM }, /* KVM */
1362 static const struct {
1363 const char * vm_pname;
1366 { "VMware Virtual Platform", VM_GUEST_VMWARE },
1367 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */
1368 { "VirtualBox", VM_GUEST_VBOX },
1369 { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1370 { "KVM", VM_GUEST_KVM },
1374 const char *vm_cpuid;
1377 { "XENXENXEN", VM_GUEST_XEN }, /* XEN */
1378 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1379 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1380 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1381 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1382 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1386 identify_hypervisor_cpuid_base(void)
1388 u_int leaf, regs[4];
1392 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1393 * http://lkml.org/lkml/2008/10/1/246
1395 * KB1009458: Mechanisms to determine if software is running in
1396 * a VMware virtual machine
1397 * http://kb.vmware.com/kb/1009458
1399 * Search for a hypervisor that we recognize. If we cannot find
1400 * a specific hypervisor, return the first information about the
1401 * hypervisor that we found, as others may be able to use.
1403 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1404 do_cpuid(leaf, regs);
1407 * KVM from Linux kernels prior to commit
1408 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1409 * to 0 rather than a valid hv_high value. Check for
1410 * the KVM signature bytes and fixup %eax to the
1411 * highest supported leaf in that case.
1413 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1414 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1417 if (regs[0] >= leaf) {
1418 for (i = 0; i < nitems(vm_cpuids); i++)
1419 if (strncmp((const char *)®s[1],
1420 vm_cpuids[i].vm_cpuid, 12) == 0) {
1421 vm_guest = vm_cpuids[i].vm_guest;
1426 * If this is the first entry or we found a
1427 * specific hypervisor, record the base, high value,
1428 * and vendor identifier.
1430 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1433 ((u_int *)&hv_vendor)[0] = regs[1];
1434 ((u_int *)&hv_vendor)[1] = regs[2];
1435 ((u_int *)&hv_vendor)[2] = regs[3];
1436 hv_vendor[12] = '\0';
1439 * If we found a specific hypervisor, then
1442 if (vm_guest != VM_GUEST_VM)
1450 identify_hypervisor(void)
1457 * If CPUID2_HV is set, we are running in a hypervisor environment.
1459 if (cpu_feature2 & CPUID2_HV) {
1460 vm_guest = VM_GUEST_VM;
1461 identify_hypervisor_cpuid_base();
1463 /* If we have a definitive vendor, we can return now. */
1464 if (*hv_vendor != '\0')
1469 * Examine SMBIOS strings for older hypervisors.
1471 p = kern_getenv("smbios.system.serial");
1473 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1474 vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1475 if (regs[1] == VMW_HVMAGIC) {
1476 vm_guest = VM_GUEST_VMWARE;
1485 * XXX: Some of these entries may not be needed since they were
1486 * added to FreeBSD before the checks above.
1488 p = kern_getenv("smbios.bios.vendor");
1490 for (i = 0; i < nitems(vm_bnames); i++)
1491 if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1492 vm_guest = vm_bnames[i].vm_guest;
1493 /* If we have a specific match, return */
1494 if (vm_guest != VM_GUEST_VM) {
1499 * We are done with bnames, but there might be
1500 * a more specific match in the pnames
1506 p = kern_getenv("smbios.system.product");
1508 for (i = 0; i < nitems(vm_pnames); i++)
1509 if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1510 vm_guest = vm_pnames[i].vm_guest;
1524 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1525 * get the largest standard CPUID function number again if it is set
1526 * from BIOS. It is necessary for probing correct CPU topology later
1527 * and for the correct operation of the AVX-aware userspace.
1529 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1530 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1531 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1532 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1533 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1534 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1535 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1536 msr &= ~IA32_MISC_EN_LIMCPUID;
1537 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1543 * Re-enable AMD Topology Extension that could be disabled by BIOS
1544 * on some notebook processors. Without the extension it's really
1545 * hard to determine the correct CPU cache topology.
1546 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1547 * Models 60h-6Fh Processors, Publication # 50742.
1549 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1550 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1551 msr = rdmsr(MSR_EXTFEATURES);
1552 if ((msr & ((uint64_t)1 << 54)) == 0) {
1553 msr |= (uint64_t)1 << 54;
1554 wrmsr(MSR_EXTFEATURES, msr);
1568 ((u_int *)&cpu_vendor)[0] = regs[1];
1569 ((u_int *)&cpu_vendor)[1] = regs[3];
1570 ((u_int *)&cpu_vendor)[2] = regs[2];
1571 cpu_vendor[12] = '\0';
1575 cpu_procinfo = regs[1];
1576 cpu_feature = regs[3];
1577 cpu_feature2 = regs[2];
1583 u_int regs[4], cpu_stdext_disable;
1585 if (cpu_high >= 6) {
1586 cpuid_count(6, 0, regs);
1587 cpu_power_eax = regs[0];
1588 cpu_power_ebx = regs[1];
1589 cpu_power_ecx = regs[2];
1590 cpu_power_edx = regs[3];
1593 if (cpu_high >= 7) {
1594 cpuid_count(7, 0, regs);
1595 cpu_stdext_feature = regs[1];
1598 * Some hypervisors failed to filter out unsupported
1599 * extended features. Allow to disable the
1600 * extensions, activation of which requires setting a
1601 * bit in CR4, and which VM monitors do not support.
1603 cpu_stdext_disable = 0;
1604 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1605 cpu_stdext_feature &= ~cpu_stdext_disable;
1607 cpu_stdext_feature2 = regs[2];
1608 cpu_stdext_feature3 = regs[3];
1610 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1611 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1616 identify_cpu_fixup_bsp(void)
1620 cpu_vendor_id = find_cpu_vendor_id();
1629 * Final stage of CPU identification.
1632 finishidentcpu(void)
1639 identify_cpu_fixup_bsp();
1641 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1643 cpu_mon_mwait_flags = regs[2];
1644 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1645 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1652 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1653 cpu_vendor_id == CPU_VENDOR_AMD ||
1654 cpu_vendor_id == CPU_VENDOR_HYGON ||
1655 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1656 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1657 cpu_vendor_id == CPU_VENDOR_NSC)) {
1658 do_cpuid(0x80000000, regs);
1659 if (regs[0] >= 0x80000000)
1660 cpu_exthigh = regs[0];
1663 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1664 cpu_vendor_id == CPU_VENDOR_AMD ||
1665 cpu_vendor_id == CPU_VENDOR_HYGON ||
1666 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1667 do_cpuid(0x80000000, regs);
1668 cpu_exthigh = regs[0];
1671 if (cpu_exthigh >= 0x80000001) {
1672 do_cpuid(0x80000001, regs);
1673 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1674 amd_feature2 = regs[2];
1676 if (cpu_exthigh >= 0x80000007) {
1677 do_cpuid(0x80000007, regs);
1678 amd_rascap = regs[1];
1679 amd_pminfo = regs[3];
1681 if (cpu_exthigh >= 0x80000008) {
1682 do_cpuid(0x80000008, regs);
1683 cpu_maxphyaddr = regs[0] & 0xff;
1684 amd_extended_feature_extensions = regs[1];
1685 cpu_procinfo2 = regs[2];
1687 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1691 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1692 if (cpu == CPU_486) {
1694 * These conditions are equivalent to:
1695 * - CPU does not support cpuid instruction.
1696 * - Cyrix/IBM CPU is detected.
1698 if (identblue() == IDENTBLUE_IBMCPU) {
1699 strcpy(cpu_vendor, "IBM");
1700 cpu_vendor_id = CPU_VENDOR_IBM;
1705 switch (cpu_id & 0xf00) {
1708 * Cyrix's datasheet does not describe DIRs.
1709 * Therefor, I assume it does not have them
1710 * and use the result of the cpuid instruction.
1711 * XXX they seem to have it for now at least. -Peter
1719 * This routine contains a trick.
1720 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1722 switch (cyrix_did & 0x00f0) {
1731 if ((cyrix_did & 0x000f) < 8)
1744 /* M2 and later CPUs are treated as M2. */
1748 * enable cpuid instruction.
1750 ccr3 = read_cyrix_reg(CCR3);
1751 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1752 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1753 write_cyrix_reg(CCR3, ccr3);
1756 cpu_high = regs[0]; /* eax */
1758 cpu_id = regs[0]; /* eax */
1759 cpu_feature = regs[3]; /* edx */
1763 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1765 * There are BlueLightning CPUs that do not change
1766 * undefined flags by dividing 5 by 2. In this case,
1767 * the CPU identification routine in locore.s leaves
1768 * cpu_vendor null string and puts CPU_486 into the
1771 if (identblue() == IDENTBLUE_IBMCPU) {
1772 strcpy(cpu_vendor, "IBM");
1773 cpu_vendor_id = CPU_VENDOR_IBM;
1782 pti_get_default(void)
1785 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1786 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1788 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1794 find_cpu_vendor_id(void)
1798 for (i = 0; i < nitems(cpu_vendors); i++)
1799 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1800 return (cpu_vendors[i].vendor_id);
1805 print_AMD_assoc(int i)
1808 printf(", fully associative\n");
1810 printf(", %d-way associative\n", i);
1814 print_AMD_l2_assoc(int i)
1817 case 0: printf(", disabled/not present\n"); break;
1818 case 1: printf(", direct mapped\n"); break;
1819 case 2: printf(", 2-way associative\n"); break;
1820 case 4: printf(", 4-way associative\n"); break;
1821 case 6: printf(", 8-way associative\n"); break;
1822 case 8: printf(", 16-way associative\n"); break;
1823 case 15: printf(", fully associative\n"); break;
1824 default: printf(", reserved configuration\n"); break;
1829 print_AMD_info(void)
1836 if (cpu_exthigh >= 0x80000005) {
1837 do_cpuid(0x80000005, regs);
1838 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1839 print_AMD_assoc(regs[0] >> 24);
1841 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1842 print_AMD_assoc((regs[0] >> 8) & 0xff);
1844 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1845 print_AMD_assoc(regs[1] >> 24);
1847 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1848 print_AMD_assoc((regs[1] >> 8) & 0xff);
1850 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1851 printf(", %d bytes/line", regs[2] & 0xff);
1852 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1853 print_AMD_assoc((regs[2] >> 16) & 0xff);
1855 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1856 printf(", %d bytes/line", regs[3] & 0xff);
1857 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1858 print_AMD_assoc((regs[3] >> 16) & 0xff);
1861 if (cpu_exthigh >= 0x80000006) {
1862 do_cpuid(0x80000006, regs);
1863 if ((regs[0] >> 16) != 0) {
1864 printf("L2 2MB data TLB: %d entries",
1865 (regs[0] >> 16) & 0xfff);
1866 print_AMD_l2_assoc(regs[0] >> 28);
1867 printf("L2 2MB instruction TLB: %d entries",
1869 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1871 printf("L2 2MB unified TLB: %d entries",
1873 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1875 if ((regs[1] >> 16) != 0) {
1876 printf("L2 4KB data TLB: %d entries",
1877 (regs[1] >> 16) & 0xfff);
1878 print_AMD_l2_assoc(regs[1] >> 28);
1880 printf("L2 4KB instruction TLB: %d entries",
1881 (regs[1] >> 16) & 0xfff);
1882 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1884 printf("L2 4KB unified TLB: %d entries",
1885 (regs[1] >> 16) & 0xfff);
1886 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1888 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1889 printf(", %d bytes/line", regs[2] & 0xff);
1890 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1891 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1895 if (((cpu_id & 0xf00) == 0x500)
1896 && (((cpu_id & 0x0f0) > 0x80)
1897 || (((cpu_id & 0x0f0) == 0x80)
1898 && (cpu_id & 0x00f) > 0x07))) {
1899 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1900 amd_whcr = rdmsr(0xc0000082);
1901 if (!(amd_whcr & (0x3ff << 22))) {
1902 printf("Write Allocate Disable\n");
1904 printf("Write Allocate Enable Limit: %dM bytes\n",
1905 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1906 printf("Write Allocate 15-16M bytes: %s\n",
1907 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1909 } else if (((cpu_id & 0xf00) == 0x500)
1910 && ((cpu_id & 0x0f0) > 0x50)) {
1911 /* K6, K6-2(old core) */
1912 amd_whcr = rdmsr(0xc0000082);
1913 if (!(amd_whcr & (0x7f << 1))) {
1914 printf("Write Allocate Disable\n");
1916 printf("Write Allocate Enable Limit: %dM bytes\n",
1917 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1918 printf("Write Allocate 15-16M bytes: %s\n",
1919 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1920 printf("Hardware Write Allocate Control: %s\n",
1921 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1926 * Opteron Rev E shows a bug as in very rare occasions a read memory
1927 * barrier is not performed as expected if it is followed by a
1928 * non-atomic read-modify-write instruction.
1929 * As long as that bug pops up very rarely (intensive machine usage
1930 * on other operating systems generally generates one unexplainable
1931 * crash any 2 months) and as long as a model specific fix would be
1932 * impractical at this stage, print out a warning string if the broken
1933 * model and family are identified.
1935 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1936 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1937 printf("WARNING: This architecture revision has known SMP "
1938 "hardware bugs which may cause random instability\n");
1942 print_INTEL_info(void)
1945 u_int rounds, regnum;
1946 u_int nwaycode, nway;
1948 if (cpu_high >= 2) {
1951 do_cpuid(0x2, regs);
1952 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1953 break; /* we have a buggy CPU */
1955 for (regnum = 0; regnum <= 3; ++regnum) {
1956 if (regs[regnum] & (1<<31))
1959 print_INTEL_TLB(regs[regnum] & 0xff);
1960 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1961 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1962 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1964 } while (--rounds > 0);
1967 if (cpu_exthigh >= 0x80000006) {
1968 do_cpuid(0x80000006, regs);
1969 nwaycode = (regs[2] >> 12) & 0x0f;
1970 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1971 nway = 1 << (nwaycode / 2);
1974 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1975 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1980 print_INTEL_TLB(u_int data)
1988 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1991 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1994 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1997 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
2000 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2003 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2006 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2009 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2012 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2015 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2018 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2021 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2024 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2027 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2030 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2033 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2036 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2039 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2042 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2045 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2048 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2050 case 0x39: /* De-listed in SDM rev. 54 */
2051 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2053 case 0x3b: /* De-listed in SDM rev. 54 */
2054 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2056 case 0x3c: /* De-listed in SDM rev. 54 */
2057 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2060 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2063 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2066 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2069 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2072 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2075 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2078 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2081 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2084 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2085 CPUID_TO_MODEL(cpu_id) == 0x6)
2086 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2088 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2091 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2094 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2097 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2100 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2103 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2106 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2109 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2112 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2115 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2118 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2121 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2124 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2127 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2130 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2133 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2136 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2139 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2142 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2145 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2148 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2151 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2154 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2157 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2160 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2163 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2166 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2169 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2172 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2175 printf("Trace cache: 12K-uops, 8-way set associative\n");
2178 printf("Trace cache: 16K-uops, 8-way set associative\n");
2181 printf("Trace cache: 32K-uops, 8-way set associative\n");
2184 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2187 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2190 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2193 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2196 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2199 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2202 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2205 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2208 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2211 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2214 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2217 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2220 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2223 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2226 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2229 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2232 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2235 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2238 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2241 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2244 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2247 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2250 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2253 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2256 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2259 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2262 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2265 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2268 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2271 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2274 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2277 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2280 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2283 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2286 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2289 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2292 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2295 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2298 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2301 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2304 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2307 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2310 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2313 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2316 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2319 printf("64-Byte prefetching\n");
2322 printf("128-Byte prefetching\n");
2328 print_svm_info(void)
2330 u_int features, regs[4];
2335 do_cpuid(0x8000000A, regs);
2338 msr = rdmsr(MSR_VM_CR);
2339 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2340 printf("(disabled in BIOS) ");
2344 if (features & (1 << 0)) {
2345 printf("%sNP", comma ? "," : "");
2348 if (features & (1 << 3)) {
2349 printf("%sNRIP", comma ? "," : "");
2352 if (features & (1 << 5)) {
2353 printf("%sVClean", comma ? "," : "");
2356 if (features & (1 << 6)) {
2357 printf("%sAFlush", comma ? "," : "");
2360 if (features & (1 << 7)) {
2361 printf("%sDAssist", comma ? "," : "");
2364 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2368 printf("Features=0x%b", features,
2370 "\001NP" /* Nested paging */
2371 "\002LbrVirt" /* LBR virtualization */
2372 "\003SVML" /* SVM lock */
2373 "\004NRIPS" /* NRIP save */
2374 "\005TscRateMsr" /* MSR based TSC rate control */
2375 "\006VmcbClean" /* VMCB clean bits */
2376 "\007FlushByAsid" /* Flush by ASID */
2377 "\010DecodeAssist" /* Decode assist */
2380 "\013PauseFilter" /* PAUSE intercept filter */
2381 "\014EncryptedMcodePatch"
2382 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2383 "\016AVIC" /* virtual interrupt controller */
2385 "\020V_VMSAVE_VMLOAD"
2387 "\022GMET" /* Guest Mode Execute Trap */
2390 "\025GuesSpecCtl" /* Guest Spec_ctl */
2403 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2408 print_transmeta_info(void)
2410 u_int regs[4], nreg = 0;
2412 do_cpuid(0x80860000, regs);
2414 if (nreg >= 0x80860001) {
2415 do_cpuid(0x80860001, regs);
2416 printf(" Processor revision %u.%u.%u.%u\n",
2417 (regs[1] >> 24) & 0xff,
2418 (regs[1] >> 16) & 0xff,
2419 (regs[1] >> 8) & 0xff,
2422 if (nreg >= 0x80860002) {
2423 do_cpuid(0x80860002, regs);
2424 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2425 (regs[1] >> 24) & 0xff,
2426 (regs[1] >> 16) & 0xff,
2427 (regs[1] >> 8) & 0xff,
2431 if (nreg >= 0x80860006) {
2433 do_cpuid(0x80860003, (u_int*) &info[0]);
2434 do_cpuid(0x80860004, (u_int*) &info[16]);
2435 do_cpuid(0x80860005, (u_int*) &info[32]);
2436 do_cpuid(0x80860006, (u_int*) &info[48]);
2438 printf(" %s\n", info);
2444 print_via_padlock_info(void)
2448 do_cpuid(0xc0000001, regs);
2449 printf("\n VIA Padlock Features=0x%b", regs[3],
2453 "\011AES-CTR" /* ACE2 */
2454 "\013SHA1,SHA256" /* PHE */
2460 vmx_settable(uint64_t basic, int msr, int true_msr)
2464 if (basic & (1ULL << 55))
2465 val = rdmsr(true_msr);
2469 /* Just report the controls that can be set to 1. */
2474 print_vmx_info(void)
2476 uint64_t basic, msr;
2477 uint32_t entry, exit, mask, pin, proc, proc2;
2480 printf("\n VT-x: ");
2481 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2482 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2483 printf("(disabled in BIOS) ");
2484 basic = rdmsr(MSR_VMX_BASIC);
2485 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2486 MSR_VMX_TRUE_PINBASED_CTLS);
2487 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2488 MSR_VMX_TRUE_PROCBASED_CTLS);
2489 if (proc & PROCBASED_SECONDARY_CONTROLS)
2490 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2491 MSR_VMX_PROCBASED_CTLS2);
2494 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2495 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2499 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2500 entry & VM_ENTRY_LOAD_PAT) {
2501 printf("%sPAT", comma ? "," : "");
2504 if (proc & PROCBASED_HLT_EXITING) {
2505 printf("%sHLT", comma ? "," : "");
2508 if (proc & PROCBASED_MTF) {
2509 printf("%sMTF", comma ? "," : "");
2512 if (proc & PROCBASED_PAUSE_EXITING) {
2513 printf("%sPAUSE", comma ? "," : "");
2516 if (proc2 & PROCBASED2_ENABLE_EPT) {
2517 printf("%sEPT", comma ? "," : "");
2520 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2521 printf("%sUG", comma ? "," : "");
2524 if (proc2 & PROCBASED2_ENABLE_VPID) {
2525 printf("%sVPID", comma ? "," : "");
2528 if (proc & PROCBASED_USE_TPR_SHADOW &&
2529 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2530 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2531 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2532 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2533 printf("%sVID", comma ? "," : "");
2535 if (pin & PINBASED_POSTED_INTERRUPT)
2536 printf(",PostIntr");
2542 printf("Basic Features=0x%b", mask,
2544 "\02132PA" /* 32-bit physical addresses */
2545 "\022SMM" /* SMM dual-monitor */
2546 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2547 "\030TRUE" /* TRUE_CTLS MSRs */
2549 printf("\n Pin-Based Controls=0x%b", pin,
2551 "\001ExtINT" /* External-interrupt exiting */
2552 "\004NMI" /* NMI exiting */
2553 "\006VNMI" /* Virtual NMIs */
2554 "\007PreTmr" /* Activate VMX-preemption timer */
2555 "\010PostIntr" /* Process posted interrupts */
2557 printf("\n Primary Processor Controls=0x%b", proc,
2559 "\003INTWIN" /* Interrupt-window exiting */
2560 "\004TSCOff" /* Use TSC offsetting */
2561 "\010HLT" /* HLT exiting */
2562 "\012INVLPG" /* INVLPG exiting */
2563 "\013MWAIT" /* MWAIT exiting */
2564 "\014RDPMC" /* RDPMC exiting */
2565 "\015RDTSC" /* RDTSC exiting */
2566 "\020CR3-LD" /* CR3-load exiting */
2567 "\021CR3-ST" /* CR3-store exiting */
2568 "\024CR8-LD" /* CR8-load exiting */
2569 "\025CR8-ST" /* CR8-store exiting */
2570 "\026TPR" /* Use TPR shadow */
2571 "\027NMIWIN" /* NMI-window exiting */
2572 "\030MOV-DR" /* MOV-DR exiting */
2573 "\031IO" /* Unconditional I/O exiting */
2574 "\032IOmap" /* Use I/O bitmaps */
2575 "\034MTF" /* Monitor trap flag */
2576 "\035MSRmap" /* Use MSR bitmaps */
2577 "\036MONITOR" /* MONITOR exiting */
2578 "\037PAUSE" /* PAUSE exiting */
2580 if (proc & PROCBASED_SECONDARY_CONTROLS)
2581 printf("\n Secondary Processor Controls=0x%b", proc2,
2583 "\001APIC" /* Virtualize APIC accesses */
2584 "\002EPT" /* Enable EPT */
2585 "\003DT" /* Descriptor-table exiting */
2586 "\004RDTSCP" /* Enable RDTSCP */
2587 "\005x2APIC" /* Virtualize x2APIC mode */
2588 "\006VPID" /* Enable VPID */
2589 "\007WBINVD" /* WBINVD exiting */
2590 "\010UG" /* Unrestricted guest */
2591 "\011APIC-reg" /* APIC-register virtualization */
2592 "\012VID" /* Virtual-interrupt delivery */
2593 "\013PAUSE-loop" /* PAUSE-loop exiting */
2594 "\014RDRAND" /* RDRAND exiting */
2595 "\015INVPCID" /* Enable INVPCID */
2596 "\016VMFUNC" /* Enable VM functions */
2597 "\017VMCS" /* VMCS shadowing */
2598 "\020EPT#VE" /* EPT-violation #VE */
2599 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2601 printf("\n Exit Controls=0x%b", mask,
2603 "\003DR" /* Save debug controls */
2604 /* Ignore Host address-space size */
2605 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2606 "\020AckInt" /* Acknowledge interrupt on exit */
2607 "\023PAT-SV" /* Save MSR_PAT */
2608 "\024PAT-LD" /* Load MSR_PAT */
2609 "\025EFER-SV" /* Save MSR_EFER */
2610 "\026EFER-LD" /* Load MSR_EFER */
2611 "\027PTMR-SV" /* Save VMX-preemption timer value */
2613 printf("\n Entry Controls=0x%b", mask,
2615 "\003DR" /* Save debug controls */
2616 /* Ignore IA-32e mode guest */
2617 /* Ignore Entry to SMM */
2618 /* Ignore Deactivate dual-monitor treatment */
2619 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2620 "\017PAT" /* Load MSR_PAT */
2621 "\020EFER" /* Load MSR_EFER */
2623 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2624 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2625 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2627 printf("\n EPT Features=0x%b", mask,
2629 "\001XO" /* Execute-only translations */
2630 "\007PW4" /* Page-walk length of 4 */
2631 "\011UC" /* EPT paging-structure mem can be UC */
2632 "\017WB" /* EPT paging-structure mem can be WB */
2633 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2634 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2635 "\025INVEPT" /* INVEPT is supported */
2636 "\026AD" /* Accessed and dirty flags for EPT */
2637 "\032single" /* INVEPT single-context type */
2638 "\033all" /* INVEPT all-context type */
2641 printf("\n VPID Features=0x%b", mask,
2643 "\001INVVPID" /* INVVPID is supported */
2644 "\011individual" /* INVVPID individual-address type */
2645 "\012single" /* INVVPID single-context type */
2646 "\013all" /* INVVPID all-context type */
2647 /* INVVPID single-context-retaining-globals type */
2648 "\014single-globals"
2654 print_hypervisor_info(void)
2657 if (*hv_vendor != '\0')
2658 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2662 * Returns the maximum physical address that can be used with the
2666 cpu_getmaxphyaddr(void)
2669 #if defined(__i386__)
2671 return (0xffffffff);
2673 return ((1ULL << cpu_maxphyaddr) - 1);