sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   amd_extended_feature_extensions;
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 u_int   cpu_fxsr;               /* SSE enabled */
 107 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 108 u_int   cpu_clflush_line_size = 32;
 109 u_int   cpu_stdext_feature;
 110 u_int   cpu_stdext_feature2;
 111 u_int   cpu_max_ext_state_size;
 112 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 113 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 114 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 115 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 116 char machine[] = MACHINE;
 117
 118 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 119     &via_feature_rng, 0,
 120     "VIA RNG feature available in CPU");
 121 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 122     &via_feature_xcrypt, 0,
 123     "VIA xcrypt feature available in CPU");
 124
 125 #ifdef __amd64__
 126 #ifdef SCTL_MASK32
 127 extern int adaptive_machine_arch;
 128 #endif
 129
 130 static int
 131 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 132 {
 133 #ifdef SCTL_MASK32
 134         static const char machine32[] = "i386";
 135 #endif
 136         int error;
 137
 138 #ifdef SCTL_MASK32
 139         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 140                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 141         else
 142 #endif
 143                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 144         return (error);
 145
 146 }
 147 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 148     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 149 #else
 150 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 151     machine, 0, "Machine class");
 152 #endif
 153
 154 static char cpu_model[128];
 155 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 156     cpu_model, 0, "Machine model");
 157
 158 static int hw_clockrate;
 159 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 160     &hw_clockrate, 0, "CPU instruction clock rate");
 161
 162 u_int hv_high;
 163 char hv_vendor[16];
 164 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 165     0, "Hypervisor vendor");
 166
 167 static eventhandler_tag tsc_post_tag;
 168
 169 static char cpu_brand[48];
 170
 171 #ifdef __i386__
 172 #define MAX_BRAND_INDEX 8
 173
 174 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 175         NULL,                   /* No brand */
 176         "Intel Celeron",
 177         "Intel Pentium III",
 178         "Intel Pentium III Xeon",
 179         NULL,
 180         NULL,
 181         NULL,
 182         NULL,
 183         "Intel Pentium 4"
 184 };
 185
 186 static struct {
 187         char    *cpu_name;
 188         int     cpu_class;
 189 } cpus[] = {
 190         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 191         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 192         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 193         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 194         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 195         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 196         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 197         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 198         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 199         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 200         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 201         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 202         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 203         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 204         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 205         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 206         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 207 };
 208 #endif
 209
 210 static struct {
 211         char    *vendor;
 212         u_int   vendor_id;
 213 } cpu_vendors[] = {
 214         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 215         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 216         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 217 #ifdef __i386__
 218         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 219         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 220         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 221         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 222         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 223         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 224         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 225 #if 0
 226         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 227         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 228 #endif
 229 #endif
 230 };
 231
 232 void
 233 printcpuinfo(void)
 234 {
 235         u_int regs[4], i;
 236         char *brand;
 237
 238         printf("CPU: ");
 239 #ifdef __i386__
 240         cpu_class = cpus[cpu].cpu_class;
 241         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 242 #else
 243         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 244 #endif
 245
 246         /* Check for extended CPUID information and a processor name. */
 247         if (cpu_exthigh >= 0x80000004) {
 248                 brand = cpu_brand;
 249                 for (i = 0x80000002; i < 0x80000005; i++) {
 250                         do_cpuid(i, regs);
 251                         memcpy(brand, regs, sizeof(regs));
 252                         brand += sizeof(regs);
 253                 }
 254         }
 255
 256         switch (cpu_vendor_id) {
 257         case CPU_VENDOR_INTEL:
 258 #ifdef __i386__
 259                 if ((cpu_id & 0xf00) > 0x300) {
 260                         u_int brand_index;
 261
 262                         cpu_model[0] = '\0';
 263
 264                         switch (cpu_id & 0x3000) {
 265                         case 0x1000:
 266                                 strcpy(cpu_model, "Overdrive ");
 267                                 break;
 268                         case 0x2000:
 269                                 strcpy(cpu_model, "Dual ");
 270                                 break;
 271                         }
 272
 273                         switch (cpu_id & 0xf00) {
 274                         case 0x400:
 275                                 strcat(cpu_model, "i486 ");
 276                                 /* Check the particular flavor of 486 */
 277                                 switch (cpu_id & 0xf0) {
 278                                 case 0x00:
 279                                 case 0x10:
 280                                         strcat(cpu_model, "DX");
 281                                         break;
 282                                 case 0x20:
 283                                         strcat(cpu_model, "SX");
 284                                         break;
 285                                 case 0x30:
 286                                         strcat(cpu_model, "DX2");
 287                                         break;
 288                                 case 0x40:
 289                                         strcat(cpu_model, "SL");
 290                                         break;
 291                                 case 0x50:
 292                                         strcat(cpu_model, "SX2");
 293                                         break;
 294                                 case 0x70:
 295                                         strcat(cpu_model,
 296                                             "DX2 Write-Back Enhanced");
 297                                         break;
 298                                 case 0x80:
 299                                         strcat(cpu_model, "DX4");
 300                                         break;
 301                                 }
 302                                 break;
 303                         case 0x500:
 304                                 /* Check the particular flavor of 586 */
 305                                 strcat(cpu_model, "Pentium");
 306                                 switch (cpu_id & 0xf0) {
 307                                 case 0x00:
 308                                         strcat(cpu_model, " A-step");
 309                                         break;
 310                                 case 0x10:
 311                                         strcat(cpu_model, "/P5");
 312                                         break;
 313                                 case 0x20:
 314                                         strcat(cpu_model, "/P54C");
 315                                         break;
 316                                 case 0x30:
 317                                         strcat(cpu_model, "/P24T");
 318                                         break;
 319                                 case 0x40:
 320                                         strcat(cpu_model, "/P55C");
 321                                         break;
 322                                 case 0x70:
 323                                         strcat(cpu_model, "/P54C");
 324                                         break;
 325                                 case 0x80:
 326                                         strcat(cpu_model, "/P55C (quarter-micron)");
 327                                         break;
 328                                 default:
 329                                         /* nothing */
 330                                         break;
 331                                 }
 332 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 333                                 /*
 334                                  * XXX - If/when Intel fixes the bug, this
 335                                  * should also check the version of the
 336                                  * CPU, not just that it's a Pentium.
 337                                  */
 338                                 has_f00f_bug = 1;
 339 #endif
 340                                 break;
 341                         case 0x600:
 342                                 /* Check the particular flavor of 686 */
 343                                 switch (cpu_id & 0xf0) {
 344                                 case 0x00:
 345                                         strcat(cpu_model, "Pentium Pro A-step");
 346                                         break;
 347                                 case 0x10:
 348                                         strcat(cpu_model, "Pentium Pro");
 349                                         break;
 350                                 case 0x30:
 351                                 case 0x50:
 352                                 case 0x60:
 353                                         strcat(cpu_model,
 354                                 "Pentium II/Pentium II Xeon/Celeron");
 355                                         cpu = CPU_PII;
 356                                         break;
 357                                 case 0x70:
 358                                 case 0x80:
 359                                 case 0xa0:
 360                                 case 0xb0:
 361                                         strcat(cpu_model,
 362                                         "Pentium III/Pentium III Xeon/Celeron");
 363                                         cpu = CPU_PIII;
 364                                         break;
 365                                 default:
 366                                         strcat(cpu_model, "Unknown 80686");
 367                                         break;
 368                                 }
 369                                 break;
 370                         case 0xf00:
 371                                 strcat(cpu_model, "Pentium 4");
 372                                 cpu = CPU_P4;
 373                                 break;
 374                         default:
 375                                 strcat(cpu_model, "unknown");
 376                                 break;
 377                         }
 378
 379                         /*
 380                          * If we didn't get a brand name from the extended
 381                          * CPUID, try to look it up in the brand table.
 382                          */
 383                         if (cpu_high > 0 && *cpu_brand == '\0') {
 384                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 385                                 if (brand_index <= MAX_BRAND_INDEX &&
 386                                     cpu_brandtable[brand_index] != NULL)
 387                                         strcpy(cpu_brand,
 388                                             cpu_brandtable[brand_index]);
 389                         }
 390                 }
 391 #else
 392                 /* Please make up your mind folks! */
 393                 strcat(cpu_model, "EM64T");
 394 #endif
 395                 break;
 396         case CPU_VENDOR_AMD:
 397                 /*
 398                  * Values taken from AMD Processor Recognition
 399                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 400                  * (also describes ``Features'' encodings.
 401                  */
 402                 strcpy(cpu_model, "AMD ");
 403 #ifdef __i386__
 404                 switch (cpu_id & 0xFF0) {
 405                 case 0x410:
 406                         strcat(cpu_model, "Standard Am486DX");
 407                         break;
 408                 case 0x430:
 409                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 410                         break;
 411                 case 0x470:
 412                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 413                         break;
 414                 case 0x480:
 415                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 416                         break;
 417                 case 0x490:
 418                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 419                         break;
 420                 case 0x4E0:
 421                         strcat(cpu_model, "Am5x86 Write-Through");
 422                         break;
 423                 case 0x4F0:
 424                         strcat(cpu_model, "Am5x86 Write-Back");
 425                         break;
 426                 case 0x500:
 427                         strcat(cpu_model, "K5 model 0");
 428                         break;
 429                 case 0x510:
 430                         strcat(cpu_model, "K5 model 1");
 431                         break;
 432                 case 0x520:
 433                         strcat(cpu_model, "K5 PR166 (model 2)");
 434                         break;
 435                 case 0x530:
 436                         strcat(cpu_model, "K5 PR200 (model 3)");
 437                         break;
 438                 case 0x560:
 439                         strcat(cpu_model, "K6");
 440                         break;
 441                 case 0x570:
 442                         strcat(cpu_model, "K6 266 (model 1)");
 443                         break;
 444                 case 0x580:
 445                         strcat(cpu_model, "K6-2");
 446                         break;
 447                 case 0x590:
 448                         strcat(cpu_model, "K6-III");
 449                         break;
 450                 case 0x5a0:
 451                         strcat(cpu_model, "Geode LX");
 452                         break;
 453                 default:
 454                         strcat(cpu_model, "Unknown");
 455                         break;
 456                 }
 457 #else
 458                 if ((cpu_id & 0xf00) == 0xf00)
 459                         strcat(cpu_model, "AMD64 Processor");
 460                 else
 461                         strcat(cpu_model, "Unknown");
 462 #endif
 463                 break;
 464 #ifdef __i386__
 465         case CPU_VENDOR_CYRIX:
 466                 strcpy(cpu_model, "Cyrix ");
 467                 switch (cpu_id & 0xff0) {
 468                 case 0x440:
 469                         strcat(cpu_model, "MediaGX");
 470                         break;
 471                 case 0x520:
 472                         strcat(cpu_model, "6x86");
 473                         break;
 474                 case 0x540:
 475                         cpu_class = CPUCLASS_586;
 476                         strcat(cpu_model, "GXm");
 477                         break;
 478                 case 0x600:
 479                         strcat(cpu_model, "6x86MX");
 480                         break;
 481                 default:
 482                         /*
 483                          * Even though CPU supports the cpuid
 484                          * instruction, it can be disabled.
 485                          * Therefore, this routine supports all Cyrix
 486                          * CPUs.
 487                          */
 488                         switch (cyrix_did & 0xf0) {
 489                         case 0x00:
 490                                 switch (cyrix_did & 0x0f) {
 491                                 case 0x00:
 492                                         strcat(cpu_model, "486SLC");
 493                                         break;
 494                                 case 0x01:
 495                                         strcat(cpu_model, "486DLC");
 496                                         break;
 497                                 case 0x02:
 498                                         strcat(cpu_model, "486SLC2");
 499                                         break;
 500                                 case 0x03:
 501                                         strcat(cpu_model, "486DLC2");
 502                                         break;
 503                                 case 0x04:
 504                                         strcat(cpu_model, "486SRx");
 505                                         break;
 506                                 case 0x05:
 507                                         strcat(cpu_model, "486DRx");
 508                                         break;
 509                                 case 0x06:
 510                                         strcat(cpu_model, "486SRx2");
 511                                         break;
 512                                 case 0x07:
 513                                         strcat(cpu_model, "486DRx2");
 514                                         break;
 515                                 case 0x08:
 516                                         strcat(cpu_model, "486SRu");
 517                                         break;
 518                                 case 0x09:
 519                                         strcat(cpu_model, "486DRu");
 520                                         break;
 521                                 case 0x0a:
 522                                         strcat(cpu_model, "486SRu2");
 523                                         break;
 524                                 case 0x0b:
 525                                         strcat(cpu_model, "486DRu2");
 526                                         break;
 527                                 default:
 528                                         strcat(cpu_model, "Unknown");
 529                                         break;
 530                                 }
 531                                 break;
 532                         case 0x10:
 533                                 switch (cyrix_did & 0x0f) {
 534                                 case 0x00:
 535                                         strcat(cpu_model, "486S");
 536                                         break;
 537                                 case 0x01:
 538                                         strcat(cpu_model, "486S2");
 539                                         break;
 540                                 case 0x02:
 541                                         strcat(cpu_model, "486Se");
 542                                         break;
 543                                 case 0x03:
 544                                         strcat(cpu_model, "486S2e");
 545                                         break;
 546                                 case 0x0a:
 547                                         strcat(cpu_model, "486DX");
 548                                         break;
 549                                 case 0x0b:
 550                                         strcat(cpu_model, "486DX2");
 551                                         break;
 552                                 case 0x0f:
 553                                         strcat(cpu_model, "486DX4");
 554                                         break;
 555                                 default:
 556                                         strcat(cpu_model, "Unknown");
 557                                         break;
 558                                 }
 559                                 break;
 560                         case 0x20:
 561                                 if ((cyrix_did & 0x0f) < 8)
 562                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 563                                 else
 564                                         strcat(cpu_model, "5x86");
 565                                 break;
 566                         case 0x30:
 567                                 strcat(cpu_model, "6x86");
 568                                 break;
 569                         case 0x40:
 570                                 if ((cyrix_did & 0xf000) == 0x3000) {
 571                                         cpu_class = CPUCLASS_586;
 572                                         strcat(cpu_model, "GXm");
 573                                 } else
 574                                         strcat(cpu_model, "MediaGX");
 575                                 break;
 576                         case 0x50:
 577                                 strcat(cpu_model, "6x86MX");
 578                                 break;
 579                         case 0xf0:
 580                                 switch (cyrix_did & 0x0f) {
 581                                 case 0x0d:
 582                                         strcat(cpu_model, "Overdrive CPU");
 583                                         break;
 584                                 case 0x0e:
 585                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 586                                         break;
 587                                 case 0x0f:
 588                                         strcat(cpu_model, "486SLC/DLC");
 589                                         break;
 590                                 default:
 591                                         strcat(cpu_model, "Unknown");
 592                                         break;
 593                                 }
 594                                 break;
 595                         default:
 596                                 strcat(cpu_model, "Unknown");
 597                                 break;
 598                         }
 599                         break;
 600                 }
 601                 break;
 602         case CPU_VENDOR_RISE:
 603                 strcpy(cpu_model, "Rise ");
 604                 switch (cpu_id & 0xff0) {
 605                 case 0x500:     /* 6401 and 6441 (Kirin) */
 606                 case 0x520:     /* 6510 (Lynx) */
 607                         strcat(cpu_model, "mP6");
 608                         break;
 609                 default:
 610                         strcat(cpu_model, "Unknown");
 611                 }
 612                 break;
 613 #endif
 614         case CPU_VENDOR_CENTAUR:
 615 #ifdef __i386__
 616                 switch (cpu_id & 0xff0) {
 617                 case 0x540:
 618                         strcpy(cpu_model, "IDT WinChip C6");
 619                         break;
 620                 case 0x580:
 621                         strcpy(cpu_model, "IDT WinChip 2");
 622                         break;
 623                 case 0x590:
 624                         strcpy(cpu_model, "IDT WinChip 3");
 625                         break;
 626                 case 0x660:
 627                         strcpy(cpu_model, "VIA C3 Samuel");
 628                         break;
 629                 case 0x670:
 630                         if (cpu_id & 0x8)
 631                                 strcpy(cpu_model, "VIA C3 Ezra");
 632                         else
 633                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 634                         break;
 635                 case 0x680:
 636                         strcpy(cpu_model, "VIA C3 Ezra-T");
 637                         break;
 638                 case 0x690:
 639                         strcpy(cpu_model, "VIA C3 Nehemiah");
 640                         break;
 641                 case 0x6a0:
 642                 case 0x6d0:
 643                         strcpy(cpu_model, "VIA C7 Esther");
 644                         break;
 645                 case 0x6f0:
 646                         strcpy(cpu_model, "VIA Nano");
 647                         break;
 648                 default:
 649                         strcpy(cpu_model, "VIA/IDT Unknown");
 650                 }
 651 #else
 652                 strcpy(cpu_model, "VIA ");
 653                 if ((cpu_id & 0xff0) == 0x6f0)
 654                         strcat(cpu_model, "Nano Processor");
 655                 else
 656                         strcat(cpu_model, "Unknown");
 657 #endif
 658                 break;
 659 #ifdef __i386__
 660         case CPU_VENDOR_IBM:
 661                 strcpy(cpu_model, "Blue Lightning CPU");
 662                 break;
 663         case CPU_VENDOR_NSC:
 664                 switch (cpu_id & 0xff0) {
 665                 case 0x540:
 666                         strcpy(cpu_model, "Geode SC1100");
 667                         cpu = CPU_GEODE1100;
 668                         break;
 669                 default:
 670                         strcpy(cpu_model, "Geode/NSC unknown");
 671                         break;
 672                 }
 673                 break;
 674 #endif
 675         default:
 676                 strcat(cpu_model, "Unknown");
 677                 break;
 678         }
 679
 680         /*
 681          * Replace cpu_model with cpu_brand minus leading spaces if
 682          * we have one.
 683          */
 684         brand = cpu_brand;
 685         while (*brand == ' ')
 686                 ++brand;
 687         if (*brand != '\0')
 688                 strcpy(cpu_model, brand);
 689
 690         printf("%s (", cpu_model);
 691         if (tsc_freq != 0) {
 692                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 693                 printf("%jd.%02d-MHz ",
 694                     (intmax_t)(tsc_freq + 4999) / 1000000,
 695                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 696         }
 697 #ifdef __i386__
 698         switch(cpu_class) {
 699         case CPUCLASS_286:
 700                 printf("286");
 701                 break;
 702         case CPUCLASS_386:
 703                 printf("386");
 704                 break;
 705 #if defined(I486_CPU)
 706         case CPUCLASS_486:
 707                 printf("486");
 708                 break;
 709 #endif
 710 #if defined(I586_CPU)
 711         case CPUCLASS_586:
 712                 printf("586");
 713                 break;
 714 #endif
 715 #if defined(I686_CPU)
 716         case CPUCLASS_686:
 717                 printf("686");
 718                 break;
 719 #endif
 720         default:
 721                 printf("Unknown");      /* will panic below... */
 722         }
 723 #else
 724         printf("K8");
 725 #endif
 726         printf("-class CPU)\n");
 727         if (*cpu_vendor)
 728                 printf("  Origin=\"%s\"", cpu_vendor);
 729         if (cpu_id)
 730                 printf("  Id=0x%x", cpu_id);
 731
 732         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 733             cpu_vendor_id == CPU_VENDOR_AMD ||
 734             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 735 #ifdef __i386__
 736             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 737             cpu_vendor_id == CPU_VENDOR_RISE ||
 738             cpu_vendor_id == CPU_VENDOR_NSC ||
 739             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 740 #endif
 741             0) {
 742                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 743                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 744                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 745 #ifdef __i386__
 746                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 747                         printf("\n  DIR=0x%04x", cyrix_did);
 748 #endif
 749
 750                 /*
 751                  * AMD CPUID Specification
 752                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 753                  *
 754                  * Intel Processor Identification and CPUID Instruction
 755                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 756                  */
 757                 if (cpu_high > 0) {
 758
 759                         /*
 760                          * Here we should probably set up flags indicating
 761                          * whether or not various features are available.
 762                          * The interesting ones are probably VME, PSE, PAE,
 763                          * and PGE.  The code already assumes without bothering
 764                          * to check that all CPUs >= Pentium have a TSC and
 765                          * MSRs.
 766                          */
 767                         printf("\n  Features=0x%b", cpu_feature,
 768                         "\020"
 769                         "\001FPU"       /* Integral FPU */
 770                         "\002VME"       /* Extended VM86 mode support */
 771                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 772                         "\004PSE"       /* 4MByte page tables */
 773                         "\005TSC"       /* Timestamp counter */
 774                         "\006MSR"       /* Machine specific registers */
 775                         "\007PAE"       /* Physical address extension */
 776                         "\010MCE"       /* Machine Check support */
 777                         "\011CX8"       /* CMPEXCH8 instruction */
 778                         "\012APIC"      /* SMP local APIC */
 779                         "\013oldMTRR"   /* Previous implementation of MTRR */
 780                         "\014SEP"       /* Fast System Call */
 781                         "\015MTRR"      /* Memory Type Range Registers */
 782                         "\016PGE"       /* PG_G (global bit) support */
 783                         "\017MCA"       /* Machine Check Architecture */
 784                         "\020CMOV"      /* CMOV instruction */
 785                         "\021PAT"       /* Page attributes table */
 786                         "\022PSE36"     /* 36 bit address space support */
 787                         "\023PN"        /* Processor Serial number */
 788                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 789                         "\025<b20>"
 790                         "\026DTS"       /* Debug Trace Store */
 791                         "\027ACPI"      /* ACPI support */
 792                         "\030MMX"       /* MMX instructions */
 793                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 794                         "\032SSE"       /* Streaming SIMD Extensions */
 795                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 796                         "\034SS"        /* Self snoop */
 797                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 798                         "\036TM"        /* Thermal Monitor clock slowdown */
 799                         "\037IA64"      /* CPU can execute IA64 instructions */
 800                         "\040PBE"       /* Pending Break Enable */
 801                         );
 802
 803                         if (cpu_feature2 != 0) {
 804                                 printf("\n  Features2=0x%b", cpu_feature2,
 805                                 "\020"
 806                                 "\001SSE3"      /* SSE3 */
 807                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 808                                 "\003DTES64"    /* 64-bit Debug Trace */
 809                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 810                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 811                                 "\006VMX"       /* Virtual Machine Extensions */
 812                                 "\007SMX"       /* Safer Mode Extensions */
 813                                 "\010EST"       /* Enhanced SpeedStep */
 814                                 "\011TM2"       /* Thermal Monitor 2 */
 815                                 "\012SSSE3"     /* SSSE3 */
 816                                 "\013CNXT-ID"   /* L1 context ID available */
 817                                 "\014SDBG"      /* IA32 silicon debug */
 818                                 "\015FMA"       /* Fused Multiply Add */
 819                                 "\016CX16"      /* CMPXCHG16B Instruction */
 820                                 "\017xTPR"      /* Send Task Priority Messages*/
 821                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 822                                 "\021<b16>"
 823                                 "\022PCID"      /* Process-context Identifiers*/
 824                                 "\023DCA"       /* Direct Cache Access */
 825                                 "\024SSE4.1"    /* SSE 4.1 */
 826                                 "\025SSE4.2"    /* SSE 4.2 */
 827                                 "\026x2APIC"    /* xAPIC Extensions */
 828                                 "\027MOVBE"     /* MOVBE Instruction */
 829                                 "\030POPCNT"    /* POPCNT Instruction */
 830                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 831                                 "\032AESNI"     /* AES Crypto */
 832                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 833                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 834                                 "\035AVX"       /* Advanced Vector Extensions */
 835                                 "\036F16C"      /* Half-precision conversions */
 836                                 "\037RDRAND"    /* RDRAND Instruction */
 837                                 "\040HV"        /* Hypervisor */
 838                                 );
 839                         }
 840
 841                         if (amd_feature != 0) {
 842                                 printf("\n  AMD Features=0x%b", amd_feature,
 843                                 "\020"          /* in hex */
 844                                 "\001<s0>"      /* Same */
 845                                 "\002<s1>"      /* Same */
 846                                 "\003<s2>"      /* Same */
 847                                 "\004<s3>"      /* Same */
 848                                 "\005<s4>"      /* Same */
 849                                 "\006<s5>"      /* Same */
 850                                 "\007<s6>"      /* Same */
 851                                 "\010<s7>"      /* Same */
 852                                 "\011<s8>"      /* Same */
 853                                 "\012<s9>"      /* Same */
 854                                 "\013<b10>"     /* Undefined */
 855                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 856                                 "\015<s12>"     /* Same */
 857                                 "\016<s13>"     /* Same */
 858                                 "\017<s14>"     /* Same */
 859                                 "\020<s15>"     /* Same */
 860                                 "\021<s16>"     /* Same */
 861                                 "\022<s17>"     /* Same */
 862                                 "\023<b18>"     /* Reserved, unknown */
 863                                 "\024MP"        /* Multiprocessor Capable */
 864                                 "\025NX"        /* Has EFER.NXE, NX */
 865                                 "\026<b21>"     /* Undefined */
 866                                 "\027MMX+"      /* AMD MMX Extensions */
 867                                 "\030<s23>"     /* Same */
 868                                 "\031<s24>"     /* Same */
 869                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 870                                 "\033Page1GB"   /* 1-GB large page support */
 871                                 "\034RDTSCP"    /* RDTSCP */
 872                                 "\035<b28>"     /* Undefined */
 873                                 "\036LM"        /* 64 bit long mode */
 874                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 875                                 "\0403DNow!"    /* AMD 3DNow! */
 876                                 );
 877                         }
 878
 879                         if (amd_feature2 != 0) {
 880                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 881                                 "\020"
 882                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 883                                 "\002CMP"       /* CMP legacy */
 884                                 "\003SVM"       /* Secure Virtual Mode */
 885                                 "\004ExtAPIC"   /* Extended APIC register */
 886                                 "\005CR8"       /* CR8 in legacy mode */
 887                                 "\006ABM"       /* LZCNT instruction */
 888                                 "\007SSE4A"     /* SSE4A */
 889                                 "\010MAS"       /* Misaligned SSE mode */
 890                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 891                                 "\012OSVW"      /* OS visible workaround */
 892                                 "\013IBS"       /* Instruction based sampling */
 893                                 "\014XOP"       /* XOP extended instructions */
 894                                 "\015SKINIT"    /* SKINIT/STGI */
 895                                 "\016WDT"       /* Watchdog timer */
 896                                 "\017<b14>"
 897                                 "\020LWP"       /* Lightweight Profiling */
 898                                 "\021FMA4"      /* 4-operand FMA instructions */
 899                                 "\022TCE"       /* Translation Cache Extension */
 900                                 "\023<b18>"
 901                                 "\024NodeId"    /* NodeId MSR support */
 902                                 "\025<b20>"
 903                                 "\026TBM"       /* Trailing Bit Manipulation */
 904                                 "\027Topology"  /* Topology Extensions */
 905                                 "\030PCXC"      /* Core perf count */
 906                                 "\031PNXC"      /* NB perf count */
 907                                 "\032<b25>"
 908                                 "\033DBE"       /* Data Breakpoint extension */
 909                                 "\034PTSC"      /* Performance TSC */
 910                                 "\035PL2I"      /* L2I perf count */
 911                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 912                                 "\037<b30>"
 913                                 "\040<b31>"
 914                                 );
 915                         }
 916
 917                         if (cpu_stdext_feature != 0) {
 918                                 printf("\n  Structured Extended Features=0x%b",
 919                                     cpu_stdext_feature,
 920                                        "\020"
 921                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 922                                        "\001FSGSBASE"
 923                                        "\002TSCADJ"
 924                                        "\003SGX"
 925                                        /* Bit Manipulation Instructions */
 926                                        "\004BMI1"
 927                                        /* Hardware Lock Elision */
 928                                        "\005HLE"
 929                                        /* Advanced Vector Instructions 2 */
 930                                        "\006AVX2"
 931                                        /* FDP_EXCPTN_ONLY */
 932                                        "\007FDPEXC"
 933                                        /* Supervisor Mode Execution Prot. */
 934                                        "\010SMEP"
 935                                        /* Bit Manipulation Instructions */
 936                                        "\011BMI2"
 937                                        "\012ERMS"
 938                                        /* Invalidate Processor Context ID */
 939                                        "\013INVPCID"
 940                                        /* Restricted Transactional Memory */
 941                                        "\014RTM"
 942                                        "\015PQM"
 943                                        "\016NFPUSG"
 944                                        /* Intel Memory Protection Extensions */
 945                                        "\017MPX"
 946                                        "\020PQE"
 947                                        /* AVX512 Foundation */
 948                                        "\021AVX512F"
 949                                        "\022AVX512DQ"
 950                                        /* Enhanced NRBG */
 951                                        "\023RDSEED"
 952                                        /* ADCX + ADOX */
 953                                        "\024ADX"
 954                                        /* Supervisor Mode Access Prevention */
 955                                        "\025SMAP"
 956                                        "\026AVX512IFMA"
 957                                        "\027PCOMMIT"
 958                                        "\030CLFLUSHOPT"
 959                                        "\031CLWB"
 960                                        "\032PROCTRACE"
 961                                        "\033AVX512PF"
 962                                        "\034AVX512ER"
 963                                        "\035AVX512CD"
 964                                        "\036SHA"
 965                                        "\037AVX512BW"
 966                                        );
 967                         }
 968
 969                         if (cpu_stdext_feature2 != 0) {
 970                                 printf("\n  Structured Extended Features2=0x%b",
 971                                     cpu_stdext_feature2,
 972                                        "\020"
 973                                        "\001PREFETCHWT1"
 974                                        "\002AVX512VBMI"
 975                                        "\003UMIP"
 976                                        "\004PKU"
 977                                        "\005OSPKE"
 978                                        "\027RDPID"
 979                                        "\037SGXLC"
 980                                        );
 981                         }
 982
 983                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 984                                 cpuid_count(0xd, 0x1, regs);
 985                                 if (regs[0] != 0) {
 986                                         printf("\n  XSAVE Features=0x%b",
 987                                             regs[0],
 988                                             "\020"
 989                                             "\001XSAVEOPT"
 990                                             "\002XSAVEC"
 991                                             "\003XINUSE"
 992                                             "\004XSAVES");
 993                                 }
 994                         }
 995
 996                         if (amd_extended_feature_extensions != 0) {
 997                                 printf("\n  "
 998                                     "AMD Extended Feature Extensions ID EBX="
 999                                     "0x%b", amd_extended_feature_extensions,
1000                                     "\020"
1001                                     "\001CLZERO"
1002                                     "\002IRPerf"
1003                                     "\003XSaveErPtr");
1004                         }
1005
1006                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1007                                 print_via_padlock_info();
1008
1009                         if (cpu_feature2 & CPUID2_VMX)
1010                                 print_vmx_info();
1011
1012                         if (amd_feature2 & AMDID2_SVM)
1013                                 print_svm_info();
1014
1015                         if ((cpu_feature & CPUID_HTT) &&
1016                             cpu_vendor_id == CPU_VENDOR_AMD)
1017                                 cpu_feature &= ~CPUID_HTT;
1018
1019                         /*
1020                          * If this CPU supports P-state invariant TSC then
1021                          * mention the capability.
1022                          */
1023                         if (tsc_is_invariant) {
1024                                 printf("\n  TSC: P-state invariant");
1025                                 if (tsc_perf_stat)
1026                                         printf(", performance statistics");
1027                         }
1028                 }
1029 #ifdef __i386__
1030         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1031                 printf("  DIR=0x%04x", cyrix_did);
1032                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1033                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1034 #ifndef CYRIX_CACHE_REALLY_WORKS
1035                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1036                         printf("\n  CPU cache: write-through mode");
1037 #endif
1038 #endif
1039         }
1040
1041         /* Avoid ugly blank lines: only print newline when we have to. */
1042         if (*cpu_vendor || cpu_id)
1043                 printf("\n");
1044
1045         if (bootverbose) {
1046                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1047                         print_AMD_info();
1048                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1049                         print_INTEL_info();
1050 #ifdef __i386__
1051                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1052                         print_transmeta_info();
1053 #endif
1054         }
1055
1056         print_hypervisor_info();
1057 }
1058
1059 #ifdef __i386__
1060 void
1061 panicifcpuunsupported(void)
1062 {
1063
1064 #if !defined(lint)
1065 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1066 #error This kernel is not configured for one of the supported CPUs
1067 #endif
1068 #else /* lint */
1069 #endif /* lint */
1070         /*
1071          * Now that we have told the user what they have,
1072          * let them know if that machine type isn't configured.
1073          */
1074         switch (cpu_class) {
1075         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1076         case CPUCLASS_386:
1077 #if !defined(I486_CPU)
1078         case CPUCLASS_486:
1079 #endif
1080 #if !defined(I586_CPU)
1081         case CPUCLASS_586:
1082 #endif
1083 #if !defined(I686_CPU)
1084         case CPUCLASS_686:
1085 #endif
1086                 panic("CPU class not configured");
1087         default:
1088                 break;
1089         }
1090 }
1091
1092 static  volatile u_int trap_by_rdmsr;
1093
1094 /*
1095  * Special exception 6 handler.
1096  * The rdmsr instruction generates invalid opcodes fault on 486-class
1097  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1098  * function identblue() when this handler is called.  Stacked eip should
1099  * be advanced.
1100  */
1101 inthand_t       bluetrap6;
1102 #ifdef __GNUCLIKE_ASM
1103 __asm
1104 ("                                                                      \n\
1105         .text                                                           \n\
1106         .p2align 2,0x90                                                 \n\
1107         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1108 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1109         ss                                                              \n\
1110         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1111         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1112         iret                                                            \n\
1113 ");
1114 #endif
1115
1116 /*
1117  * Special exception 13 handler.
1118  * Accessing non-existent MSR generates general protection fault.
1119  */
1120 inthand_t       bluetrap13;
1121 #ifdef __GNUCLIKE_ASM
1122 __asm
1123 ("                                                                      \n\
1124         .text                                                           \n\
1125         .p2align 2,0x90                                                 \n\
1126         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1127 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1128         ss                                                              \n\
1129         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1130         popl    %eax            /* discard error code */                \n\
1131         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1132         iret                                                            \n\
1133 ");
1134 #endif
1135
1136 /*
1137  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1138  * support cpuid instruction.  This function should be called after
1139  * loading interrupt descriptor table register.
1140  *
1141  * I don't like this method that handles fault, but I couldn't get
1142  * information for any other methods.  Does blue giant know?
1143  */
1144 static int
1145 identblue(void)
1146 {
1147
1148         trap_by_rdmsr = 0;
1149
1150         /*
1151          * Cyrix 486-class CPU does not support rdmsr instruction.
1152          * The rdmsr instruction generates invalid opcode fault, and exception
1153          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1154          * bluetrap6() set the magic number to trap_by_rdmsr.
1155          */
1156         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1157             GSEL(GCODE_SEL, SEL_KPL));
1158
1159         /*
1160          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1161          * In this case, rdmsr generates general protection fault, and
1162          * exception will be trapped by bluetrap13().
1163          */
1164         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1165             GSEL(GCODE_SEL, SEL_KPL));
1166
1167         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1168
1169         if (trap_by_rdmsr == 0xa8c1d)
1170                 return IDENTBLUE_CYRIX486;
1171         else if (trap_by_rdmsr == 0xa89c4)
1172                 return IDENTBLUE_CYRIXM2;
1173         return IDENTBLUE_IBMCPU;
1174 }
1175
1176
1177 /*
1178  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1179  *
1180  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1181  * +-------+-------+---------------+
1182  * |  SID  |  RID  |   Device ID   |
1183  * |    (DIR 1)    |    (DIR 0)    |
1184  * +-------+-------+---------------+
1185  */
1186 static void
1187 identifycyrix(void)
1188 {
1189         register_t saveintr;
1190         int     ccr2_test = 0, dir_test = 0;
1191         u_char  ccr2, ccr3;
1192
1193         saveintr = intr_disable();
1194
1195         ccr2 = read_cyrix_reg(CCR2);
1196         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1197         read_cyrix_reg(CCR2);
1198         if (read_cyrix_reg(CCR2) != ccr2)
1199                 ccr2_test = 1;
1200         write_cyrix_reg(CCR2, ccr2);
1201
1202         ccr3 = read_cyrix_reg(CCR3);
1203         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1204         read_cyrix_reg(CCR3);
1205         if (read_cyrix_reg(CCR3) != ccr3)
1206                 dir_test = 1;                                   /* CPU supports DIRs. */
1207         write_cyrix_reg(CCR3, ccr3);
1208
1209         if (dir_test) {
1210                 /* Device ID registers are available. */
1211                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1212                 cyrix_did += read_cyrix_reg(DIR0);
1213         } else if (ccr2_test)
1214                 cyrix_did = 0x0010;             /* 486S A-step */
1215         else
1216                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1217
1218         intr_restore(saveintr);
1219 }
1220 #endif
1221
1222 /* Update TSC freq with the value indicated by the caller. */
1223 static void
1224 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1225 {
1226
1227         /* If there was an error during the transition, don't do anything. */
1228         if (status != 0)
1229                 return;
1230
1231         /* Total setting for this level gives the new frequency in MHz. */
1232         hw_clockrate = level->total_set.freq;
1233 }
1234
1235 static void
1236 hook_tsc_freq(void *arg __unused)
1237 {
1238
1239         if (tsc_is_invariant)
1240                 return;
1241
1242         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1243             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1244 }
1245
1246 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1247
1248 static const char *const vm_bnames[] = {
1249         "QEMU",                         /* QEMU */
1250         "Plex86",                       /* Plex86 */
1251         "Bochs",                        /* Bochs */
1252         "Xen",                          /* Xen */
1253         "BHYVE",                        /* bhyve */
1254         "Seabios",                      /* KVM */
1255         NULL
1256 };
1257
1258 static const char *const vm_pnames[] = {
1259         "VMware Virtual Platform",      /* VMWare VM */
1260         "Virtual Machine",              /* Microsoft VirtualPC */
1261         "VirtualBox",                   /* Sun xVM VirtualBox */
1262         "Parallels Virtual Platform",   /* Parallels VM */
1263         "KVM",                          /* KVM */
1264         NULL
1265 };
1266
1267 void
1268 identify_hypervisor(void)
1269 {
1270         u_int regs[4];
1271         char *p;
1272         int i;
1273
1274         /*
1275          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1276          * http://lkml.org/lkml/2008/10/1/246
1277          *
1278          * KB1009458: Mechanisms to determine if software is running in
1279          * a VMware virtual machine
1280          * http://kb.vmware.com/kb/1009458
1281          */
1282         if (cpu_feature2 & CPUID2_HV) {
1283                 vm_guest = VM_GUEST_VM;
1284                 do_cpuid(0x40000000, regs);
1285                 if (regs[0] >= 0x40000000) {
1286                         hv_high = regs[0];
1287                         ((u_int *)&hv_vendor)[0] = regs[1];
1288                         ((u_int *)&hv_vendor)[1] = regs[2];
1289                         ((u_int *)&hv_vendor)[2] = regs[3];
1290                         hv_vendor[12] = '\0';
1291                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1292                                 vm_guest = VM_GUEST_VMWARE;
1293                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1294                                 vm_guest = VM_GUEST_HV;
1295                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1296                                 vm_guest = VM_GUEST_KVM;
1297                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1298                                 vm_guest = VM_GUEST_BHYVE;
1299                 }
1300                 return;
1301         }
1302
1303         /*
1304          * Examine SMBIOS strings for older hypervisors.
1305          */
1306         p = kern_getenv("smbios.system.serial");
1307         if (p != NULL) {
1308                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1309                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1310                         if (regs[1] == VMW_HVMAGIC) {
1311                                 vm_guest = VM_GUEST_VMWARE;
1312                                 freeenv(p);
1313                                 return;
1314                         }
1315                 }
1316                 freeenv(p);
1317         }
1318
1319         /*
1320          * XXX: Some of these entries may not be needed since they were
1321          * added to FreeBSD before the checks above.
1322          */
1323         p = kern_getenv("smbios.bios.vendor");
1324         if (p != NULL) {
1325                 for (i = 0; vm_bnames[i] != NULL; i++)
1326                         if (strcmp(p, vm_bnames[i]) == 0) {
1327                                 vm_guest = VM_GUEST_VM;
1328                                 freeenv(p);
1329                                 return;
1330                         }
1331                 freeenv(p);
1332         }
1333         p = kern_getenv("smbios.system.product");
1334         if (p != NULL) {
1335                 for (i = 0; vm_pnames[i] != NULL; i++)
1336                         if (strcmp(p, vm_pnames[i]) == 0) {
1337                                 vm_guest = VM_GUEST_VM;
1338                                 freeenv(p);
1339                                 return;
1340                         }
1341                 freeenv(p);
1342         }
1343 }
1344
1345 bool
1346 fix_cpuid(void)
1347 {
1348         uint64_t msr;
1349
1350         /*
1351          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1352          * get the largest standard CPUID function number again if it is set
1353          * from BIOS.  It is necessary for probing correct CPU topology later
1354          * and for the correct operation of the AVX-aware userspace.
1355          */
1356         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1357             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1358             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1359             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1360             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1361                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1362                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1363                         msr &= ~IA32_MISC_EN_LIMCPUID;
1364                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1365                         return (true);
1366                 }
1367         }
1368
1369         /*
1370          * Re-enable AMD Topology Extension that could be disabled by BIOS
1371          * on some notebook processors.  Without the extension it's really
1372          * hard to determine the correct CPU cache topology.
1373          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1374          * Models 60h-6Fh Processors, Publication # 50742.
1375          */
1376         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1377                 msr = rdmsr(MSR_EXTFEATURES);
1378                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1379                         msr |= (uint64_t)1 << 54;
1380                         wrmsr(MSR_EXTFEATURES, msr);
1381                         return (true);
1382                 }
1383         }
1384         return (false);
1385 }
1386
1387 #ifdef __amd64__
1388 void
1389 identify_cpu(void)
1390 {
1391         u_int regs[4];
1392
1393         do_cpuid(0, regs);
1394         cpu_high = regs[0];
1395         ((u_int *)&cpu_vendor)[0] = regs[1];
1396         ((u_int *)&cpu_vendor)[1] = regs[3];
1397         ((u_int *)&cpu_vendor)[2] = regs[2];
1398         cpu_vendor[12] = '\0';
1399
1400         do_cpuid(1, regs);
1401         cpu_id = regs[0];
1402         cpu_procinfo = regs[1];
1403         cpu_feature = regs[3];
1404         cpu_feature2 = regs[2];
1405 }
1406 #endif
1407
1408 /*
1409  * Final stage of CPU identification.
1410  */
1411 void
1412 finishidentcpu(void)
1413 {
1414         u_int regs[4], cpu_stdext_disable;
1415 #ifdef __i386__
1416         u_char ccr3;
1417 #endif
1418
1419         cpu_vendor_id = find_cpu_vendor_id();
1420
1421         if (fix_cpuid()) {
1422                 do_cpuid(0, regs);
1423                 cpu_high = regs[0];
1424         }
1425
1426         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1427                 do_cpuid(5, regs);
1428                 cpu_mon_mwait_flags = regs[2];
1429                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1430                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1431         }
1432
1433         if (cpu_high >= 7) {
1434                 cpuid_count(7, 0, regs);
1435                 cpu_stdext_feature = regs[1];
1436
1437                 /*
1438                  * Some hypervisors failed to filter out unsupported
1439                  * extended features.  Allow to disable the
1440                  * extensions, activation of which requires setting a
1441                  * bit in CR4, and which VM monitors do not support.
1442                  */
1443                 cpu_stdext_disable = 0;
1444                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1445                 cpu_stdext_feature &= ~cpu_stdext_disable;
1446
1447                 cpu_stdext_feature2 = regs[2];
1448         }
1449
1450 #ifdef __i386__
1451         if (cpu_high > 0 &&
1452             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1453              cpu_vendor_id == CPU_VENDOR_AMD ||
1454              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1455              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1456              cpu_vendor_id == CPU_VENDOR_NSC)) {
1457                 do_cpuid(0x80000000, regs);
1458                 if (regs[0] >= 0x80000000)
1459                         cpu_exthigh = regs[0];
1460         }
1461 #else
1462         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1463             cpu_vendor_id == CPU_VENDOR_AMD ||
1464             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1465                 do_cpuid(0x80000000, regs);
1466                 cpu_exthigh = regs[0];
1467         }
1468 #endif
1469         if (cpu_exthigh >= 0x80000001) {
1470                 do_cpuid(0x80000001, regs);
1471                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1472                 amd_feature2 = regs[2];
1473         }
1474         if (cpu_exthigh >= 0x80000007) {
1475                 do_cpuid(0x80000007, regs);
1476                 amd_rascap = regs[1];
1477                 amd_pminfo = regs[3];
1478         }
1479         if (cpu_exthigh >= 0x80000008) {
1480                 do_cpuid(0x80000008, regs);
1481                 cpu_maxphyaddr = regs[0] & 0xff;
1482                 amd_extended_feature_extensions = regs[1];
1483                 cpu_procinfo2 = regs[2];
1484         } else {
1485                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1486         }
1487
1488 #ifdef __i386__
1489         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1490                 if (cpu == CPU_486) {
1491                         /*
1492                          * These conditions are equivalent to:
1493                          *     - CPU does not support cpuid instruction.
1494                          *     - Cyrix/IBM CPU is detected.
1495                          */
1496                         if (identblue() == IDENTBLUE_IBMCPU) {
1497                                 strcpy(cpu_vendor, "IBM");
1498                                 cpu_vendor_id = CPU_VENDOR_IBM;
1499                                 cpu = CPU_BLUE;
1500                                 return;
1501                         }
1502                 }
1503                 switch (cpu_id & 0xf00) {
1504                 case 0x600:
1505                         /*
1506                          * Cyrix's datasheet does not describe DIRs.
1507                          * Therefor, I assume it does not have them
1508                          * and use the result of the cpuid instruction.
1509                          * XXX they seem to have it for now at least. -Peter
1510                          */
1511                         identifycyrix();
1512                         cpu = CPU_M2;
1513                         break;
1514                 default:
1515                         identifycyrix();
1516                         /*
1517                          * This routine contains a trick.
1518                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1519                          */
1520                         switch (cyrix_did & 0x00f0) {
1521                         case 0x00:
1522                         case 0xf0:
1523                                 cpu = CPU_486DLC;
1524                                 break;
1525                         case 0x10:
1526                                 cpu = CPU_CY486DX;
1527                                 break;
1528                         case 0x20:
1529                                 if ((cyrix_did & 0x000f) < 8)
1530                                         cpu = CPU_M1;
1531                                 else
1532                                         cpu = CPU_M1SC;
1533                                 break;
1534                         case 0x30:
1535                                 cpu = CPU_M1;
1536                                 break;
1537                         case 0x40:
1538                                 /* MediaGX CPU */
1539                                 cpu = CPU_M1SC;
1540                                 break;
1541                         default:
1542                                 /* M2 and later CPUs are treated as M2. */
1543                                 cpu = CPU_M2;
1544
1545                                 /*
1546                                  * enable cpuid instruction.
1547                                  */
1548                                 ccr3 = read_cyrix_reg(CCR3);
1549                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1550                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1551                                 write_cyrix_reg(CCR3, ccr3);
1552
1553                                 do_cpuid(0, regs);
1554                                 cpu_high = regs[0];     /* eax */
1555                                 do_cpuid(1, regs);
1556                                 cpu_id = regs[0];       /* eax */
1557                                 cpu_feature = regs[3];  /* edx */
1558                                 break;
1559                         }
1560                 }
1561         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1562                 /*
1563                  * There are BlueLightning CPUs that do not change
1564                  * undefined flags by dividing 5 by 2.  In this case,
1565                  * the CPU identification routine in locore.s leaves
1566                  * cpu_vendor null string and puts CPU_486 into the
1567                  * cpu.
1568                  */
1569                 if (identblue() == IDENTBLUE_IBMCPU) {
1570                         strcpy(cpu_vendor, "IBM");
1571                         cpu_vendor_id = CPU_VENDOR_IBM;
1572                         cpu = CPU_BLUE;
1573                         return;
1574                 }
1575         }
1576 #endif
1577 }
1578
1579 static u_int
1580 find_cpu_vendor_id(void)
1581 {
1582         int     i;
1583
1584         for (i = 0; i < nitems(cpu_vendors); i++)
1585                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1586                         return (cpu_vendors[i].vendor_id);
1587         return (0);
1588 }
1589
1590 static void
1591 print_AMD_assoc(int i)
1592 {
1593         if (i == 255)
1594                 printf(", fully associative\n");
1595         else
1596                 printf(", %d-way associative\n", i);
1597 }
1598
1599 static void
1600 print_AMD_l2_assoc(int i)
1601 {
1602         switch (i & 0x0f) {
1603         case 0: printf(", disabled/not present\n"); break;
1604         case 1: printf(", direct mapped\n"); break;
1605         case 2: printf(", 2-way associative\n"); break;
1606         case 4: printf(", 4-way associative\n"); break;
1607         case 6: printf(", 8-way associative\n"); break;
1608         case 8: printf(", 16-way associative\n"); break;
1609         case 15: printf(", fully associative\n"); break;
1610         default: printf(", reserved configuration\n"); break;
1611         }
1612 }
1613
1614 static void
1615 print_AMD_info(void)
1616 {
1617 #ifdef __i386__
1618         uint64_t amd_whcr;
1619 #endif
1620         u_int regs[4];
1621
1622         if (cpu_exthigh >= 0x80000005) {
1623                 do_cpuid(0x80000005, regs);
1624                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1625                 print_AMD_assoc(regs[0] >> 24);
1626
1627                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1628                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1629
1630                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1631                 print_AMD_assoc(regs[1] >> 24);
1632
1633                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1634                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1635
1636                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1637                 printf(", %d bytes/line", regs[2] & 0xff);
1638                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1639                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1640
1641                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1642                 printf(", %d bytes/line", regs[3] & 0xff);
1643                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1644                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1645         }
1646
1647         if (cpu_exthigh >= 0x80000006) {
1648                 do_cpuid(0x80000006, regs);
1649                 if ((regs[0] >> 16) != 0) {
1650                         printf("L2 2MB data TLB: %d entries",
1651                             (regs[0] >> 16) & 0xfff);
1652                         print_AMD_l2_assoc(regs[0] >> 28);
1653                         printf("L2 2MB instruction TLB: %d entries",
1654                             regs[0] & 0xfff);
1655                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1656                 } else {
1657                         printf("L2 2MB unified TLB: %d entries",
1658                             regs[0] & 0xfff);
1659                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1660                 }
1661                 if ((regs[1] >> 16) != 0) {
1662                         printf("L2 4KB data TLB: %d entries",
1663                             (regs[1] >> 16) & 0xfff);
1664                         print_AMD_l2_assoc(regs[1] >> 28);
1665
1666                         printf("L2 4KB instruction TLB: %d entries",
1667                             (regs[1] >> 16) & 0xfff);
1668                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1669                 } else {
1670                         printf("L2 4KB unified TLB: %d entries",
1671                             (regs[1] >> 16) & 0xfff);
1672                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1673                 }
1674                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1675                 printf(", %d bytes/line", regs[2] & 0xff);
1676                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1677                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1678         }
1679
1680 #ifdef __i386__
1681         if (((cpu_id & 0xf00) == 0x500)
1682             && (((cpu_id & 0x0f0) > 0x80)
1683                 || (((cpu_id & 0x0f0) == 0x80)
1684                     && (cpu_id & 0x00f) > 0x07))) {
1685                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1686                 amd_whcr = rdmsr(0xc0000082);
1687                 if (!(amd_whcr & (0x3ff << 22))) {
1688                         printf("Write Allocate Disable\n");
1689                 } else {
1690                         printf("Write Allocate Enable Limit: %dM bytes\n",
1691                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1692                         printf("Write Allocate 15-16M bytes: %s\n",
1693                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1694                 }
1695         } else if (((cpu_id & 0xf00) == 0x500)
1696                    && ((cpu_id & 0x0f0) > 0x50)) {
1697                 /* K6, K6-2(old core) */
1698                 amd_whcr = rdmsr(0xc0000082);
1699                 if (!(amd_whcr & (0x7f << 1))) {
1700                         printf("Write Allocate Disable\n");
1701                 } else {
1702                         printf("Write Allocate Enable Limit: %dM bytes\n",
1703                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1704                         printf("Write Allocate 15-16M bytes: %s\n",
1705                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1706                         printf("Hardware Write Allocate Control: %s\n",
1707                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1708                 }
1709         }
1710 #endif
1711         /*
1712          * Opteron Rev E shows a bug as in very rare occasions a read memory
1713          * barrier is not performed as expected if it is followed by a
1714          * non-atomic read-modify-write instruction.
1715          * As long as that bug pops up very rarely (intensive machine usage
1716          * on other operating systems generally generates one unexplainable
1717          * crash any 2 months) and as long as a model specific fix would be
1718          * impractical at this stage, print out a warning string if the broken
1719          * model and family are identified.
1720          */
1721         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1722             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1723                 printf("WARNING: This architecture revision has known SMP "
1724                     "hardware bugs which may cause random instability\n");
1725 }
1726
1727 static void
1728 print_INTEL_info(void)
1729 {
1730         u_int regs[4];
1731         u_int rounds, regnum;
1732         u_int nwaycode, nway;
1733
1734         if (cpu_high >= 2) {
1735                 rounds = 0;
1736                 do {
1737                         do_cpuid(0x2, regs);
1738                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1739                                 break;  /* we have a buggy CPU */
1740
1741                         for (regnum = 0; regnum <= 3; ++regnum) {
1742                                 if (regs[regnum] & (1<<31))
1743                                         continue;
1744                                 if (regnum != 0)
1745                                         print_INTEL_TLB(regs[regnum] & 0xff);
1746                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1747                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1748                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1749                         }
1750                 } while (--rounds > 0);
1751         }
1752
1753         if (cpu_exthigh >= 0x80000006) {
1754                 do_cpuid(0x80000006, regs);
1755                 nwaycode = (regs[2] >> 12) & 0x0f;
1756                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1757                         nway = 1 << (nwaycode / 2);
1758                 else
1759                         nway = 0;
1760                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1761                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1762         }
1763 }
1764
1765 static void
1766 print_INTEL_TLB(u_int data)
1767 {
1768         switch (data) {
1769         case 0x0:
1770         case 0x40:
1771         default:
1772                 break;
1773         case 0x1:
1774                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1775                 break;
1776         case 0x2:
1777                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1778                 break;
1779         case 0x3:
1780                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1781                 break;
1782         case 0x4:
1783                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1784                 break;
1785         case 0x6:
1786                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1787                 break;
1788         case 0x8:
1789                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1790                 break;
1791         case 0x9:
1792                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1793                 break;
1794         case 0xa:
1795                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1796                 break;
1797         case 0xb:
1798                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1799                 break;
1800         case 0xc:
1801                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1802                 break;
1803         case 0xd:
1804                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1805                 break;
1806         case 0xe:
1807                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1808                 break;
1809         case 0x1d:
1810                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1811                 break;
1812         case 0x21:
1813                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1814                 break;
1815         case 0x22:
1816                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1817                 break;
1818         case 0x23:
1819                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1820                 break;
1821         case 0x24:
1822                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1823                 break;
1824         case 0x25:
1825                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1826                 break;
1827         case 0x29:
1828                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1829                 break;
1830         case 0x2c:
1831                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1832                 break;
1833         case 0x30:
1834                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1835                 break;
1836         case 0x39: /* De-listed in SDM rev. 54 */
1837                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1838                 break;
1839         case 0x3b: /* De-listed in SDM rev. 54 */
1840                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1841                 break;
1842         case 0x3c: /* De-listed in SDM rev. 54 */
1843                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1844                 break;
1845         case 0x41:
1846                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1847                 break;
1848         case 0x42:
1849                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1850                 break;
1851         case 0x43:
1852                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1853                 break;
1854         case 0x44:
1855                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1856                 break;
1857         case 0x45:
1858                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1859                 break;
1860         case 0x46:
1861                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1862                 break;
1863         case 0x47:
1864                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1865                 break;
1866         case 0x48:
1867                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1868                 break;
1869         case 0x49:
1870                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1871                     CPUID_TO_MODEL(cpu_id) == 0x6)
1872                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1873                 else
1874                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1875                 break;
1876         case 0x4a:
1877                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1878                 break;
1879         case 0x4b:
1880                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1881                 break;
1882         case 0x4c:
1883                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1884                 break;
1885         case 0x4d:
1886                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1887                 break;
1888         case 0x4e:
1889                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1890                 break;
1891         case 0x4f:
1892                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1893                 break;
1894         case 0x50:
1895                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1896                 break;
1897         case 0x51:
1898                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1899                 break;
1900         case 0x52:
1901                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1902                 break;
1903         case 0x55:
1904                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1905                 break;
1906         case 0x56:
1907                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1908                 break;
1909         case 0x57:
1910                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1911                 break;
1912         case 0x59:
1913                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1914                 break;
1915         case 0x5a:
1916                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1917                 break;
1918         case 0x5b:
1919                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1920                 break;
1921         case 0x5c:
1922                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1923                 break;
1924         case 0x5d:
1925                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1926                 break;
1927         case 0x60:
1928                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1929                 break;
1930         case 0x61:
1931                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1932                 break;
1933         case 0x63:
1934                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1935                 break;
1936         case 0x64:
1937                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1938                 break;
1939         case 0x66:
1940                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1941                 break;
1942         case 0x67:
1943                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1944                 break;
1945         case 0x68:
1946                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1947                 break;
1948         case 0x6a:
1949                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1950                 break;
1951         case 0x6b:
1952                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1953                 break;
1954         case 0x6c:
1955                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1956                 break;
1957         case 0x6d:
1958                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
1959                 break;
1960         case 0x70:
1961                 printf("Trace cache: 12K-uops, 8-way set associative\n");
1962                 break;
1963         case 0x71:
1964                 printf("Trace cache: 16K-uops, 8-way set associative\n");
1965                 break;
1966         case 0x72:
1967                 printf("Trace cache: 32K-uops, 8-way set associative\n");
1968                 break;
1969         case 0x76:
1970                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
1971                 break;
1972         case 0x78:
1973                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
1974                 break;
1975         case 0x79:
1976                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1977                 break;
1978         case 0x7a:
1979                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1980                 break;
1981         case 0x7b:
1982                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1983                 break;
1984         case 0x7c:
1985                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1986                 break;
1987         case 0x7d:
1988                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
1989                 break;
1990         case 0x7f:
1991                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
1992                 break;
1993         case 0x80:
1994                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
1995                 break;
1996         case 0x82:
1997                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
1998                 break;
1999         case 0x83:
2000                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2001                 break;
2002         case 0x84:
2003                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2004                 break;
2005         case 0x85:
2006                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2007                 break;
2008         case 0x86:
2009                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2010                 break;
2011         case 0x87:
2012                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2013                 break;
2014         case 0xa0:
2015                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2016                 break;
2017         case 0xb0:
2018                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2019                 break;
2020         case 0xb1:
2021                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2022                 break;
2023         case 0xb2:
2024                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2025                 break;
2026         case 0xb3:
2027                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2028                 break;
2029         case 0xb4:
2030                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2031                 break;
2032         case 0xb5:
2033                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2034                 break;
2035         case 0xb6:
2036                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2037                 break;
2038         case 0xba:
2039                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2040                 break;
2041         case 0xc0:
2042                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2043                 break;
2044         case 0xc1:
2045                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2046                 break;
2047         case 0xc2:
2048                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2049                 break;
2050         case 0xc3:
2051                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2052                 break;
2053         case 0xc4:
2054                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2055                 break;
2056         case 0xca:
2057                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2058                 break;
2059         case 0xd0:
2060                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2061                 break;
2062         case 0xd1:
2063                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2064                 break;
2065         case 0xd2:
2066                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2067                 break;
2068         case 0xd6:
2069                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2070                 break;
2071         case 0xd7:
2072                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2073                 break;
2074         case 0xd8:
2075                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2076                 break;
2077         case 0xdc:
2078                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2079                 break;
2080         case 0xdd:
2081                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2082                 break;
2083         case 0xde:
2084                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2085                 break;
2086         case 0xe2:
2087                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2088                 break;
2089         case 0xe3:
2090                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2091                 break;
2092         case 0xe4:
2093                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2094                 break;
2095         case 0xea:
2096                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2097                 break;
2098         case 0xeb:
2099                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2100                 break;
2101         case 0xec:
2102                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2103                 break;
2104         case 0xf0:
2105                 printf("64-Byte prefetching\n");
2106                 break;
2107         case 0xf1:
2108                 printf("128-Byte prefetching\n");
2109                 break;
2110         }
2111 }
2112
2113 static void
2114 print_svm_info(void)
2115 {
2116         u_int features, regs[4];
2117         uint64_t msr;
2118         int comma;
2119
2120         printf("\n  SVM: ");
2121         do_cpuid(0x8000000A, regs);
2122         features = regs[3];
2123
2124         msr = rdmsr(MSR_VM_CR);
2125         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2126                 printf("(disabled in BIOS) ");
2127
2128         if (!bootverbose) {
2129                 comma = 0;
2130                 if (features & (1 << 0)) {
2131                         printf("%sNP", comma ? "," : "");
2132                         comma = 1;
2133                 }
2134                 if (features & (1 << 3)) {
2135                         printf("%sNRIP", comma ? "," : "");
2136                         comma = 1;
2137                 }
2138                 if (features & (1 << 5)) {
2139                         printf("%sVClean", comma ? "," : "");
2140                         comma = 1;
2141                 }
2142                 if (features & (1 << 6)) {
2143                         printf("%sAFlush", comma ? "," : "");
2144                         comma = 1;
2145                 }
2146                 if (features & (1 << 7)) {
2147                         printf("%sDAssist", comma ? "," : "");
2148                         comma = 1;
2149                 }
2150                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2151                 return;
2152         }
2153
2154         printf("Features=0x%b", features,
2155                "\020"
2156                "\001NP"                 /* Nested paging */
2157                "\002LbrVirt"            /* LBR virtualization */
2158                "\003SVML"               /* SVM lock */
2159                "\004NRIPS"              /* NRIP save */
2160                "\005TscRateMsr"         /* MSR based TSC rate control */
2161                "\006VmcbClean"          /* VMCB clean bits */
2162                "\007FlushByAsid"        /* Flush by ASID */
2163                "\010DecodeAssist"       /* Decode assist */
2164                "\011<b8>"
2165                "\012<b9>"
2166                "\013PauseFilter"        /* PAUSE intercept filter */
2167                "\014EncryptedMcodePatch"
2168                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2169                "\016AVIC"               /* virtual interrupt controller */
2170                "\017<b14>"
2171                "\020V_VMSAVE_VMLOAD"
2172                "\021vGIF"
2173                "\022<b17>"
2174                "\023<b18>"
2175                "\024<b19>"
2176                "\025<b20>"
2177                "\026<b21>"
2178                "\027<b22>"
2179                "\030<b23>"
2180                "\031<b24>"
2181                "\032<b25>"
2182                "\033<b26>"
2183                "\034<b27>"
2184                "\035<b28>"
2185                "\036<b29>"
2186                "\037<b30>"
2187                "\040<b31>"
2188                 );
2189         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2190 }
2191
2192 #ifdef __i386__
2193 static void
2194 print_transmeta_info(void)
2195 {
2196         u_int regs[4], nreg = 0;
2197
2198         do_cpuid(0x80860000, regs);
2199         nreg = regs[0];
2200         if (nreg >= 0x80860001) {
2201                 do_cpuid(0x80860001, regs);
2202                 printf("  Processor revision %u.%u.%u.%u\n",
2203                        (regs[1] >> 24) & 0xff,
2204                        (regs[1] >> 16) & 0xff,
2205                        (regs[1] >> 8) & 0xff,
2206                        regs[1] & 0xff);
2207         }
2208         if (nreg >= 0x80860002) {
2209                 do_cpuid(0x80860002, regs);
2210                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2211                        (regs[1] >> 24) & 0xff,
2212                        (regs[1] >> 16) & 0xff,
2213                        (regs[1] >> 8) & 0xff,
2214                        regs[1] & 0xff,
2215                        regs[2]);
2216         }
2217         if (nreg >= 0x80860006) {
2218                 char info[65];
2219                 do_cpuid(0x80860003, (u_int*) &info[0]);
2220                 do_cpuid(0x80860004, (u_int*) &info[16]);
2221                 do_cpuid(0x80860005, (u_int*) &info[32]);
2222                 do_cpuid(0x80860006, (u_int*) &info[48]);
2223                 info[64] = 0;
2224                 printf("  %s\n", info);
2225         }
2226 }
2227 #endif
2228
2229 static void
2230 print_via_padlock_info(void)
2231 {
2232         u_int regs[4];
2233
2234         do_cpuid(0xc0000001, regs);
2235         printf("\n  VIA Padlock Features=0x%b", regs[3],
2236         "\020"
2237         "\003RNG"               /* RNG */
2238         "\007AES"               /* ACE */
2239         "\011AES-CTR"           /* ACE2 */
2240         "\013SHA1,SHA256"       /* PHE */
2241         "\015RSA"               /* PMM */
2242         );
2243 }
2244
2245 static uint32_t
2246 vmx_settable(uint64_t basic, int msr, int true_msr)
2247 {
2248         uint64_t val;
2249
2250         if (basic & (1ULL << 55))
2251                 val = rdmsr(true_msr);
2252         else
2253                 val = rdmsr(msr);
2254
2255         /* Just report the controls that can be set to 1. */
2256         return (val >> 32);
2257 }
2258
2259 static void
2260 print_vmx_info(void)
2261 {
2262         uint64_t basic, msr;
2263         uint32_t entry, exit, mask, pin, proc, proc2;
2264         int comma;
2265
2266         printf("\n  VT-x: ");
2267         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2268         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2269                 printf("(disabled in BIOS) ");
2270         basic = rdmsr(MSR_VMX_BASIC);
2271         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2272             MSR_VMX_TRUE_PINBASED_CTLS);
2273         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2274             MSR_VMX_TRUE_PROCBASED_CTLS);
2275         if (proc & PROCBASED_SECONDARY_CONTROLS)
2276                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2277                     MSR_VMX_PROCBASED_CTLS2);
2278         else
2279                 proc2 = 0;
2280         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2281         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2282
2283         if (!bootverbose) {
2284                 comma = 0;
2285                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2286                     entry & VM_ENTRY_LOAD_PAT) {
2287                         printf("%sPAT", comma ? "," : "");
2288                         comma = 1;
2289                 }
2290                 if (proc & PROCBASED_HLT_EXITING) {
2291                         printf("%sHLT", comma ? "," : "");
2292                         comma = 1;
2293                 }
2294                 if (proc & PROCBASED_MTF) {
2295                         printf("%sMTF", comma ? "," : "");
2296                         comma = 1;
2297                 }
2298                 if (proc & PROCBASED_PAUSE_EXITING) {
2299                         printf("%sPAUSE", comma ? "," : "");
2300                         comma = 1;
2301                 }
2302                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2303                         printf("%sEPT", comma ? "," : "");
2304                         comma = 1;
2305                 }
2306                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2307                         printf("%sUG", comma ? "," : "");
2308                         comma = 1;
2309                 }
2310                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2311                         printf("%sVPID", comma ? "," : "");
2312                         comma = 1;
2313                 }
2314                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2315                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2316                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2317                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2318                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2319                         printf("%sVID", comma ? "," : "");
2320                         comma = 1;
2321                         if (pin & PINBASED_POSTED_INTERRUPT)
2322                                 printf(",PostIntr");
2323                 }
2324                 return;
2325         }
2326
2327         mask = basic >> 32;
2328         printf("Basic Features=0x%b", mask,
2329         "\020"
2330         "\02132PA"              /* 32-bit physical addresses */
2331         "\022SMM"               /* SMM dual-monitor */
2332         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2333         "\030TRUE"              /* TRUE_CTLS MSRs */
2334         );
2335         printf("\n        Pin-Based Controls=0x%b", pin,
2336         "\020"
2337         "\001ExtINT"            /* External-interrupt exiting */
2338         "\004NMI"               /* NMI exiting */
2339         "\006VNMI"              /* Virtual NMIs */
2340         "\007PreTmr"            /* Activate VMX-preemption timer */
2341         "\010PostIntr"          /* Process posted interrupts */
2342         );
2343         printf("\n        Primary Processor Controls=0x%b", proc,
2344         "\020"
2345         "\003INTWIN"            /* Interrupt-window exiting */
2346         "\004TSCOff"            /* Use TSC offsetting */
2347         "\010HLT"               /* HLT exiting */
2348         "\012INVLPG"            /* INVLPG exiting */
2349         "\013MWAIT"             /* MWAIT exiting */
2350         "\014RDPMC"             /* RDPMC exiting */
2351         "\015RDTSC"             /* RDTSC exiting */
2352         "\020CR3-LD"            /* CR3-load exiting */
2353         "\021CR3-ST"            /* CR3-store exiting */
2354         "\024CR8-LD"            /* CR8-load exiting */
2355         "\025CR8-ST"            /* CR8-store exiting */
2356         "\026TPR"               /* Use TPR shadow */
2357         "\027NMIWIN"            /* NMI-window exiting */
2358         "\030MOV-DR"            /* MOV-DR exiting */
2359         "\031IO"                /* Unconditional I/O exiting */
2360         "\032IOmap"             /* Use I/O bitmaps */
2361         "\034MTF"               /* Monitor trap flag */
2362         "\035MSRmap"            /* Use MSR bitmaps */
2363         "\036MONITOR"           /* MONITOR exiting */
2364         "\037PAUSE"             /* PAUSE exiting */
2365         );
2366         if (proc & PROCBASED_SECONDARY_CONTROLS)
2367                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2368                 "\020"
2369                 "\001APIC"              /* Virtualize APIC accesses */
2370                 "\002EPT"               /* Enable EPT */
2371                 "\003DT"                /* Descriptor-table exiting */
2372                 "\004RDTSCP"            /* Enable RDTSCP */
2373                 "\005x2APIC"            /* Virtualize x2APIC mode */
2374                 "\006VPID"              /* Enable VPID */
2375                 "\007WBINVD"            /* WBINVD exiting */
2376                 "\010UG"                /* Unrestricted guest */
2377                 "\011APIC-reg"          /* APIC-register virtualization */
2378                 "\012VID"               /* Virtual-interrupt delivery */
2379                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2380                 "\014RDRAND"            /* RDRAND exiting */
2381                 "\015INVPCID"           /* Enable INVPCID */
2382                 "\016VMFUNC"            /* Enable VM functions */
2383                 "\017VMCS"              /* VMCS shadowing */
2384                 "\020EPT#VE"            /* EPT-violation #VE */
2385                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2386                 );
2387         printf("\n        Exit Controls=0x%b", mask,
2388         "\020"
2389         "\003DR"                /* Save debug controls */
2390                                 /* Ignore Host address-space size */
2391         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2392         "\020AckInt"            /* Acknowledge interrupt on exit */
2393         "\023PAT-SV"            /* Save MSR_PAT */
2394         "\024PAT-LD"            /* Load MSR_PAT */
2395         "\025EFER-SV"           /* Save MSR_EFER */
2396         "\026EFER-LD"           /* Load MSR_EFER */
2397         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2398         );
2399         printf("\n        Entry Controls=0x%b", mask,
2400         "\020"
2401         "\003DR"                /* Save debug controls */
2402                                 /* Ignore IA-32e mode guest */
2403                                 /* Ignore Entry to SMM */
2404                                 /* Ignore Deactivate dual-monitor treatment */
2405         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2406         "\017PAT"               /* Load MSR_PAT */
2407         "\020EFER"              /* Load MSR_EFER */
2408         );
2409         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2410             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2411                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2412                 mask = msr;
2413                 printf("\n        EPT Features=0x%b", mask,
2414                 "\020"
2415                 "\001XO"                /* Execute-only translations */
2416                 "\007PW4"               /* Page-walk length of 4 */
2417                 "\011UC"                /* EPT paging-structure mem can be UC */
2418                 "\017WB"                /* EPT paging-structure mem can be WB */
2419                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2420                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2421                 "\025INVEPT"            /* INVEPT is supported */
2422                 "\026AD"                /* Accessed and dirty flags for EPT */
2423                 "\032single"            /* INVEPT single-context type */
2424                 "\033all"               /* INVEPT all-context type */
2425                 );
2426                 mask = msr >> 32;
2427                 printf("\n        VPID Features=0x%b", mask,
2428                 "\020"
2429                 "\001INVVPID"           /* INVVPID is supported */
2430                 "\011individual"        /* INVVPID individual-address type */
2431                 "\012single"            /* INVVPID single-context type */
2432                 "\013all"               /* INVVPID all-context type */
2433                  /* INVVPID single-context-retaining-globals type */
2434                 "\014single-globals"
2435                 );
2436         }
2437 }
2438
2439 static void
2440 print_hypervisor_info(void)
2441 {
2442
2443         if (*hv_vendor)
2444                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2445 }