sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine/intr_machdep.h>
  61 #include <machine/md_var.h>
  62 #include <machine/segments.h>
  63 #include <machine/specialreg.h>
  64
  65 #include <amd64/vmm/intel/vmx_controls.h>
  66 #include <x86/isa/icu.h>
  67 #include <x86/vmware.h>
  68
  69 #ifdef __i386__
  70 #define IDENTBLUE_CYRIX486      0
  71 #define IDENTBLUE_IBMCPU        1
  72 #define IDENTBLUE_CYRIXM2       2
  73
  74 static void identifycyrix(void);
  75 static void print_transmeta_info(void);
  76 #endif
  77 static u_int find_cpu_vendor_id(void);
  78 static void print_AMD_info(void);
  79 static void print_INTEL_info(void);
  80 static void print_INTEL_TLB(u_int data);
  81 static void print_hypervisor_info(void);
  82 static void print_svm_info(void);
  83 static void print_via_padlock_info(void);
  84 static void print_vmx_info(void);
  85
  86 #ifdef __i386__
  87 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  88 int     cpu_class;
  89 #endif
  90 u_int   cpu_feature;            /* Feature flags */
  91 u_int   cpu_feature2;           /* Feature flags */
  92 u_int   amd_feature;            /* AMD feature flags */
  93 u_int   amd_feature2;           /* AMD feature flags */
  94 u_int   amd_rascap;             /* AMD RAS capabilities */
  95 u_int   amd_pminfo;             /* AMD advanced power management info */
  96 u_int   amd_extended_feature_extensions;
  97 u_int   via_feature_rng;        /* VIA RNG features */
  98 u_int   via_feature_xcrypt;     /* VIA ACE features */
  99 u_int   cpu_high;               /* Highest arg to CPUID */
 100 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 101 u_int   cpu_id;                 /* Stepping ID */
 102 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 103 u_int   cpu_procinfo2;          /* Multicore info */
 104 char    cpu_vendor[20];         /* CPU Origin code */
 105 u_int   cpu_vendor_id;          /* CPU vendor ID */
 106 u_int   cpu_fxsr;               /* SSE enabled */
 107 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 108 u_int   cpu_clflush_line_size = 32;
 109 u_int   cpu_stdext_feature;     /* %ebx */
 110 u_int   cpu_stdext_feature2;    /* %ecx */
 111 u_int   cpu_stdext_feature3;    /* %edx */
 112 uint64_t cpu_ia32_arch_caps;
 113 u_int   cpu_max_ext_state_size;
 114 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 115 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 116 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 117 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 118 char machine[] = MACHINE;
 119
 120 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 121     &via_feature_rng, 0,
 122     "VIA RNG feature available in CPU");
 123 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 124     &via_feature_xcrypt, 0,
 125     "VIA xcrypt feature available in CPU");
 126
 127 #ifdef __amd64__
 128 #ifdef SCTL_MASK32
 129 extern int adaptive_machine_arch;
 130 #endif
 131
 132 static int
 133 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 134 {
 135 #ifdef SCTL_MASK32
 136         static const char machine32[] = "i386";
 137 #endif
 138         int error;
 139
 140 #ifdef SCTL_MASK32
 141         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 142                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 143         else
 144 #endif
 145                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 146         return (error);
 147
 148 }
 149 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 150     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 151 #else
 152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 153     machine, 0, "Machine class");
 154 #endif
 155
 156 static char cpu_model[128];
 157 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 158     cpu_model, 0, "Machine model");
 159
 160 static int hw_clockrate;
 161 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 162     &hw_clockrate, 0, "CPU instruction clock rate");
 163
 164 u_int hv_high;
 165 char hv_vendor[16];
 166 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 167     0, "Hypervisor vendor");
 168
 169 static eventhandler_tag tsc_post_tag;
 170
 171 static char cpu_brand[48];
 172
 173 #ifdef __i386__
 174 #define MAX_BRAND_INDEX 8
 175
 176 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 177         NULL,                   /* No brand */
 178         "Intel Celeron",
 179         "Intel Pentium III",
 180         "Intel Pentium III Xeon",
 181         NULL,
 182         NULL,
 183         NULL,
 184         NULL,
 185         "Intel Pentium 4"
 186 };
 187
 188 static struct {
 189         char    *cpu_name;
 190         int     cpu_class;
 191 } cpus[] = {
 192         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 193         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 194         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 195         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 196         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 197         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 198         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 199         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 200         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 201         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 202         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 203         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 204         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 205         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 206         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 207         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 208         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 209 };
 210 #endif
 211
 212 static struct {
 213         char    *vendor;
 214         u_int   vendor_id;
 215 } cpu_vendors[] = {
 216         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 217         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 218         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 219 #ifdef __i386__
 220         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 221         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 222         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 223         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 224         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 225         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 226         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 227 #if 0
 228         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 229         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 230 #endif
 231 #endif
 232 };
 233
 234 void
 235 printcpuinfo(void)
 236 {
 237         u_int regs[4], i;
 238         char *brand;
 239
 240         printf("CPU: ");
 241 #ifdef __i386__
 242         cpu_class = cpus[cpu].cpu_class;
 243         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 244 #else
 245         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 246 #endif
 247
 248         /* Check for extended CPUID information and a processor name. */
 249         if (cpu_exthigh >= 0x80000004) {
 250                 brand = cpu_brand;
 251                 for (i = 0x80000002; i < 0x80000005; i++) {
 252                         do_cpuid(i, regs);
 253                         memcpy(brand, regs, sizeof(regs));
 254                         brand += sizeof(regs);
 255                 }
 256         }
 257
 258         switch (cpu_vendor_id) {
 259         case CPU_VENDOR_INTEL:
 260 #ifdef __i386__
 261                 if ((cpu_id & 0xf00) > 0x300) {
 262                         u_int brand_index;
 263
 264                         cpu_model[0] = '\0';
 265
 266                         switch (cpu_id & 0x3000) {
 267                         case 0x1000:
 268                                 strcpy(cpu_model, "Overdrive ");
 269                                 break;
 270                         case 0x2000:
 271                                 strcpy(cpu_model, "Dual ");
 272                                 break;
 273                         }
 274
 275                         switch (cpu_id & 0xf00) {
 276                         case 0x400:
 277                                 strcat(cpu_model, "i486 ");
 278                                 /* Check the particular flavor of 486 */
 279                                 switch (cpu_id & 0xf0) {
 280                                 case 0x00:
 281                                 case 0x10:
 282                                         strcat(cpu_model, "DX");
 283                                         break;
 284                                 case 0x20:
 285                                         strcat(cpu_model, "SX");
 286                                         break;
 287                                 case 0x30:
 288                                         strcat(cpu_model, "DX2");
 289                                         break;
 290                                 case 0x40:
 291                                         strcat(cpu_model, "SL");
 292                                         break;
 293                                 case 0x50:
 294                                         strcat(cpu_model, "SX2");
 295                                         break;
 296                                 case 0x70:
 297                                         strcat(cpu_model,
 298                                             "DX2 Write-Back Enhanced");
 299                                         break;
 300                                 case 0x80:
 301                                         strcat(cpu_model, "DX4");
 302                                         break;
 303                                 }
 304                                 break;
 305                         case 0x500:
 306                                 /* Check the particular flavor of 586 */
 307                                 strcat(cpu_model, "Pentium");
 308                                 switch (cpu_id & 0xf0) {
 309                                 case 0x00:
 310                                         strcat(cpu_model, " A-step");
 311                                         break;
 312                                 case 0x10:
 313                                         strcat(cpu_model, "/P5");
 314                                         break;
 315                                 case 0x20:
 316                                         strcat(cpu_model, "/P54C");
 317                                         break;
 318                                 case 0x30:
 319                                         strcat(cpu_model, "/P24T");
 320                                         break;
 321                                 case 0x40:
 322                                         strcat(cpu_model, "/P55C");
 323                                         break;
 324                                 case 0x70:
 325                                         strcat(cpu_model, "/P54C");
 326                                         break;
 327                                 case 0x80:
 328                                         strcat(cpu_model, "/P55C (quarter-micron)");
 329                                         break;
 330                                 default:
 331                                         /* nothing */
 332                                         break;
 333                                 }
 334 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 335                                 /*
 336                                  * XXX - If/when Intel fixes the bug, this
 337                                  * should also check the version of the
 338                                  * CPU, not just that it's a Pentium.
 339                                  */
 340                                 has_f00f_bug = 1;
 341 #endif
 342                                 break;
 343                         case 0x600:
 344                                 /* Check the particular flavor of 686 */
 345                                 switch (cpu_id & 0xf0) {
 346                                 case 0x00:
 347                                         strcat(cpu_model, "Pentium Pro A-step");
 348                                         break;
 349                                 case 0x10:
 350                                         strcat(cpu_model, "Pentium Pro");
 351                                         break;
 352                                 case 0x30:
 353                                 case 0x50:
 354                                 case 0x60:
 355                                         strcat(cpu_model,
 356                                 "Pentium II/Pentium II Xeon/Celeron");
 357                                         cpu = CPU_PII;
 358                                         break;
 359                                 case 0x70:
 360                                 case 0x80:
 361                                 case 0xa0:
 362                                 case 0xb0:
 363                                         strcat(cpu_model,
 364                                         "Pentium III/Pentium III Xeon/Celeron");
 365                                         cpu = CPU_PIII;
 366                                         break;
 367                                 default:
 368                                         strcat(cpu_model, "Unknown 80686");
 369                                         break;
 370                                 }
 371                                 break;
 372                         case 0xf00:
 373                                 strcat(cpu_model, "Pentium 4");
 374                                 cpu = CPU_P4;
 375                                 break;
 376                         default:
 377                                 strcat(cpu_model, "unknown");
 378                                 break;
 379                         }
 380
 381                         /*
 382                          * If we didn't get a brand name from the extended
 383                          * CPUID, try to look it up in the brand table.
 384                          */
 385                         if (cpu_high > 0 && *cpu_brand == '\0') {
 386                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 387                                 if (brand_index <= MAX_BRAND_INDEX &&
 388                                     cpu_brandtable[brand_index] != NULL)
 389                                         strcpy(cpu_brand,
 390                                             cpu_brandtable[brand_index]);
 391                         }
 392                 }
 393 #else
 394                 /* Please make up your mind folks! */
 395                 strcat(cpu_model, "EM64T");
 396 #endif
 397                 break;
 398         case CPU_VENDOR_AMD:
 399                 /*
 400                  * Values taken from AMD Processor Recognition
 401                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 402                  * (also describes ``Features'' encodings.
 403                  */
 404                 strcpy(cpu_model, "AMD ");
 405 #ifdef __i386__
 406                 switch (cpu_id & 0xFF0) {
 407                 case 0x410:
 408                         strcat(cpu_model, "Standard Am486DX");
 409                         break;
 410                 case 0x430:
 411                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 412                         break;
 413                 case 0x470:
 414                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 415                         break;
 416                 case 0x480:
 417                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 418                         break;
 419                 case 0x490:
 420                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 421                         break;
 422                 case 0x4E0:
 423                         strcat(cpu_model, "Am5x86 Write-Through");
 424                         break;
 425                 case 0x4F0:
 426                         strcat(cpu_model, "Am5x86 Write-Back");
 427                         break;
 428                 case 0x500:
 429                         strcat(cpu_model, "K5 model 0");
 430                         break;
 431                 case 0x510:
 432                         strcat(cpu_model, "K5 model 1");
 433                         break;
 434                 case 0x520:
 435                         strcat(cpu_model, "K5 PR166 (model 2)");
 436                         break;
 437                 case 0x530:
 438                         strcat(cpu_model, "K5 PR200 (model 3)");
 439                         break;
 440                 case 0x560:
 441                         strcat(cpu_model, "K6");
 442                         break;
 443                 case 0x570:
 444                         strcat(cpu_model, "K6 266 (model 1)");
 445                         break;
 446                 case 0x580:
 447                         strcat(cpu_model, "K6-2");
 448                         break;
 449                 case 0x590:
 450                         strcat(cpu_model, "K6-III");
 451                         break;
 452                 case 0x5a0:
 453                         strcat(cpu_model, "Geode LX");
 454                         break;
 455                 default:
 456                         strcat(cpu_model, "Unknown");
 457                         break;
 458                 }
 459 #else
 460                 if ((cpu_id & 0xf00) == 0xf00)
 461                         strcat(cpu_model, "AMD64 Processor");
 462                 else
 463                         strcat(cpu_model, "Unknown");
 464 #endif
 465                 break;
 466 #ifdef __i386__
 467         case CPU_VENDOR_CYRIX:
 468                 strcpy(cpu_model, "Cyrix ");
 469                 switch (cpu_id & 0xff0) {
 470                 case 0x440:
 471                         strcat(cpu_model, "MediaGX");
 472                         break;
 473                 case 0x520:
 474                         strcat(cpu_model, "6x86");
 475                         break;
 476                 case 0x540:
 477                         cpu_class = CPUCLASS_586;
 478                         strcat(cpu_model, "GXm");
 479                         break;
 480                 case 0x600:
 481                         strcat(cpu_model, "6x86MX");
 482                         break;
 483                 default:
 484                         /*
 485                          * Even though CPU supports the cpuid
 486                          * instruction, it can be disabled.
 487                          * Therefore, this routine supports all Cyrix
 488                          * CPUs.
 489                          */
 490                         switch (cyrix_did & 0xf0) {
 491                         case 0x00:
 492                                 switch (cyrix_did & 0x0f) {
 493                                 case 0x00:
 494                                         strcat(cpu_model, "486SLC");
 495                                         break;
 496                                 case 0x01:
 497                                         strcat(cpu_model, "486DLC");
 498                                         break;
 499                                 case 0x02:
 500                                         strcat(cpu_model, "486SLC2");
 501                                         break;
 502                                 case 0x03:
 503                                         strcat(cpu_model, "486DLC2");
 504                                         break;
 505                                 case 0x04:
 506                                         strcat(cpu_model, "486SRx");
 507                                         break;
 508                                 case 0x05:
 509                                         strcat(cpu_model, "486DRx");
 510                                         break;
 511                                 case 0x06:
 512                                         strcat(cpu_model, "486SRx2");
 513                                         break;
 514                                 case 0x07:
 515                                         strcat(cpu_model, "486DRx2");
 516                                         break;
 517                                 case 0x08:
 518                                         strcat(cpu_model, "486SRu");
 519                                         break;
 520                                 case 0x09:
 521                                         strcat(cpu_model, "486DRu");
 522                                         break;
 523                                 case 0x0a:
 524                                         strcat(cpu_model, "486SRu2");
 525                                         break;
 526                                 case 0x0b:
 527                                         strcat(cpu_model, "486DRu2");
 528                                         break;
 529                                 default:
 530                                         strcat(cpu_model, "Unknown");
 531                                         break;
 532                                 }
 533                                 break;
 534                         case 0x10:
 535                                 switch (cyrix_did & 0x0f) {
 536                                 case 0x00:
 537                                         strcat(cpu_model, "486S");
 538                                         break;
 539                                 case 0x01:
 540                                         strcat(cpu_model, "486S2");
 541                                         break;
 542                                 case 0x02:
 543                                         strcat(cpu_model, "486Se");
 544                                         break;
 545                                 case 0x03:
 546                                         strcat(cpu_model, "486S2e");
 547                                         break;
 548                                 case 0x0a:
 549                                         strcat(cpu_model, "486DX");
 550                                         break;
 551                                 case 0x0b:
 552                                         strcat(cpu_model, "486DX2");
 553                                         break;
 554                                 case 0x0f:
 555                                         strcat(cpu_model, "486DX4");
 556                                         break;
 557                                 default:
 558                                         strcat(cpu_model, "Unknown");
 559                                         break;
 560                                 }
 561                                 break;
 562                         case 0x20:
 563                                 if ((cyrix_did & 0x0f) < 8)
 564                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 565                                 else
 566                                         strcat(cpu_model, "5x86");
 567                                 break;
 568                         case 0x30:
 569                                 strcat(cpu_model, "6x86");
 570                                 break;
 571                         case 0x40:
 572                                 if ((cyrix_did & 0xf000) == 0x3000) {
 573                                         cpu_class = CPUCLASS_586;
 574                                         strcat(cpu_model, "GXm");
 575                                 } else
 576                                         strcat(cpu_model, "MediaGX");
 577                                 break;
 578                         case 0x50:
 579                                 strcat(cpu_model, "6x86MX");
 580                                 break;
 581                         case 0xf0:
 582                                 switch (cyrix_did & 0x0f) {
 583                                 case 0x0d:
 584                                         strcat(cpu_model, "Overdrive CPU");
 585                                         break;
 586                                 case 0x0e:
 587                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 588                                         break;
 589                                 case 0x0f:
 590                                         strcat(cpu_model, "486SLC/DLC");
 591                                         break;
 592                                 default:
 593                                         strcat(cpu_model, "Unknown");
 594                                         break;
 595                                 }
 596                                 break;
 597                         default:
 598                                 strcat(cpu_model, "Unknown");
 599                                 break;
 600                         }
 601                         break;
 602                 }
 603                 break;
 604         case CPU_VENDOR_RISE:
 605                 strcpy(cpu_model, "Rise ");
 606                 switch (cpu_id & 0xff0) {
 607                 case 0x500:     /* 6401 and 6441 (Kirin) */
 608                 case 0x520:     /* 6510 (Lynx) */
 609                         strcat(cpu_model, "mP6");
 610                         break;
 611                 default:
 612                         strcat(cpu_model, "Unknown");
 613                 }
 614                 break;
 615 #endif
 616         case CPU_VENDOR_CENTAUR:
 617 #ifdef __i386__
 618                 switch (cpu_id & 0xff0) {
 619                 case 0x540:
 620                         strcpy(cpu_model, "IDT WinChip C6");
 621                         break;
 622                 case 0x580:
 623                         strcpy(cpu_model, "IDT WinChip 2");
 624                         break;
 625                 case 0x590:
 626                         strcpy(cpu_model, "IDT WinChip 3");
 627                         break;
 628                 case 0x660:
 629                         strcpy(cpu_model, "VIA C3 Samuel");
 630                         break;
 631                 case 0x670:
 632                         if (cpu_id & 0x8)
 633                                 strcpy(cpu_model, "VIA C3 Ezra");
 634                         else
 635                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 636                         break;
 637                 case 0x680:
 638                         strcpy(cpu_model, "VIA C3 Ezra-T");
 639                         break;
 640                 case 0x690:
 641                         strcpy(cpu_model, "VIA C3 Nehemiah");
 642                         break;
 643                 case 0x6a0:
 644                 case 0x6d0:
 645                         strcpy(cpu_model, "VIA C7 Esther");
 646                         break;
 647                 case 0x6f0:
 648                         strcpy(cpu_model, "VIA Nano");
 649                         break;
 650                 default:
 651                         strcpy(cpu_model, "VIA/IDT Unknown");
 652                 }
 653 #else
 654                 strcpy(cpu_model, "VIA ");
 655                 if ((cpu_id & 0xff0) == 0x6f0)
 656                         strcat(cpu_model, "Nano Processor");
 657                 else
 658                         strcat(cpu_model, "Unknown");
 659 #endif
 660                 break;
 661 #ifdef __i386__
 662         case CPU_VENDOR_IBM:
 663                 strcpy(cpu_model, "Blue Lightning CPU");
 664                 break;
 665         case CPU_VENDOR_NSC:
 666                 switch (cpu_id & 0xff0) {
 667                 case 0x540:
 668                         strcpy(cpu_model, "Geode SC1100");
 669                         cpu = CPU_GEODE1100;
 670                         break;
 671                 default:
 672                         strcpy(cpu_model, "Geode/NSC unknown");
 673                         break;
 674                 }
 675                 break;
 676 #endif
 677         default:
 678                 strcat(cpu_model, "Unknown");
 679                 break;
 680         }
 681
 682         /*
 683          * Replace cpu_model with cpu_brand minus leading spaces if
 684          * we have one.
 685          */
 686         brand = cpu_brand;
 687         while (*brand == ' ')
 688                 ++brand;
 689         if (*brand != '\0')
 690                 strcpy(cpu_model, brand);
 691
 692         printf("%s (", cpu_model);
 693         if (tsc_freq != 0) {
 694                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 695                 printf("%jd.%02d-MHz ",
 696                     (intmax_t)(tsc_freq + 4999) / 1000000,
 697                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 698         }
 699 #ifdef __i386__
 700         switch(cpu_class) {
 701         case CPUCLASS_286:
 702                 printf("286");
 703                 break;
 704         case CPUCLASS_386:
 705                 printf("386");
 706                 break;
 707 #if defined(I486_CPU)
 708         case CPUCLASS_486:
 709                 printf("486");
 710                 break;
 711 #endif
 712 #if defined(I586_CPU)
 713         case CPUCLASS_586:
 714                 printf("586");
 715                 break;
 716 #endif
 717 #if defined(I686_CPU)
 718         case CPUCLASS_686:
 719                 printf("686");
 720                 break;
 721 #endif
 722         default:
 723                 printf("Unknown");      /* will panic below... */
 724         }
 725 #else
 726         printf("K8");
 727 #endif
 728         printf("-class CPU)\n");
 729         if (*cpu_vendor)
 730                 printf("  Origin=\"%s\"", cpu_vendor);
 731         if (cpu_id)
 732                 printf("  Id=0x%x", cpu_id);
 733
 734         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 735             cpu_vendor_id == CPU_VENDOR_AMD ||
 736             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 737 #ifdef __i386__
 738             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 739             cpu_vendor_id == CPU_VENDOR_RISE ||
 740             cpu_vendor_id == CPU_VENDOR_NSC ||
 741             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 742 #endif
 743             0) {
 744                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 745                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 746                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 747 #ifdef __i386__
 748                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 749                         printf("\n  DIR=0x%04x", cyrix_did);
 750 #endif
 751
 752                 /*
 753                  * AMD CPUID Specification
 754                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 755                  *
 756                  * Intel Processor Identification and CPUID Instruction
 757                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 758                  */
 759                 if (cpu_high > 0) {
 760
 761                         /*
 762                          * Here we should probably set up flags indicating
 763                          * whether or not various features are available.
 764                          * The interesting ones are probably VME, PSE, PAE,
 765                          * and PGE.  The code already assumes without bothering
 766                          * to check that all CPUs >= Pentium have a TSC and
 767                          * MSRs.
 768                          */
 769                         printf("\n  Features=0x%b", cpu_feature,
 770                         "\020"
 771                         "\001FPU"       /* Integral FPU */
 772                         "\002VME"       /* Extended VM86 mode support */
 773                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 774                         "\004PSE"       /* 4MByte page tables */
 775                         "\005TSC"       /* Timestamp counter */
 776                         "\006MSR"       /* Machine specific registers */
 777                         "\007PAE"       /* Physical address extension */
 778                         "\010MCE"       /* Machine Check support */
 779                         "\011CX8"       /* CMPEXCH8 instruction */
 780                         "\012APIC"      /* SMP local APIC */
 781                         "\013oldMTRR"   /* Previous implementation of MTRR */
 782                         "\014SEP"       /* Fast System Call */
 783                         "\015MTRR"      /* Memory Type Range Registers */
 784                         "\016PGE"       /* PG_G (global bit) support */
 785                         "\017MCA"       /* Machine Check Architecture */
 786                         "\020CMOV"      /* CMOV instruction */
 787                         "\021PAT"       /* Page attributes table */
 788                         "\022PSE36"     /* 36 bit address space support */
 789                         "\023PN"        /* Processor Serial number */
 790                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 791                         "\025<b20>"
 792                         "\026DTS"       /* Debug Trace Store */
 793                         "\027ACPI"      /* ACPI support */
 794                         "\030MMX"       /* MMX instructions */
 795                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 796                         "\032SSE"       /* Streaming SIMD Extensions */
 797                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 798                         "\034SS"        /* Self snoop */
 799                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 800                         "\036TM"        /* Thermal Monitor clock slowdown */
 801                         "\037IA64"      /* CPU can execute IA64 instructions */
 802                         "\040PBE"       /* Pending Break Enable */
 803                         );
 804
 805                         if (cpu_feature2 != 0) {
 806                                 printf("\n  Features2=0x%b", cpu_feature2,
 807                                 "\020"
 808                                 "\001SSE3"      /* SSE3 */
 809                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 810                                 "\003DTES64"    /* 64-bit Debug Trace */
 811                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 812                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 813                                 "\006VMX"       /* Virtual Machine Extensions */
 814                                 "\007SMX"       /* Safer Mode Extensions */
 815                                 "\010EST"       /* Enhanced SpeedStep */
 816                                 "\011TM2"       /* Thermal Monitor 2 */
 817                                 "\012SSSE3"     /* SSSE3 */
 818                                 "\013CNXT-ID"   /* L1 context ID available */
 819                                 "\014SDBG"      /* IA32 silicon debug */
 820                                 "\015FMA"       /* Fused Multiply Add */
 821                                 "\016CX16"      /* CMPXCHG16B Instruction */
 822                                 "\017xTPR"      /* Send Task Priority Messages*/
 823                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 824                                 "\021<b16>"
 825                                 "\022PCID"      /* Process-context Identifiers*/
 826                                 "\023DCA"       /* Direct Cache Access */
 827                                 "\024SSE4.1"    /* SSE 4.1 */
 828                                 "\025SSE4.2"    /* SSE 4.2 */
 829                                 "\026x2APIC"    /* xAPIC Extensions */
 830                                 "\027MOVBE"     /* MOVBE Instruction */
 831                                 "\030POPCNT"    /* POPCNT Instruction */
 832                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 833                                 "\032AESNI"     /* AES Crypto */
 834                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 835                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 836                                 "\035AVX"       /* Advanced Vector Extensions */
 837                                 "\036F16C"      /* Half-precision conversions */
 838                                 "\037RDRAND"    /* RDRAND Instruction */
 839                                 "\040HV"        /* Hypervisor */
 840                                 );
 841                         }
 842
 843                         if (amd_feature != 0) {
 844                                 printf("\n  AMD Features=0x%b", amd_feature,
 845                                 "\020"          /* in hex */
 846                                 "\001<s0>"      /* Same */
 847                                 "\002<s1>"      /* Same */
 848                                 "\003<s2>"      /* Same */
 849                                 "\004<s3>"      /* Same */
 850                                 "\005<s4>"      /* Same */
 851                                 "\006<s5>"      /* Same */
 852                                 "\007<s6>"      /* Same */
 853                                 "\010<s7>"      /* Same */
 854                                 "\011<s8>"      /* Same */
 855                                 "\012<s9>"      /* Same */
 856                                 "\013<b10>"     /* Undefined */
 857                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 858                                 "\015<s12>"     /* Same */
 859                                 "\016<s13>"     /* Same */
 860                                 "\017<s14>"     /* Same */
 861                                 "\020<s15>"     /* Same */
 862                                 "\021<s16>"     /* Same */
 863                                 "\022<s17>"     /* Same */
 864                                 "\023<b18>"     /* Reserved, unknown */
 865                                 "\024MP"        /* Multiprocessor Capable */
 866                                 "\025NX"        /* Has EFER.NXE, NX */
 867                                 "\026<b21>"     /* Undefined */
 868                                 "\027MMX+"      /* AMD MMX Extensions */
 869                                 "\030<s23>"     /* Same */
 870                                 "\031<s24>"     /* Same */
 871                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 872                                 "\033Page1GB"   /* 1-GB large page support */
 873                                 "\034RDTSCP"    /* RDTSCP */
 874                                 "\035<b28>"     /* Undefined */
 875                                 "\036LM"        /* 64 bit long mode */
 876                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 877                                 "\0403DNow!"    /* AMD 3DNow! */
 878                                 );
 879                         }
 880
 881                         if (amd_feature2 != 0) {
 882                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 883                                 "\020"
 884                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 885                                 "\002CMP"       /* CMP legacy */
 886                                 "\003SVM"       /* Secure Virtual Mode */
 887                                 "\004ExtAPIC"   /* Extended APIC register */
 888                                 "\005CR8"       /* CR8 in legacy mode */
 889                                 "\006ABM"       /* LZCNT instruction */
 890                                 "\007SSE4A"     /* SSE4A */
 891                                 "\010MAS"       /* Misaligned SSE mode */
 892                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 893                                 "\012OSVW"      /* OS visible workaround */
 894                                 "\013IBS"       /* Instruction based sampling */
 895                                 "\014XOP"       /* XOP extended instructions */
 896                                 "\015SKINIT"    /* SKINIT/STGI */
 897                                 "\016WDT"       /* Watchdog timer */
 898                                 "\017<b14>"
 899                                 "\020LWP"       /* Lightweight Profiling */
 900                                 "\021FMA4"      /* 4-operand FMA instructions */
 901                                 "\022TCE"       /* Translation Cache Extension */
 902                                 "\023<b18>"
 903                                 "\024NodeId"    /* NodeId MSR support */
 904                                 "\025<b20>"
 905                                 "\026TBM"       /* Trailing Bit Manipulation */
 906                                 "\027Topology"  /* Topology Extensions */
 907                                 "\030PCXC"      /* Core perf count */
 908                                 "\031PNXC"      /* NB perf count */
 909                                 "\032<b25>"
 910                                 "\033DBE"       /* Data Breakpoint extension */
 911                                 "\034PTSC"      /* Performance TSC */
 912                                 "\035PL2I"      /* L2I perf count */
 913                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 914                                 "\037<b30>"
 915                                 "\040<b31>"
 916                                 );
 917                         }
 918
 919                         if (cpu_stdext_feature != 0) {
 920                                 printf("\n  Structured Extended Features=0x%b",
 921                                     cpu_stdext_feature,
 922                                        "\020"
 923                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 924                                        "\001FSGSBASE"
 925                                        "\002TSCADJ"
 926                                        "\003SGX"
 927                                        /* Bit Manipulation Instructions */
 928                                        "\004BMI1"
 929                                        /* Hardware Lock Elision */
 930                                        "\005HLE"
 931                                        /* Advanced Vector Instructions 2 */
 932                                        "\006AVX2"
 933                                        /* FDP_EXCPTN_ONLY */
 934                                        "\007FDPEXC"
 935                                        /* Supervisor Mode Execution Prot. */
 936                                        "\010SMEP"
 937                                        /* Bit Manipulation Instructions */
 938                                        "\011BMI2"
 939                                        "\012ERMS"
 940                                        /* Invalidate Processor Context ID */
 941                                        "\013INVPCID"
 942                                        /* Restricted Transactional Memory */
 943                                        "\014RTM"
 944                                        "\015PQM"
 945                                        "\016NFPUSG"
 946                                        /* Intel Memory Protection Extensions */
 947                                        "\017MPX"
 948                                        "\020PQE"
 949                                        /* AVX512 Foundation */
 950                                        "\021AVX512F"
 951                                        "\022AVX512DQ"
 952                                        /* Enhanced NRBG */
 953                                        "\023RDSEED"
 954                                        /* ADCX + ADOX */
 955                                        "\024ADX"
 956                                        /* Supervisor Mode Access Prevention */
 957                                        "\025SMAP"
 958                                        "\026AVX512IFMA"
 959                                        "\027PCOMMIT"
 960                                        "\030CLFLUSHOPT"
 961                                        "\031CLWB"
 962                                        "\032PROCTRACE"
 963                                        "\033AVX512PF"
 964                                        "\034AVX512ER"
 965                                        "\035AVX512CD"
 966                                        "\036SHA"
 967                                        "\037AVX512BW"
 968                                        "\040AVX512VL"
 969                                        );
 970                         }
 971
 972                         if (cpu_stdext_feature2 != 0) {
 973                                 printf("\n  Structured Extended Features2=0x%b",
 974                                     cpu_stdext_feature2,
 975                                        "\020"
 976                                        "\001PREFETCHWT1"
 977                                        "\002AVX512VBMI"
 978                                        "\003UMIP"
 979                                        "\004PKU"
 980                                        "\005OSPKE"
 981                                        "\027RDPID"
 982                                        "\037SGXLC"
 983                                        );
 984                         }
 985
 986                         if (cpu_stdext_feature3 != 0) {
 987                                 printf("\n  Structured Extended Features3=0x%b",
 988                                     cpu_stdext_feature3,
 989                                        "\020"
 990                                        "\033IBPB"
 991                                        "\034STIBP"
 992                                        "\036ARCH_CAP"
 993                                        );
 994                         }
 995
 996                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
 997                                 cpuid_count(0xd, 0x1, regs);
 998                                 if (regs[0] != 0) {
 999                                         printf("\n  XSAVE Features=0x%b",
1000                                             regs[0],
1001                                             "\020"
1002                                             "\001XSAVEOPT"
1003                                             "\002XSAVEC"
1004                                             "\003XINUSE"
1005                                             "\004XSAVES");
1006                                 }
1007                         }
1008
1009                         if (cpu_ia32_arch_caps != 0) {
1010                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1011                                     (u_int)cpu_ia32_arch_caps,
1012                                        "\020"
1013                                        "\001RDCL_NO"
1014                                        "\002IBRS_ALL"
1015                                        );
1016                         }
1017
1018                         if (amd_extended_feature_extensions != 0) {
1019                                 printf("\n  "
1020                                     "AMD Extended Feature Extensions ID EBX="
1021                                     "0x%b", amd_extended_feature_extensions,
1022                                     "\020"
1023                                     "\001CLZERO"
1024                                     "\002IRPerf"
1025                                     "\003XSaveErPtr");
1026                         }
1027
1028                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1029                                 print_via_padlock_info();
1030
1031                         if (cpu_feature2 & CPUID2_VMX)
1032                                 print_vmx_info();
1033
1034                         if (amd_feature2 & AMDID2_SVM)
1035                                 print_svm_info();
1036
1037                         if ((cpu_feature & CPUID_HTT) &&
1038                             cpu_vendor_id == CPU_VENDOR_AMD)
1039                                 cpu_feature &= ~CPUID_HTT;
1040
1041                         /*
1042                          * If this CPU supports P-state invariant TSC then
1043                          * mention the capability.
1044                          */
1045                         if (tsc_is_invariant) {
1046                                 printf("\n  TSC: P-state invariant");
1047                                 if (tsc_perf_stat)
1048                                         printf(", performance statistics");
1049                         }
1050                 }
1051 #ifdef __i386__
1052         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1053                 printf("  DIR=0x%04x", cyrix_did);
1054                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1055                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1056 #ifndef CYRIX_CACHE_REALLY_WORKS
1057                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1058                         printf("\n  CPU cache: write-through mode");
1059 #endif
1060 #endif
1061         }
1062
1063         /* Avoid ugly blank lines: only print newline when we have to. */
1064         if (*cpu_vendor || cpu_id)
1065                 printf("\n");
1066
1067         if (bootverbose) {
1068                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1069                         print_AMD_info();
1070                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1071                         print_INTEL_info();
1072 #ifdef __i386__
1073                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1074                         print_transmeta_info();
1075 #endif
1076         }
1077
1078         print_hypervisor_info();
1079 }
1080
1081 #ifdef __i386__
1082 void
1083 panicifcpuunsupported(void)
1084 {
1085
1086 #if !defined(lint)
1087 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1088 #error This kernel is not configured for one of the supported CPUs
1089 #endif
1090 #else /* lint */
1091 #endif /* lint */
1092         /*
1093          * Now that we have told the user what they have,
1094          * let them know if that machine type isn't configured.
1095          */
1096         switch (cpu_class) {
1097         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1098         case CPUCLASS_386:
1099 #if !defined(I486_CPU)
1100         case CPUCLASS_486:
1101 #endif
1102 #if !defined(I586_CPU)
1103         case CPUCLASS_586:
1104 #endif
1105 #if !defined(I686_CPU)
1106         case CPUCLASS_686:
1107 #endif
1108                 panic("CPU class not configured");
1109         default:
1110                 break;
1111         }
1112 }
1113
1114 static  volatile u_int trap_by_rdmsr;
1115
1116 /*
1117  * Special exception 6 handler.
1118  * The rdmsr instruction generates invalid opcodes fault on 486-class
1119  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1120  * function identblue() when this handler is called.  Stacked eip should
1121  * be advanced.
1122  */
1123 inthand_t       bluetrap6;
1124 #ifdef __GNUCLIKE_ASM
1125 __asm
1126 ("                                                                      \n\
1127         .text                                                           \n\
1128         .p2align 2,0x90                                                 \n\
1129         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1130 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1131         ss                                                              \n\
1132         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1133         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1134         iret                                                            \n\
1135 ");
1136 #endif
1137
1138 /*
1139  * Special exception 13 handler.
1140  * Accessing non-existent MSR generates general protection fault.
1141  */
1142 inthand_t       bluetrap13;
1143 #ifdef __GNUCLIKE_ASM
1144 __asm
1145 ("                                                                      \n\
1146         .text                                                           \n\
1147         .p2align 2,0x90                                                 \n\
1148         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1149 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1150         ss                                                              \n\
1151         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1152         popl    %eax            /* discard error code */                \n\
1153         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1154         iret                                                            \n\
1155 ");
1156 #endif
1157
1158 /*
1159  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1160  * support cpuid instruction.  This function should be called after
1161  * loading interrupt descriptor table register.
1162  *
1163  * I don't like this method that handles fault, but I couldn't get
1164  * information for any other methods.  Does blue giant know?
1165  */
1166 static int
1167 identblue(void)
1168 {
1169
1170         trap_by_rdmsr = 0;
1171
1172         /*
1173          * Cyrix 486-class CPU does not support rdmsr instruction.
1174          * The rdmsr instruction generates invalid opcode fault, and exception
1175          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1176          * bluetrap6() set the magic number to trap_by_rdmsr.
1177          */
1178         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1179             GSEL(GCODE_SEL, SEL_KPL));
1180
1181         /*
1182          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1183          * In this case, rdmsr generates general protection fault, and
1184          * exception will be trapped by bluetrap13().
1185          */
1186         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1187             GSEL(GCODE_SEL, SEL_KPL));
1188
1189         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1190
1191         if (trap_by_rdmsr == 0xa8c1d)
1192                 return IDENTBLUE_CYRIX486;
1193         else if (trap_by_rdmsr == 0xa89c4)
1194                 return IDENTBLUE_CYRIXM2;
1195         return IDENTBLUE_IBMCPU;
1196 }
1197
1198
1199 /*
1200  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1201  *
1202  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1203  * +-------+-------+---------------+
1204  * |  SID  |  RID  |   Device ID   |
1205  * |    (DIR 1)    |    (DIR 0)    |
1206  * +-------+-------+---------------+
1207  */
1208 static void
1209 identifycyrix(void)
1210 {
1211         register_t saveintr;
1212         int     ccr2_test = 0, dir_test = 0;
1213         u_char  ccr2, ccr3;
1214
1215         saveintr = intr_disable();
1216
1217         ccr2 = read_cyrix_reg(CCR2);
1218         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1219         read_cyrix_reg(CCR2);
1220         if (read_cyrix_reg(CCR2) != ccr2)
1221                 ccr2_test = 1;
1222         write_cyrix_reg(CCR2, ccr2);
1223
1224         ccr3 = read_cyrix_reg(CCR3);
1225         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1226         read_cyrix_reg(CCR3);
1227         if (read_cyrix_reg(CCR3) != ccr3)
1228                 dir_test = 1;                                   /* CPU supports DIRs. */
1229         write_cyrix_reg(CCR3, ccr3);
1230
1231         if (dir_test) {
1232                 /* Device ID registers are available. */
1233                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1234                 cyrix_did += read_cyrix_reg(DIR0);
1235         } else if (ccr2_test)
1236                 cyrix_did = 0x0010;             /* 486S A-step */
1237         else
1238                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1239
1240         intr_restore(saveintr);
1241 }
1242 #endif
1243
1244 /* Update TSC freq with the value indicated by the caller. */
1245 static void
1246 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1247 {
1248
1249         /* If there was an error during the transition, don't do anything. */
1250         if (status != 0)
1251                 return;
1252
1253         /* Total setting for this level gives the new frequency in MHz. */
1254         hw_clockrate = level->total_set.freq;
1255 }
1256
1257 static void
1258 hook_tsc_freq(void *arg __unused)
1259 {
1260
1261         if (tsc_is_invariant)
1262                 return;
1263
1264         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1265             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1266 }
1267
1268 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1269
1270 static const char *const vm_bnames[] = {
1271         "QEMU",                         /* QEMU */
1272         "Plex86",                       /* Plex86 */
1273         "Bochs",                        /* Bochs */
1274         "Xen",                          /* Xen */
1275         "BHYVE",                        /* bhyve */
1276         "Seabios",                      /* KVM */
1277         NULL
1278 };
1279
1280 static const char *const vm_pnames[] = {
1281         "VMware Virtual Platform",      /* VMWare VM */
1282         "Virtual Machine",              /* Microsoft VirtualPC */
1283         "VirtualBox",                   /* Sun xVM VirtualBox */
1284         "Parallels Virtual Platform",   /* Parallels VM */
1285         "KVM",                          /* KVM */
1286         NULL
1287 };
1288
1289 void
1290 identify_hypervisor(void)
1291 {
1292         u_int regs[4];
1293         char *p;
1294         int i;
1295
1296         /*
1297          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1298          * http://lkml.org/lkml/2008/10/1/246
1299          *
1300          * KB1009458: Mechanisms to determine if software is running in
1301          * a VMware virtual machine
1302          * http://kb.vmware.com/kb/1009458
1303          */
1304         if (cpu_feature2 & CPUID2_HV) {
1305                 vm_guest = VM_GUEST_VM;
1306                 do_cpuid(0x40000000, regs);
1307                 if (regs[0] >= 0x40000000) {
1308                         hv_high = regs[0];
1309                         ((u_int *)&hv_vendor)[0] = regs[1];
1310                         ((u_int *)&hv_vendor)[1] = regs[2];
1311                         ((u_int *)&hv_vendor)[2] = regs[3];
1312                         hv_vendor[12] = '\0';
1313                         if (strcmp(hv_vendor, "VMwareVMware") == 0)
1314                                 vm_guest = VM_GUEST_VMWARE;
1315                         else if (strcmp(hv_vendor, "Microsoft Hv") == 0)
1316                                 vm_guest = VM_GUEST_HV;
1317                         else if (strcmp(hv_vendor, "KVMKVMKVM") == 0)
1318                                 vm_guest = VM_GUEST_KVM;
1319                         else if (strcmp(hv_vendor, "bhyve bhyve") == 0)
1320                                 vm_guest = VM_GUEST_BHYVE;
1321                 }
1322                 return;
1323         }
1324
1325         /*
1326          * Examine SMBIOS strings for older hypervisors.
1327          */
1328         p = kern_getenv("smbios.system.serial");
1329         if (p != NULL) {
1330                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1331                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1332                         if (regs[1] == VMW_HVMAGIC) {
1333                                 vm_guest = VM_GUEST_VMWARE;
1334                                 freeenv(p);
1335                                 return;
1336                         }
1337                 }
1338                 freeenv(p);
1339         }
1340
1341         /*
1342          * XXX: Some of these entries may not be needed since they were
1343          * added to FreeBSD before the checks above.
1344          */
1345         p = kern_getenv("smbios.bios.vendor");
1346         if (p != NULL) {
1347                 for (i = 0; vm_bnames[i] != NULL; i++)
1348                         if (strcmp(p, vm_bnames[i]) == 0) {
1349                                 vm_guest = VM_GUEST_VM;
1350                                 freeenv(p);
1351                                 return;
1352                         }
1353                 freeenv(p);
1354         }
1355         p = kern_getenv("smbios.system.product");
1356         if (p != NULL) {
1357                 for (i = 0; vm_pnames[i] != NULL; i++)
1358                         if (strcmp(p, vm_pnames[i]) == 0) {
1359                                 vm_guest = VM_GUEST_VM;
1360                                 freeenv(p);
1361                                 return;
1362                         }
1363                 freeenv(p);
1364         }
1365 }
1366
1367 bool
1368 fix_cpuid(void)
1369 {
1370         uint64_t msr;
1371
1372         /*
1373          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1374          * get the largest standard CPUID function number again if it is set
1375          * from BIOS.  It is necessary for probing correct CPU topology later
1376          * and for the correct operation of the AVX-aware userspace.
1377          */
1378         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1379             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1380             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1381             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1382             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1383                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1384                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1385                         msr &= ~IA32_MISC_EN_LIMCPUID;
1386                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1387                         return (true);
1388                 }
1389         }
1390
1391         /*
1392          * Re-enable AMD Topology Extension that could be disabled by BIOS
1393          * on some notebook processors.  Without the extension it's really
1394          * hard to determine the correct CPU cache topology.
1395          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1396          * Models 60h-6Fh Processors, Publication # 50742.
1397          */
1398         if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x15) {
1399                 msr = rdmsr(MSR_EXTFEATURES);
1400                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1401                         msr |= (uint64_t)1 << 54;
1402                         wrmsr(MSR_EXTFEATURES, msr);
1403                         return (true);
1404                 }
1405         }
1406         return (false);
1407 }
1408
1409 void
1410 identify_cpu1(void)
1411 {
1412         u_int regs[4];
1413
1414         do_cpuid(0, regs);
1415         cpu_high = regs[0];
1416         ((u_int *)&cpu_vendor)[0] = regs[1];
1417         ((u_int *)&cpu_vendor)[1] = regs[3];
1418         ((u_int *)&cpu_vendor)[2] = regs[2];
1419         cpu_vendor[12] = '\0';
1420
1421         do_cpuid(1, regs);
1422         cpu_id = regs[0];
1423         cpu_procinfo = regs[1];
1424         cpu_feature = regs[3];
1425         cpu_feature2 = regs[2];
1426 }
1427
1428 void
1429 identify_cpu2(void)
1430 {
1431         u_int regs[4], cpu_stdext_disable;
1432
1433         if (cpu_high >= 7) {
1434                 cpuid_count(7, 0, regs);
1435                 cpu_stdext_feature = regs[1];
1436
1437                 /*
1438                  * Some hypervisors failed to filter out unsupported
1439                  * extended features.  Allow to disable the
1440                  * extensions, activation of which requires setting a
1441                  * bit in CR4, and which VM monitors do not support.
1442                  */
1443                 cpu_stdext_disable = 0;
1444                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1445                 cpu_stdext_feature &= ~cpu_stdext_disable;
1446
1447                 cpu_stdext_feature2 = regs[2];
1448                 cpu_stdext_feature3 = regs[3];
1449
1450                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1451                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1452         }
1453 }
1454
1455 /*
1456  * Final stage of CPU identification.
1457  */
1458 void
1459 finishidentcpu(void)
1460 {
1461         u_int regs[4];
1462 #ifdef __i386__
1463         u_char ccr3;
1464 #endif
1465
1466         cpu_vendor_id = find_cpu_vendor_id();
1467
1468         if (fix_cpuid()) {
1469                 do_cpuid(0, regs);
1470                 cpu_high = regs[0];
1471         }
1472
1473         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1474                 do_cpuid(5, regs);
1475                 cpu_mon_mwait_flags = regs[2];
1476                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1477                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1478         }
1479
1480         identify_cpu2();
1481
1482 #ifdef __i386__
1483         if (cpu_high > 0 &&
1484             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1485              cpu_vendor_id == CPU_VENDOR_AMD ||
1486              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1487              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1488              cpu_vendor_id == CPU_VENDOR_NSC)) {
1489                 do_cpuid(0x80000000, regs);
1490                 if (regs[0] >= 0x80000000)
1491                         cpu_exthigh = regs[0];
1492         }
1493 #else
1494         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1495             cpu_vendor_id == CPU_VENDOR_AMD ||
1496             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1497                 do_cpuid(0x80000000, regs);
1498                 cpu_exthigh = regs[0];
1499         }
1500 #endif
1501         if (cpu_exthigh >= 0x80000001) {
1502                 do_cpuid(0x80000001, regs);
1503                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1504                 amd_feature2 = regs[2];
1505         }
1506         if (cpu_exthigh >= 0x80000007) {
1507                 do_cpuid(0x80000007, regs);
1508                 amd_rascap = regs[1];
1509                 amd_pminfo = regs[3];
1510         }
1511         if (cpu_exthigh >= 0x80000008) {
1512                 do_cpuid(0x80000008, regs);
1513                 cpu_maxphyaddr = regs[0] & 0xff;
1514                 amd_extended_feature_extensions = regs[1];
1515                 cpu_procinfo2 = regs[2];
1516         } else {
1517                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1518         }
1519
1520 #ifdef __i386__
1521         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1522                 if (cpu == CPU_486) {
1523                         /*
1524                          * These conditions are equivalent to:
1525                          *     - CPU does not support cpuid instruction.
1526                          *     - Cyrix/IBM CPU is detected.
1527                          */
1528                         if (identblue() == IDENTBLUE_IBMCPU) {
1529                                 strcpy(cpu_vendor, "IBM");
1530                                 cpu_vendor_id = CPU_VENDOR_IBM;
1531                                 cpu = CPU_BLUE;
1532                                 return;
1533                         }
1534                 }
1535                 switch (cpu_id & 0xf00) {
1536                 case 0x600:
1537                         /*
1538                          * Cyrix's datasheet does not describe DIRs.
1539                          * Therefor, I assume it does not have them
1540                          * and use the result of the cpuid instruction.
1541                          * XXX they seem to have it for now at least. -Peter
1542                          */
1543                         identifycyrix();
1544                         cpu = CPU_M2;
1545                         break;
1546                 default:
1547                         identifycyrix();
1548                         /*
1549                          * This routine contains a trick.
1550                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1551                          */
1552                         switch (cyrix_did & 0x00f0) {
1553                         case 0x00:
1554                         case 0xf0:
1555                                 cpu = CPU_486DLC;
1556                                 break;
1557                         case 0x10:
1558                                 cpu = CPU_CY486DX;
1559                                 break;
1560                         case 0x20:
1561                                 if ((cyrix_did & 0x000f) < 8)
1562                                         cpu = CPU_M1;
1563                                 else
1564                                         cpu = CPU_M1SC;
1565                                 break;
1566                         case 0x30:
1567                                 cpu = CPU_M1;
1568                                 break;
1569                         case 0x40:
1570                                 /* MediaGX CPU */
1571                                 cpu = CPU_M1SC;
1572                                 break;
1573                         default:
1574                                 /* M2 and later CPUs are treated as M2. */
1575                                 cpu = CPU_M2;
1576
1577                                 /*
1578                                  * enable cpuid instruction.
1579                                  */
1580                                 ccr3 = read_cyrix_reg(CCR3);
1581                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1582                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1583                                 write_cyrix_reg(CCR3, ccr3);
1584
1585                                 do_cpuid(0, regs);
1586                                 cpu_high = regs[0];     /* eax */
1587                                 do_cpuid(1, regs);
1588                                 cpu_id = regs[0];       /* eax */
1589                                 cpu_feature = regs[3];  /* edx */
1590                                 break;
1591                         }
1592                 }
1593         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1594                 /*
1595                  * There are BlueLightning CPUs that do not change
1596                  * undefined flags by dividing 5 by 2.  In this case,
1597                  * the CPU identification routine in locore.s leaves
1598                  * cpu_vendor null string and puts CPU_486 into the
1599                  * cpu.
1600                  */
1601                 if (identblue() == IDENTBLUE_IBMCPU) {
1602                         strcpy(cpu_vendor, "IBM");
1603                         cpu_vendor_id = CPU_VENDOR_IBM;
1604                         cpu = CPU_BLUE;
1605                         return;
1606                 }
1607         }
1608 #endif
1609 }
1610
1611 int
1612 pti_get_default(void)
1613 {
1614
1615         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1616                 return (0);
1617
1618         return (1);
1619 }
1620
1621 static u_int
1622 find_cpu_vendor_id(void)
1623 {
1624         int     i;
1625
1626         for (i = 0; i < nitems(cpu_vendors); i++)
1627                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1628                         return (cpu_vendors[i].vendor_id);
1629         return (0);
1630 }
1631
1632 static void
1633 print_AMD_assoc(int i)
1634 {
1635         if (i == 255)
1636                 printf(", fully associative\n");
1637         else
1638                 printf(", %d-way associative\n", i);
1639 }
1640
1641 static void
1642 print_AMD_l2_assoc(int i)
1643 {
1644         switch (i & 0x0f) {
1645         case 0: printf(", disabled/not present\n"); break;
1646         case 1: printf(", direct mapped\n"); break;
1647         case 2: printf(", 2-way associative\n"); break;
1648         case 4: printf(", 4-way associative\n"); break;
1649         case 6: printf(", 8-way associative\n"); break;
1650         case 8: printf(", 16-way associative\n"); break;
1651         case 15: printf(", fully associative\n"); break;
1652         default: printf(", reserved configuration\n"); break;
1653         }
1654 }
1655
1656 static void
1657 print_AMD_info(void)
1658 {
1659 #ifdef __i386__
1660         uint64_t amd_whcr;
1661 #endif
1662         u_int regs[4];
1663
1664         if (cpu_exthigh >= 0x80000005) {
1665                 do_cpuid(0x80000005, regs);
1666                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1667                 print_AMD_assoc(regs[0] >> 24);
1668
1669                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1670                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1671
1672                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1673                 print_AMD_assoc(regs[1] >> 24);
1674
1675                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1676                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1677
1678                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1679                 printf(", %d bytes/line", regs[2] & 0xff);
1680                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1681                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1682
1683                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1684                 printf(", %d bytes/line", regs[3] & 0xff);
1685                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1686                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1687         }
1688
1689         if (cpu_exthigh >= 0x80000006) {
1690                 do_cpuid(0x80000006, regs);
1691                 if ((regs[0] >> 16) != 0) {
1692                         printf("L2 2MB data TLB: %d entries",
1693                             (regs[0] >> 16) & 0xfff);
1694                         print_AMD_l2_assoc(regs[0] >> 28);
1695                         printf("L2 2MB instruction TLB: %d entries",
1696                             regs[0] & 0xfff);
1697                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1698                 } else {
1699                         printf("L2 2MB unified TLB: %d entries",
1700                             regs[0] & 0xfff);
1701                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1702                 }
1703                 if ((regs[1] >> 16) != 0) {
1704                         printf("L2 4KB data TLB: %d entries",
1705                             (regs[1] >> 16) & 0xfff);
1706                         print_AMD_l2_assoc(regs[1] >> 28);
1707
1708                         printf("L2 4KB instruction TLB: %d entries",
1709                             (regs[1] >> 16) & 0xfff);
1710                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1711                 } else {
1712                         printf("L2 4KB unified TLB: %d entries",
1713                             (regs[1] >> 16) & 0xfff);
1714                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1715                 }
1716                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1717                 printf(", %d bytes/line", regs[2] & 0xff);
1718                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1719                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1720         }
1721
1722 #ifdef __i386__
1723         if (((cpu_id & 0xf00) == 0x500)
1724             && (((cpu_id & 0x0f0) > 0x80)
1725                 || (((cpu_id & 0x0f0) == 0x80)
1726                     && (cpu_id & 0x00f) > 0x07))) {
1727                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1728                 amd_whcr = rdmsr(0xc0000082);
1729                 if (!(amd_whcr & (0x3ff << 22))) {
1730                         printf("Write Allocate Disable\n");
1731                 } else {
1732                         printf("Write Allocate Enable Limit: %dM bytes\n",
1733                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1734                         printf("Write Allocate 15-16M bytes: %s\n",
1735                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1736                 }
1737         } else if (((cpu_id & 0xf00) == 0x500)
1738                    && ((cpu_id & 0x0f0) > 0x50)) {
1739                 /* K6, K6-2(old core) */
1740                 amd_whcr = rdmsr(0xc0000082);
1741                 if (!(amd_whcr & (0x7f << 1))) {
1742                         printf("Write Allocate Disable\n");
1743                 } else {
1744                         printf("Write Allocate Enable Limit: %dM bytes\n",
1745                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1746                         printf("Write Allocate 15-16M bytes: %s\n",
1747                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1748                         printf("Hardware Write Allocate Control: %s\n",
1749                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1750                 }
1751         }
1752 #endif
1753         /*
1754          * Opteron Rev E shows a bug as in very rare occasions a read memory
1755          * barrier is not performed as expected if it is followed by a
1756          * non-atomic read-modify-write instruction.
1757          * As long as that bug pops up very rarely (intensive machine usage
1758          * on other operating systems generally generates one unexplainable
1759          * crash any 2 months) and as long as a model specific fix would be
1760          * impractical at this stage, print out a warning string if the broken
1761          * model and family are identified.
1762          */
1763         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1764             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1765                 printf("WARNING: This architecture revision has known SMP "
1766                     "hardware bugs which may cause random instability\n");
1767 }
1768
1769 static void
1770 print_INTEL_info(void)
1771 {
1772         u_int regs[4];
1773         u_int rounds, regnum;
1774         u_int nwaycode, nway;
1775
1776         if (cpu_high >= 2) {
1777                 rounds = 0;
1778                 do {
1779                         do_cpuid(0x2, regs);
1780                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1781                                 break;  /* we have a buggy CPU */
1782
1783                         for (regnum = 0; regnum <= 3; ++regnum) {
1784                                 if (regs[regnum] & (1<<31))
1785                                         continue;
1786                                 if (regnum != 0)
1787                                         print_INTEL_TLB(regs[regnum] & 0xff);
1788                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1789                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1790                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1791                         }
1792                 } while (--rounds > 0);
1793         }
1794
1795         if (cpu_exthigh >= 0x80000006) {
1796                 do_cpuid(0x80000006, regs);
1797                 nwaycode = (regs[2] >> 12) & 0x0f;
1798                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1799                         nway = 1 << (nwaycode / 2);
1800                 else
1801                         nway = 0;
1802                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1803                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1804         }
1805 }
1806
1807 static void
1808 print_INTEL_TLB(u_int data)
1809 {
1810         switch (data) {
1811         case 0x0:
1812         case 0x40:
1813         default:
1814                 break;
1815         case 0x1:
1816                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1817                 break;
1818         case 0x2:
1819                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1820                 break;
1821         case 0x3:
1822                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1823                 break;
1824         case 0x4:
1825                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1826                 break;
1827         case 0x6:
1828                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1829                 break;
1830         case 0x8:
1831                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1832                 break;
1833         case 0x9:
1834                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1835                 break;
1836         case 0xa:
1837                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1838                 break;
1839         case 0xb:
1840                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1841                 break;
1842         case 0xc:
1843                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1844                 break;
1845         case 0xd:
1846                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1847                 break;
1848         case 0xe:
1849                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1850                 break;
1851         case 0x1d:
1852                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
1853                 break;
1854         case 0x21:
1855                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
1856                 break;
1857         case 0x22:
1858                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1859                 break;
1860         case 0x23:
1861                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1862                 break;
1863         case 0x24:
1864                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
1865                 break;
1866         case 0x25:
1867                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1868                 break;
1869         case 0x29:
1870                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
1871                 break;
1872         case 0x2c:
1873                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
1874                 break;
1875         case 0x30:
1876                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
1877                 break;
1878         case 0x39: /* De-listed in SDM rev. 54 */
1879                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1880                 break;
1881         case 0x3b: /* De-listed in SDM rev. 54 */
1882                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
1883                 break;
1884         case 0x3c: /* De-listed in SDM rev. 54 */
1885                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1886                 break;
1887         case 0x41:
1888                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
1889                 break;
1890         case 0x42:
1891                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
1892                 break;
1893         case 0x43:
1894                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
1895                 break;
1896         case 0x44:
1897                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
1898                 break;
1899         case 0x45:
1900                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
1901                 break;
1902         case 0x46:
1903                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
1904                 break;
1905         case 0x47:
1906                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
1907                 break;
1908         case 0x48:
1909                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
1910                 break;
1911         case 0x49:
1912                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
1913                     CPUID_TO_MODEL(cpu_id) == 0x6)
1914                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
1915                 else
1916                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
1917                 break;
1918         case 0x4a:
1919                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
1920                 break;
1921         case 0x4b:
1922                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
1923                 break;
1924         case 0x4c:
1925                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
1926                 break;
1927         case 0x4d:
1928                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
1929                 break;
1930         case 0x4e:
1931                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
1932                 break;
1933         case 0x4f:
1934                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
1935                 break;
1936         case 0x50:
1937                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
1938                 break;
1939         case 0x51:
1940                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
1941                 break;
1942         case 0x52:
1943                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
1944                 break;
1945         case 0x55:
1946                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
1947                 break;
1948         case 0x56:
1949                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
1950                 break;
1951         case 0x57:
1952                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
1953                 break;
1954         case 0x59:
1955                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
1956                 break;
1957         case 0x5a:
1958                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
1959                 break;
1960         case 0x5b:
1961                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
1962                 break;
1963         case 0x5c:
1964                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
1965                 break;
1966         case 0x5d:
1967                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
1968                 break;
1969         case 0x60:
1970                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
1971                 break;
1972         case 0x61:
1973                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
1974                 break;
1975         case 0x63:
1976                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
1977                 break;
1978         case 0x64:
1979                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
1980                 break;
1981         case 0x66:
1982                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1983                 break;
1984         case 0x67:
1985                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
1986                 break;
1987         case 0x68:
1988                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
1989                 break;
1990         case 0x6a:
1991                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
1992                 break;
1993         case 0x6b:
1994                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
1995                 break;
1996         case 0x6c:
1997                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
1998                 break;
1999         case 0x6d:
2000                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2001                 break;
2002         case 0x70:
2003                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2004                 break;
2005         case 0x71:
2006                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2007                 break;
2008         case 0x72:
2009                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2010                 break;
2011         case 0x76:
2012                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2013                 break;
2014         case 0x78:
2015                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2016                 break;
2017         case 0x79:
2018                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2019                 break;
2020         case 0x7a:
2021                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2022                 break;
2023         case 0x7b:
2024                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2025                 break;
2026         case 0x7c:
2027                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2028                 break;
2029         case 0x7d:
2030                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2031                 break;
2032         case 0x7f:
2033                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2034                 break;
2035         case 0x80:
2036                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2037                 break;
2038         case 0x82:
2039                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2040                 break;
2041         case 0x83:
2042                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2043                 break;
2044         case 0x84:
2045                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2046                 break;
2047         case 0x85:
2048                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2049                 break;
2050         case 0x86:
2051                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2052                 break;
2053         case 0x87:
2054                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2055                 break;
2056         case 0xa0:
2057                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2058                 break;
2059         case 0xb0:
2060                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2061                 break;
2062         case 0xb1:
2063                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2064                 break;
2065         case 0xb2:
2066                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2067                 break;
2068         case 0xb3:
2069                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2070                 break;
2071         case 0xb4:
2072                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2073                 break;
2074         case 0xb5:
2075                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2076                 break;
2077         case 0xb6:
2078                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2079                 break;
2080         case 0xba:
2081                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2082                 break;
2083         case 0xc0:
2084                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2085                 break;
2086         case 0xc1:
2087                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2088                 break;
2089         case 0xc2:
2090                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2091                 break;
2092         case 0xc3:
2093                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2094                 break;
2095         case 0xc4:
2096                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2097                 break;
2098         case 0xca:
2099                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2100                 break;
2101         case 0xd0:
2102                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2103                 break;
2104         case 0xd1:
2105                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2106                 break;
2107         case 0xd2:
2108                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2109                 break;
2110         case 0xd6:
2111                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2112                 break;
2113         case 0xd7:
2114                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2115                 break;
2116         case 0xd8:
2117                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2118                 break;
2119         case 0xdc:
2120                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2121                 break;
2122         case 0xdd:
2123                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2124                 break;
2125         case 0xde:
2126                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2127                 break;
2128         case 0xe2:
2129                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2130                 break;
2131         case 0xe3:
2132                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2133                 break;
2134         case 0xe4:
2135                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2136                 break;
2137         case 0xea:
2138                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2139                 break;
2140         case 0xeb:
2141                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2142                 break;
2143         case 0xec:
2144                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2145                 break;
2146         case 0xf0:
2147                 printf("64-Byte prefetching\n");
2148                 break;
2149         case 0xf1:
2150                 printf("128-Byte prefetching\n");
2151                 break;
2152         }
2153 }
2154
2155 static void
2156 print_svm_info(void)
2157 {
2158         u_int features, regs[4];
2159         uint64_t msr;
2160         int comma;
2161
2162         printf("\n  SVM: ");
2163         do_cpuid(0x8000000A, regs);
2164         features = regs[3];
2165
2166         msr = rdmsr(MSR_VM_CR);
2167         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2168                 printf("(disabled in BIOS) ");
2169
2170         if (!bootverbose) {
2171                 comma = 0;
2172                 if (features & (1 << 0)) {
2173                         printf("%sNP", comma ? "," : "");
2174                         comma = 1;
2175                 }
2176                 if (features & (1 << 3)) {
2177                         printf("%sNRIP", comma ? "," : "");
2178                         comma = 1;
2179                 }
2180                 if (features & (1 << 5)) {
2181                         printf("%sVClean", comma ? "," : "");
2182                         comma = 1;
2183                 }
2184                 if (features & (1 << 6)) {
2185                         printf("%sAFlush", comma ? "," : "");
2186                         comma = 1;
2187                 }
2188                 if (features & (1 << 7)) {
2189                         printf("%sDAssist", comma ? "," : "");
2190                         comma = 1;
2191                 }
2192                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2193                 return;
2194         }
2195
2196         printf("Features=0x%b", features,
2197                "\020"
2198                "\001NP"                 /* Nested paging */
2199                "\002LbrVirt"            /* LBR virtualization */
2200                "\003SVML"               /* SVM lock */
2201                "\004NRIPS"              /* NRIP save */
2202                "\005TscRateMsr"         /* MSR based TSC rate control */
2203                "\006VmcbClean"          /* VMCB clean bits */
2204                "\007FlushByAsid"        /* Flush by ASID */
2205                "\010DecodeAssist"       /* Decode assist */
2206                "\011<b8>"
2207                "\012<b9>"
2208                "\013PauseFilter"        /* PAUSE intercept filter */
2209                "\014EncryptedMcodePatch"
2210                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2211                "\016AVIC"               /* virtual interrupt controller */
2212                "\017<b14>"
2213                "\020V_VMSAVE_VMLOAD"
2214                "\021vGIF"
2215                "\022<b17>"
2216                "\023<b18>"
2217                "\024<b19>"
2218                "\025<b20>"
2219                "\026<b21>"
2220                "\027<b22>"
2221                "\030<b23>"
2222                "\031<b24>"
2223                "\032<b25>"
2224                "\033<b26>"
2225                "\034<b27>"
2226                "\035<b28>"
2227                "\036<b29>"
2228                "\037<b30>"
2229                "\040<b31>"
2230                 );
2231         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2232 }
2233
2234 #ifdef __i386__
2235 static void
2236 print_transmeta_info(void)
2237 {
2238         u_int regs[4], nreg = 0;
2239
2240         do_cpuid(0x80860000, regs);
2241         nreg = regs[0];
2242         if (nreg >= 0x80860001) {
2243                 do_cpuid(0x80860001, regs);
2244                 printf("  Processor revision %u.%u.%u.%u\n",
2245                        (regs[1] >> 24) & 0xff,
2246                        (regs[1] >> 16) & 0xff,
2247                        (regs[1] >> 8) & 0xff,
2248                        regs[1] & 0xff);
2249         }
2250         if (nreg >= 0x80860002) {
2251                 do_cpuid(0x80860002, regs);
2252                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2253                        (regs[1] >> 24) & 0xff,
2254                        (regs[1] >> 16) & 0xff,
2255                        (regs[1] >> 8) & 0xff,
2256                        regs[1] & 0xff,
2257                        regs[2]);
2258         }
2259         if (nreg >= 0x80860006) {
2260                 char info[65];
2261                 do_cpuid(0x80860003, (u_int*) &info[0]);
2262                 do_cpuid(0x80860004, (u_int*) &info[16]);
2263                 do_cpuid(0x80860005, (u_int*) &info[32]);
2264                 do_cpuid(0x80860006, (u_int*) &info[48]);
2265                 info[64] = 0;
2266                 printf("  %s\n", info);
2267         }
2268 }
2269 #endif
2270
2271 static void
2272 print_via_padlock_info(void)
2273 {
2274         u_int regs[4];
2275
2276         do_cpuid(0xc0000001, regs);
2277         printf("\n  VIA Padlock Features=0x%b", regs[3],
2278         "\020"
2279         "\003RNG"               /* RNG */
2280         "\007AES"               /* ACE */
2281         "\011AES-CTR"           /* ACE2 */
2282         "\013SHA1,SHA256"       /* PHE */
2283         "\015RSA"               /* PMM */
2284         );
2285 }
2286
2287 static uint32_t
2288 vmx_settable(uint64_t basic, int msr, int true_msr)
2289 {
2290         uint64_t val;
2291
2292         if (basic & (1ULL << 55))
2293                 val = rdmsr(true_msr);
2294         else
2295                 val = rdmsr(msr);
2296
2297         /* Just report the controls that can be set to 1. */
2298         return (val >> 32);
2299 }
2300
2301 static void
2302 print_vmx_info(void)
2303 {
2304         uint64_t basic, msr;
2305         uint32_t entry, exit, mask, pin, proc, proc2;
2306         int comma;
2307
2308         printf("\n  VT-x: ");
2309         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2310         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2311                 printf("(disabled in BIOS) ");
2312         basic = rdmsr(MSR_VMX_BASIC);
2313         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2314             MSR_VMX_TRUE_PINBASED_CTLS);
2315         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2316             MSR_VMX_TRUE_PROCBASED_CTLS);
2317         if (proc & PROCBASED_SECONDARY_CONTROLS)
2318                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2319                     MSR_VMX_PROCBASED_CTLS2);
2320         else
2321                 proc2 = 0;
2322         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2323         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2324
2325         if (!bootverbose) {
2326                 comma = 0;
2327                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2328                     entry & VM_ENTRY_LOAD_PAT) {
2329                         printf("%sPAT", comma ? "," : "");
2330                         comma = 1;
2331                 }
2332                 if (proc & PROCBASED_HLT_EXITING) {
2333                         printf("%sHLT", comma ? "," : "");
2334                         comma = 1;
2335                 }
2336                 if (proc & PROCBASED_MTF) {
2337                         printf("%sMTF", comma ? "," : "");
2338                         comma = 1;
2339                 }
2340                 if (proc & PROCBASED_PAUSE_EXITING) {
2341                         printf("%sPAUSE", comma ? "," : "");
2342                         comma = 1;
2343                 }
2344                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2345                         printf("%sEPT", comma ? "," : "");
2346                         comma = 1;
2347                 }
2348                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2349                         printf("%sUG", comma ? "," : "");
2350                         comma = 1;
2351                 }
2352                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2353                         printf("%sVPID", comma ? "," : "");
2354                         comma = 1;
2355                 }
2356                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2357                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2358                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2359                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2360                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2361                         printf("%sVID", comma ? "," : "");
2362                         comma = 1;
2363                         if (pin & PINBASED_POSTED_INTERRUPT)
2364                                 printf(",PostIntr");
2365                 }
2366                 return;
2367         }
2368
2369         mask = basic >> 32;
2370         printf("Basic Features=0x%b", mask,
2371         "\020"
2372         "\02132PA"              /* 32-bit physical addresses */
2373         "\022SMM"               /* SMM dual-monitor */
2374         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2375         "\030TRUE"              /* TRUE_CTLS MSRs */
2376         );
2377         printf("\n        Pin-Based Controls=0x%b", pin,
2378         "\020"
2379         "\001ExtINT"            /* External-interrupt exiting */
2380         "\004NMI"               /* NMI exiting */
2381         "\006VNMI"              /* Virtual NMIs */
2382         "\007PreTmr"            /* Activate VMX-preemption timer */
2383         "\010PostIntr"          /* Process posted interrupts */
2384         );
2385         printf("\n        Primary Processor Controls=0x%b", proc,
2386         "\020"
2387         "\003INTWIN"            /* Interrupt-window exiting */
2388         "\004TSCOff"            /* Use TSC offsetting */
2389         "\010HLT"               /* HLT exiting */
2390         "\012INVLPG"            /* INVLPG exiting */
2391         "\013MWAIT"             /* MWAIT exiting */
2392         "\014RDPMC"             /* RDPMC exiting */
2393         "\015RDTSC"             /* RDTSC exiting */
2394         "\020CR3-LD"            /* CR3-load exiting */
2395         "\021CR3-ST"            /* CR3-store exiting */
2396         "\024CR8-LD"            /* CR8-load exiting */
2397         "\025CR8-ST"            /* CR8-store exiting */
2398         "\026TPR"               /* Use TPR shadow */
2399         "\027NMIWIN"            /* NMI-window exiting */
2400         "\030MOV-DR"            /* MOV-DR exiting */
2401         "\031IO"                /* Unconditional I/O exiting */
2402         "\032IOmap"             /* Use I/O bitmaps */
2403         "\034MTF"               /* Monitor trap flag */
2404         "\035MSRmap"            /* Use MSR bitmaps */
2405         "\036MONITOR"           /* MONITOR exiting */
2406         "\037PAUSE"             /* PAUSE exiting */
2407         );
2408         if (proc & PROCBASED_SECONDARY_CONTROLS)
2409                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2410                 "\020"
2411                 "\001APIC"              /* Virtualize APIC accesses */
2412                 "\002EPT"               /* Enable EPT */
2413                 "\003DT"                /* Descriptor-table exiting */
2414                 "\004RDTSCP"            /* Enable RDTSCP */
2415                 "\005x2APIC"            /* Virtualize x2APIC mode */
2416                 "\006VPID"              /* Enable VPID */
2417                 "\007WBINVD"            /* WBINVD exiting */
2418                 "\010UG"                /* Unrestricted guest */
2419                 "\011APIC-reg"          /* APIC-register virtualization */
2420                 "\012VID"               /* Virtual-interrupt delivery */
2421                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2422                 "\014RDRAND"            /* RDRAND exiting */
2423                 "\015INVPCID"           /* Enable INVPCID */
2424                 "\016VMFUNC"            /* Enable VM functions */
2425                 "\017VMCS"              /* VMCS shadowing */
2426                 "\020EPT#VE"            /* EPT-violation #VE */
2427                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2428                 );
2429         printf("\n        Exit Controls=0x%b", mask,
2430         "\020"
2431         "\003DR"                /* Save debug controls */
2432                                 /* Ignore Host address-space size */
2433         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2434         "\020AckInt"            /* Acknowledge interrupt on exit */
2435         "\023PAT-SV"            /* Save MSR_PAT */
2436         "\024PAT-LD"            /* Load MSR_PAT */
2437         "\025EFER-SV"           /* Save MSR_EFER */
2438         "\026EFER-LD"           /* Load MSR_EFER */
2439         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2440         );
2441         printf("\n        Entry Controls=0x%b", mask,
2442         "\020"
2443         "\003DR"                /* Save debug controls */
2444                                 /* Ignore IA-32e mode guest */
2445                                 /* Ignore Entry to SMM */
2446                                 /* Ignore Deactivate dual-monitor treatment */
2447         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2448         "\017PAT"               /* Load MSR_PAT */
2449         "\020EFER"              /* Load MSR_EFER */
2450         );
2451         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2452             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2453                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2454                 mask = msr;
2455                 printf("\n        EPT Features=0x%b", mask,
2456                 "\020"
2457                 "\001XO"                /* Execute-only translations */
2458                 "\007PW4"               /* Page-walk length of 4 */
2459                 "\011UC"                /* EPT paging-structure mem can be UC */
2460                 "\017WB"                /* EPT paging-structure mem can be WB */
2461                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2462                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2463                 "\025INVEPT"            /* INVEPT is supported */
2464                 "\026AD"                /* Accessed and dirty flags for EPT */
2465                 "\032single"            /* INVEPT single-context type */
2466                 "\033all"               /* INVEPT all-context type */
2467                 );
2468                 mask = msr >> 32;
2469                 printf("\n        VPID Features=0x%b", mask,
2470                 "\020"
2471                 "\001INVVPID"           /* INVVPID is supported */
2472                 "\011individual"        /* INVVPID individual-address type */
2473                 "\012single"            /* INVVPID single-context type */
2474                 "\013all"               /* INVVPID all-context type */
2475                  /* INVVPID single-context-retaining-globals type */
2476                 "\014single-globals"
2477                 );
2478         }
2479 }
2480
2481 static void
2482 print_hypervisor_info(void)
2483 {
2484
2485         if (*hv_vendor)
2486                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2487 }