sys/x86/x86/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include "opt_cpu.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/bus.h>
  48 #include <sys/cpu.h>
  49 #include <sys/eventhandler.h>
  50 #include <sys/limits.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <vm/vm.h>
  57 #include <vm/pmap.h>
  58
  59 #include <machine/asmacros.h>
  60 #include <machine/clock.h>
  61 #include <machine/cputypes.h>
  62 #include <machine/frame.h>
  63 #include <machine/intr_machdep.h>
  64 #include <machine/md_var.h>
  65 #include <machine/segments.h>
  66 #include <machine/specialreg.h>
  67
  68 #include <amd64/vmm/intel/vmx_controls.h>
  69 #include <x86/isa/icu.h>
  70 #include <x86/vmware.h>
  71
  72 #ifdef __i386__
  73 #define IDENTBLUE_CYRIX486      0
  74 #define IDENTBLUE_IBMCPU        1
  75 #define IDENTBLUE_CYRIXM2       2
  76
  77 static void identifycyrix(void);
  78 static void print_transmeta_info(void);
  79 #endif
  80 static u_int find_cpu_vendor_id(void);
  81 static void print_AMD_info(void);
  82 static void print_INTEL_info(void);
  83 static void print_INTEL_TLB(u_int data);
  84 static void print_hypervisor_info(void);
  85 static void print_svm_info(void);
  86 static void print_via_padlock_info(void);
  87 static void print_vmx_info(void);
  88
  89 #ifdef __i386__
  90 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
  91 int     cpu_class;
  92 #endif
  93 u_int   cpu_feature;            /* Feature flags */
  94 u_int   cpu_feature2;           /* Feature flags */
  95 u_int   amd_feature;            /* AMD feature flags */
  96 u_int   amd_feature2;           /* AMD feature flags */
  97 u_int   amd_rascap;             /* AMD RAS capabilities */
  98 u_int   amd_pminfo;             /* AMD advanced power management info */
  99 u_int   amd_extended_feature_extensions;
 100 u_int   via_feature_rng;        /* VIA RNG features */
 101 u_int   via_feature_xcrypt;     /* VIA ACE features */
 102 u_int   cpu_high;               /* Highest arg to CPUID */
 103 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
 104 u_int   cpu_id;                 /* Stepping ID */
 105 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
 106 u_int   cpu_procinfo2;          /* Multicore info */
 107 char    cpu_vendor[20];         /* CPU Origin code */
 108 u_int   cpu_vendor_id;          /* CPU vendor ID */
 109 u_int   cpu_fxsr;               /* SSE enabled */
 110 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
 111 u_int   cpu_clflush_line_size = 32;
 112 u_int   cpu_stdext_feature;     /* %ebx */
 113 u_int   cpu_stdext_feature2;    /* %ecx */
 114 u_int   cpu_stdext_feature3;    /* %edx */
 115 uint64_t cpu_ia32_arch_caps;
 116 u_int   cpu_max_ext_state_size;
 117 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
 118 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
 119 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
 120 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
 121 u_int   cpu_power_eax;          /* 06H: Power management leaf, %eax */
 122 u_int   cpu_power_ebx;          /* 06H: Power management leaf, %eax */
 123 u_int   cpu_power_ecx;          /* 06H: Power management leaf, %eax */
 124 u_int   cpu_power_edx;          /* 06H: Power management leaf, %eax */
 125 char machine[] = MACHINE;
 126
 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
 128     &via_feature_rng, 0,
 129     "VIA RNG feature available in CPU");
 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
 131     &via_feature_xcrypt, 0,
 132     "VIA xcrypt feature available in CPU");
 133
 134 #ifdef __amd64__
 135 #ifdef SCTL_MASK32
 136 extern int adaptive_machine_arch;
 137 #endif
 138
 139 static int
 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
 141 {
 142 #ifdef SCTL_MASK32
 143         static const char machine32[] = "i386";
 144 #endif
 145         int error;
 146
 147 #ifdef SCTL_MASK32
 148         if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
 149                 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
 150         else
 151 #endif
 152                 error = SYSCTL_OUT(req, machine, sizeof(machine));
 153         return (error);
 154
 155 }
 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
 157     CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
 158 #else
 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
 160     machine, 0, "Machine class");
 161 #endif
 162
 163 static char cpu_model[128];
 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
 165     cpu_model, 0, "Machine model");
 166
 167 static int hw_clockrate;
 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
 169     &hw_clockrate, 0, "CPU instruction clock rate");
 170
 171 u_int hv_base;
 172 u_int hv_high;
 173 char hv_vendor[16];
 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
 175     0, "Hypervisor vendor");
 176
 177 static eventhandler_tag tsc_post_tag;
 178
 179 static char cpu_brand[48];
 180
 181 #ifdef __i386__
 182 #define MAX_BRAND_INDEX 8
 183
 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 185         NULL,                   /* No brand */
 186         "Intel Celeron",
 187         "Intel Pentium III",
 188         "Intel Pentium III Xeon",
 189         NULL,
 190         NULL,
 191         NULL,
 192         NULL,
 193         "Intel Pentium 4"
 194 };
 195
 196 static struct {
 197         char    *cpu_name;
 198         int     cpu_class;
 199 } cpus[] = {
 200         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 201         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 202         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 203         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 204         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 205         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 206         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 207         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 208         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 209         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 210         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 211         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 212         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 213         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 214         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 215         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 216         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 217 };
 218 #endif
 219
 220 static struct {
 221         char    *vendor;
 222         u_int   vendor_id;
 223 } cpu_vendors[] = {
 224         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 225         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 226         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 227 #ifdef __i386__
 228         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 229         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 230         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 231         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 232         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 233         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 234         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 235 #if 0
 236         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 237         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 238 #endif
 239 #endif
 240 };
 241
 242 void
 243 printcpuinfo(void)
 244 {
 245         u_int regs[4], i;
 246         char *brand;
 247
 248         printf("CPU: ");
 249 #ifdef __i386__
 250         cpu_class = cpus[cpu].cpu_class;
 251         strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
 252 #else
 253         strncpy(cpu_model, "Hammer", sizeof (cpu_model));
 254 #endif
 255
 256         /* Check for extended CPUID information and a processor name. */
 257         if (cpu_exthigh >= 0x80000004) {
 258                 brand = cpu_brand;
 259                 for (i = 0x80000002; i < 0x80000005; i++) {
 260                         do_cpuid(i, regs);
 261                         memcpy(brand, regs, sizeof(regs));
 262                         brand += sizeof(regs);
 263                 }
 264         }
 265
 266         switch (cpu_vendor_id) {
 267         case CPU_VENDOR_INTEL:
 268 #ifdef __i386__
 269                 if ((cpu_id & 0xf00) > 0x300) {
 270                         u_int brand_index;
 271
 272                         cpu_model[0] = '\0';
 273
 274                         switch (cpu_id & 0x3000) {
 275                         case 0x1000:
 276                                 strcpy(cpu_model, "Overdrive ");
 277                                 break;
 278                         case 0x2000:
 279                                 strcpy(cpu_model, "Dual ");
 280                                 break;
 281                         }
 282
 283                         switch (cpu_id & 0xf00) {
 284                         case 0x400:
 285                                 strcat(cpu_model, "i486 ");
 286                                 /* Check the particular flavor of 486 */
 287                                 switch (cpu_id & 0xf0) {
 288                                 case 0x00:
 289                                 case 0x10:
 290                                         strcat(cpu_model, "DX");
 291                                         break;
 292                                 case 0x20:
 293                                         strcat(cpu_model, "SX");
 294                                         break;
 295                                 case 0x30:
 296                                         strcat(cpu_model, "DX2");
 297                                         break;
 298                                 case 0x40:
 299                                         strcat(cpu_model, "SL");
 300                                         break;
 301                                 case 0x50:
 302                                         strcat(cpu_model, "SX2");
 303                                         break;
 304                                 case 0x70:
 305                                         strcat(cpu_model,
 306                                             "DX2 Write-Back Enhanced");
 307                                         break;
 308                                 case 0x80:
 309                                         strcat(cpu_model, "DX4");
 310                                         break;
 311                                 }
 312                                 break;
 313                         case 0x500:
 314                                 /* Check the particular flavor of 586 */
 315                                 strcat(cpu_model, "Pentium");
 316                                 switch (cpu_id & 0xf0) {
 317                                 case 0x00:
 318                                         strcat(cpu_model, " A-step");
 319                                         break;
 320                                 case 0x10:
 321                                         strcat(cpu_model, "/P5");
 322                                         break;
 323                                 case 0x20:
 324                                         strcat(cpu_model, "/P54C");
 325                                         break;
 326                                 case 0x30:
 327                                         strcat(cpu_model, "/P24T");
 328                                         break;
 329                                 case 0x40:
 330                                         strcat(cpu_model, "/P55C");
 331                                         break;
 332                                 case 0x70:
 333                                         strcat(cpu_model, "/P54C");
 334                                         break;
 335                                 case 0x80:
 336                                         strcat(cpu_model, "/P55C (quarter-micron)");
 337                                         break;
 338                                 default:
 339                                         /* nothing */
 340                                         break;
 341                                 }
 342 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 343                                 /*
 344                                  * XXX - If/when Intel fixes the bug, this
 345                                  * should also check the version of the
 346                                  * CPU, not just that it's a Pentium.
 347                                  */
 348                                 has_f00f_bug = 1;
 349 #endif
 350                                 break;
 351                         case 0x600:
 352                                 /* Check the particular flavor of 686 */
 353                                 switch (cpu_id & 0xf0) {
 354                                 case 0x00:
 355                                         strcat(cpu_model, "Pentium Pro A-step");
 356                                         break;
 357                                 case 0x10:
 358                                         strcat(cpu_model, "Pentium Pro");
 359                                         break;
 360                                 case 0x30:
 361                                 case 0x50:
 362                                 case 0x60:
 363                                         strcat(cpu_model,
 364                                 "Pentium II/Pentium II Xeon/Celeron");
 365                                         cpu = CPU_PII;
 366                                         break;
 367                                 case 0x70:
 368                                 case 0x80:
 369                                 case 0xa0:
 370                                 case 0xb0:
 371                                         strcat(cpu_model,
 372                                         "Pentium III/Pentium III Xeon/Celeron");
 373                                         cpu = CPU_PIII;
 374                                         break;
 375                                 default:
 376                                         strcat(cpu_model, "Unknown 80686");
 377                                         break;
 378                                 }
 379                                 break;
 380                         case 0xf00:
 381                                 strcat(cpu_model, "Pentium 4");
 382                                 cpu = CPU_P4;
 383                                 break;
 384                         default:
 385                                 strcat(cpu_model, "unknown");
 386                                 break;
 387                         }
 388
 389                         /*
 390                          * If we didn't get a brand name from the extended
 391                          * CPUID, try to look it up in the brand table.
 392                          */
 393                         if (cpu_high > 0 && *cpu_brand == '\0') {
 394                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 395                                 if (brand_index <= MAX_BRAND_INDEX &&
 396                                     cpu_brandtable[brand_index] != NULL)
 397                                         strcpy(cpu_brand,
 398                                             cpu_brandtable[brand_index]);
 399                         }
 400                 }
 401 #else
 402                 /* Please make up your mind folks! */
 403                 strcat(cpu_model, "EM64T");
 404 #endif
 405                 break;
 406         case CPU_VENDOR_AMD:
 407                 /*
 408                  * Values taken from AMD Processor Recognition
 409                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 410                  * (also describes ``Features'' encodings.
 411                  */
 412                 strcpy(cpu_model, "AMD ");
 413 #ifdef __i386__
 414                 switch (cpu_id & 0xFF0) {
 415                 case 0x410:
 416                         strcat(cpu_model, "Standard Am486DX");
 417                         break;
 418                 case 0x430:
 419                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 420                         break;
 421                 case 0x470:
 422                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 423                         break;
 424                 case 0x480:
 425                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 426                         break;
 427                 case 0x490:
 428                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 429                         break;
 430                 case 0x4E0:
 431                         strcat(cpu_model, "Am5x86 Write-Through");
 432                         break;
 433                 case 0x4F0:
 434                         strcat(cpu_model, "Am5x86 Write-Back");
 435                         break;
 436                 case 0x500:
 437                         strcat(cpu_model, "K5 model 0");
 438                         break;
 439                 case 0x510:
 440                         strcat(cpu_model, "K5 model 1");
 441                         break;
 442                 case 0x520:
 443                         strcat(cpu_model, "K5 PR166 (model 2)");
 444                         break;
 445                 case 0x530:
 446                         strcat(cpu_model, "K5 PR200 (model 3)");
 447                         break;
 448                 case 0x560:
 449                         strcat(cpu_model, "K6");
 450                         break;
 451                 case 0x570:
 452                         strcat(cpu_model, "K6 266 (model 1)");
 453                         break;
 454                 case 0x580:
 455                         strcat(cpu_model, "K6-2");
 456                         break;
 457                 case 0x590:
 458                         strcat(cpu_model, "K6-III");
 459                         break;
 460                 case 0x5a0:
 461                         strcat(cpu_model, "Geode LX");
 462                         break;
 463                 default:
 464                         strcat(cpu_model, "Unknown");
 465                         break;
 466                 }
 467 #else
 468                 if ((cpu_id & 0xf00) == 0xf00)
 469                         strcat(cpu_model, "AMD64 Processor");
 470                 else
 471                         strcat(cpu_model, "Unknown");
 472 #endif
 473                 break;
 474 #ifdef __i386__
 475         case CPU_VENDOR_CYRIX:
 476                 strcpy(cpu_model, "Cyrix ");
 477                 switch (cpu_id & 0xff0) {
 478                 case 0x440:
 479                         strcat(cpu_model, "MediaGX");
 480                         break;
 481                 case 0x520:
 482                         strcat(cpu_model, "6x86");
 483                         break;
 484                 case 0x540:
 485                         cpu_class = CPUCLASS_586;
 486                         strcat(cpu_model, "GXm");
 487                         break;
 488                 case 0x600:
 489                         strcat(cpu_model, "6x86MX");
 490                         break;
 491                 default:
 492                         /*
 493                          * Even though CPU supports the cpuid
 494                          * instruction, it can be disabled.
 495                          * Therefore, this routine supports all Cyrix
 496                          * CPUs.
 497                          */
 498                         switch (cyrix_did & 0xf0) {
 499                         case 0x00:
 500                                 switch (cyrix_did & 0x0f) {
 501                                 case 0x00:
 502                                         strcat(cpu_model, "486SLC");
 503                                         break;
 504                                 case 0x01:
 505                                         strcat(cpu_model, "486DLC");
 506                                         break;
 507                                 case 0x02:
 508                                         strcat(cpu_model, "486SLC2");
 509                                         break;
 510                                 case 0x03:
 511                                         strcat(cpu_model, "486DLC2");
 512                                         break;
 513                                 case 0x04:
 514                                         strcat(cpu_model, "486SRx");
 515                                         break;
 516                                 case 0x05:
 517                                         strcat(cpu_model, "486DRx");
 518                                         break;
 519                                 case 0x06:
 520                                         strcat(cpu_model, "486SRx2");
 521                                         break;
 522                                 case 0x07:
 523                                         strcat(cpu_model, "486DRx2");
 524                                         break;
 525                                 case 0x08:
 526                                         strcat(cpu_model, "486SRu");
 527                                         break;
 528                                 case 0x09:
 529                                         strcat(cpu_model, "486DRu");
 530                                         break;
 531                                 case 0x0a:
 532                                         strcat(cpu_model, "486SRu2");
 533                                         break;
 534                                 case 0x0b:
 535                                         strcat(cpu_model, "486DRu2");
 536                                         break;
 537                                 default:
 538                                         strcat(cpu_model, "Unknown");
 539                                         break;
 540                                 }
 541                                 break;
 542                         case 0x10:
 543                                 switch (cyrix_did & 0x0f) {
 544                                 case 0x00:
 545                                         strcat(cpu_model, "486S");
 546                                         break;
 547                                 case 0x01:
 548                                         strcat(cpu_model, "486S2");
 549                                         break;
 550                                 case 0x02:
 551                                         strcat(cpu_model, "486Se");
 552                                         break;
 553                                 case 0x03:
 554                                         strcat(cpu_model, "486S2e");
 555                                         break;
 556                                 case 0x0a:
 557                                         strcat(cpu_model, "486DX");
 558                                         break;
 559                                 case 0x0b:
 560                                         strcat(cpu_model, "486DX2");
 561                                         break;
 562                                 case 0x0f:
 563                                         strcat(cpu_model, "486DX4");
 564                                         break;
 565                                 default:
 566                                         strcat(cpu_model, "Unknown");
 567                                         break;
 568                                 }
 569                                 break;
 570                         case 0x20:
 571                                 if ((cyrix_did & 0x0f) < 8)
 572                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 573                                 else
 574                                         strcat(cpu_model, "5x86");
 575                                 break;
 576                         case 0x30:
 577                                 strcat(cpu_model, "6x86");
 578                                 break;
 579                         case 0x40:
 580                                 if ((cyrix_did & 0xf000) == 0x3000) {
 581                                         cpu_class = CPUCLASS_586;
 582                                         strcat(cpu_model, "GXm");
 583                                 } else
 584                                         strcat(cpu_model, "MediaGX");
 585                                 break;
 586                         case 0x50:
 587                                 strcat(cpu_model, "6x86MX");
 588                                 break;
 589                         case 0xf0:
 590                                 switch (cyrix_did & 0x0f) {
 591                                 case 0x0d:
 592                                         strcat(cpu_model, "Overdrive CPU");
 593                                         break;
 594                                 case 0x0e:
 595                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 596                                         break;
 597                                 case 0x0f:
 598                                         strcat(cpu_model, "486SLC/DLC");
 599                                         break;
 600                                 default:
 601                                         strcat(cpu_model, "Unknown");
 602                                         break;
 603                                 }
 604                                 break;
 605                         default:
 606                                 strcat(cpu_model, "Unknown");
 607                                 break;
 608                         }
 609                         break;
 610                 }
 611                 break;
 612         case CPU_VENDOR_RISE:
 613                 strcpy(cpu_model, "Rise ");
 614                 switch (cpu_id & 0xff0) {
 615                 case 0x500:     /* 6401 and 6441 (Kirin) */
 616                 case 0x520:     /* 6510 (Lynx) */
 617                         strcat(cpu_model, "mP6");
 618                         break;
 619                 default:
 620                         strcat(cpu_model, "Unknown");
 621                 }
 622                 break;
 623 #endif
 624         case CPU_VENDOR_CENTAUR:
 625 #ifdef __i386__
 626                 switch (cpu_id & 0xff0) {
 627                 case 0x540:
 628                         strcpy(cpu_model, "IDT WinChip C6");
 629                         break;
 630                 case 0x580:
 631                         strcpy(cpu_model, "IDT WinChip 2");
 632                         break;
 633                 case 0x590:
 634                         strcpy(cpu_model, "IDT WinChip 3");
 635                         break;
 636                 case 0x660:
 637                         strcpy(cpu_model, "VIA C3 Samuel");
 638                         break;
 639                 case 0x670:
 640                         if (cpu_id & 0x8)
 641                                 strcpy(cpu_model, "VIA C3 Ezra");
 642                         else
 643                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 644                         break;
 645                 case 0x680:
 646                         strcpy(cpu_model, "VIA C3 Ezra-T");
 647                         break;
 648                 case 0x690:
 649                         strcpy(cpu_model, "VIA C3 Nehemiah");
 650                         break;
 651                 case 0x6a0:
 652                 case 0x6d0:
 653                         strcpy(cpu_model, "VIA C7 Esther");
 654                         break;
 655                 case 0x6f0:
 656                         strcpy(cpu_model, "VIA Nano");
 657                         break;
 658                 default:
 659                         strcpy(cpu_model, "VIA/IDT Unknown");
 660                 }
 661 #else
 662                 strcpy(cpu_model, "VIA ");
 663                 if ((cpu_id & 0xff0) == 0x6f0)
 664                         strcat(cpu_model, "Nano Processor");
 665                 else
 666                         strcat(cpu_model, "Unknown");
 667 #endif
 668                 break;
 669 #ifdef __i386__
 670         case CPU_VENDOR_IBM:
 671                 strcpy(cpu_model, "Blue Lightning CPU");
 672                 break;
 673         case CPU_VENDOR_NSC:
 674                 switch (cpu_id & 0xff0) {
 675                 case 0x540:
 676                         strcpy(cpu_model, "Geode SC1100");
 677                         cpu = CPU_GEODE1100;
 678                         break;
 679                 default:
 680                         strcpy(cpu_model, "Geode/NSC unknown");
 681                         break;
 682                 }
 683                 break;
 684 #endif
 685         default:
 686                 strcat(cpu_model, "Unknown");
 687                 break;
 688         }
 689
 690         /*
 691          * Replace cpu_model with cpu_brand minus leading spaces if
 692          * we have one.
 693          */
 694         brand = cpu_brand;
 695         while (*brand == ' ')
 696                 ++brand;
 697         if (*brand != '\0')
 698                 strcpy(cpu_model, brand);
 699
 700         printf("%s (", cpu_model);
 701         if (tsc_freq != 0) {
 702                 hw_clockrate = (tsc_freq + 5000) / 1000000;
 703                 printf("%jd.%02d-MHz ",
 704                     (intmax_t)(tsc_freq + 4999) / 1000000,
 705                     (u_int)((tsc_freq + 4999) / 10000) % 100);
 706         }
 707 #ifdef __i386__
 708         switch(cpu_class) {
 709         case CPUCLASS_286:
 710                 printf("286");
 711                 break;
 712         case CPUCLASS_386:
 713                 printf("386");
 714                 break;
 715 #if defined(I486_CPU)
 716         case CPUCLASS_486:
 717                 printf("486");
 718                 break;
 719 #endif
 720 #if defined(I586_CPU)
 721         case CPUCLASS_586:
 722                 printf("586");
 723                 break;
 724 #endif
 725 #if defined(I686_CPU)
 726         case CPUCLASS_686:
 727                 printf("686");
 728                 break;
 729 #endif
 730         default:
 731                 printf("Unknown");      /* will panic below... */
 732         }
 733 #else
 734         printf("K8");
 735 #endif
 736         printf("-class CPU)\n");
 737         if (*cpu_vendor)
 738                 printf("  Origin=\"%s\"", cpu_vendor);
 739         if (cpu_id)
 740                 printf("  Id=0x%x", cpu_id);
 741
 742         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 743             cpu_vendor_id == CPU_VENDOR_AMD ||
 744             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 745 #ifdef __i386__
 746             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 747             cpu_vendor_id == CPU_VENDOR_RISE ||
 748             cpu_vendor_id == CPU_VENDOR_NSC ||
 749             (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
 750 #endif
 751             0) {
 752                 printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
 753                 printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
 754                 printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
 755 #ifdef __i386__
 756                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 757                         printf("\n  DIR=0x%04x", cyrix_did);
 758 #endif
 759
 760                 /*
 761                  * AMD CPUID Specification
 762                  * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
 763                  *
 764                  * Intel Processor Identification and CPUID Instruction
 765                  * http://www.intel.com/assets/pdf/appnote/241618.pdf
 766                  */
 767                 if (cpu_high > 0) {
 768
 769                         /*
 770                          * Here we should probably set up flags indicating
 771                          * whether or not various features are available.
 772                          * The interesting ones are probably VME, PSE, PAE,
 773                          * and PGE.  The code already assumes without bothering
 774                          * to check that all CPUs >= Pentium have a TSC and
 775                          * MSRs.
 776                          */
 777                         printf("\n  Features=0x%b", cpu_feature,
 778                         "\020"
 779                         "\001FPU"       /* Integral FPU */
 780                         "\002VME"       /* Extended VM86 mode support */
 781                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 782                         "\004PSE"       /* 4MByte page tables */
 783                         "\005TSC"       /* Timestamp counter */
 784                         "\006MSR"       /* Machine specific registers */
 785                         "\007PAE"       /* Physical address extension */
 786                         "\010MCE"       /* Machine Check support */
 787                         "\011CX8"       /* CMPEXCH8 instruction */
 788                         "\012APIC"      /* SMP local APIC */
 789                         "\013oldMTRR"   /* Previous implementation of MTRR */
 790                         "\014SEP"       /* Fast System Call */
 791                         "\015MTRR"      /* Memory Type Range Registers */
 792                         "\016PGE"       /* PG_G (global bit) support */
 793                         "\017MCA"       /* Machine Check Architecture */
 794                         "\020CMOV"      /* CMOV instruction */
 795                         "\021PAT"       /* Page attributes table */
 796                         "\022PSE36"     /* 36 bit address space support */
 797                         "\023PN"        /* Processor Serial number */
 798                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 799                         "\025<b20>"
 800                         "\026DTS"       /* Debug Trace Store */
 801                         "\027ACPI"      /* ACPI support */
 802                         "\030MMX"       /* MMX instructions */
 803                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 804                         "\032SSE"       /* Streaming SIMD Extensions */
 805                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 806                         "\034SS"        /* Self snoop */
 807                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 808                         "\036TM"        /* Thermal Monitor clock slowdown */
 809                         "\037IA64"      /* CPU can execute IA64 instructions */
 810                         "\040PBE"       /* Pending Break Enable */
 811                         );
 812
 813                         if (cpu_feature2 != 0) {
 814                                 printf("\n  Features2=0x%b", cpu_feature2,
 815                                 "\020"
 816                                 "\001SSE3"      /* SSE3 */
 817                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 818                                 "\003DTES64"    /* 64-bit Debug Trace */
 819                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 820                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 821                                 "\006VMX"       /* Virtual Machine Extensions */
 822                                 "\007SMX"       /* Safer Mode Extensions */
 823                                 "\010EST"       /* Enhanced SpeedStep */
 824                                 "\011TM2"       /* Thermal Monitor 2 */
 825                                 "\012SSSE3"     /* SSSE3 */
 826                                 "\013CNXT-ID"   /* L1 context ID available */
 827                                 "\014SDBG"      /* IA32 silicon debug */
 828                                 "\015FMA"       /* Fused Multiply Add */
 829                                 "\016CX16"      /* CMPXCHG16B Instruction */
 830                                 "\017xTPR"      /* Send Task Priority Messages*/
 831                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 832                                 "\021<b16>"
 833                                 "\022PCID"      /* Process-context Identifiers*/
 834                                 "\023DCA"       /* Direct Cache Access */
 835                                 "\024SSE4.1"    /* SSE 4.1 */
 836                                 "\025SSE4.2"    /* SSE 4.2 */
 837                                 "\026x2APIC"    /* xAPIC Extensions */
 838                                 "\027MOVBE"     /* MOVBE Instruction */
 839                                 "\030POPCNT"    /* POPCNT Instruction */
 840                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 841                                 "\032AESNI"     /* AES Crypto */
 842                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 843                                 "\034OSXSAVE"   /* OS-Enabled State Management*/
 844                                 "\035AVX"       /* Advanced Vector Extensions */
 845                                 "\036F16C"      /* Half-precision conversions */
 846                                 "\037RDRAND"    /* RDRAND Instruction */
 847                                 "\040HV"        /* Hypervisor */
 848                                 );
 849                         }
 850
 851                         if (amd_feature != 0) {
 852                                 printf("\n  AMD Features=0x%b", amd_feature,
 853                                 "\020"          /* in hex */
 854                                 "\001<s0>"      /* Same */
 855                                 "\002<s1>"      /* Same */
 856                                 "\003<s2>"      /* Same */
 857                                 "\004<s3>"      /* Same */
 858                                 "\005<s4>"      /* Same */
 859                                 "\006<s5>"      /* Same */
 860                                 "\007<s6>"      /* Same */
 861                                 "\010<s7>"      /* Same */
 862                                 "\011<s8>"      /* Same */
 863                                 "\012<s9>"      /* Same */
 864                                 "\013<b10>"     /* Undefined */
 865                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 866                                 "\015<s12>"     /* Same */
 867                                 "\016<s13>"     /* Same */
 868                                 "\017<s14>"     /* Same */
 869                                 "\020<s15>"     /* Same */
 870                                 "\021<s16>"     /* Same */
 871                                 "\022<s17>"     /* Same */
 872                                 "\023<b18>"     /* Reserved, unknown */
 873                                 "\024MP"        /* Multiprocessor Capable */
 874                                 "\025NX"        /* Has EFER.NXE, NX */
 875                                 "\026<b21>"     /* Undefined */
 876                                 "\027MMX+"      /* AMD MMX Extensions */
 877                                 "\030<s23>"     /* Same */
 878                                 "\031<s24>"     /* Same */
 879                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 880                                 "\033Page1GB"   /* 1-GB large page support */
 881                                 "\034RDTSCP"    /* RDTSCP */
 882                                 "\035<b28>"     /* Undefined */
 883                                 "\036LM"        /* 64 bit long mode */
 884                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 885                                 "\0403DNow!"    /* AMD 3DNow! */
 886                                 );
 887                         }
 888
 889                         if (amd_feature2 != 0) {
 890                                 printf("\n  AMD Features2=0x%b", amd_feature2,
 891                                 "\020"
 892                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 893                                 "\002CMP"       /* CMP legacy */
 894                                 "\003SVM"       /* Secure Virtual Mode */
 895                                 "\004ExtAPIC"   /* Extended APIC register */
 896                                 "\005CR8"       /* CR8 in legacy mode */
 897                                 "\006ABM"       /* LZCNT instruction */
 898                                 "\007SSE4A"     /* SSE4A */
 899                                 "\010MAS"       /* Misaligned SSE mode */
 900                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 901                                 "\012OSVW"      /* OS visible workaround */
 902                                 "\013IBS"       /* Instruction based sampling */
 903                                 "\014XOP"       /* XOP extended instructions */
 904                                 "\015SKINIT"    /* SKINIT/STGI */
 905                                 "\016WDT"       /* Watchdog timer */
 906                                 "\017<b14>"
 907                                 "\020LWP"       /* Lightweight Profiling */
 908                                 "\021FMA4"      /* 4-operand FMA instructions */
 909                                 "\022TCE"       /* Translation Cache Extension */
 910                                 "\023<b18>"
 911                                 "\024NodeId"    /* NodeId MSR support */
 912                                 "\025<b20>"
 913                                 "\026TBM"       /* Trailing Bit Manipulation */
 914                                 "\027Topology"  /* Topology Extensions */
 915                                 "\030PCXC"      /* Core perf count */
 916                                 "\031PNXC"      /* NB perf count */
 917                                 "\032<b25>"
 918                                 "\033DBE"       /* Data Breakpoint extension */
 919                                 "\034PTSC"      /* Performance TSC */
 920                                 "\035PL2I"      /* L2I perf count */
 921                                 "\036MWAITX"    /* MONITORX/MWAITX instructions */
 922                                 "\037<b30>"
 923                                 "\040<b31>"
 924                                 );
 925                         }
 926
 927                         if (cpu_stdext_feature != 0) {
 928                                 printf("\n  Structured Extended Features=0x%b",
 929                                     cpu_stdext_feature,
 930                                        "\020"
 931                                        /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
 932                                        "\001FSGSBASE"
 933                                        "\002TSCADJ"
 934                                        "\003SGX"
 935                                        /* Bit Manipulation Instructions */
 936                                        "\004BMI1"
 937                                        /* Hardware Lock Elision */
 938                                        "\005HLE"
 939                                        /* Advanced Vector Instructions 2 */
 940                                        "\006AVX2"
 941                                        /* FDP_EXCPTN_ONLY */
 942                                        "\007FDPEXC"
 943                                        /* Supervisor Mode Execution Prot. */
 944                                        "\010SMEP"
 945                                        /* Bit Manipulation Instructions */
 946                                        "\011BMI2"
 947                                        "\012ERMS"
 948                                        /* Invalidate Processor Context ID */
 949                                        "\013INVPCID"
 950                                        /* Restricted Transactional Memory */
 951                                        "\014RTM"
 952                                        "\015PQM"
 953                                        "\016NFPUSG"
 954                                        /* Intel Memory Protection Extensions */
 955                                        "\017MPX"
 956                                        "\020PQE"
 957                                        /* AVX512 Foundation */
 958                                        "\021AVX512F"
 959                                        "\022AVX512DQ"
 960                                        /* Enhanced NRBG */
 961                                        "\023RDSEED"
 962                                        /* ADCX + ADOX */
 963                                        "\024ADX"
 964                                        /* Supervisor Mode Access Prevention */
 965                                        "\025SMAP"
 966                                        "\026AVX512IFMA"
 967                                        /* Formerly PCOMMIT */
 968                                        "\027<b22>"
 969                                        "\030CLFLUSHOPT"
 970                                        "\031CLWB"
 971                                        "\032PROCTRACE"
 972                                        "\033AVX512PF"
 973                                        "\034AVX512ER"
 974                                        "\035AVX512CD"
 975                                        "\036SHA"
 976                                        "\037AVX512BW"
 977                                        "\040AVX512VL"
 978                                        );
 979                         }
 980
 981                         if (cpu_stdext_feature2 != 0) {
 982                                 printf("\n  Structured Extended Features2=0x%b",
 983                                     cpu_stdext_feature2,
 984                                        "\020"
 985                                        "\001PREFETCHWT1"
 986                                        "\002AVX512VBMI"
 987                                        "\003UMIP"
 988                                        "\004PKU"
 989                                        "\005OSPKE"
 990                                        "\006WAITPKG"
 991                                        "\007AVX512VBMI2"
 992                                        "\011GFNI"
 993                                        "\012VAES"
 994                                        "\013VPCLMULQDQ"
 995                                        "\014AVX512VNNI"
 996                                        "\015AVX512BITALG"
 997                                        "\016AVX512VPOPCNTDQ"
 998                                        "\027RDPID"
 999                                        "\032CLDEMOTE"
1000                                        "\034MOVDIRI"
1001                                        "\035MOVDIR64B"
1002                                        "\036ENQCMD"
1003                                        "\037SGXLC"
1004                                        );
1005                         }
1006
1007                         if (cpu_stdext_feature3 != 0) {
1008                                 printf("\n  Structured Extended Features3=0x%b",
1009                                     cpu_stdext_feature3,
1010                                        "\020"
1011                                        "\003AVX512_4VNNIW"
1012                                        "\004AVX512_4FMAPS"
1013                                        "\011AVX512VP2INTERSECT"
1014                                        "\013MD_CLEAR"
1015                                        "\016TSXFA"
1016                                        "\023PCONFIG"
1017                                        "\033IBPB"
1018                                        "\034STIBP"
1019                                        "\035L1DFL"
1020                                        "\036ARCH_CAP"
1021                                        "\037CORE_CAP"
1022                                        "\040SSBD"
1023                                        );
1024                         }
1025
1026                         if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1027                                 cpuid_count(0xd, 0x1, regs);
1028                                 if (regs[0] != 0) {
1029                                         printf("\n  XSAVE Features=0x%b",
1030                                             regs[0],
1031                                             "\020"
1032                                             "\001XSAVEOPT"
1033                                             "\002XSAVEC"
1034                                             "\003XINUSE"
1035                                             "\004XSAVES");
1036                                 }
1037                         }
1038
1039                         if (cpu_ia32_arch_caps != 0) {
1040                                 printf("\n  IA32_ARCH_CAPS=0x%b",
1041                                     (u_int)cpu_ia32_arch_caps,
1042                                        "\020"
1043                                        "\001RDCL_NO"
1044                                        "\002IBRS_ALL"
1045                                        "\003RSBA"
1046                                        "\004SKIP_L1DFL_VME"
1047                                        "\005SSB_NO"
1048                                        "\006MDS_NO"
1049                                        );
1050                         }
1051
1052                         if (amd_extended_feature_extensions != 0) {
1053                                 u_int amd_fe_masked;
1054
1055                                 amd_fe_masked = amd_extended_feature_extensions;
1056                                 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1057                                         amd_fe_masked &=
1058                                             ~(AMDFEID_IBRS_ALWAYSON |
1059                                                 AMDFEID_PREFER_IBRS);
1060                                 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1061                                         amd_fe_masked &=
1062                                             ~AMDFEID_STIBP_ALWAYSON;
1063
1064                                 printf("\n  "
1065                                     "AMD Extended Feature Extensions ID EBX="
1066                                     "0x%b", amd_fe_masked,
1067                                     "\020"
1068                                     "\001CLZERO"
1069                                     "\002IRPerf"
1070                                     "\003XSaveErPtr"
1071                                     "\005RDPRU"
1072                                     "\011MCOMMIT"
1073                                     "\012WBNOINVD"
1074                                     "\015IBPB"
1075                                     "\017IBRS"
1076                                     "\020STIBP"
1077                                     "\021IBRS_ALWAYSON"
1078                                     "\022STIBP_ALWAYSON"
1079                                     "\023PREFER_IBRS"
1080                                     "\031SSBD"
1081                                     "\032VIRT_SSBD"
1082                                     "\033SSB_NO"
1083                                     );
1084                         }
1085
1086                         if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1087                                 print_via_padlock_info();
1088
1089                         if (cpu_feature2 & CPUID2_VMX)
1090                                 print_vmx_info();
1091
1092                         if (amd_feature2 & AMDID2_SVM)
1093                                 print_svm_info();
1094
1095                         if ((cpu_feature & CPUID_HTT) &&
1096                             cpu_vendor_id == CPU_VENDOR_AMD)
1097                                 cpu_feature &= ~CPUID_HTT;
1098
1099                         /*
1100                          * If this CPU supports P-state invariant TSC then
1101                          * mention the capability.
1102                          */
1103                         if (tsc_is_invariant) {
1104                                 printf("\n  TSC: P-state invariant");
1105                                 if (tsc_perf_stat)
1106                                         printf(", performance statistics");
1107                         }
1108                 }
1109 #ifdef __i386__
1110         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1111                 printf("  DIR=0x%04x", cyrix_did);
1112                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1113                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1114 #ifndef CYRIX_CACHE_REALLY_WORKS
1115                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1116                         printf("\n  CPU cache: write-through mode");
1117 #endif
1118 #endif
1119         }
1120
1121         /* Avoid ugly blank lines: only print newline when we have to. */
1122         if (*cpu_vendor || cpu_id)
1123                 printf("\n");
1124
1125         if (bootverbose) {
1126                 if (cpu_vendor_id == CPU_VENDOR_AMD)
1127                         print_AMD_info();
1128                 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1129                         print_INTEL_info();
1130 #ifdef __i386__
1131                 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1132                         print_transmeta_info();
1133 #endif
1134         }
1135
1136         print_hypervisor_info();
1137 }
1138
1139 #ifdef __i386__
1140 void
1141 panicifcpuunsupported(void)
1142 {
1143
1144 #if !defined(lint)
1145 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1146 #error This kernel is not configured for one of the supported CPUs
1147 #endif
1148 #else /* lint */
1149 #endif /* lint */
1150         /*
1151          * Now that we have told the user what they have,
1152          * let them know if that machine type isn't configured.
1153          */
1154         switch (cpu_class) {
1155         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
1156         case CPUCLASS_386:
1157 #if !defined(I486_CPU)
1158         case CPUCLASS_486:
1159 #endif
1160 #if !defined(I586_CPU)
1161         case CPUCLASS_586:
1162 #endif
1163 #if !defined(I686_CPU)
1164         case CPUCLASS_686:
1165 #endif
1166                 panic("CPU class not configured");
1167         default:
1168                 break;
1169         }
1170 }
1171
1172 static  volatile u_int trap_by_rdmsr;
1173
1174 /*
1175  * Special exception 6 handler.
1176  * The rdmsr instruction generates invalid opcodes fault on 486-class
1177  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1178  * function identblue() when this handler is called.  Stacked eip should
1179  * be advanced.
1180  */
1181 inthand_t       bluetrap6;
1182 #ifdef __GNUCLIKE_ASM
1183 __asm
1184 ("                                                                      \n\
1185         .text                                                           \n\
1186         .p2align 2,0x90                                                 \n\
1187         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
1188 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
1189         ss                                                              \n\
1190         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1191         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1192         iret                                                            \n\
1193 ");
1194 #endif
1195
1196 /*
1197  * Special exception 13 handler.
1198  * Accessing non-existent MSR generates general protection fault.
1199  */
1200 inthand_t       bluetrap13;
1201 #ifdef __GNUCLIKE_ASM
1202 __asm
1203 ("                                                                      \n\
1204         .text                                                           \n\
1205         .p2align 2,0x90                                                 \n\
1206         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1207 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1208         ss                                                              \n\
1209         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1210         popl    %eax            /* discard error code */                \n\
1211         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1212         iret                                                            \n\
1213 ");
1214 #endif
1215
1216 /*
1217  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1218  * support cpuid instruction.  This function should be called after
1219  * loading interrupt descriptor table register.
1220  *
1221  * I don't like this method that handles fault, but I couldn't get
1222  * information for any other methods.  Does blue giant know?
1223  */
1224 static int
1225 identblue(void)
1226 {
1227
1228         trap_by_rdmsr = 0;
1229
1230         /*
1231          * Cyrix 486-class CPU does not support rdmsr instruction.
1232          * The rdmsr instruction generates invalid opcode fault, and exception
1233          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1234          * bluetrap6() set the magic number to trap_by_rdmsr.
1235          */
1236         setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1237             GSEL(GCODE_SEL, SEL_KPL));
1238
1239         /*
1240          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1241          * In this case, rdmsr generates general protection fault, and
1242          * exception will be trapped by bluetrap13().
1243          */
1244         setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1245             GSEL(GCODE_SEL, SEL_KPL));
1246
1247         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1248
1249         if (trap_by_rdmsr == 0xa8c1d)
1250                 return IDENTBLUE_CYRIX486;
1251         else if (trap_by_rdmsr == 0xa89c4)
1252                 return IDENTBLUE_CYRIXM2;
1253         return IDENTBLUE_IBMCPU;
1254 }
1255
1256
1257 /*
1258  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1259  *
1260  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1261  * +-------+-------+---------------+
1262  * |  SID  |  RID  |   Device ID   |
1263  * |    (DIR 1)    |    (DIR 0)    |
1264  * +-------+-------+---------------+
1265  */
1266 static void
1267 identifycyrix(void)
1268 {
1269         register_t saveintr;
1270         int     ccr2_test = 0, dir_test = 0;
1271         u_char  ccr2, ccr3;
1272
1273         saveintr = intr_disable();
1274
1275         ccr2 = read_cyrix_reg(CCR2);
1276         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1277         read_cyrix_reg(CCR2);
1278         if (read_cyrix_reg(CCR2) != ccr2)
1279                 ccr2_test = 1;
1280         write_cyrix_reg(CCR2, ccr2);
1281
1282         ccr3 = read_cyrix_reg(CCR3);
1283         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1284         read_cyrix_reg(CCR3);
1285         if (read_cyrix_reg(CCR3) != ccr3)
1286                 dir_test = 1;                                   /* CPU supports DIRs. */
1287         write_cyrix_reg(CCR3, ccr3);
1288
1289         if (dir_test) {
1290                 /* Device ID registers are available. */
1291                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1292                 cyrix_did += read_cyrix_reg(DIR0);
1293         } else if (ccr2_test)
1294                 cyrix_did = 0x0010;             /* 486S A-step */
1295         else
1296                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1297
1298         intr_restore(saveintr);
1299 }
1300 #endif
1301
1302 /* Update TSC freq with the value indicated by the caller. */
1303 static void
1304 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1305 {
1306
1307         /* If there was an error during the transition, don't do anything. */
1308         if (status != 0)
1309                 return;
1310
1311         /* Total setting for this level gives the new frequency in MHz. */
1312         hw_clockrate = level->total_set.freq;
1313 }
1314
1315 static void
1316 hook_tsc_freq(void *arg __unused)
1317 {
1318
1319         if (tsc_is_invariant)
1320                 return;
1321
1322         tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1323             tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1324 }
1325
1326 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1327
1328 static const struct {
1329         const char *    vm_bname;
1330         int             vm_guest;
1331 } vm_bnames[] = {
1332         { "QEMU",       VM_GUEST_VM },          /* QEMU */
1333         { "Plex86",     VM_GUEST_VM },          /* Plex86 */
1334         { "Bochs",      VM_GUEST_VM },          /* Bochs */
1335         { "Xen",        VM_GUEST_XEN },         /* Xen */
1336         { "BHYVE",      VM_GUEST_BHYVE },       /* bhyve */
1337         { "Seabios",    VM_GUEST_KVM },         /* KVM */
1338 };
1339
1340 static const struct {
1341         const char *    vm_pname;
1342         int             vm_guest;
1343 } vm_pnames[] = {
1344         { "VMware Virtual Platform",    VM_GUEST_VMWARE },
1345         { "Virtual Machine",            VM_GUEST_VM }, /* Microsoft VirtualPC */
1346         { "VirtualBox",                 VM_GUEST_VBOX },
1347         { "Parallels Virtual Platform", VM_GUEST_PARALLELS },
1348         { "KVM",                        VM_GUEST_KVM },
1349 };
1350
1351 static struct {
1352         const char      *vm_cpuid;
1353         int             vm_guest;
1354 } vm_cpuids[] = {
1355         { "XENXENXEN",          VM_GUEST_XEN },         /* XEN */
1356         { "Microsoft Hv",       VM_GUEST_HV },          /* Microsoft Hyper-V */
1357         { "VMwareVMware",       VM_GUEST_VMWARE },      /* VMware VM */
1358         { "KVMKVMKVM",          VM_GUEST_KVM },         /* KVM */
1359         { "bhyve bhyve ",       VM_GUEST_BHYVE },       /* bhyve */
1360         { "VBoxVBoxVBox",       VM_GUEST_VBOX },        /* VirtualBox */
1361 };
1362
1363 static void
1364 identify_hypervisor_cpuid_base(void)
1365 {
1366         u_int leaf, regs[4];
1367         int i;
1368
1369         /*
1370          * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1371          * http://lkml.org/lkml/2008/10/1/246
1372          *
1373          * KB1009458: Mechanisms to determine if software is running in
1374          * a VMware virtual machine
1375          * http://kb.vmware.com/kb/1009458
1376          *
1377          * Search for a hypervisor that we recognize. If we cannot find
1378          * a specific hypervisor, return the first information about the
1379          * hypervisor that we found, as others may be able to use.
1380          */
1381         for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1382                 do_cpuid(leaf, regs);
1383
1384                 /*
1385                  * KVM from Linux kernels prior to commit
1386                  * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1387                  * to 0 rather than a valid hv_high value.  Check for
1388                  * the KVM signature bytes and fixup %eax to the
1389                  * highest supported leaf in that case.
1390                  */
1391                 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1392                     regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1393                         regs[0] = leaf + 1;
1394
1395                 if (regs[0] >= leaf) {
1396                         for (i = 0; i < nitems(vm_cpuids); i++)
1397                                 if (strncmp((const char *)&regs[1],
1398                                     vm_cpuids[i].vm_cpuid, 12) == 0) {
1399                                         vm_guest = vm_cpuids[i].vm_guest;
1400                                         break;
1401                                 }
1402
1403                         /*
1404                          * If this is the first entry or we found a
1405                          * specific hypervisor, record the base, high value,
1406                          * and vendor identifier.
1407                          */
1408                         if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1409                                 hv_base = leaf;
1410                                 hv_high = regs[0];
1411                                 ((u_int *)&hv_vendor)[0] = regs[1];
1412                                 ((u_int *)&hv_vendor)[1] = regs[2];
1413                                 ((u_int *)&hv_vendor)[2] = regs[3];
1414                                 hv_vendor[12] = '\0';
1415
1416                                 /*
1417                                  * If we found a specific hypervisor, then
1418                                  * we are finished.
1419                                  */
1420                                 if (vm_guest != VM_GUEST_VM)
1421                                         return;
1422                         }
1423                 }
1424         }
1425 }
1426
1427 void
1428 identify_hypervisor(void)
1429 {
1430         u_int regs[4];
1431         char *p;
1432         int i;
1433
1434         /*
1435          * If CPUID2_HV is set, we are running in a hypervisor environment.
1436          */
1437         if (cpu_feature2 & CPUID2_HV) {
1438                 vm_guest = VM_GUEST_VM;
1439                 identify_hypervisor_cpuid_base();
1440
1441                 /* If we have a definitive vendor, we can return now. */
1442                 if (*hv_vendor != '\0')
1443                         return;
1444         }
1445
1446         /*
1447          * Examine SMBIOS strings for older hypervisors.
1448          */
1449         p = kern_getenv("smbios.system.serial");
1450         if (p != NULL) {
1451                 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1452                         vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1453                         if (regs[1] == VMW_HVMAGIC) {
1454                                 vm_guest = VM_GUEST_VMWARE;
1455                                 freeenv(p);
1456                                 return;
1457                         }
1458                 }
1459                 freeenv(p);
1460         }
1461
1462         /*
1463          * XXX: Some of these entries may not be needed since they were
1464          * added to FreeBSD before the checks above.
1465          */
1466         p = kern_getenv("smbios.bios.vendor");
1467         if (p != NULL) {
1468                 for (i = 0; i < nitems(vm_bnames); i++)
1469                         if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1470                                 vm_guest = vm_bnames[i].vm_guest;
1471                                 /* If we have a specific match, return */
1472                                 if (vm_guest != VM_GUEST_VM) {
1473                                         freeenv(p);
1474                                         return;
1475                                 }
1476                                 /*
1477                                  * We are done with bnames, but there might be
1478                                  * a more specific match in the pnames
1479                                  */
1480                                 break;
1481                         }
1482                 freeenv(p);
1483         }
1484         p = kern_getenv("smbios.system.product");
1485         if (p != NULL) {
1486                 for (i = 0; i < nitems(vm_pnames); i++)
1487                         if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1488                                 vm_guest = vm_pnames[i].vm_guest;
1489                                 freeenv(p);
1490                                 return;
1491                         }
1492                 freeenv(p);
1493         }
1494 }
1495
1496 bool
1497 fix_cpuid(void)
1498 {
1499         uint64_t msr;
1500
1501         /*
1502          * Clear "Limit CPUID Maxval" bit and return true if the caller should
1503          * get the largest standard CPUID function number again if it is set
1504          * from BIOS.  It is necessary for probing correct CPU topology later
1505          * and for the correct operation of the AVX-aware userspace.
1506          */
1507         if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1508             ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1509             CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1510             (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1511             CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1512                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1513                 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1514                         msr &= ~IA32_MISC_EN_LIMCPUID;
1515                         wrmsr(MSR_IA32_MISC_ENABLE, msr);
1516                         return (true);
1517                 }
1518         }
1519
1520         /*
1521          * Re-enable AMD Topology Extension that could be disabled by BIOS
1522          * on some notebook processors.  Without the extension it's really
1523          * hard to determine the correct CPU cache topology.
1524          * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1525          * Models 60h-6Fh Processors, Publication # 50742.
1526          */
1527         if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1528             CPUID_TO_FAMILY(cpu_id) == 0x15) {
1529                 msr = rdmsr(MSR_EXTFEATURES);
1530                 if ((msr & ((uint64_t)1 << 54)) == 0) {
1531                         msr |= (uint64_t)1 << 54;
1532                         wrmsr(MSR_EXTFEATURES, msr);
1533                         return (true);
1534                 }
1535         }
1536         return (false);
1537 }
1538
1539 void
1540 identify_cpu1(void)
1541 {
1542         u_int regs[4];
1543
1544         do_cpuid(0, regs);
1545         cpu_high = regs[0];
1546         ((u_int *)&cpu_vendor)[0] = regs[1];
1547         ((u_int *)&cpu_vendor)[1] = regs[3];
1548         ((u_int *)&cpu_vendor)[2] = regs[2];
1549         cpu_vendor[12] = '\0';
1550
1551         do_cpuid(1, regs);
1552         cpu_id = regs[0];
1553         cpu_procinfo = regs[1];
1554         cpu_feature = regs[3];
1555         cpu_feature2 = regs[2];
1556 }
1557
1558 void
1559 identify_cpu2(void)
1560 {
1561         u_int regs[4], cpu_stdext_disable;
1562
1563         if (cpu_high >= 6) {
1564                 cpuid_count(6, 0, regs);
1565                 cpu_power_eax = regs[0];
1566                 cpu_power_ebx = regs[1];
1567                 cpu_power_ecx = regs[2];
1568                 cpu_power_edx = regs[3];
1569         }
1570
1571         if (cpu_high >= 7) {
1572                 cpuid_count(7, 0, regs);
1573                 cpu_stdext_feature = regs[1];
1574
1575                 /*
1576                  * Some hypervisors failed to filter out unsupported
1577                  * extended features.  Allow to disable the
1578                  * extensions, activation of which requires setting a
1579                  * bit in CR4, and which VM monitors do not support.
1580                  */
1581                 cpu_stdext_disable = 0;
1582                 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1583                 cpu_stdext_feature &= ~cpu_stdext_disable;
1584
1585                 cpu_stdext_feature2 = regs[2];
1586                 cpu_stdext_feature3 = regs[3];
1587
1588                 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1589                         cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1590         }
1591 }
1592
1593 void
1594 identify_cpu_fixup_bsp(void)
1595 {
1596         u_int regs[4];
1597
1598         cpu_vendor_id = find_cpu_vendor_id();
1599
1600         if (fix_cpuid()) {
1601                 do_cpuid(0, regs);
1602                 cpu_high = regs[0];
1603         }
1604 }
1605
1606 /*
1607  * Final stage of CPU identification.
1608  */
1609 void
1610 finishidentcpu(void)
1611 {
1612         u_int regs[4];
1613 #ifdef __i386__
1614         u_char ccr3;
1615 #endif
1616
1617         identify_cpu_fixup_bsp();
1618
1619         if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1620                 do_cpuid(5, regs);
1621                 cpu_mon_mwait_flags = regs[2];
1622                 cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1623                 cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1624         }
1625
1626         identify_cpu2();
1627
1628 #ifdef __i386__
1629         if (cpu_high > 0 &&
1630             (cpu_vendor_id == CPU_VENDOR_INTEL ||
1631              cpu_vendor_id == CPU_VENDOR_AMD ||
1632              cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1633              cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1634              cpu_vendor_id == CPU_VENDOR_NSC)) {
1635                 do_cpuid(0x80000000, regs);
1636                 if (regs[0] >= 0x80000000)
1637                         cpu_exthigh = regs[0];
1638         }
1639 #else
1640         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1641             cpu_vendor_id == CPU_VENDOR_AMD ||
1642             cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1643                 do_cpuid(0x80000000, regs);
1644                 cpu_exthigh = regs[0];
1645         }
1646 #endif
1647         if (cpu_exthigh >= 0x80000001) {
1648                 do_cpuid(0x80000001, regs);
1649                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1650                 amd_feature2 = regs[2];
1651         }
1652         if (cpu_exthigh >= 0x80000007) {
1653                 do_cpuid(0x80000007, regs);
1654                 amd_rascap = regs[1];
1655                 amd_pminfo = regs[3];
1656         }
1657         if (cpu_exthigh >= 0x80000008) {
1658                 do_cpuid(0x80000008, regs);
1659                 cpu_maxphyaddr = regs[0] & 0xff;
1660                 amd_extended_feature_extensions = regs[1];
1661                 cpu_procinfo2 = regs[2];
1662         } else {
1663                 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1664         }
1665
1666 #ifdef __i386__
1667         if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1668                 if (cpu == CPU_486) {
1669                         /*
1670                          * These conditions are equivalent to:
1671                          *     - CPU does not support cpuid instruction.
1672                          *     - Cyrix/IBM CPU is detected.
1673                          */
1674                         if (identblue() == IDENTBLUE_IBMCPU) {
1675                                 strcpy(cpu_vendor, "IBM");
1676                                 cpu_vendor_id = CPU_VENDOR_IBM;
1677                                 cpu = CPU_BLUE;
1678                                 return;
1679                         }
1680                 }
1681                 switch (cpu_id & 0xf00) {
1682                 case 0x600:
1683                         /*
1684                          * Cyrix's datasheet does not describe DIRs.
1685                          * Therefor, I assume it does not have them
1686                          * and use the result of the cpuid instruction.
1687                          * XXX they seem to have it for now at least. -Peter
1688                          */
1689                         identifycyrix();
1690                         cpu = CPU_M2;
1691                         break;
1692                 default:
1693                         identifycyrix();
1694                         /*
1695                          * This routine contains a trick.
1696                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1697                          */
1698                         switch (cyrix_did & 0x00f0) {
1699                         case 0x00:
1700                         case 0xf0:
1701                                 cpu = CPU_486DLC;
1702                                 break;
1703                         case 0x10:
1704                                 cpu = CPU_CY486DX;
1705                                 break;
1706                         case 0x20:
1707                                 if ((cyrix_did & 0x000f) < 8)
1708                                         cpu = CPU_M1;
1709                                 else
1710                                         cpu = CPU_M1SC;
1711                                 break;
1712                         case 0x30:
1713                                 cpu = CPU_M1;
1714                                 break;
1715                         case 0x40:
1716                                 /* MediaGX CPU */
1717                                 cpu = CPU_M1SC;
1718                                 break;
1719                         default:
1720                                 /* M2 and later CPUs are treated as M2. */
1721                                 cpu = CPU_M2;
1722
1723                                 /*
1724                                  * enable cpuid instruction.
1725                                  */
1726                                 ccr3 = read_cyrix_reg(CCR3);
1727                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1728                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1729                                 write_cyrix_reg(CCR3, ccr3);
1730
1731                                 do_cpuid(0, regs);
1732                                 cpu_high = regs[0];     /* eax */
1733                                 do_cpuid(1, regs);
1734                                 cpu_id = regs[0];       /* eax */
1735                                 cpu_feature = regs[3];  /* edx */
1736                                 break;
1737                         }
1738                 }
1739         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1740                 /*
1741                  * There are BlueLightning CPUs that do not change
1742                  * undefined flags by dividing 5 by 2.  In this case,
1743                  * the CPU identification routine in locore.s leaves
1744                  * cpu_vendor null string and puts CPU_486 into the
1745                  * cpu.
1746                  */
1747                 if (identblue() == IDENTBLUE_IBMCPU) {
1748                         strcpy(cpu_vendor, "IBM");
1749                         cpu_vendor_id = CPU_VENDOR_IBM;
1750                         cpu = CPU_BLUE;
1751                         return;
1752                 }
1753         }
1754 #endif
1755 }
1756
1757 int
1758 pti_get_default(void)
1759 {
1760
1761         if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0)
1762                 return (0);
1763         if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1764                 return (0);
1765         return (1);
1766 }
1767
1768 static u_int
1769 find_cpu_vendor_id(void)
1770 {
1771         int     i;
1772
1773         for (i = 0; i < nitems(cpu_vendors); i++)
1774                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1775                         return (cpu_vendors[i].vendor_id);
1776         return (0);
1777 }
1778
1779 static void
1780 print_AMD_assoc(int i)
1781 {
1782         if (i == 255)
1783                 printf(", fully associative\n");
1784         else
1785                 printf(", %d-way associative\n", i);
1786 }
1787
1788 static void
1789 print_AMD_l2_assoc(int i)
1790 {
1791         switch (i & 0x0f) {
1792         case 0: printf(", disabled/not present\n"); break;
1793         case 1: printf(", direct mapped\n"); break;
1794         case 2: printf(", 2-way associative\n"); break;
1795         case 4: printf(", 4-way associative\n"); break;
1796         case 6: printf(", 8-way associative\n"); break;
1797         case 8: printf(", 16-way associative\n"); break;
1798         case 15: printf(", fully associative\n"); break;
1799         default: printf(", reserved configuration\n"); break;
1800         }
1801 }
1802
1803 static void
1804 print_AMD_info(void)
1805 {
1806 #ifdef __i386__
1807         uint64_t amd_whcr;
1808 #endif
1809         u_int regs[4];
1810
1811         if (cpu_exthigh >= 0x80000005) {
1812                 do_cpuid(0x80000005, regs);
1813                 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1814                 print_AMD_assoc(regs[0] >> 24);
1815
1816                 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1817                 print_AMD_assoc((regs[0] >> 8) & 0xff);
1818
1819                 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1820                 print_AMD_assoc(regs[1] >> 24);
1821
1822                 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1823                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1824
1825                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1826                 printf(", %d bytes/line", regs[2] & 0xff);
1827                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1828                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1829
1830                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1831                 printf(", %d bytes/line", regs[3] & 0xff);
1832                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1833                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1834         }
1835
1836         if (cpu_exthigh >= 0x80000006) {
1837                 do_cpuid(0x80000006, regs);
1838                 if ((regs[0] >> 16) != 0) {
1839                         printf("L2 2MB data TLB: %d entries",
1840                             (regs[0] >> 16) & 0xfff);
1841                         print_AMD_l2_assoc(regs[0] >> 28);
1842                         printf("L2 2MB instruction TLB: %d entries",
1843                             regs[0] & 0xfff);
1844                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1845                 } else {
1846                         printf("L2 2MB unified TLB: %d entries",
1847                             regs[0] & 0xfff);
1848                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1849                 }
1850                 if ((regs[1] >> 16) != 0) {
1851                         printf("L2 4KB data TLB: %d entries",
1852                             (regs[1] >> 16) & 0xfff);
1853                         print_AMD_l2_assoc(regs[1] >> 28);
1854
1855                         printf("L2 4KB instruction TLB: %d entries",
1856                             (regs[1] >> 16) & 0xfff);
1857                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1858                 } else {
1859                         printf("L2 4KB unified TLB: %d entries",
1860                             (regs[1] >> 16) & 0xfff);
1861                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1862                 }
1863                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1864                 printf(", %d bytes/line", regs[2] & 0xff);
1865                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1866                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1867         }
1868
1869 #ifdef __i386__
1870         if (((cpu_id & 0xf00) == 0x500)
1871             && (((cpu_id & 0x0f0) > 0x80)
1872                 || (((cpu_id & 0x0f0) == 0x80)
1873                     && (cpu_id & 0x00f) > 0x07))) {
1874                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1875                 amd_whcr = rdmsr(0xc0000082);
1876                 if (!(amd_whcr & (0x3ff << 22))) {
1877                         printf("Write Allocate Disable\n");
1878                 } else {
1879                         printf("Write Allocate Enable Limit: %dM bytes\n",
1880                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1881                         printf("Write Allocate 15-16M bytes: %s\n",
1882                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1883                 }
1884         } else if (((cpu_id & 0xf00) == 0x500)
1885                    && ((cpu_id & 0x0f0) > 0x50)) {
1886                 /* K6, K6-2(old core) */
1887                 amd_whcr = rdmsr(0xc0000082);
1888                 if (!(amd_whcr & (0x7f << 1))) {
1889                         printf("Write Allocate Disable\n");
1890                 } else {
1891                         printf("Write Allocate Enable Limit: %dM bytes\n",
1892                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1893                         printf("Write Allocate 15-16M bytes: %s\n",
1894                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1895                         printf("Hardware Write Allocate Control: %s\n",
1896                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1897                 }
1898         }
1899 #endif
1900         /*
1901          * Opteron Rev E shows a bug as in very rare occasions a read memory
1902          * barrier is not performed as expected if it is followed by a
1903          * non-atomic read-modify-write instruction.
1904          * As long as that bug pops up very rarely (intensive machine usage
1905          * on other operating systems generally generates one unexplainable
1906          * crash any 2 months) and as long as a model specific fix would be
1907          * impractical at this stage, print out a warning string if the broken
1908          * model and family are identified.
1909          */
1910         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1911             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1912                 printf("WARNING: This architecture revision has known SMP "
1913                     "hardware bugs which may cause random instability\n");
1914 }
1915
1916 static void
1917 print_INTEL_info(void)
1918 {
1919         u_int regs[4];
1920         u_int rounds, regnum;
1921         u_int nwaycode, nway;
1922
1923         if (cpu_high >= 2) {
1924                 rounds = 0;
1925                 do {
1926                         do_cpuid(0x2, regs);
1927                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1928                                 break;  /* we have a buggy CPU */
1929
1930                         for (regnum = 0; regnum <= 3; ++regnum) {
1931                                 if (regs[regnum] & (1<<31))
1932                                         continue;
1933                                 if (regnum != 0)
1934                                         print_INTEL_TLB(regs[regnum] & 0xff);
1935                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1936                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1937                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1938                         }
1939                 } while (--rounds > 0);
1940         }
1941
1942         if (cpu_exthigh >= 0x80000006) {
1943                 do_cpuid(0x80000006, regs);
1944                 nwaycode = (regs[2] >> 12) & 0x0f;
1945                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1946                         nway = 1 << (nwaycode / 2);
1947                 else
1948                         nway = 0;
1949                 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1950                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1951         }
1952 }
1953
1954 static void
1955 print_INTEL_TLB(u_int data)
1956 {
1957         switch (data) {
1958         case 0x0:
1959         case 0x40:
1960         default:
1961                 break;
1962         case 0x1:
1963                 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1964                 break;
1965         case 0x2:
1966                 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1967                 break;
1968         case 0x3:
1969                 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1970                 break;
1971         case 0x4:
1972                 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1973                 break;
1974         case 0x6:
1975                 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1976                 break;
1977         case 0x8:
1978                 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
1979                 break;
1980         case 0x9:
1981                 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
1982                 break;
1983         case 0xa:
1984                 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
1985                 break;
1986         case 0xb:
1987                 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
1988                 break;
1989         case 0xc:
1990                 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
1991                 break;
1992         case 0xd:
1993                 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
1994                 break;
1995         case 0xe:
1996                 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
1997                 break;
1998         case 0x1d:
1999                 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2000                 break;
2001         case 0x21:
2002                 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2003                 break;
2004         case 0x22:
2005                 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2006                 break;
2007         case 0x23:
2008                 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2009                 break;
2010         case 0x24:
2011                 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2012                 break;
2013         case 0x25:
2014                 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2015                 break;
2016         case 0x29:
2017                 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2018                 break;
2019         case 0x2c:
2020                 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2021                 break;
2022         case 0x30:
2023                 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2024                 break;
2025         case 0x39: /* De-listed in SDM rev. 54 */
2026                 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2027                 break;
2028         case 0x3b: /* De-listed in SDM rev. 54 */
2029                 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2030                 break;
2031         case 0x3c: /* De-listed in SDM rev. 54 */
2032                 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2033                 break;
2034         case 0x41:
2035                 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2036                 break;
2037         case 0x42:
2038                 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2039                 break;
2040         case 0x43:
2041                 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2042                 break;
2043         case 0x44:
2044                 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2045                 break;
2046         case 0x45:
2047                 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2048                 break;
2049         case 0x46:
2050                 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2051                 break;
2052         case 0x47:
2053                 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2054                 break;
2055         case 0x48:
2056                 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2057                 break;
2058         case 0x49:
2059                 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2060                     CPUID_TO_MODEL(cpu_id) == 0x6)
2061                         printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2062                 else
2063                         printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2064                 break;
2065         case 0x4a:
2066                 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2067                 break;
2068         case 0x4b:
2069                 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2070                 break;
2071         case 0x4c:
2072                 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2073                 break;
2074         case 0x4d:
2075                 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2076                 break;
2077         case 0x4e:
2078                 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2079                 break;
2080         case 0x4f:
2081                 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2082                 break;
2083         case 0x50:
2084                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2085                 break;
2086         case 0x51:
2087                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2088                 break;
2089         case 0x52:
2090                 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2091                 break;
2092         case 0x55:
2093                 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2094                 break;
2095         case 0x56:
2096                 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2097                 break;
2098         case 0x57:
2099                 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2100                 break;
2101         case 0x59:
2102                 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2103                 break;
2104         case 0x5a:
2105                 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2106                 break;
2107         case 0x5b:
2108                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2109                 break;
2110         case 0x5c:
2111                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2112                 break;
2113         case 0x5d:
2114                 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2115                 break;
2116         case 0x60:
2117                 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2118                 break;
2119         case 0x61:
2120                 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2121                 break;
2122         case 0x63:
2123                 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2124                 break;
2125         case 0x64:
2126                 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2127                 break;
2128         case 0x66:
2129                 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2130                 break;
2131         case 0x67:
2132                 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2133                 break;
2134         case 0x68:
2135                 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2136                 break;
2137         case 0x6a:
2138                 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2139                 break;
2140         case 0x6b:
2141                 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2142                 break;
2143         case 0x6c:
2144                 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2145                 break;
2146         case 0x6d:
2147                 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2148                 break;
2149         case 0x70:
2150                 printf("Trace cache: 12K-uops, 8-way set associative\n");
2151                 break;
2152         case 0x71:
2153                 printf("Trace cache: 16K-uops, 8-way set associative\n");
2154                 break;
2155         case 0x72:
2156                 printf("Trace cache: 32K-uops, 8-way set associative\n");
2157                 break;
2158         case 0x76:
2159                 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2160                 break;
2161         case 0x78:
2162                 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2163                 break;
2164         case 0x79:
2165                 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2166                 break;
2167         case 0x7a:
2168                 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2169                 break;
2170         case 0x7b:
2171                 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2172                 break;
2173         case 0x7c:
2174                 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2175                 break;
2176         case 0x7d:
2177                 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2178                 break;
2179         case 0x7f:
2180                 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2181                 break;
2182         case 0x80:
2183                 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2184                 break;
2185         case 0x82:
2186                 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2187                 break;
2188         case 0x83:
2189                 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2190                 break;
2191         case 0x84:
2192                 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2193                 break;
2194         case 0x85:
2195                 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2196                 break;
2197         case 0x86:
2198                 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2199                 break;
2200         case 0x87:
2201                 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2202                 break;
2203         case 0xa0:
2204                 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2205                 break;
2206         case 0xb0:
2207                 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2208                 break;
2209         case 0xb1:
2210                 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2211                 break;
2212         case 0xb2:
2213                 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2214                 break;
2215         case 0xb3:
2216                 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2217                 break;
2218         case 0xb4:
2219                 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2220                 break;
2221         case 0xb5:
2222                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2223                 break;
2224         case 0xb6:
2225                 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2226                 break;
2227         case 0xba:
2228                 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2229                 break;
2230         case 0xc0:
2231                 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2232                 break;
2233         case 0xc1:
2234                 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2235                 break;
2236         case 0xc2:
2237                 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2238                 break;
2239         case 0xc3:
2240                 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2241                 break;
2242         case 0xc4:
2243                 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2244                 break;
2245         case 0xca:
2246                 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2247                 break;
2248         case 0xd0:
2249                 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2250                 break;
2251         case 0xd1:
2252                 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2253                 break;
2254         case 0xd2:
2255                 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2256                 break;
2257         case 0xd6:
2258                 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2259                 break;
2260         case 0xd7:
2261                 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2262                 break;
2263         case 0xd8:
2264                 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2265                 break;
2266         case 0xdc:
2267                 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2268                 break;
2269         case 0xdd:
2270                 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2271                 break;
2272         case 0xde:
2273                 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2274                 break;
2275         case 0xe2:
2276                 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2277                 break;
2278         case 0xe3:
2279                 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2280                 break;
2281         case 0xe4:
2282                 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2283                 break;
2284         case 0xea:
2285                 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2286                 break;
2287         case 0xeb:
2288                 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2289                 break;
2290         case 0xec:
2291                 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2292                 break;
2293         case 0xf0:
2294                 printf("64-Byte prefetching\n");
2295                 break;
2296         case 0xf1:
2297                 printf("128-Byte prefetching\n");
2298                 break;
2299         }
2300 }
2301
2302 static void
2303 print_svm_info(void)
2304 {
2305         u_int features, regs[4];
2306         uint64_t msr;
2307         int comma;
2308
2309         printf("\n  SVM: ");
2310         do_cpuid(0x8000000A, regs);
2311         features = regs[3];
2312
2313         msr = rdmsr(MSR_VM_CR);
2314         if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2315                 printf("(disabled in BIOS) ");
2316
2317         if (!bootverbose) {
2318                 comma = 0;
2319                 if (features & (1 << 0)) {
2320                         printf("%sNP", comma ? "," : "");
2321                         comma = 1;
2322                 }
2323                 if (features & (1 << 3)) {
2324                         printf("%sNRIP", comma ? "," : "");
2325                         comma = 1;
2326                 }
2327                 if (features & (1 << 5)) {
2328                         printf("%sVClean", comma ? "," : "");
2329                         comma = 1;
2330                 }
2331                 if (features & (1 << 6)) {
2332                         printf("%sAFlush", comma ? "," : "");
2333                         comma = 1;
2334                 }
2335                 if (features & (1 << 7)) {
2336                         printf("%sDAssist", comma ? "," : "");
2337                         comma = 1;
2338                 }
2339                 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2340                 return;
2341         }
2342
2343         printf("Features=0x%b", features,
2344                "\020"
2345                "\001NP"                 /* Nested paging */
2346                "\002LbrVirt"            /* LBR virtualization */
2347                "\003SVML"               /* SVM lock */
2348                "\004NRIPS"              /* NRIP save */
2349                "\005TscRateMsr"         /* MSR based TSC rate control */
2350                "\006VmcbClean"          /* VMCB clean bits */
2351                "\007FlushByAsid"        /* Flush by ASID */
2352                "\010DecodeAssist"       /* Decode assist */
2353                "\011<b8>"
2354                "\012<b9>"
2355                "\013PauseFilter"        /* PAUSE intercept filter */
2356                "\014EncryptedMcodePatch"
2357                "\015PauseFilterThreshold" /* PAUSE filter threshold */
2358                "\016AVIC"               /* virtual interrupt controller */
2359                "\017<b14>"
2360                "\020V_VMSAVE_VMLOAD"
2361                "\021vGIF"
2362                "\022GMET"               /* Guest Mode Execute Trap */
2363                "\023<b18>"
2364                "\024<b19>"
2365                "\025<b20>"
2366                "\026<b21>"
2367                "\027<b22>"
2368                "\030<b23>"
2369                "\031<b24>"
2370                "\032<b25>"
2371                "\033<b26>"
2372                "\034<b27>"
2373                "\035<b28>"
2374                "\036<b29>"
2375                "\037<b30>"
2376                "\040<b31>"
2377                 );
2378         printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2379 }
2380
2381 #ifdef __i386__
2382 static void
2383 print_transmeta_info(void)
2384 {
2385         u_int regs[4], nreg = 0;
2386
2387         do_cpuid(0x80860000, regs);
2388         nreg = regs[0];
2389         if (nreg >= 0x80860001) {
2390                 do_cpuid(0x80860001, regs);
2391                 printf("  Processor revision %u.%u.%u.%u\n",
2392                        (regs[1] >> 24) & 0xff,
2393                        (regs[1] >> 16) & 0xff,
2394                        (regs[1] >> 8) & 0xff,
2395                        regs[1] & 0xff);
2396         }
2397         if (nreg >= 0x80860002) {
2398                 do_cpuid(0x80860002, regs);
2399                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2400                        (regs[1] >> 24) & 0xff,
2401                        (regs[1] >> 16) & 0xff,
2402                        (regs[1] >> 8) & 0xff,
2403                        regs[1] & 0xff,
2404                        regs[2]);
2405         }
2406         if (nreg >= 0x80860006) {
2407                 char info[65];
2408                 do_cpuid(0x80860003, (u_int*) &info[0]);
2409                 do_cpuid(0x80860004, (u_int*) &info[16]);
2410                 do_cpuid(0x80860005, (u_int*) &info[32]);
2411                 do_cpuid(0x80860006, (u_int*) &info[48]);
2412                 info[64] = 0;
2413                 printf("  %s\n", info);
2414         }
2415 }
2416 #endif
2417
2418 static void
2419 print_via_padlock_info(void)
2420 {
2421         u_int regs[4];
2422
2423         do_cpuid(0xc0000001, regs);
2424         printf("\n  VIA Padlock Features=0x%b", regs[3],
2425         "\020"
2426         "\003RNG"               /* RNG */
2427         "\007AES"               /* ACE */
2428         "\011AES-CTR"           /* ACE2 */
2429         "\013SHA1,SHA256"       /* PHE */
2430         "\015RSA"               /* PMM */
2431         );
2432 }
2433
2434 static uint32_t
2435 vmx_settable(uint64_t basic, int msr, int true_msr)
2436 {
2437         uint64_t val;
2438
2439         if (basic & (1ULL << 55))
2440                 val = rdmsr(true_msr);
2441         else
2442                 val = rdmsr(msr);
2443
2444         /* Just report the controls that can be set to 1. */
2445         return (val >> 32);
2446 }
2447
2448 static void
2449 print_vmx_info(void)
2450 {
2451         uint64_t basic, msr;
2452         uint32_t entry, exit, mask, pin, proc, proc2;
2453         int comma;
2454
2455         printf("\n  VT-x: ");
2456         msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2457         if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2458                 printf("(disabled in BIOS) ");
2459         basic = rdmsr(MSR_VMX_BASIC);
2460         pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2461             MSR_VMX_TRUE_PINBASED_CTLS);
2462         proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2463             MSR_VMX_TRUE_PROCBASED_CTLS);
2464         if (proc & PROCBASED_SECONDARY_CONTROLS)
2465                 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2466                     MSR_VMX_PROCBASED_CTLS2);
2467         else
2468                 proc2 = 0;
2469         exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2470         entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2471
2472         if (!bootverbose) {
2473                 comma = 0;
2474                 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2475                     entry & VM_ENTRY_LOAD_PAT) {
2476                         printf("%sPAT", comma ? "," : "");
2477                         comma = 1;
2478                 }
2479                 if (proc & PROCBASED_HLT_EXITING) {
2480                         printf("%sHLT", comma ? "," : "");
2481                         comma = 1;
2482                 }
2483                 if (proc & PROCBASED_MTF) {
2484                         printf("%sMTF", comma ? "," : "");
2485                         comma = 1;
2486                 }
2487                 if (proc & PROCBASED_PAUSE_EXITING) {
2488                         printf("%sPAUSE", comma ? "," : "");
2489                         comma = 1;
2490                 }
2491                 if (proc2 & PROCBASED2_ENABLE_EPT) {
2492                         printf("%sEPT", comma ? "," : "");
2493                         comma = 1;
2494                 }
2495                 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2496                         printf("%sUG", comma ? "," : "");
2497                         comma = 1;
2498                 }
2499                 if (proc2 & PROCBASED2_ENABLE_VPID) {
2500                         printf("%sVPID", comma ? "," : "");
2501                         comma = 1;
2502                 }
2503                 if (proc & PROCBASED_USE_TPR_SHADOW &&
2504                     proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2505                     proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2506                     proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2507                     proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2508                         printf("%sVID", comma ? "," : "");
2509                         comma = 1;
2510                         if (pin & PINBASED_POSTED_INTERRUPT)
2511                                 printf(",PostIntr");
2512                 }
2513                 return;
2514         }
2515
2516         mask = basic >> 32;
2517         printf("Basic Features=0x%b", mask,
2518         "\020"
2519         "\02132PA"              /* 32-bit physical addresses */
2520         "\022SMM"               /* SMM dual-monitor */
2521         "\027INS/OUTS"          /* VM-exit info for INS and OUTS */
2522         "\030TRUE"              /* TRUE_CTLS MSRs */
2523         );
2524         printf("\n        Pin-Based Controls=0x%b", pin,
2525         "\020"
2526         "\001ExtINT"            /* External-interrupt exiting */
2527         "\004NMI"               /* NMI exiting */
2528         "\006VNMI"              /* Virtual NMIs */
2529         "\007PreTmr"            /* Activate VMX-preemption timer */
2530         "\010PostIntr"          /* Process posted interrupts */
2531         );
2532         printf("\n        Primary Processor Controls=0x%b", proc,
2533         "\020"
2534         "\003INTWIN"            /* Interrupt-window exiting */
2535         "\004TSCOff"            /* Use TSC offsetting */
2536         "\010HLT"               /* HLT exiting */
2537         "\012INVLPG"            /* INVLPG exiting */
2538         "\013MWAIT"             /* MWAIT exiting */
2539         "\014RDPMC"             /* RDPMC exiting */
2540         "\015RDTSC"             /* RDTSC exiting */
2541         "\020CR3-LD"            /* CR3-load exiting */
2542         "\021CR3-ST"            /* CR3-store exiting */
2543         "\024CR8-LD"            /* CR8-load exiting */
2544         "\025CR8-ST"            /* CR8-store exiting */
2545         "\026TPR"               /* Use TPR shadow */
2546         "\027NMIWIN"            /* NMI-window exiting */
2547         "\030MOV-DR"            /* MOV-DR exiting */
2548         "\031IO"                /* Unconditional I/O exiting */
2549         "\032IOmap"             /* Use I/O bitmaps */
2550         "\034MTF"               /* Monitor trap flag */
2551         "\035MSRmap"            /* Use MSR bitmaps */
2552         "\036MONITOR"           /* MONITOR exiting */
2553         "\037PAUSE"             /* PAUSE exiting */
2554         );
2555         if (proc & PROCBASED_SECONDARY_CONTROLS)
2556                 printf("\n        Secondary Processor Controls=0x%b", proc2,
2557                 "\020"
2558                 "\001APIC"              /* Virtualize APIC accesses */
2559                 "\002EPT"               /* Enable EPT */
2560                 "\003DT"                /* Descriptor-table exiting */
2561                 "\004RDTSCP"            /* Enable RDTSCP */
2562                 "\005x2APIC"            /* Virtualize x2APIC mode */
2563                 "\006VPID"              /* Enable VPID */
2564                 "\007WBINVD"            /* WBINVD exiting */
2565                 "\010UG"                /* Unrestricted guest */
2566                 "\011APIC-reg"          /* APIC-register virtualization */
2567                 "\012VID"               /* Virtual-interrupt delivery */
2568                 "\013PAUSE-loop"        /* PAUSE-loop exiting */
2569                 "\014RDRAND"            /* RDRAND exiting */
2570                 "\015INVPCID"           /* Enable INVPCID */
2571                 "\016VMFUNC"            /* Enable VM functions */
2572                 "\017VMCS"              /* VMCS shadowing */
2573                 "\020EPT#VE"            /* EPT-violation #VE */
2574                 "\021XSAVES"            /* Enable XSAVES/XRSTORS */
2575                 );
2576         printf("\n        Exit Controls=0x%b", mask,
2577         "\020"
2578         "\003DR"                /* Save debug controls */
2579                                 /* Ignore Host address-space size */
2580         "\015PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2581         "\020AckInt"            /* Acknowledge interrupt on exit */
2582         "\023PAT-SV"            /* Save MSR_PAT */
2583         "\024PAT-LD"            /* Load MSR_PAT */
2584         "\025EFER-SV"           /* Save MSR_EFER */
2585         "\026EFER-LD"           /* Load MSR_EFER */
2586         "\027PTMR-SV"           /* Save VMX-preemption timer value */
2587         );
2588         printf("\n        Entry Controls=0x%b", mask,
2589         "\020"
2590         "\003DR"                /* Save debug controls */
2591                                 /* Ignore IA-32e mode guest */
2592                                 /* Ignore Entry to SMM */
2593                                 /* Ignore Deactivate dual-monitor treatment */
2594         "\016PERF"              /* Load MSR_PERF_GLOBAL_CTRL */
2595         "\017PAT"               /* Load MSR_PAT */
2596         "\020EFER"              /* Load MSR_EFER */
2597         );
2598         if (proc & PROCBASED_SECONDARY_CONTROLS &&
2599             (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2600                 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2601                 mask = msr;
2602                 printf("\n        EPT Features=0x%b", mask,
2603                 "\020"
2604                 "\001XO"                /* Execute-only translations */
2605                 "\007PW4"               /* Page-walk length of 4 */
2606                 "\011UC"                /* EPT paging-structure mem can be UC */
2607                 "\017WB"                /* EPT paging-structure mem can be WB */
2608                 "\0212M"                /* EPT PDE can map a 2-Mbyte page */
2609                 "\0221G"                /* EPT PDPTE can map a 1-Gbyte page */
2610                 "\025INVEPT"            /* INVEPT is supported */
2611                 "\026AD"                /* Accessed and dirty flags for EPT */
2612                 "\032single"            /* INVEPT single-context type */
2613                 "\033all"               /* INVEPT all-context type */
2614                 );
2615                 mask = msr >> 32;
2616                 printf("\n        VPID Features=0x%b", mask,
2617                 "\020"
2618                 "\001INVVPID"           /* INVVPID is supported */
2619                 "\011individual"        /* INVVPID individual-address type */
2620                 "\012single"            /* INVVPID single-context type */
2621                 "\013all"               /* INVVPID all-context type */
2622                  /* INVVPID single-context-retaining-globals type */
2623                 "\014single-globals"
2624                 );
2625         }
2626 }
2627
2628 static void
2629 print_hypervisor_info(void)
2630 {
2631
2632         if (*hv_vendor != '\0')
2633                 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2634 }
2635
2636 /*
2637  * Returns the maximum physical address that can be used with the
2638  * current system.
2639  */
2640 vm_paddr_t
2641 cpu_getmaxphyaddr(void)
2642 {
2643
2644 #if defined(__i386__)
2645         if (!pae_mode)
2646                 return (0xffffffff);
2647 #endif
2648         return ((1ULL << cpu_maxphyaddr) - 1);
2649 }