2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Machine dependent interrupt code for x86. For x86, we have to
31 * deal with different PICs. Thus, we use the passed in vector to lookup
32 * an interrupt source associated with that vector. The interrupt source
33 * describes which PIC the source belongs to and includes methods to handle
37 #include "opt_atpic.h"
41 #include <sys/param.h>
43 #include <sys/interrupt.h>
45 #include <sys/kernel.h>
47 #include <sys/malloc.h>
48 #include <sys/mutex.h>
52 #include <sys/syslog.h>
53 #include <sys/systm.h>
54 #include <sys/vmmeter.h>
55 #include <machine/clock.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/smp.h>
63 #include <machine/segments.h>
64 #include <machine/frame.h>
65 #include <dev/ic/i8259.h>
66 #include <x86/isa/icu.h>
68 #include <pc98/cbus/cbus.h>
70 #include <isa/isareg.h>
74 #define MAX_STRAY_LOG 5
76 typedef void (*mask_fn)(void *);
78 static int intrcnt_index;
79 static struct intsrc **interrupt_sources;
80 static struct sx intrsrc_lock;
81 static struct mtx intrpic_lock;
82 static struct mtx intrcnt_lock;
83 static TAILQ_HEAD(pics_head, pic) pics;
86 #if defined(SMP) && !defined(EARLY_AP_STARTUP)
87 static int assign_cpu;
92 size_t sintrcnt = sizeof(intrcnt);
93 size_t sintrnames = sizeof(intrnames);
96 static MALLOC_DEFINE(M_INTR, "intr", "Interrupt Sources");
98 static int intr_assign_cpu(void *arg, int cpu);
99 static void intr_disable_src(void *arg);
100 static void intr_init(void *__dummy);
101 static int intr_pic_registered(struct pic *pic);
102 static void intrcnt_setname(const char *name, int index);
103 static void intrcnt_updatename(struct intsrc *is);
104 static void intrcnt_register(struct intsrc *is);
107 * SYSINIT levels for SI_SUB_INTR:
109 * SI_ORDER_FIRST: Initialize locks and pics TAILQ, xen_hvm_cpu_init
110 * SI_ORDER_SECOND: Xen PICs
111 * SI_ORDER_THIRD: Add I/O APIC PICs, alloc MSI and Xen IRQ ranges
112 * SI_ORDER_FOURTH: Add 8259A PICs
113 * SI_ORDER_FOURTH + 1: Finalize interrupt count and add interrupt sources
114 * SI_ORDER_MIDDLE: SMP interrupt counters
115 * SI_ORDER_ANY: Enable interrupts on BSP
119 intr_pic_registered(struct pic *pic)
123 TAILQ_FOREACH(p, &pics, pics) {
131 * Register a new interrupt controller (PIC). This is to support suspend
132 * and resume where we suspend/resume controllers rather than individual
133 * sources. This also allows controllers with no active sources (such as
134 * 8259As in a system using the APICs) to participate in suspend and resume.
137 intr_register_pic(struct pic *pic)
141 mtx_lock(&intrpic_lock);
142 if (intr_pic_registered(pic))
145 TAILQ_INSERT_TAIL(&pics, pic, pics);
148 mtx_unlock(&intrpic_lock);
153 * Allocate interrupt source arrays and register interrupt sources
154 * once the number of interrupts is known.
157 intr_init_sources(void *arg)
161 MPASS(num_io_irqs > 0);
163 interrupt_sources = mallocarray(num_io_irqs, sizeof(*interrupt_sources),
164 M_INTR, M_WAITOK | M_ZERO);
167 * - 1 ??? dummy counter.
168 * - 2 counters for each I/O interrupt.
169 * - 1 counter for each CPU for lapic timer.
170 * - 1 counter for each CPU for the Hyper-V vmbus driver.
171 * - 8 counters for each CPU for IPI counters for SMP.
173 nintrcnt = 1 + num_io_irqs * 2 + mp_ncpus * 2;
176 nintrcnt += 8 * mp_ncpus;
178 intrcnt = mallocarray(nintrcnt, sizeof(u_long), M_INTR, M_WAITOK |
180 intrnames = mallocarray(nintrcnt, MAXCOMLEN + 1, M_INTR, M_WAITOK |
182 sintrcnt = nintrcnt * sizeof(u_long);
183 sintrnames = nintrcnt * (MAXCOMLEN + 1);
185 intrcnt_setname("???", 0);
189 * NB: intrpic_lock is not held here to avoid LORs due to
190 * malloc() in intr_register_source(). However, we are still
191 * single-threaded at this point in startup so the list of
192 * PICs shouldn't change.
194 TAILQ_FOREACH(pic, &pics, pics) {
195 if (pic->pic_register_sources != NULL)
196 pic->pic_register_sources(pic);
199 SYSINIT(intr_init_sources, SI_SUB_INTR, SI_ORDER_FOURTH + 1, intr_init_sources,
203 * Register a new interrupt source with the global interrupt system.
204 * The global interrupts need to be disabled when this function is
208 intr_register_source(struct intsrc *isrc)
212 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
213 vector = isrc->is_pic->pic_vector(isrc);
214 KASSERT(vector < num_io_irqs, ("IRQ %d too large (%u irqs)", vector,
216 if (interrupt_sources[vector] != NULL)
218 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
219 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
220 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
224 sx_xlock(&intrsrc_lock);
225 if (interrupt_sources[vector] != NULL) {
226 sx_xunlock(&intrsrc_lock);
227 intr_event_destroy(isrc->is_event);
230 intrcnt_register(isrc);
231 interrupt_sources[vector] = isrc;
232 isrc->is_handlers = 0;
233 sx_xunlock(&intrsrc_lock);
238 intr_lookup_source(int vector)
241 if (vector < 0 || vector >= num_io_irqs)
243 return (interrupt_sources[vector]);
247 intr_add_handler(const char *name, int vector, driver_filter_t filter,
248 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
253 isrc = intr_lookup_source(vector);
256 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
257 arg, intr_priority(flags), flags, cookiep);
259 sx_xlock(&intrsrc_lock);
260 intrcnt_updatename(isrc);
262 if (isrc->is_handlers == 1) {
263 isrc->is_pic->pic_enable_intr(isrc);
264 isrc->is_pic->pic_enable_source(isrc);
266 sx_xunlock(&intrsrc_lock);
272 intr_remove_handler(void *cookie)
277 isrc = intr_handler_source(cookie);
278 error = intr_event_remove_handler(cookie);
280 sx_xlock(&intrsrc_lock);
282 if (isrc->is_handlers == 0) {
283 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
284 isrc->is_pic->pic_disable_intr(isrc);
286 intrcnt_updatename(isrc);
287 sx_xunlock(&intrsrc_lock);
293 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
297 isrc = intr_lookup_source(vector);
300 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
304 intr_disable_src(void *arg)
309 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
313 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
315 struct intr_event *ie;
319 * We count software interrupts when we process them. The
320 * code here follows previous practice, but there's an
321 * argument for counting hardware interrupts when they're
325 PCPU_INC(cnt.v_intr);
330 * XXX: We assume that IRQ 0 is only used for the ISA timer
333 vector = isrc->is_pic->pic_vector(isrc);
338 * For stray interrupts, mask and EOI the source, bump the
339 * stray count, and log the condition.
341 if (intr_event_handle(ie, frame) != 0) {
342 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
343 (*isrc->is_straycount)++;
344 if (*isrc->is_straycount < MAX_STRAY_LOG)
345 log(LOG_ERR, "stray irq%d\n", vector);
346 else if (*isrc->is_straycount == MAX_STRAY_LOG)
348 "too many stray irq %d's: not logging anymore\n",
354 intr_resume(bool suspend_cancelled)
361 mtx_lock(&intrpic_lock);
362 TAILQ_FOREACH(pic, &pics, pics) {
363 if (pic->pic_resume != NULL)
364 pic->pic_resume(pic, suspend_cancelled);
366 mtx_unlock(&intrpic_lock);
374 mtx_lock(&intrpic_lock);
375 TAILQ_FOREACH_REVERSE(pic, &pics, pics_head, pics) {
376 if (pic->pic_suspend != NULL)
377 pic->pic_suspend(pic);
379 mtx_unlock(&intrpic_lock);
383 intr_assign_cpu(void *arg, int cpu)
389 #ifdef EARLY_AP_STARTUP
390 MPASS(mp_ncpus == 1 || smp_started);
392 /* Nothing to do if there is only a single CPU. */
393 if (mp_ncpus > 1 && cpu != NOCPU) {
396 * Don't do anything during early boot. We will pick up the
397 * assignment once the APs are started.
399 if (assign_cpu && cpu != NOCPU) {
402 sx_xlock(&intrsrc_lock);
403 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
404 sx_xunlock(&intrsrc_lock);
414 intrcnt_setname(const char *name, int index)
417 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
422 intrcnt_updatename(struct intsrc *is)
425 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
429 intrcnt_register(struct intsrc *is)
431 char straystr[MAXCOMLEN + 1];
433 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
434 mtx_lock_spin(&intrcnt_lock);
435 MPASS(intrcnt_index + 2 <= nintrcnt);
436 is->is_index = intrcnt_index;
438 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
439 is->is_pic->pic_vector(is));
440 intrcnt_updatename(is);
441 is->is_count = &intrcnt[is->is_index];
442 intrcnt_setname(straystr, is->is_index + 1);
443 is->is_straycount = &intrcnt[is->is_index + 1];
444 mtx_unlock_spin(&intrcnt_lock);
448 intrcnt_add(const char *name, u_long **countp)
451 mtx_lock_spin(&intrcnt_lock);
452 MPASS(intrcnt_index < nintrcnt);
453 *countp = &intrcnt[intrcnt_index];
454 intrcnt_setname(name, intrcnt_index);
456 mtx_unlock_spin(&intrcnt_lock);
460 intr_init(void *dummy __unused)
464 mtx_init(&intrpic_lock, "intrpic", NULL, MTX_DEF);
465 sx_init(&intrsrc_lock, "intrsrc");
466 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
468 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
471 intr_init_final(void *dummy __unused)
475 * Enable interrupts on the BSP after all of the interrupt
476 * controllers are initialized. Device interrupts are still
477 * disabled in the interrupt controllers until interrupt
478 * handlers are registered. Interrupts are enabled on each AP
479 * after their first context switch.
483 SYSINIT(intr_init_final, SI_SUB_INTR, SI_ORDER_ANY, intr_init_final, NULL);
486 /* Initialize the two 8259A's to a known-good shutdown state. */
491 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
492 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
493 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID));
494 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE);
495 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
496 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
498 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
499 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
500 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_SLAVEID);
501 outb(IO_ICU2 + ICU_IMR_OFFSET, SLAVE_MODE);
502 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
503 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
507 /* Add a description to an active interrupt handler. */
509 intr_describe(u_int vector, void *ih, const char *descr)
514 isrc = intr_lookup_source(vector);
517 error = intr_event_describe_handler(isrc->is_event, ih, descr);
520 intrcnt_updatename(isrc);
530 sx_xlock(&intrsrc_lock);
531 for (v = 0; v < num_io_irqs; v++) {
532 is = interrupt_sources[v];
535 if (is->is_pic->pic_reprogram_pin != NULL)
536 is->is_pic->pic_reprogram_pin(is);
538 sx_xunlock(&intrsrc_lock);
543 * Dump data about interrupt handlers
545 DB_SHOW_COMMAND(irqs, db_show_irqs)
547 struct intsrc **isrc;
551 if (strcmp(modif, "v") == 0)
555 isrc = interrupt_sources;
556 for (i = 0; i < num_io_irqs && !db_pager_quit; i++, isrc++)
558 db_dump_intr_event((*isrc)->is_event, verbose);
564 * Support for balancing interrupt sources across CPUs. For now we just
565 * allocate CPUs round-robin.
568 cpuset_t intr_cpus = CPUSET_T_INITIALIZER(0x1);
569 static int current_cpu;
572 * Return the CPU that the next interrupt source should use. For now
573 * this just returns the next local APIC according to round-robin.
580 #ifdef EARLY_AP_STARTUP
581 MPASS(mp_ncpus == 1 || smp_started);
583 return (PCPU_GET(apic_id));
585 /* Leave all interrupts on the BSP during boot. */
587 return (PCPU_GET(apic_id));
590 mtx_lock_spin(&icu_lock);
591 apic_id = cpu_apic_ids[current_cpu];
594 if (current_cpu > mp_maxid)
596 } while (!CPU_ISSET(current_cpu, &intr_cpus));
597 mtx_unlock_spin(&icu_lock);
601 /* Attempt to bind the specified IRQ to the specified CPU. */
603 intr_bind(u_int vector, u_char cpu)
607 isrc = intr_lookup_source(vector);
610 return (intr_event_bind(isrc->is_event, cpu));
614 * Add a CPU to our mask of valid CPUs that can be destinations of
618 intr_add_cpu(u_int cpu)
622 panic("%s: Invalid CPU ID", __func__);
624 printf("INTR: Adding local APIC %d as a target\n",
627 CPU_SET(cpu, &intr_cpus);
630 #ifndef EARLY_AP_STARTUP
632 * Distribute all the interrupt sources among the available CPUs once the
633 * AP's have been launched.
636 intr_shuffle_irqs(void *arg __unused)
641 /* Don't bother on UP. */
645 /* Round-robin assign a CPU to each enabled source. */
646 sx_xlock(&intrsrc_lock);
648 for (i = 0; i < num_io_irqs; i++) {
649 isrc = interrupt_sources[i];
650 if (isrc != NULL && isrc->is_handlers > 0) {
652 * If this event is already bound to a CPU,
653 * then assign the source to that CPU instead
654 * of picking one via round-robin. Note that
655 * this is careful to only advance the
656 * round-robin if the CPU assignment succeeds.
658 if (isrc->is_event->ie_cpu != NOCPU)
659 (void)isrc->is_pic->pic_assign_cpu(isrc,
660 cpu_apic_ids[isrc->is_event->ie_cpu]);
661 else if (isrc->is_pic->pic_assign_cpu(isrc,
662 cpu_apic_ids[current_cpu]) == 0)
663 (void)intr_next_cpu();
667 sx_xunlock(&intrsrc_lock);
669 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
674 * Always route interrupts to the current processor in the UP case.
680 return (PCPU_GET(apic_id));