2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Machine dependent interrupt code for x86. For x86, we have to
33 * deal with different PICs. Thus, we use the passed in vector to lookup
34 * an interrupt source associated with that vector. The interrupt source
35 * describes which PIC the source belongs to and includes methods to handle
39 #include "opt_atpic.h"
42 #include <sys/param.h>
44 #include <sys/interrupt.h>
46 #include <sys/kernel.h>
48 #include <sys/mutex.h>
50 #include <sys/queue.h>
54 #include <sys/sysctl.h>
55 #include <sys/syslog.h>
56 #include <sys/systm.h>
57 #include <sys/taskqueue.h>
58 #include <sys/vmmeter.h>
59 #include <machine/clock.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/smp.h>
67 #include <machine/segments.h>
68 #include <machine/frame.h>
69 #include <dev/ic/i8259.h>
70 #include <x86/isa/icu.h>
71 #include <isa/isareg.h>
76 #define MAX_STRAY_LOG 5
78 typedef void (*mask_fn)(void *);
80 static int intrcnt_index;
81 static struct intsrc *interrupt_sources[NUM_IO_INTS];
83 static struct intsrc *interrupt_sorted[NUM_IO_INTS];
84 CTASSERT(sizeof(interrupt_sources) == sizeof(interrupt_sorted));
85 static int intrbalance;
86 SYSCTL_INT(_hw, OID_AUTO, intrbalance, CTLFLAG_RW, &intrbalance, 0,
87 "Interrupt auto-balance interval (seconds). Zero disables.");
88 static struct timeout_task intrbalance_task;
90 static struct sx intrsrc_lock;
91 static struct mtx intrpic_lock;
92 static struct mtx intrcnt_lock;
93 static TAILQ_HEAD(pics_head, pic) pics;
95 #if defined(SMP) && !defined(EARLY_AP_STARTUP)
96 static int assign_cpu;
99 u_long intrcnt[INTRCNT_COUNT];
100 char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
101 size_t sintrcnt = sizeof(intrcnt);
102 size_t sintrnames = sizeof(intrnames);
104 static int intr_assign_cpu(void *arg, int cpu);
105 static void intr_disable_src(void *arg);
106 static void intr_init(void *__dummy);
107 static int intr_pic_registered(struct pic *pic);
108 static void intrcnt_setname(const char *name, int index);
109 static void intrcnt_updatename(struct intsrc *is);
110 static void intrcnt_register(struct intsrc *is);
113 intr_pic_registered(struct pic *pic)
117 TAILQ_FOREACH(p, &pics, pics) {
125 * Register a new interrupt controller (PIC). This is to support suspend
126 * and resume where we suspend/resume controllers rather than individual
127 * sources. This also allows controllers with no active sources (such as
128 * 8259As in a system using the APICs) to participate in suspend and resume.
131 intr_register_pic(struct pic *pic)
135 mtx_lock(&intrpic_lock);
136 if (intr_pic_registered(pic))
139 TAILQ_INSERT_TAIL(&pics, pic, pics);
142 mtx_unlock(&intrpic_lock);
147 * Register a new interrupt source with the global interrupt system.
148 * The global interrupts need to be disabled when this function is
152 intr_register_source(struct intsrc *isrc)
156 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
157 vector = isrc->is_pic->pic_vector(isrc);
158 if (interrupt_sources[vector] != NULL)
160 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
161 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
162 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
166 sx_xlock(&intrsrc_lock);
167 if (interrupt_sources[vector] != NULL) {
168 sx_xunlock(&intrsrc_lock);
169 intr_event_destroy(isrc->is_event);
172 intrcnt_register(isrc);
173 interrupt_sources[vector] = isrc;
174 isrc->is_handlers = 0;
175 sx_xunlock(&intrsrc_lock);
180 intr_lookup_source(int vector)
183 if (vector < 0 || vector >= nitems(interrupt_sources))
185 return (interrupt_sources[vector]);
189 intr_add_handler(const char *name, int vector, driver_filter_t filter,
190 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
196 isrc = intr_lookup_source(vector);
199 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
200 arg, intr_priority(flags), flags, cookiep);
202 sx_xlock(&intrsrc_lock);
203 intrcnt_updatename(isrc);
205 if (isrc->is_handlers == 1) {
206 isrc->is_domain = domain;
207 isrc->is_pic->pic_enable_intr(isrc);
208 isrc->is_pic->pic_enable_source(isrc);
210 sx_xunlock(&intrsrc_lock);
216 intr_remove_handler(void *cookie)
221 isrc = intr_handler_source(cookie);
222 error = intr_event_remove_handler(cookie);
224 sx_xlock(&intrsrc_lock);
226 if (isrc->is_handlers == 0) {
227 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
228 isrc->is_pic->pic_disable_intr(isrc);
230 intrcnt_updatename(isrc);
231 sx_xunlock(&intrsrc_lock);
237 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
241 isrc = intr_lookup_source(vector);
244 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
248 intr_disable_src(void *arg)
253 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
257 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
259 struct intr_event *ie;
263 * We count software interrupts when we process them. The
264 * code here follows previous practice, but there's an
265 * argument for counting hardware interrupts when they're
274 * XXX: We assume that IRQ 0 is only used for the ISA timer
277 vector = isrc->is_pic->pic_vector(isrc);
282 * For stray interrupts, mask and EOI the source, bump the
283 * stray count, and log the condition.
285 if (intr_event_handle(ie, frame) != 0) {
286 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
287 (*isrc->is_straycount)++;
288 if (*isrc->is_straycount < MAX_STRAY_LOG)
289 log(LOG_ERR, "stray irq%d\n", vector);
290 else if (*isrc->is_straycount == MAX_STRAY_LOG)
292 "too many stray irq %d's: not logging anymore\n",
298 intr_resume(bool suspend_cancelled)
305 mtx_lock(&intrpic_lock);
306 TAILQ_FOREACH(pic, &pics, pics) {
307 if (pic->pic_resume != NULL)
308 pic->pic_resume(pic, suspend_cancelled);
310 mtx_unlock(&intrpic_lock);
318 mtx_lock(&intrpic_lock);
319 TAILQ_FOREACH_REVERSE(pic, &pics, pics_head, pics) {
320 if (pic->pic_suspend != NULL)
321 pic->pic_suspend(pic);
323 mtx_unlock(&intrpic_lock);
327 intr_assign_cpu(void *arg, int cpu)
333 #ifdef EARLY_AP_STARTUP
334 MPASS(mp_ncpus == 1 || smp_started);
336 /* Nothing to do if there is only a single CPU. */
337 if (mp_ncpus > 1 && cpu != NOCPU) {
340 * Don't do anything during early boot. We will pick up the
341 * assignment once the APs are started.
343 if (assign_cpu && cpu != NOCPU) {
346 sx_xlock(&intrsrc_lock);
347 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
350 sx_xunlock(&intrsrc_lock);
360 intrcnt_setname(const char *name, int index)
363 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
368 intrcnt_updatename(struct intsrc *is)
371 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
375 intrcnt_register(struct intsrc *is)
377 char straystr[MAXCOMLEN + 1];
379 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
380 mtx_lock_spin(&intrcnt_lock);
381 is->is_index = intrcnt_index;
383 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
384 is->is_pic->pic_vector(is));
385 intrcnt_updatename(is);
386 is->is_count = &intrcnt[is->is_index];
387 intrcnt_setname(straystr, is->is_index + 1);
388 is->is_straycount = &intrcnt[is->is_index + 1];
389 mtx_unlock_spin(&intrcnt_lock);
393 intrcnt_add(const char *name, u_long **countp)
396 mtx_lock_spin(&intrcnt_lock);
397 *countp = &intrcnt[intrcnt_index];
398 intrcnt_setname(name, intrcnt_index);
400 mtx_unlock_spin(&intrcnt_lock);
404 intr_init(void *dummy __unused)
407 intrcnt_setname("???", 0);
410 mtx_init(&intrpic_lock, "intrpic", NULL, MTX_DEF);
411 sx_init(&intrsrc_lock, "intrsrc");
412 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
414 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
417 intr_init_final(void *dummy __unused)
421 * Enable interrupts on the BSP after all of the interrupt
422 * controllers are initialized. Device interrupts are still
423 * disabled in the interrupt controllers until interrupt
424 * handlers are registered. Interrupts are enabled on each AP
425 * after their first context switch.
429 SYSINIT(intr_init_final, SI_SUB_INTR, SI_ORDER_ANY, intr_init_final, NULL);
432 /* Initialize the two 8259A's to a known-good shutdown state. */
437 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
438 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
439 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID));
440 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE);
441 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
442 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
444 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
445 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
446 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_SLAVEID);
447 outb(IO_ICU2 + ICU_IMR_OFFSET, SLAVE_MODE);
448 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
449 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
453 /* Add a description to an active interrupt handler. */
455 intr_describe(u_int vector, void *ih, const char *descr)
460 isrc = intr_lookup_source(vector);
463 error = intr_event_describe_handler(isrc->is_event, ih, descr);
466 intrcnt_updatename(isrc);
476 sx_xlock(&intrsrc_lock);
477 for (v = 0; v < NUM_IO_INTS; v++) {
478 is = interrupt_sources[v];
481 if (is->is_pic->pic_reprogram_pin != NULL)
482 is->is_pic->pic_reprogram_pin(is);
484 sx_xunlock(&intrsrc_lock);
489 * Dump data about interrupt handlers
491 DB_SHOW_COMMAND(irqs, db_show_irqs)
493 struct intsrc **isrc;
496 if (strcmp(modif, "v") == 0)
500 isrc = interrupt_sources;
501 for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
503 db_dump_intr_event((*isrc)->is_event, verbose);
509 * Support for balancing interrupt sources across CPUs. For now we just
510 * allocate CPUs round-robin.
513 cpuset_t intr_cpus = CPUSET_T_INITIALIZER(0x1);
514 static int current_cpu[MAXMEMDOM];
521 for (i = 0; i < vm_ndomains; i++) {
523 if (!CPU_ISSET(current_cpu[i], &intr_cpus) ||
524 !CPU_ISSET(current_cpu[i], &cpuset_domain[i]))
530 * Return the CPU that the next interrupt source should use. For now
531 * this just returns the next local APIC according to round-robin.
534 intr_next_cpu(int domain)
538 #ifdef EARLY_AP_STARTUP
539 MPASS(mp_ncpus == 1 || smp_started);
541 return (PCPU_GET(apic_id));
543 /* Leave all interrupts on the BSP during boot. */
545 return (PCPU_GET(apic_id));
548 mtx_lock_spin(&icu_lock);
549 apic_id = cpu_apic_ids[current_cpu[domain]];
551 current_cpu[domain]++;
552 if (current_cpu[domain] > mp_maxid)
553 current_cpu[domain] = 0;
554 } while (!CPU_ISSET(current_cpu[domain], &intr_cpus) ||
555 !CPU_ISSET(current_cpu[domain], &cpuset_domain[domain]));
556 mtx_unlock_spin(&icu_lock);
560 /* Attempt to bind the specified IRQ to the specified CPU. */
562 intr_bind(u_int vector, u_char cpu)
566 isrc = intr_lookup_source(vector);
569 return (intr_event_bind(isrc->is_event, cpu));
573 * Add a CPU to our mask of valid CPUs that can be destinations of
577 intr_add_cpu(u_int cpu)
581 panic("%s: Invalid CPU ID", __func__);
583 printf("INTR: Adding local APIC %d as a target\n",
586 CPU_SET(cpu, &intr_cpus);
589 #ifdef EARLY_AP_STARTUP
591 intr_smp_startup(void *arg __unused)
597 SYSINIT(intr_smp_startup, SI_SUB_SMP, SI_ORDER_SECOND, intr_smp_startup,
602 * Distribute all the interrupt sources among the available CPUs once the
603 * AP's have been launched.
606 intr_shuffle_irqs(void *arg __unused)
613 /* Don't bother on UP. */
617 /* Round-robin assign a CPU to each enabled source. */
618 sx_xlock(&intrsrc_lock);
620 for (i = 0; i < NUM_IO_INTS; i++) {
621 isrc = interrupt_sources[i];
622 if (isrc != NULL && isrc->is_handlers > 0) {
624 * If this event is already bound to a CPU,
625 * then assign the source to that CPU instead
626 * of picking one via round-robin. Note that
627 * this is careful to only advance the
628 * round-robin if the CPU assignment succeeds.
630 cpu = isrc->is_event->ie_cpu;
632 cpu = current_cpu[isrc->is_domain];
633 if (isrc->is_pic->pic_assign_cpu(isrc,
634 cpu_apic_ids[cpu]) == 0) {
636 if (isrc->is_event->ie_cpu == NOCPU)
637 intr_next_cpu(isrc->is_domain);
641 sx_xunlock(&intrsrc_lock);
643 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
648 * TODO: Export this information in a non-MD fashion, integrate with vmstat -i.
651 sysctl_hw_intrs(SYSCTL_HANDLER_ARGS)
658 error = sysctl_wire_old_buffer(req, 0);
662 sbuf_new_for_sysctl(&sbuf, NULL, 128, req);
663 sx_slock(&intrsrc_lock);
664 for (i = 0; i < NUM_IO_INTS; i++) {
665 isrc = interrupt_sources[i];
668 sbuf_printf(&sbuf, "%s:%d @cpu%d(domain%d): %ld\n",
669 isrc->is_event->ie_fullname,
676 sx_sunlock(&intrsrc_lock);
677 error = sbuf_finish(&sbuf);
681 SYSCTL_PROC(_hw, OID_AUTO, intrs, CTLTYPE_STRING | CTLFLAG_RW,
682 0, 0, sysctl_hw_intrs, "A", "interrupt:number @cpu: count");
685 * Compare two, possibly NULL, entries in the interrupt source array
689 intrcmp(const void *one, const void *two)
691 const struct intsrc *i1, *i2;
693 i1 = *(const struct intsrc * const *)one;
694 i2 = *(const struct intsrc * const *)two;
695 if (i1 != NULL && i2 != NULL)
696 return (*i1->is_count - *i2->is_count);
705 * Balance IRQs across available CPUs according to load.
708 intr_balance(void *dummy __unused, int pending __unused)
715 interval = intrbalance;
720 * Sort interrupts according to count.
722 sx_xlock(&intrsrc_lock);
723 memcpy(interrupt_sorted, interrupt_sources, sizeof(interrupt_sorted));
724 qsort(interrupt_sorted, NUM_IO_INTS, sizeof(interrupt_sorted[0]),
728 * Restart the scan from the same location to avoid moving in the
734 * Assign round-robin from most loaded to least.
736 for (i = NUM_IO_INTS - 1; i >= 0; i--) {
737 isrc = interrupt_sorted[i];
738 if (isrc == NULL || isrc->is_event->ie_cpu != NOCPU)
740 cpu = current_cpu[isrc->is_domain];
741 intr_next_cpu(isrc->is_domain);
742 if (isrc->is_cpu != cpu &&
743 isrc->is_pic->pic_assign_cpu(isrc,
744 cpu_apic_ids[cpu]) == 0)
747 sx_xunlock(&intrsrc_lock);
749 taskqueue_enqueue_timeout(taskqueue_thread, &intrbalance_task,
750 interval ? hz * interval : hz * 60);
755 intr_balance_init(void *dummy __unused)
758 TIMEOUT_TASK_INIT(taskqueue_thread, &intrbalance_task, 0, intr_balance,
760 taskqueue_enqueue_timeout(taskqueue_thread, &intrbalance_task, hz);
762 SYSINIT(intr_balance_init, SI_SUB_SMP, SI_ORDER_ANY, intr_balance_init, NULL);
766 * Always route interrupts to the current processor in the UP case.
769 intr_next_cpu(int domain)
772 return (PCPU_GET(apic_id));