2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Machine dependent interrupt code for x86. For x86, we have to
33 * deal with different PICs. Thus, we use the passed in vector to lookup
34 * an interrupt source associated with that vector. The interrupt source
35 * describes which PIC the source belongs to and includes methods to handle
39 #include "opt_atpic.h"
42 #include <sys/param.h>
44 #include <sys/interrupt.h>
46 #include <sys/kernel.h>
48 #include <sys/mutex.h>
50 #include <sys/queue.h>
54 #include <sys/sysctl.h>
55 #include <sys/syslog.h>
56 #include <sys/systm.h>
57 #include <sys/taskqueue.h>
58 #include <sys/vmmeter.h>
59 #include <machine/clock.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/smp.h>
67 #include <machine/segments.h>
68 #include <machine/frame.h>
69 #include <dev/ic/i8259.h>
70 #include <x86/isa/icu.h>
71 #include <isa/isareg.h>
74 #define MAX_STRAY_LOG 5
76 typedef void (*mask_fn)(void *);
78 static int intrcnt_index;
79 static struct intsrc *interrupt_sources[NUM_IO_INTS];
81 static struct intsrc *interrupt_sorted[NUM_IO_INTS];
82 CTASSERT(sizeof(interrupt_sources) == sizeof(interrupt_sorted));
83 static int intrbalance;
84 SYSCTL_INT(_hw, OID_AUTO, intrbalance, CTLFLAG_RW, &intrbalance, 0,
85 "Interrupt auto-balance interval (seconds). Zero disables.");
86 static struct timeout_task intrbalance_task;
88 static struct sx intrsrc_lock;
89 static struct mtx intrpic_lock;
90 static struct mtx intrcnt_lock;
91 static TAILQ_HEAD(pics_head, pic) pics;
93 #if defined(SMP) && !defined(EARLY_AP_STARTUP)
94 static int assign_cpu;
97 u_long intrcnt[INTRCNT_COUNT];
98 char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
99 size_t sintrcnt = sizeof(intrcnt);
100 size_t sintrnames = sizeof(intrnames);
102 static int intr_assign_cpu(void *arg, int cpu);
103 static void intr_disable_src(void *arg);
104 static void intr_init(void *__dummy);
105 static int intr_pic_registered(struct pic *pic);
106 static void intrcnt_setname(const char *name, int index);
107 static void intrcnt_updatename(struct intsrc *is);
108 static void intrcnt_register(struct intsrc *is);
111 intr_pic_registered(struct pic *pic)
115 TAILQ_FOREACH(p, &pics, pics) {
123 * Register a new interrupt controller (PIC). This is to support suspend
124 * and resume where we suspend/resume controllers rather than individual
125 * sources. This also allows controllers with no active sources (such as
126 * 8259As in a system using the APICs) to participate in suspend and resume.
129 intr_register_pic(struct pic *pic)
133 mtx_lock(&intrpic_lock);
134 if (intr_pic_registered(pic))
137 TAILQ_INSERT_TAIL(&pics, pic, pics);
140 mtx_unlock(&intrpic_lock);
145 * Register a new interrupt source with the global interrupt system.
146 * The global interrupts need to be disabled when this function is
150 intr_register_source(struct intsrc *isrc)
154 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
155 vector = isrc->is_pic->pic_vector(isrc);
156 if (interrupt_sources[vector] != NULL)
158 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
159 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
160 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
164 sx_xlock(&intrsrc_lock);
165 if (interrupt_sources[vector] != NULL) {
166 sx_xunlock(&intrsrc_lock);
167 intr_event_destroy(isrc->is_event);
170 intrcnt_register(isrc);
171 interrupt_sources[vector] = isrc;
172 isrc->is_handlers = 0;
173 sx_xunlock(&intrsrc_lock);
178 intr_lookup_source(int vector)
181 return (interrupt_sources[vector]);
185 intr_add_handler(const char *name, int vector, driver_filter_t filter,
186 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
191 isrc = intr_lookup_source(vector);
194 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
195 arg, intr_priority(flags), flags, cookiep);
197 sx_xlock(&intrsrc_lock);
198 intrcnt_updatename(isrc);
200 if (isrc->is_handlers == 1) {
201 isrc->is_pic->pic_enable_intr(isrc);
202 isrc->is_pic->pic_enable_source(isrc);
204 sx_xunlock(&intrsrc_lock);
210 intr_remove_handler(void *cookie)
215 isrc = intr_handler_source(cookie);
216 error = intr_event_remove_handler(cookie);
218 sx_xlock(&intrsrc_lock);
220 if (isrc->is_handlers == 0) {
221 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
222 isrc->is_pic->pic_disable_intr(isrc);
224 intrcnt_updatename(isrc);
225 sx_xunlock(&intrsrc_lock);
231 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
235 isrc = intr_lookup_source(vector);
238 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
242 intr_disable_src(void *arg)
247 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
251 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
253 struct intr_event *ie;
257 * We count software interrupts when we process them. The
258 * code here follows previous practice, but there's an
259 * argument for counting hardware interrupts when they're
268 * XXX: We assume that IRQ 0 is only used for the ISA timer
271 vector = isrc->is_pic->pic_vector(isrc);
276 * For stray interrupts, mask and EOI the source, bump the
277 * stray count, and log the condition.
279 if (intr_event_handle(ie, frame) != 0) {
280 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
281 (*isrc->is_straycount)++;
282 if (*isrc->is_straycount < MAX_STRAY_LOG)
283 log(LOG_ERR, "stray irq%d\n", vector);
284 else if (*isrc->is_straycount == MAX_STRAY_LOG)
286 "too many stray irq %d's: not logging anymore\n",
292 intr_resume(bool suspend_cancelled)
299 mtx_lock(&intrpic_lock);
300 TAILQ_FOREACH(pic, &pics, pics) {
301 if (pic->pic_resume != NULL)
302 pic->pic_resume(pic, suspend_cancelled);
304 mtx_unlock(&intrpic_lock);
312 mtx_lock(&intrpic_lock);
313 TAILQ_FOREACH_REVERSE(pic, &pics, pics_head, pics) {
314 if (pic->pic_suspend != NULL)
315 pic->pic_suspend(pic);
317 mtx_unlock(&intrpic_lock);
321 intr_assign_cpu(void *arg, int cpu)
327 #ifdef EARLY_AP_STARTUP
328 MPASS(mp_ncpus == 1 || smp_started);
330 /* Nothing to do if there is only a single CPU. */
331 if (mp_ncpus > 1 && cpu != NOCPU) {
334 * Don't do anything during early boot. We will pick up the
335 * assignment once the APs are started.
337 if (assign_cpu && cpu != NOCPU) {
340 sx_xlock(&intrsrc_lock);
341 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
344 sx_xunlock(&intrsrc_lock);
354 intrcnt_setname(const char *name, int index)
357 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
362 intrcnt_updatename(struct intsrc *is)
365 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
369 intrcnt_register(struct intsrc *is)
371 char straystr[MAXCOMLEN + 1];
373 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
374 mtx_lock_spin(&intrcnt_lock);
375 is->is_index = intrcnt_index;
377 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
378 is->is_pic->pic_vector(is));
379 intrcnt_updatename(is);
380 is->is_count = &intrcnt[is->is_index];
381 intrcnt_setname(straystr, is->is_index + 1);
382 is->is_straycount = &intrcnt[is->is_index + 1];
383 mtx_unlock_spin(&intrcnt_lock);
387 intrcnt_add(const char *name, u_long **countp)
390 mtx_lock_spin(&intrcnt_lock);
391 *countp = &intrcnt[intrcnt_index];
392 intrcnt_setname(name, intrcnt_index);
394 mtx_unlock_spin(&intrcnt_lock);
398 intr_init(void *dummy __unused)
401 intrcnt_setname("???", 0);
404 mtx_init(&intrpic_lock, "intrpic", NULL, MTX_DEF);
405 sx_init(&intrsrc_lock, "intrsrc");
406 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
408 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
411 intr_init_final(void *dummy __unused)
415 * Enable interrupts on the BSP after all of the interrupt
416 * controllers are initialized. Device interrupts are still
417 * disabled in the interrupt controllers until interrupt
418 * handlers are registered. Interrupts are enabled on each AP
419 * after their first context switch.
423 SYSINIT(intr_init_final, SI_SUB_INTR, SI_ORDER_ANY, intr_init_final, NULL);
426 /* Initialize the two 8259A's to a known-good shutdown state. */
431 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
432 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
433 outb(IO_ICU1 + ICU_IMR_OFFSET, IRQ_MASK(ICU_SLAVEID));
434 outb(IO_ICU1 + ICU_IMR_OFFSET, MASTER_MODE);
435 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
436 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
438 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
439 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
440 outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_SLAVEID);
441 outb(IO_ICU2 + ICU_IMR_OFFSET, SLAVE_MODE);
442 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
443 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
447 /* Add a description to an active interrupt handler. */
449 intr_describe(u_int vector, void *ih, const char *descr)
454 isrc = intr_lookup_source(vector);
457 error = intr_event_describe_handler(isrc->is_event, ih, descr);
460 intrcnt_updatename(isrc);
470 sx_xlock(&intrsrc_lock);
471 for (v = 0; v < NUM_IO_INTS; v++) {
472 is = interrupt_sources[v];
475 if (is->is_pic->pic_reprogram_pin != NULL)
476 is->is_pic->pic_reprogram_pin(is);
478 sx_xunlock(&intrsrc_lock);
483 * Dump data about interrupt handlers
485 DB_SHOW_COMMAND(irqs, db_show_irqs)
487 struct intsrc **isrc;
490 if (strcmp(modif, "v") == 0)
494 isrc = interrupt_sources;
495 for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
497 db_dump_intr_event((*isrc)->is_event, verbose);
503 * Support for balancing interrupt sources across CPUs. For now we just
504 * allocate CPUs round-robin.
507 cpuset_t intr_cpus = CPUSET_T_INITIALIZER(0x1);
508 static int current_cpu;
511 * Return the CPU that the next interrupt source should use. For now
512 * this just returns the next local APIC according to round-robin.
519 #ifdef EARLY_AP_STARTUP
520 MPASS(mp_ncpus == 1 || smp_started);
522 return (PCPU_GET(apic_id));
524 /* Leave all interrupts on the BSP during boot. */
526 return (PCPU_GET(apic_id));
529 mtx_lock_spin(&icu_lock);
530 apic_id = cpu_apic_ids[current_cpu];
533 if (current_cpu > mp_maxid)
535 } while (!CPU_ISSET(current_cpu, &intr_cpus));
536 mtx_unlock_spin(&icu_lock);
540 /* Attempt to bind the specified IRQ to the specified CPU. */
542 intr_bind(u_int vector, u_char cpu)
546 isrc = intr_lookup_source(vector);
549 return (intr_event_bind(isrc->is_event, cpu));
553 * Add a CPU to our mask of valid CPUs that can be destinations of
557 intr_add_cpu(u_int cpu)
561 panic("%s: Invalid CPU ID", __func__);
563 printf("INTR: Adding local APIC %d as a target\n",
566 CPU_SET(cpu, &intr_cpus);
569 #ifndef EARLY_AP_STARTUP
571 * Distribute all the interrupt sources among the available CPUs once the
572 * AP's have been launched.
575 intr_shuffle_irqs(void *arg __unused)
581 /* Don't bother on UP. */
585 /* Round-robin assign a CPU to each enabled source. */
586 sx_xlock(&intrsrc_lock);
588 for (i = 0; i < NUM_IO_INTS; i++) {
589 isrc = interrupt_sources[i];
590 if (isrc != NULL && isrc->is_handlers > 0) {
592 * If this event is already bound to a CPU,
593 * then assign the source to that CPU instead
594 * of picking one via round-robin. Note that
595 * this is careful to only advance the
596 * round-robin if the CPU assignment succeeds.
598 cpu = isrc->is_event->ie_cpu;
601 if (isrc->is_pic->pic_assign_cpu(isrc,
602 cpu_apic_ids[cpu]) == 0) {
604 if (isrc->is_event->ie_cpu == NOCPU)
609 sx_xunlock(&intrsrc_lock);
611 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
616 * TODO: Export this information in a non-MD fashion, integrate with vmstat -i.
619 sysctl_hw_intrs(SYSCTL_HANDLER_ARGS)
626 error = sysctl_wire_old_buffer(req, 0);
630 sbuf_new_for_sysctl(&sbuf, NULL, 128, req);
631 sx_slock(&intrsrc_lock);
632 for (i = 0; i < NUM_IO_INTS; i++) {
633 isrc = interrupt_sources[i];
636 sbuf_printf(&sbuf, "%s:%d @%d: %ld\n",
637 isrc->is_event->ie_fullname,
643 sx_sunlock(&intrsrc_lock);
644 error = sbuf_finish(&sbuf);
648 SYSCTL_PROC(_hw, OID_AUTO, intrs, CTLTYPE_STRING | CTLFLAG_RW,
649 0, 0, sysctl_hw_intrs, "A", "interrupt:number @cpu: count");
652 * Compare two, possibly NULL, entries in the interrupt source array
656 intrcmp(const void *one, const void *two)
658 const struct intsrc *i1, *i2;
660 i1 = *(const struct intsrc * const *)one;
661 i2 = *(const struct intsrc * const *)two;
662 if (i1 != NULL && i2 != NULL)
663 return (*i1->is_count - *i2->is_count);
672 * Balance IRQs across available CPUs according to load.
675 intr_balance(void *dummy __unused, int pending __unused)
682 interval = intrbalance;
687 * Sort interrupts according to count.
689 sx_xlock(&intrsrc_lock);
690 memcpy(interrupt_sorted, interrupt_sources, sizeof(interrupt_sorted));
691 qsort(interrupt_sorted, NUM_IO_INTS, sizeof(interrupt_sorted[0]),
695 * Restart the scan from the same location to avoid moving in the
701 * Assign round-robin from most loaded to least.
703 for (i = NUM_IO_INTS - 1; i >= 0; i--) {
704 isrc = interrupt_sorted[i];
705 if (isrc == NULL || isrc->is_event->ie_cpu != NOCPU)
709 if (isrc->is_cpu != cpu &&
710 isrc->is_pic->pic_assign_cpu(isrc,
711 cpu_apic_ids[cpu]) == 0)
714 sx_xunlock(&intrsrc_lock);
716 taskqueue_enqueue_timeout(taskqueue_thread, &intrbalance_task,
717 interval ? hz * interval : hz * 60);
722 intr_balance_init(void *dummy __unused)
725 TIMEOUT_TASK_INIT(taskqueue_thread, &intrbalance_task, 0, intr_balance,
727 taskqueue_enqueue_timeout(taskqueue_thread, &intrbalance_task, hz);
729 SYSINIT(intr_balance_init, SI_SUB_SMP, SI_ORDER_ANY, intr_balance_init, NULL);
733 * Always route interrupts to the current processor in the UP case.
739 return (PCPU_GET(apic_id));