2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
51 #include <x86/apicreg.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <x86/apicvar.h>
55 #include <machine/resource.h>
56 #include <machine/segments.h>
57 #include <x86/iommu/iommu_intrmap.h>
59 #define IOAPIC_ISA_INTS 16
60 #define IOAPIC_MEM_REGION 32
61 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
62 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
64 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
67 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
68 * as laid out in the ACPI System Interrupt number model where each I/O
69 * APIC has a contiguous chunk of the System Interrupt address space.
70 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
71 * IRQs behave as PCI IRQs by default. We also assume that the pin for
72 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
73 * configuration of individual pins as indicated by their tables.
75 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
76 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
77 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
80 struct ioapic_intsrc {
81 struct intsrc io_intsrc;
87 u_int io_edgetrigger:1;
91 u_int io_remap_cookie;
96 u_int io_id:8; /* logical ID */
97 u_int io_apic_id:8; /* Id as enumerated by MADT */
98 u_int io_hw_apic_id:8; /* Content of APIC ID register */
99 u_int io_intbase:8; /* System Interrupt base */
102 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
104 STAILQ_ENTRY(ioapic) io_next;
105 device_t pci_dev; /* matched pci device, if found */
106 struct resource *pci_wnd; /* BAR 0, should be same or alias to
108 struct ioapic_intsrc io_pins[0];
111 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
112 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
113 static const char *ioapic_bus_string(int bus_type);
114 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
115 static void ioapic_register_sources(struct pic *pic);
116 static void ioapic_enable_source(struct intsrc *isrc);
117 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
118 static void ioapic_eoi_source(struct intsrc *isrc);
119 static void ioapic_enable_intr(struct intsrc *isrc);
120 static void ioapic_disable_intr(struct intsrc *isrc);
121 static int ioapic_vector(struct intsrc *isrc);
122 static int ioapic_source_pending(struct intsrc *isrc);
123 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
124 enum intr_polarity pol);
125 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
126 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
127 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
128 static void ioapic_reprogram_intpin(struct intsrc *isrc);
130 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
131 struct pic ioapic_template = {
132 .pic_register_sources = ioapic_register_sources,
133 .pic_enable_source = ioapic_enable_source,
134 .pic_disable_source = ioapic_disable_source,
135 .pic_eoi_source = ioapic_eoi_source,
136 .pic_enable_intr = ioapic_enable_intr,
137 .pic_disable_intr = ioapic_disable_intr,
138 .pic_vector = ioapic_vector,
139 .pic_source_pending = ioapic_source_pending,
141 .pic_resume = ioapic_resume,
142 .pic_config_intr = ioapic_config_intr,
143 .pic_assign_cpu = ioapic_assign_cpu,
144 .pic_reprogram_pin = ioapic_reprogram_intpin,
147 static u_int next_ioapic_base;
148 static u_int next_id;
150 static int enable_extint;
151 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
152 "Enable the ExtINT pin in the first I/O APIC");
155 _ioapic_eoi_source(struct intsrc *isrc, int locked)
157 struct ioapic_intsrc *src;
159 volatile uint32_t *apic_eoi;
163 if (!lapic_eoi_suppression)
165 src = (struct ioapic_intsrc *)isrc;
166 if (src->io_edgetrigger)
168 io = (struct ioapic *)isrc->is_pic;
171 * Handle targeted EOI for level-triggered pins, if broadcast
172 * EOI suppression is supported by LAPICs.
176 * If IOAPIC has EOI Register, simply write vector
177 * number into the reg.
179 apic_eoi = (volatile uint32_t *)((volatile char *)
180 io->io_addr + IOAPIC_EOIR);
181 *apic_eoi = src->io_vector;
184 * Otherwise, if IO-APIC is too old to provide EOIR,
185 * do what Intel did for the Linux kernel. Temporary
186 * switch the pin to edge-trigger and back, masking
187 * the pin during the trick.
190 mtx_lock_spin(&icu_lock);
191 low1 = src->io_lowreg;
192 low1 &= ~IOART_TRGRLVL;
193 low1 |= IOART_TRGREDG | IOART_INTMSET;
194 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
196 low1 = src->io_lowreg;
197 if (src->io_masked != 0)
198 low1 |= IOART_INTMSET;
199 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
202 mtx_unlock_spin(&icu_lock);
207 ioapic_read(volatile ioapic_t *apic, int reg)
210 mtx_assert(&icu_lock, MA_OWNED);
211 apic->ioregsel = reg;
212 return (apic->iowin);
216 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
219 mtx_assert(&icu_lock, MA_OWNED);
220 apic->ioregsel = reg;
225 ioapic_bus_string(int bus_type)
241 ioapic_print_irq(struct ioapic_intsrc *intpin)
244 switch (intpin->io_irq) {
258 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus),
264 ioapic_enable_source(struct intsrc *isrc)
266 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
267 struct ioapic *io = (struct ioapic *)isrc->is_pic;
270 mtx_lock_spin(&icu_lock);
271 if (intpin->io_masked) {
272 flags = intpin->io_lowreg & ~IOART_INTMASK;
273 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
275 intpin->io_masked = 0;
277 mtx_unlock_spin(&icu_lock);
281 ioapic_disable_source(struct intsrc *isrc, int eoi)
283 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
284 struct ioapic *io = (struct ioapic *)isrc->is_pic;
287 mtx_lock_spin(&icu_lock);
288 if (!intpin->io_masked && !intpin->io_edgetrigger) {
289 flags = intpin->io_lowreg | IOART_INTMSET;
290 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
292 intpin->io_masked = 1;
296 _ioapic_eoi_source(isrc, 1);
298 mtx_unlock_spin(&icu_lock);
302 ioapic_eoi_source(struct intsrc *isrc)
305 _ioapic_eoi_source(isrc, 0);
309 * Completely program an intpin based on the data in its interrupt source
313 ioapic_program_intpin(struct ioapic_intsrc *intpin)
315 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
322 * If a pin is completely invalid or if it is valid but hasn't
323 * been enabled yet, just ensure that the pin is masked.
325 mtx_assert(&icu_lock, MA_OWNED);
326 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 &&
327 intpin->io_vector == 0)) {
328 low = ioapic_read(io->io_addr,
329 IOAPIC_REDTBL_LO(intpin->io_intpin));
330 if ((low & IOART_INTMASK) == IOART_INTMCLR)
331 ioapic_write(io->io_addr,
332 IOAPIC_REDTBL_LO(intpin->io_intpin),
333 low | IOART_INTMSET);
335 mtx_unlock_spin(&icu_lock);
336 iommu_unmap_ioapic_intr(io->io_apic_id,
337 &intpin->io_remap_cookie);
338 mtx_lock_spin(&icu_lock);
344 mtx_unlock_spin(&icu_lock);
345 error = iommu_map_ioapic_intr(io->io_apic_id,
346 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
347 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
349 mtx_lock_spin(&icu_lock);
351 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
353 intpin->io_lowreg = low;
354 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
357 } else if (error != EOPNOTSUPP) {
363 * Set the destination. Note that with Intel interrupt remapping,
364 * the previously reserved bits 55:48 now have a purpose so ensure
368 high = intpin->io_cpu << APIC_ID_SHIFT;
370 /* Program the rest of the low word. */
371 if (intpin->io_edgetrigger)
372 low |= IOART_TRGREDG;
374 low |= IOART_TRGRLVL;
375 if (intpin->io_activehi)
379 if (intpin->io_masked)
380 low |= IOART_INTMSET;
381 switch (intpin->io_irq) {
383 KASSERT(intpin->io_edgetrigger,
384 ("ExtINT not edge triggered"));
385 low |= IOART_DELEXINT;
388 KASSERT(intpin->io_edgetrigger,
389 ("NMI not edge triggered"));
393 KASSERT(intpin->io_edgetrigger,
394 ("SMI not edge triggered"));
398 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
400 low |= IOART_DELFIXED | intpin->io_vector;
403 /* Write the values to the APIC. */
404 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high);
405 intpin->io_lowreg = low;
406 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
410 ioapic_reprogram_intpin(struct intsrc *isrc)
413 mtx_lock_spin(&icu_lock);
414 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
415 mtx_unlock_spin(&icu_lock);
419 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
421 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
422 struct ioapic *io = (struct ioapic *)isrc->is_pic;
423 u_int old_vector, new_vector;
428 * - Stick to the first cpu for all I/O APIC pins.
429 * - And don't allow destination cpu changes.
431 if (vm_guest == VM_GUEST_HV) {
432 if (intpin->io_vector)
439 * keep 1st core as the destination for NMI
441 if (intpin->io_irq == IRQ_NMI)
445 * Set us up to free the old irq.
447 old_vector = intpin->io_vector;
448 old_id = intpin->io_cpu;
449 if (old_vector && apic_id == old_id)
453 * Allocate an APIC vector for this interrupt pin. Once
454 * we have a vector we program the interrupt pin.
456 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
461 * Mask the old intpin if it is enabled while it is migrated.
463 * At least some level-triggered interrupts seem to need the
464 * extra DELAY() to avoid being stuck in a non-EOI'd state.
466 mtx_lock_spin(&icu_lock);
467 if (!intpin->io_masked && !intpin->io_edgetrigger) {
468 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
469 intpin->io_lowreg | IOART_INTMSET);
470 mtx_unlock_spin(&icu_lock);
472 mtx_lock_spin(&icu_lock);
475 intpin->io_cpu = apic_id;
476 intpin->io_vector = new_vector;
477 if (isrc->is_handlers > 0)
478 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
480 printf("ioapic%u: routing intpin %u (", io->io_id,
482 ioapic_print_irq(intpin);
483 printf(") to lapic %u vector %u\n", intpin->io_cpu,
486 ioapic_program_intpin(intpin);
487 mtx_unlock_spin(&icu_lock);
490 * Free the old vector after the new one is established. This is done
491 * to prevent races where we could miss an interrupt.
494 if (isrc->is_handlers > 0)
495 apic_disable_vector(old_id, old_vector);
496 apic_free_vector(old_id, old_vector, intpin->io_irq);
502 ioapic_enable_intr(struct intsrc *isrc)
504 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
506 if (intpin->io_vector == 0)
507 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0)
508 panic("Couldn't find an APIC vector for IRQ %d",
510 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
515 ioapic_disable_intr(struct intsrc *isrc)
517 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
520 if (intpin->io_vector != 0) {
521 /* Mask this interrupt pin and free its APIC vector. */
522 vector = intpin->io_vector;
523 apic_disable_vector(intpin->io_cpu, vector);
524 mtx_lock_spin(&icu_lock);
525 intpin->io_masked = 1;
526 intpin->io_vector = 0;
527 ioapic_program_intpin(intpin);
528 mtx_unlock_spin(&icu_lock);
529 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
534 ioapic_vector(struct intsrc *isrc)
536 struct ioapic_intsrc *pin;
538 pin = (struct ioapic_intsrc *)isrc;
539 return (pin->io_irq);
543 ioapic_source_pending(struct intsrc *isrc)
545 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
547 if (intpin->io_vector == 0)
549 return (lapic_intr_pending(intpin->io_vector));
553 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
554 enum intr_polarity pol)
556 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
557 struct ioapic *io = (struct ioapic *)isrc->is_pic;
560 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
561 ("%s: Conforming trigger or polarity\n", __func__));
564 * EISA interrupts always use active high polarity, so don't allow
565 * them to be set to active low.
567 * XXX: Should we write to the ELCR if the trigger mode changes for
568 * an EISA IRQ or an ISA IRQ with the ELCR present?
570 mtx_lock_spin(&icu_lock);
571 if (intpin->io_bus == APIC_BUS_EISA)
572 pol = INTR_POLARITY_HIGH;
574 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
576 printf("ioapic%u: Changing trigger for pin %u to %s\n",
577 io->io_id, intpin->io_intpin,
578 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
579 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
582 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
584 printf("ioapic%u: Changing polarity for pin %u to %s\n",
585 io->io_id, intpin->io_intpin,
586 pol == INTR_POLARITY_HIGH ? "high" : "low");
587 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
591 ioapic_program_intpin(intpin);
592 mtx_unlock_spin(&icu_lock);
597 ioapic_resume(struct pic *pic, bool suspend_cancelled)
599 struct ioapic *io = (struct ioapic *)pic;
602 mtx_lock_spin(&icu_lock);
603 for (i = 0; i < io->io_numintr; i++)
604 ioapic_program_intpin(&io->io_pins[i]);
605 mtx_unlock_spin(&icu_lock);
609 * Create a plain I/O APIC object.
612 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
615 struct ioapic_intsrc *intpin;
616 volatile ioapic_t *apic;
620 /* Map the register window so we can access the device. */
621 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
622 mtx_lock_spin(&icu_lock);
623 value = ioapic_read(apic, IOAPIC_VER);
624 mtx_unlock_spin(&icu_lock);
626 /* If it's version register doesn't seem to work, punt. */
627 if (value == 0xffffffff) {
628 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
632 /* Determine the number of vectors and set the APIC ID. */
633 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
634 io = malloc(sizeof(struct ioapic) +
635 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
636 io->io_pic = ioapic_template;
639 mtx_lock_spin(&icu_lock);
640 io->io_id = next_id++;
641 io->io_hw_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
642 io->io_apic_id = apic_id == -1 ? io->io_hw_apic_id : apic_id;
643 mtx_unlock_spin(&icu_lock);
644 if (io->io_hw_apic_id != apic_id)
645 printf("ioapic%u: MADT APIC ID %d != hw id %d\n", io->io_id,
646 apic_id, io->io_hw_apic_id);
648 intbase = next_ioapic_base;
649 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
651 } else if (intbase != next_ioapic_base && bootverbose)
652 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
653 io->io_id, intbase, next_ioapic_base);
654 io->io_intbase = intbase;
655 next_ioapic_base = intbase + numintr;
656 if (next_ioapic_base > num_io_irqs)
657 num_io_irqs = next_ioapic_base;
658 io->io_numintr = numintr;
663 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
664 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
668 * The summary information about IO-APIC versions is taken from
669 * the Linux kernel source:
671 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
672 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
674 * IO-APICs with version >= 0x20 have working EOIR register.
676 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
679 * Initialize pins. Start off with interrupts disabled. Default
680 * to active-hi and edge-triggered for ISA interrupts and active-lo
681 * and level-triggered for all others.
683 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
684 mtx_lock_spin(&icu_lock);
685 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
686 intpin->io_intsrc.is_pic = (struct pic *)io;
687 intpin->io_intpin = i;
688 intpin->io_irq = intbase + i;
691 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
692 * Assume that pins 1-15 are ISA interrupts and that all
693 * other pins are PCI interrupts.
695 if (intpin->io_irq == 0)
696 ioapic_set_extint(io, i);
697 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
698 intpin->io_bus = APIC_BUS_ISA;
699 intpin->io_activehi = 1;
700 intpin->io_edgetrigger = 1;
701 intpin->io_masked = 1;
703 intpin->io_bus = APIC_BUS_PCI;
704 intpin->io_activehi = 0;
705 intpin->io_edgetrigger = 0;
706 intpin->io_masked = 1;
710 * Route interrupts to the BSP by default. Interrupts may
711 * be routed to other CPUs later after they are enabled.
713 intpin->io_cpu = PCPU_GET(apic_id);
714 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
715 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
717 /* dummy, but sets cookie */
718 mtx_unlock_spin(&icu_lock);
719 iommu_map_ioapic_intr(io->io_apic_id,
720 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
721 intpin->io_activehi, intpin->io_irq,
722 &intpin->io_remap_cookie, NULL, NULL);
723 mtx_lock_spin(&icu_lock);
726 mtx_unlock_spin(&icu_lock);
732 ioapic_get_vector(void *cookie, u_int pin)
736 io = (struct ioapic *)cookie;
737 if (pin >= io->io_numintr)
739 return (io->io_pins[pin].io_irq);
743 ioapic_disable_pin(void *cookie, u_int pin)
747 io = (struct ioapic *)cookie;
748 if (pin >= io->io_numintr)
750 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
752 io->io_pins[pin].io_irq = IRQ_DISABLED;
754 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
759 ioapic_remap_vector(void *cookie, u_int pin, int vector)
763 io = (struct ioapic *)cookie;
764 if (pin >= io->io_numintr || vector < 0)
766 if (io->io_pins[pin].io_irq < 0)
768 io->io_pins[pin].io_irq = vector;
770 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
776 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
780 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
782 io = (struct ioapic *)cookie;
783 if (pin >= io->io_numintr)
785 if (io->io_pins[pin].io_irq < 0)
787 if (io->io_pins[pin].io_bus == bus_type)
789 io->io_pins[pin].io_bus = bus_type;
791 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
792 ioapic_bus_string(bus_type));
797 ioapic_set_nmi(void *cookie, u_int pin)
801 io = (struct ioapic *)cookie;
802 if (pin >= io->io_numintr)
804 if (io->io_pins[pin].io_irq == IRQ_NMI)
806 if (io->io_pins[pin].io_irq < 0)
808 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
809 io->io_pins[pin].io_irq = IRQ_NMI;
810 io->io_pins[pin].io_masked = 0;
811 io->io_pins[pin].io_edgetrigger = 1;
812 io->io_pins[pin].io_activehi = 1;
814 printf("ioapic%u: Routing NMI -> intpin %d\n",
820 ioapic_set_smi(void *cookie, u_int pin)
824 io = (struct ioapic *)cookie;
825 if (pin >= io->io_numintr)
827 if (io->io_pins[pin].io_irq == IRQ_SMI)
829 if (io->io_pins[pin].io_irq < 0)
831 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
832 io->io_pins[pin].io_irq = IRQ_SMI;
833 io->io_pins[pin].io_masked = 0;
834 io->io_pins[pin].io_edgetrigger = 1;
835 io->io_pins[pin].io_activehi = 1;
837 printf("ioapic%u: Routing SMI -> intpin %d\n",
843 ioapic_set_extint(void *cookie, u_int pin)
847 io = (struct ioapic *)cookie;
848 if (pin >= io->io_numintr)
850 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
852 if (io->io_pins[pin].io_irq < 0)
854 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
855 io->io_pins[pin].io_irq = IRQ_EXTINT;
857 io->io_pins[pin].io_masked = 0;
859 io->io_pins[pin].io_masked = 1;
860 io->io_pins[pin].io_edgetrigger = 1;
861 io->io_pins[pin].io_activehi = 1;
863 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
869 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
874 io = (struct ioapic *)cookie;
875 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
877 if (io->io_pins[pin].io_irq < 0)
879 activehi = (pol == INTR_POLARITY_HIGH);
880 if (io->io_pins[pin].io_activehi == activehi)
882 io->io_pins[pin].io_activehi = activehi;
884 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
885 pol == INTR_POLARITY_HIGH ? "high" : "low");
890 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
895 io = (struct ioapic *)cookie;
896 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
898 if (io->io_pins[pin].io_irq < 0)
900 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
901 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
903 io->io_pins[pin].io_edgetrigger = edgetrigger;
905 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
906 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
911 * Register a complete I/O APIC object with the interrupt subsystem.
914 ioapic_register(void *cookie)
916 struct ioapic_intsrc *pin;
918 volatile ioapic_t *apic;
922 io = (struct ioapic *)cookie;
924 mtx_lock_spin(&icu_lock);
925 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
926 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
927 mtx_unlock_spin(&icu_lock);
928 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
929 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
930 io->io_intbase + io->io_numintr - 1);
933 * Reprogram pins to handle special case pins (such as NMI and
934 * SMI) and disable normal pins until a handler is registered.
936 intr_register_pic(&io->io_pic);
937 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
938 ioapic_reprogram_intpin(&pin->io_intsrc);
942 * Add interrupt sources for I/O APIC interrupt pins.
945 ioapic_register_sources(struct pic *pic)
947 struct ioapic_intsrc *pin;
951 io = (struct ioapic *)pic;
952 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
953 if (pin->io_irq >= 0)
954 intr_register_source(&pin->io_intsrc);
958 /* A simple new-bus driver to consume PCI I/O APIC devices. */
960 ioapic_pci_probe(device_t dev)
963 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
964 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
965 switch (pci_get_progif(dev)) {
966 case PCIP_BASEPERIPH_PIC_IO_APIC:
967 device_set_desc(dev, "IO APIC");
969 case PCIP_BASEPERIPH_PIC_IOX_APIC:
970 device_set_desc(dev, "IO(x) APIC");
982 ioapic_pci_attach(device_t dev)
984 struct resource *res;
985 volatile ioapic_t *apic;
991 * Try to match the enumerated ioapic. Match BAR start
992 * against io_paddr. Due to a fear that PCI window is not the
993 * same as the MADT reported io window, but an alias, read the
994 * APIC ID from the mapped BAR and match against it.
997 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
998 RF_ACTIVE | RF_SHAREABLE);
1001 device_printf(dev, "cannot activate BAR0\n");
1004 apic = (volatile ioapic_t *)rman_get_virtual(res);
1005 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
1008 "BAR0 too small (%jd) for IOAPIC window\n",
1009 (uintmax_t)rman_get_size(res));
1012 mtx_lock_spin(&icu_lock);
1013 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
1014 /* First match by io window address */
1015 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1016 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
1019 /* Then by apic id */
1020 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1021 if (io->io_hw_apic_id == apic_id)
1024 mtx_unlock_spin(&icu_lock);
1027 "cannot match pci bar apic id %d against MADT, BAR0 %#jx\n",
1028 apic_id, (uintmax_t)rman_get_start(res));
1030 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1033 KASSERT(io->pci_dev == NULL,
1034 ("ioapic %d pci_dev not NULL", io->io_id));
1035 KASSERT(io->pci_wnd == NULL,
1036 ("ioapic %d pci_wnd not NULL", io->io_id));
1040 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1041 io->io_hw_apic_id != apic_id)) {
1042 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1043 "MADT id %d hw id %d paddr@%jx\n",
1044 pci_get_domain(dev), pci_get_bus(dev),
1045 pci_get_slot(dev), pci_get_function(dev),
1046 (uintmax_t)rman_get_start(res), apic_id,
1047 io->io_apic_id, io->io_hw_apic_id, (uintmax_t)io->io_paddr);
1049 mtx_unlock_spin(&icu_lock);
1053 static device_method_t ioapic_pci_methods[] = {
1054 /* Device interface */
1055 DEVMETHOD(device_probe, ioapic_pci_probe),
1056 DEVMETHOD(device_attach, ioapic_pci_attach),
1061 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1063 static devclass_t ioapic_devclass;
1064 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
1067 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1073 mtx_lock_spin(&icu_lock);
1074 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1075 if (io->io_apic_id == apic_id)
1078 mtx_unlock_spin(&icu_lock);
1079 if (io == NULL || io->pci_dev == NULL)
1081 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1089 * A new-bus driver to consume the memory resources associated with
1090 * the APICs in the system. On some systems ACPI or PnPBIOS system
1091 * resource devices may already claim these resources. To keep from
1092 * breaking those devices, we attach ourself to the nexus device after
1093 * legacy0 and acpi0 and ignore any allocation failures.
1096 apic_identify(driver_t *driver, device_t parent)
1100 * Add at order 12. acpi0 is probed at order 10 and legacy0
1101 * is probed at order 11.
1103 if (lapic_paddr != 0)
1104 BUS_ADD_CHILD(parent, 12, "apic", 0);
1108 apic_probe(device_t dev)
1111 device_set_desc(dev, "APIC resources");
1117 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1121 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1123 panic("apic_add_resource: resource %d failed set with %d", rid,
1125 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1129 apic_attach(device_t dev)
1134 /* Reserve the local APIC. */
1135 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1137 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1138 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1144 static device_method_t apic_methods[] = {
1145 /* Device interface */
1146 DEVMETHOD(device_identify, apic_identify),
1147 DEVMETHOD(device_probe, apic_probe),
1148 DEVMETHOD(device_attach, apic_attach),
1153 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1155 static devclass_t apic_devclass;
1156 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
1158 #include "opt_ddb.h"
1161 #include <ddb/ddb.h>
1164 ioapic_delivery_mode(uint32_t mode)
1168 case IOART_DELFIXED:
1170 case IOART_DELLOPRI:
1171 return ("lowestpri");
1182 case IOART_DELEXINT:
1190 db_ioapic_read(volatile ioapic_t *apic, int reg)
1193 apic->ioregsel = reg;
1194 return (apic->iowin);
1198 db_show_ioapic_one(volatile ioapic_t *io_addr)
1203 r = db_ioapic_read(io_addr, IOAPIC_VER);
1204 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1205 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1206 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1207 for (i = 0; i < mre; i++) {
1208 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1209 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1210 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1211 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1212 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1213 (hi & IOART_DEST) >> 24,
1214 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1215 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1216 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1217 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1218 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1219 ioapic_delivery_mode(lo & IOART_DELMOD),
1220 (lo & IOART_INTVEC));
1224 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1226 struct ioapic *ioapic;
1230 db_printf("usage: show ioapic index\n");
1236 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1238 db_show_ioapic_one(ioapic->io_addr);
1245 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1247 struct ioapic *ioapic;
1249 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1250 db_show_ioapic_one(ioapic->io_addr);