2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/sysctl.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
48 #include <x86/apicreg.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <x86/apicvar.h>
52 #include <machine/resource.h>
53 #include <machine/segments.h>
55 #define IOAPIC_ISA_INTS 16
56 #define IOAPIC_MEM_REGION 32
57 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
58 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
60 #define IRQ_EXTINT (NUM_IO_INTS + 1)
61 #define IRQ_NMI (NUM_IO_INTS + 2)
62 #define IRQ_SMI (NUM_IO_INTS + 3)
63 #define IRQ_DISABLED (NUM_IO_INTS + 4)
65 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
68 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
69 * as laid out in the ACPI System Interrupt number model where each I/O
70 * APIC has a contiguous chunk of the System Interrupt address space.
71 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
72 * IRQs behave as PCI IRQs by default. We also assume that the pin for
73 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
74 * configuration of individual pins as indicated by their tables.
76 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
77 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
78 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
81 struct ioapic_intsrc {
82 struct intsrc io_intsrc;
88 u_int io_edgetrigger:1;
96 u_int io_id:8; /* logical ID */
98 u_int io_intbase:8; /* System Interrupt base */
100 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
102 STAILQ_ENTRY(ioapic) io_next;
103 struct ioapic_intsrc io_pins[0];
106 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
107 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
108 static const char *ioapic_bus_string(int bus_type);
109 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
110 static void ioapic_enable_source(struct intsrc *isrc);
111 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
112 static void ioapic_eoi_source(struct intsrc *isrc);
113 static void ioapic_enable_intr(struct intsrc *isrc);
114 static void ioapic_disable_intr(struct intsrc *isrc);
115 static int ioapic_vector(struct intsrc *isrc);
116 static int ioapic_source_pending(struct intsrc *isrc);
117 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
118 enum intr_polarity pol);
119 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
120 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
121 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
123 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
124 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
125 ioapic_eoi_source, ioapic_enable_intr,
126 ioapic_disable_intr, ioapic_vector,
127 ioapic_source_pending, NULL, ioapic_resume,
128 ioapic_config_intr, ioapic_assign_cpu };
130 static int next_ioapic_base;
131 static u_int next_id;
133 static SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
134 static int enable_extint;
135 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
136 "Enable the ExtINT pin in the first I/O APIC");
139 _ioapic_eoi_source(struct intsrc *isrc)
145 ioapic_read(volatile ioapic_t *apic, int reg)
148 mtx_assert(&icu_lock, MA_OWNED);
149 apic->ioregsel = reg;
150 return (apic->iowin);
154 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
157 mtx_assert(&icu_lock, MA_OWNED);
158 apic->ioregsel = reg;
163 ioapic_bus_string(int bus_type)
179 ioapic_print_irq(struct ioapic_intsrc *intpin)
182 switch (intpin->io_irq) {
196 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
202 ioapic_enable_source(struct intsrc *isrc)
204 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
205 struct ioapic *io = (struct ioapic *)isrc->is_pic;
208 mtx_lock_spin(&icu_lock);
209 if (intpin->io_masked) {
210 flags = intpin->io_lowreg & ~IOART_INTMASK;
211 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
213 intpin->io_masked = 0;
215 mtx_unlock_spin(&icu_lock);
219 ioapic_disable_source(struct intsrc *isrc, int eoi)
221 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
222 struct ioapic *io = (struct ioapic *)isrc->is_pic;
225 mtx_lock_spin(&icu_lock);
226 if (!intpin->io_masked && !intpin->io_edgetrigger) {
227 flags = intpin->io_lowreg | IOART_INTMSET;
228 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
230 intpin->io_masked = 1;
234 _ioapic_eoi_source(isrc);
236 mtx_unlock_spin(&icu_lock);
240 ioapic_eoi_source(struct intsrc *isrc)
243 _ioapic_eoi_source(isrc);
247 * Completely program an intpin based on the data in its interrupt source
251 ioapic_program_intpin(struct ioapic_intsrc *intpin)
253 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
254 uint32_t low, high, value;
257 * If a pin is completely invalid or if it is valid but hasn't
258 * been enabled yet, just ensure that the pin is masked.
260 mtx_assert(&icu_lock, MA_OWNED);
261 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
262 intpin->io_vector == 0)) {
263 low = ioapic_read(io->io_addr,
264 IOAPIC_REDTBL_LO(intpin->io_intpin));
265 if ((low & IOART_INTMASK) == IOART_INTMCLR)
266 ioapic_write(io->io_addr,
267 IOAPIC_REDTBL_LO(intpin->io_intpin),
268 low | IOART_INTMSET);
272 /* Set the destination. */
274 high = intpin->io_cpu << APIC_ID_SHIFT;
276 /* Program the rest of the low word. */
277 if (intpin->io_edgetrigger)
278 low |= IOART_TRGREDG;
280 low |= IOART_TRGRLVL;
281 if (intpin->io_activehi)
285 if (intpin->io_masked)
286 low |= IOART_INTMSET;
287 switch (intpin->io_irq) {
289 KASSERT(intpin->io_edgetrigger,
290 ("ExtINT not edge triggered"));
291 low |= IOART_DELEXINT;
294 KASSERT(intpin->io_edgetrigger,
295 ("NMI not edge triggered"));
299 KASSERT(intpin->io_edgetrigger,
300 ("SMI not edge triggered"));
304 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
306 low |= IOART_DELFIXED | intpin->io_vector;
309 /* Write the values to the APIC. */
310 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
311 value &= ~IOART_DEST;
313 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
314 intpin->io_lowreg = low;
315 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
319 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
321 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
322 struct ioapic *io = (struct ioapic *)isrc->is_pic;
323 u_int old_vector, new_vector;
327 * keep 1st core as the destination for NMI
329 if (intpin->io_irq == IRQ_NMI)
333 * Set us up to free the old irq.
335 old_vector = intpin->io_vector;
336 old_id = intpin->io_cpu;
337 if (old_vector && apic_id == old_id)
341 * Allocate an APIC vector for this interrupt pin. Once
342 * we have a vector we program the interrupt pin.
344 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
349 * Mask the old intpin if it is enabled while it is migrated.
351 * At least some level-triggered interrupts seem to need the
352 * extra DELAY() to avoid being stuck in a non-EOI'd state.
354 mtx_lock_spin(&icu_lock);
355 if (!intpin->io_masked && !intpin->io_edgetrigger) {
356 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
357 intpin->io_lowreg | IOART_INTMSET);
358 mtx_unlock_spin(&icu_lock);
360 mtx_lock_spin(&icu_lock);
363 intpin->io_cpu = apic_id;
364 intpin->io_vector = new_vector;
365 if (isrc->is_handlers > 0)
366 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
368 printf("ioapic%u: routing intpin %u (", io->io_id,
370 ioapic_print_irq(intpin);
371 printf(") to lapic %u vector %u\n", intpin->io_cpu,
374 ioapic_program_intpin(intpin);
375 mtx_unlock_spin(&icu_lock);
378 * Free the old vector after the new one is established. This is done
379 * to prevent races where we could miss an interrupt.
382 if (isrc->is_handlers > 0)
383 apic_disable_vector(old_id, old_vector);
384 apic_free_vector(old_id, old_vector, intpin->io_irq);
390 ioapic_enable_intr(struct intsrc *isrc)
392 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
394 if (intpin->io_vector == 0)
395 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
396 panic("Couldn't find an APIC vector for IRQ %d",
398 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
403 ioapic_disable_intr(struct intsrc *isrc)
405 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
408 if (intpin->io_vector != 0) {
409 /* Mask this interrupt pin and free its APIC vector. */
410 vector = intpin->io_vector;
411 apic_disable_vector(intpin->io_cpu, vector);
412 mtx_lock_spin(&icu_lock);
413 intpin->io_masked = 1;
414 intpin->io_vector = 0;
415 ioapic_program_intpin(intpin);
416 mtx_unlock_spin(&icu_lock);
417 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
422 ioapic_vector(struct intsrc *isrc)
424 struct ioapic_intsrc *pin;
426 pin = (struct ioapic_intsrc *)isrc;
427 return (pin->io_irq);
431 ioapic_source_pending(struct intsrc *isrc)
433 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
435 if (intpin->io_vector == 0)
437 return (lapic_intr_pending(intpin->io_vector));
441 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
442 enum intr_polarity pol)
444 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
445 struct ioapic *io = (struct ioapic *)isrc->is_pic;
448 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
449 ("%s: Conforming trigger or polarity\n", __func__));
452 * EISA interrupts always use active high polarity, so don't allow
453 * them to be set to active low.
455 * XXX: Should we write to the ELCR if the trigger mode changes for
456 * an EISA IRQ or an ISA IRQ with the ELCR present?
458 mtx_lock_spin(&icu_lock);
459 if (intpin->io_bus == APIC_BUS_EISA)
460 pol = INTR_POLARITY_HIGH;
462 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
464 printf("ioapic%u: Changing trigger for pin %u to %s\n",
465 io->io_id, intpin->io_intpin,
466 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
467 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
470 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
472 printf("ioapic%u: Changing polarity for pin %u to %s\n",
473 io->io_id, intpin->io_intpin,
474 pol == INTR_POLARITY_HIGH ? "high" : "low");
475 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
479 ioapic_program_intpin(intpin);
480 mtx_unlock_spin(&icu_lock);
485 ioapic_resume(struct pic *pic, bool suspend_cancelled)
487 struct ioapic *io = (struct ioapic *)pic;
490 mtx_lock_spin(&icu_lock);
491 for (i = 0; i < io->io_numintr; i++)
492 ioapic_program_intpin(&io->io_pins[i]);
493 mtx_unlock_spin(&icu_lock);
497 * Create a plain I/O APIC object.
500 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
503 struct ioapic_intsrc *intpin;
504 volatile ioapic_t *apic;
508 /* Map the register window so we can access the device. */
509 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
510 mtx_lock_spin(&icu_lock);
511 value = ioapic_read(apic, IOAPIC_VER);
512 mtx_unlock_spin(&icu_lock);
514 /* If it's version register doesn't seem to work, punt. */
515 if (value == 0xffffffff) {
516 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
520 /* Determine the number of vectors and set the APIC ID. */
521 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
522 io = malloc(sizeof(struct ioapic) +
523 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
524 io->io_pic = ioapic_template;
525 mtx_lock_spin(&icu_lock);
526 io->io_id = next_id++;
527 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
528 if (apic_id != -1 && io->io_apic_id != apic_id) {
529 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
530 mtx_unlock_spin(&icu_lock);
531 io->io_apic_id = apic_id;
532 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
535 mtx_unlock_spin(&icu_lock);
537 intbase = next_ioapic_base;
538 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
540 } else if (intbase != next_ioapic_base && bootverbose)
541 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
542 io->io_id, intbase, next_ioapic_base);
543 io->io_intbase = intbase;
544 next_ioapic_base = intbase + numintr;
545 io->io_numintr = numintr;
550 * Initialize pins. Start off with interrupts disabled. Default
551 * to active-hi and edge-triggered for ISA interrupts and active-lo
552 * and level-triggered for all others.
554 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
555 mtx_lock_spin(&icu_lock);
556 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
557 intpin->io_intsrc.is_pic = (struct pic *)io;
558 intpin->io_intpin = i;
559 intpin->io_irq = intbase + i;
562 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
563 * Assume that pins 1-15 are ISA interrupts and that all
564 * other pins are PCI interrupts.
566 if (intpin->io_irq == 0)
567 ioapic_set_extint(io, i);
568 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
569 intpin->io_bus = APIC_BUS_ISA;
570 intpin->io_activehi = 1;
571 intpin->io_edgetrigger = 1;
572 intpin->io_masked = 1;
574 intpin->io_bus = APIC_BUS_PCI;
575 intpin->io_activehi = 0;
576 intpin->io_edgetrigger = 0;
577 intpin->io_masked = 1;
581 * Route interrupts to the BSP by default. Interrupts may
582 * be routed to other CPUs later after they are enabled.
584 intpin->io_cpu = PCPU_GET(apic_id);
585 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
586 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
588 mtx_unlock_spin(&icu_lock);
594 ioapic_get_vector(void *cookie, u_int pin)
598 io = (struct ioapic *)cookie;
599 if (pin >= io->io_numintr)
601 return (io->io_pins[pin].io_irq);
605 ioapic_disable_pin(void *cookie, u_int pin)
609 io = (struct ioapic *)cookie;
610 if (pin >= io->io_numintr)
612 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
614 io->io_pins[pin].io_irq = IRQ_DISABLED;
616 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
621 ioapic_remap_vector(void *cookie, u_int pin, int vector)
625 io = (struct ioapic *)cookie;
626 if (pin >= io->io_numintr || vector < 0)
628 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
630 io->io_pins[pin].io_irq = vector;
632 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
638 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
642 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
644 io = (struct ioapic *)cookie;
645 if (pin >= io->io_numintr)
647 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
649 if (io->io_pins[pin].io_bus == bus_type)
651 io->io_pins[pin].io_bus = bus_type;
653 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
654 ioapic_bus_string(bus_type));
659 ioapic_set_nmi(void *cookie, u_int pin)
663 io = (struct ioapic *)cookie;
664 if (pin >= io->io_numintr)
666 if (io->io_pins[pin].io_irq == IRQ_NMI)
668 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
670 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
671 io->io_pins[pin].io_irq = IRQ_NMI;
672 io->io_pins[pin].io_masked = 0;
673 io->io_pins[pin].io_edgetrigger = 1;
674 io->io_pins[pin].io_activehi = 1;
676 printf("ioapic%u: Routing NMI -> intpin %d\n",
682 ioapic_set_smi(void *cookie, u_int pin)
686 io = (struct ioapic *)cookie;
687 if (pin >= io->io_numintr)
689 if (io->io_pins[pin].io_irq == IRQ_SMI)
691 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
693 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
694 io->io_pins[pin].io_irq = IRQ_SMI;
695 io->io_pins[pin].io_masked = 0;
696 io->io_pins[pin].io_edgetrigger = 1;
697 io->io_pins[pin].io_activehi = 1;
699 printf("ioapic%u: Routing SMI -> intpin %d\n",
705 ioapic_set_extint(void *cookie, u_int pin)
709 io = (struct ioapic *)cookie;
710 if (pin >= io->io_numintr)
712 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
714 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
716 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
717 io->io_pins[pin].io_irq = IRQ_EXTINT;
719 io->io_pins[pin].io_masked = 0;
721 io->io_pins[pin].io_masked = 1;
722 io->io_pins[pin].io_edgetrigger = 1;
723 io->io_pins[pin].io_activehi = 1;
725 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
731 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
736 io = (struct ioapic *)cookie;
737 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
739 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
741 activehi = (pol == INTR_POLARITY_HIGH);
742 if (io->io_pins[pin].io_activehi == activehi)
744 io->io_pins[pin].io_activehi = activehi;
746 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
747 pol == INTR_POLARITY_HIGH ? "high" : "low");
752 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
757 io = (struct ioapic *)cookie;
758 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
760 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
762 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
763 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
765 io->io_pins[pin].io_edgetrigger = edgetrigger;
767 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
768 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
773 * Register a complete I/O APIC object with the interrupt subsystem.
776 ioapic_register(void *cookie)
778 struct ioapic_intsrc *pin;
780 volatile ioapic_t *apic;
784 io = (struct ioapic *)cookie;
786 mtx_lock_spin(&icu_lock);
787 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
788 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
789 mtx_unlock_spin(&icu_lock);
790 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
791 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
792 io->io_intbase + io->io_numintr - 1);
794 /* Register valid pins as interrupt sources. */
795 intr_register_pic(&io->io_pic);
796 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
797 if (pin->io_irq < NUM_IO_INTS)
798 intr_register_source(&pin->io_intsrc);
801 /* A simple new-bus driver to consume PCI I/O APIC devices. */
803 ioapic_pci_probe(device_t dev)
806 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
807 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
808 switch (pci_get_progif(dev)) {
809 case PCIP_BASEPERIPH_PIC_IO_APIC:
810 device_set_desc(dev, "IO APIC");
812 case PCIP_BASEPERIPH_PIC_IOX_APIC:
813 device_set_desc(dev, "IO(x) APIC");
825 ioapic_pci_attach(device_t dev)
831 static device_method_t ioapic_pci_methods[] = {
832 /* Device interface */
833 DEVMETHOD(device_probe, ioapic_pci_probe),
834 DEVMETHOD(device_attach, ioapic_pci_attach),
839 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
841 static devclass_t ioapic_devclass;
842 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
845 * A new-bus driver to consume the memory resources associated with
846 * the APICs in the system. On some systems ACPI or PnPBIOS system
847 * resource devices may already claim these resources. To keep from
848 * breaking those devices, we attach ourself to the nexus device after
849 * legacy0 and acpi0 and ignore any allocation failures.
852 apic_identify(driver_t *driver, device_t parent)
856 * Add at order 12. acpi0 is probed at order 10 and legacy0
857 * is probed at order 11.
859 if (lapic_paddr != 0)
860 BUS_ADD_CHILD(parent, 12, "apic", 0);
864 apic_probe(device_t dev)
867 device_set_desc(dev, "APIC resources");
873 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
879 * Resources use long's to track resources, so we can't
880 * include memory regions above 4GB.
885 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
887 panic("apic_add_resource: resource %d failed set with %d", rid,
889 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
893 apic_attach(device_t dev)
898 /* Reserve the local APIC. */
899 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t));
901 STAILQ_FOREACH(io, &ioapic_list, io_next) {
902 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
908 static device_method_t apic_methods[] = {
909 /* Device interface */
910 DEVMETHOD(device_identify, apic_identify),
911 DEVMETHOD(device_probe, apic_probe),
912 DEVMETHOD(device_attach, apic_attach),
917 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
919 static devclass_t apic_devclass;
920 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
928 ioapic_delivery_mode(uint32_t mode)
935 return ("lowestpri");
954 db_ioapic_read(volatile ioapic_t *apic, int reg)
957 apic->ioregsel = reg;
958 return (apic->iowin);
962 db_show_ioapic_one(volatile ioapic_t *io_addr)
967 r = db_ioapic_read(io_addr, IOAPIC_VER);
968 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
969 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
970 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
971 for (i = 0; i < mre; i++) {
972 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
973 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
974 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
975 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
976 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
977 (hi & IOART_DEST) >> 24,
978 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
979 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
980 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
981 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
982 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
983 ioapic_delivery_mode(lo & IOART_DELMOD),
984 (lo & IOART_INTVEC));
988 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
990 struct ioapic *ioapic;
994 db_printf("usage: show ioapic index\n");
1000 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1002 db_show_ioapic_one(ioapic->io_addr);
1009 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1011 struct ioapic *ioapic;
1013 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1014 db_show_ioapic_one(ioapic->io_addr);