2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
51 #include <x86/apicreg.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <x86/apicvar.h>
55 #include <machine/resource.h>
56 #include <machine/segments.h>
57 #include <x86/iommu/iommu_intrmap.h>
59 #define IOAPIC_ISA_INTS 16
60 #define IOAPIC_MEM_REGION 32
61 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
62 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
64 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
67 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
68 * as laid out in the ACPI System Interrupt number model where each I/O
69 * APIC has a contiguous chunk of the System Interrupt address space.
70 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
71 * IRQs behave as PCI IRQs by default. We also assume that the pin for
72 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
73 * configuration of individual pins as indicated by their tables.
75 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
76 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
77 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
80 struct ioapic_intsrc {
81 struct intsrc io_intsrc;
87 u_int io_edgetrigger:1;
91 u_int io_remap_cookie;
96 u_int io_id:8; /* logical ID */
98 u_int io_intbase:8; /* System Interrupt base */
101 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
103 STAILQ_ENTRY(ioapic) io_next;
104 device_t pci_dev; /* matched pci device, if found */
105 struct resource *pci_wnd; /* BAR 0, should be same or alias to
107 struct ioapic_intsrc io_pins[0];
110 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
111 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
112 static const char *ioapic_bus_string(int bus_type);
113 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
114 static void ioapic_register_sources(struct pic *pic);
115 static void ioapic_enable_source(struct intsrc *isrc);
116 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
117 static void ioapic_eoi_source(struct intsrc *isrc);
118 static void ioapic_enable_intr(struct intsrc *isrc);
119 static void ioapic_disable_intr(struct intsrc *isrc);
120 static int ioapic_vector(struct intsrc *isrc);
121 static int ioapic_source_pending(struct intsrc *isrc);
122 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
123 enum intr_polarity pol);
124 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
125 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
126 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
127 static void ioapic_reprogram_intpin(struct intsrc *isrc);
129 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
130 struct pic ioapic_template = {
131 .pic_register_sources = ioapic_register_sources,
132 .pic_enable_source = ioapic_enable_source,
133 .pic_disable_source = ioapic_disable_source,
134 .pic_eoi_source = ioapic_eoi_source,
135 .pic_enable_intr = ioapic_enable_intr,
136 .pic_disable_intr = ioapic_disable_intr,
137 .pic_vector = ioapic_vector,
138 .pic_source_pending = ioapic_source_pending,
140 .pic_resume = ioapic_resume,
141 .pic_config_intr = ioapic_config_intr,
142 .pic_assign_cpu = ioapic_assign_cpu,
143 .pic_reprogram_pin = ioapic_reprogram_intpin,
146 static u_int next_ioapic_base;
147 static u_int next_id;
149 static int enable_extint;
150 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
151 "Enable the ExtINT pin in the first I/O APIC");
154 _ioapic_eoi_source(struct intsrc *isrc, int locked)
156 struct ioapic_intsrc *src;
158 volatile uint32_t *apic_eoi;
162 if (!lapic_eoi_suppression)
164 src = (struct ioapic_intsrc *)isrc;
165 if (src->io_edgetrigger)
167 io = (struct ioapic *)isrc->is_pic;
170 * Handle targeted EOI for level-triggered pins, if broadcast
171 * EOI suppression is supported by LAPICs.
175 * If IOAPIC has EOI Register, simply write vector
176 * number into the reg.
178 apic_eoi = (volatile uint32_t *)((volatile char *)
179 io->io_addr + IOAPIC_EOIR);
180 *apic_eoi = src->io_vector;
183 * Otherwise, if IO-APIC is too old to provide EOIR,
184 * do what Intel did for the Linux kernel. Temporary
185 * switch the pin to edge-trigger and back, masking
186 * the pin during the trick.
189 mtx_lock_spin(&icu_lock);
190 low1 = src->io_lowreg;
191 low1 &= ~IOART_TRGRLVL;
192 low1 |= IOART_TRGREDG | IOART_INTMSET;
193 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
195 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
198 mtx_unlock_spin(&icu_lock);
203 ioapic_read(volatile ioapic_t *apic, int reg)
206 mtx_assert(&icu_lock, MA_OWNED);
207 apic->ioregsel = reg;
208 return (apic->iowin);
212 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
215 mtx_assert(&icu_lock, MA_OWNED);
216 apic->ioregsel = reg;
221 ioapic_bus_string(int bus_type)
237 ioapic_print_irq(struct ioapic_intsrc *intpin)
240 switch (intpin->io_irq) {
254 printf("%s IRQ %d", ioapic_bus_string(intpin->io_bus),
260 ioapic_enable_source(struct intsrc *isrc)
262 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
263 struct ioapic *io = (struct ioapic *)isrc->is_pic;
266 mtx_lock_spin(&icu_lock);
267 if (intpin->io_masked) {
268 flags = intpin->io_lowreg & ~IOART_INTMASK;
269 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
271 intpin->io_masked = 0;
273 mtx_unlock_spin(&icu_lock);
277 ioapic_disable_source(struct intsrc *isrc, int eoi)
279 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
280 struct ioapic *io = (struct ioapic *)isrc->is_pic;
283 mtx_lock_spin(&icu_lock);
284 if (!intpin->io_masked && !intpin->io_edgetrigger) {
285 flags = intpin->io_lowreg | IOART_INTMSET;
286 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
288 intpin->io_masked = 1;
292 _ioapic_eoi_source(isrc, 1);
294 mtx_unlock_spin(&icu_lock);
298 ioapic_eoi_source(struct intsrc *isrc)
301 _ioapic_eoi_source(isrc, 0);
305 * Completely program an intpin based on the data in its interrupt source
309 ioapic_program_intpin(struct ioapic_intsrc *intpin)
311 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
318 * If a pin is completely invalid or if it is valid but hasn't
319 * been enabled yet, just ensure that the pin is masked.
321 mtx_assert(&icu_lock, MA_OWNED);
322 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq >= 0 &&
323 intpin->io_vector == 0)) {
324 low = ioapic_read(io->io_addr,
325 IOAPIC_REDTBL_LO(intpin->io_intpin));
326 if ((low & IOART_INTMASK) == IOART_INTMCLR)
327 ioapic_write(io->io_addr,
328 IOAPIC_REDTBL_LO(intpin->io_intpin),
329 low | IOART_INTMSET);
331 mtx_unlock_spin(&icu_lock);
332 iommu_unmap_ioapic_intr(io->io_apic_id,
333 &intpin->io_remap_cookie);
334 mtx_lock_spin(&icu_lock);
340 mtx_unlock_spin(&icu_lock);
341 error = iommu_map_ioapic_intr(io->io_apic_id,
342 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
343 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
345 mtx_lock_spin(&icu_lock);
347 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
349 intpin->io_lowreg = low;
350 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
353 } else if (error != EOPNOTSUPP) {
359 * Set the destination. Note that with Intel interrupt remapping,
360 * the previously reserved bits 55:48 now have a purpose so ensure
364 high = intpin->io_cpu << APIC_ID_SHIFT;
366 /* Program the rest of the low word. */
367 if (intpin->io_edgetrigger)
368 low |= IOART_TRGREDG;
370 low |= IOART_TRGRLVL;
371 if (intpin->io_activehi)
375 if (intpin->io_masked)
376 low |= IOART_INTMSET;
377 switch (intpin->io_irq) {
379 KASSERT(intpin->io_edgetrigger,
380 ("ExtINT not edge triggered"));
381 low |= IOART_DELEXINT;
384 KASSERT(intpin->io_edgetrigger,
385 ("NMI not edge triggered"));
389 KASSERT(intpin->io_edgetrigger,
390 ("SMI not edge triggered"));
394 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
396 low |= IOART_DELFIXED | intpin->io_vector;
399 /* Write the values to the APIC. */
400 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high);
401 intpin->io_lowreg = low;
402 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
406 ioapic_reprogram_intpin(struct intsrc *isrc)
409 mtx_lock_spin(&icu_lock);
410 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
411 mtx_unlock_spin(&icu_lock);
415 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
417 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
418 struct ioapic *io = (struct ioapic *)isrc->is_pic;
419 u_int old_vector, new_vector;
424 * - Stick to the first cpu for all I/O APIC pins.
425 * - And don't allow destination cpu changes.
427 if (vm_guest == VM_GUEST_HV) {
428 if (intpin->io_vector)
435 * keep 1st core as the destination for NMI
437 if (intpin->io_irq == IRQ_NMI)
441 * Set us up to free the old irq.
443 old_vector = intpin->io_vector;
444 old_id = intpin->io_cpu;
445 if (old_vector && apic_id == old_id)
449 * Allocate an APIC vector for this interrupt pin. Once
450 * we have a vector we program the interrupt pin.
452 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
457 * Mask the old intpin if it is enabled while it is migrated.
459 * At least some level-triggered interrupts seem to need the
460 * extra DELAY() to avoid being stuck in a non-EOI'd state.
462 mtx_lock_spin(&icu_lock);
463 if (!intpin->io_masked && !intpin->io_edgetrigger) {
464 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
465 intpin->io_lowreg | IOART_INTMSET);
466 mtx_unlock_spin(&icu_lock);
468 mtx_lock_spin(&icu_lock);
471 intpin->io_cpu = apic_id;
472 intpin->io_vector = new_vector;
473 if (isrc->is_handlers > 0)
474 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
476 printf("ioapic%u: routing intpin %u (", io->io_id,
478 ioapic_print_irq(intpin);
479 printf(") to lapic %u vector %u\n", intpin->io_cpu,
482 ioapic_program_intpin(intpin);
483 mtx_unlock_spin(&icu_lock);
486 * Free the old vector after the new one is established. This is done
487 * to prevent races where we could miss an interrupt.
490 if (isrc->is_handlers > 0)
491 apic_disable_vector(old_id, old_vector);
492 apic_free_vector(old_id, old_vector, intpin->io_irq);
498 ioapic_enable_intr(struct intsrc *isrc)
500 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
502 if (intpin->io_vector == 0)
503 if (ioapic_assign_cpu(isrc, intr_next_cpu(isrc->is_domain)) != 0)
504 panic("Couldn't find an APIC vector for IRQ %d",
506 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
511 ioapic_disable_intr(struct intsrc *isrc)
513 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
516 if (intpin->io_vector != 0) {
517 /* Mask this interrupt pin and free its APIC vector. */
518 vector = intpin->io_vector;
519 apic_disable_vector(intpin->io_cpu, vector);
520 mtx_lock_spin(&icu_lock);
521 intpin->io_masked = 1;
522 intpin->io_vector = 0;
523 ioapic_program_intpin(intpin);
524 mtx_unlock_spin(&icu_lock);
525 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
530 ioapic_vector(struct intsrc *isrc)
532 struct ioapic_intsrc *pin;
534 pin = (struct ioapic_intsrc *)isrc;
535 return (pin->io_irq);
539 ioapic_source_pending(struct intsrc *isrc)
541 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
543 if (intpin->io_vector == 0)
545 return (lapic_intr_pending(intpin->io_vector));
549 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
550 enum intr_polarity pol)
552 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
553 struct ioapic *io = (struct ioapic *)isrc->is_pic;
556 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
557 ("%s: Conforming trigger or polarity\n", __func__));
560 * EISA interrupts always use active high polarity, so don't allow
561 * them to be set to active low.
563 * XXX: Should we write to the ELCR if the trigger mode changes for
564 * an EISA IRQ or an ISA IRQ with the ELCR present?
566 mtx_lock_spin(&icu_lock);
567 if (intpin->io_bus == APIC_BUS_EISA)
568 pol = INTR_POLARITY_HIGH;
570 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
572 printf("ioapic%u: Changing trigger for pin %u to %s\n",
573 io->io_id, intpin->io_intpin,
574 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
575 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
578 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
580 printf("ioapic%u: Changing polarity for pin %u to %s\n",
581 io->io_id, intpin->io_intpin,
582 pol == INTR_POLARITY_HIGH ? "high" : "low");
583 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
587 ioapic_program_intpin(intpin);
588 mtx_unlock_spin(&icu_lock);
593 ioapic_resume(struct pic *pic, bool suspend_cancelled)
595 struct ioapic *io = (struct ioapic *)pic;
598 mtx_lock_spin(&icu_lock);
599 for (i = 0; i < io->io_numintr; i++)
600 ioapic_program_intpin(&io->io_pins[i]);
601 mtx_unlock_spin(&icu_lock);
605 * Create a plain I/O APIC object.
608 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
611 struct ioapic_intsrc *intpin;
612 volatile ioapic_t *apic;
616 /* Map the register window so we can access the device. */
617 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
618 mtx_lock_spin(&icu_lock);
619 value = ioapic_read(apic, IOAPIC_VER);
620 mtx_unlock_spin(&icu_lock);
622 /* If it's version register doesn't seem to work, punt. */
623 if (value == 0xffffffff) {
624 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
628 /* Determine the number of vectors and set the APIC ID. */
629 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
630 io = malloc(sizeof(struct ioapic) +
631 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
632 io->io_pic = ioapic_template;
635 mtx_lock_spin(&icu_lock);
636 io->io_id = next_id++;
637 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
638 if (apic_id != -1 && io->io_apic_id != apic_id) {
639 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
640 mtx_unlock_spin(&icu_lock);
641 io->io_apic_id = apic_id;
642 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
645 mtx_unlock_spin(&icu_lock);
647 intbase = next_ioapic_base;
648 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
650 } else if (intbase != next_ioapic_base && bootverbose)
651 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
652 io->io_id, intbase, next_ioapic_base);
653 io->io_intbase = intbase;
654 next_ioapic_base = intbase + numintr;
655 if (next_ioapic_base > num_io_irqs)
656 num_io_irqs = next_ioapic_base;
657 io->io_numintr = numintr;
662 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
663 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
667 * The summary information about IO-APIC versions is taken from
668 * the Linux kernel source:
670 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
671 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
673 * IO-APICs with version >= 0x20 have working EOIR register.
675 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
678 * Initialize pins. Start off with interrupts disabled. Default
679 * to active-hi and edge-triggered for ISA interrupts and active-lo
680 * and level-triggered for all others.
682 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
683 mtx_lock_spin(&icu_lock);
684 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
685 intpin->io_intsrc.is_pic = (struct pic *)io;
686 intpin->io_intpin = i;
687 intpin->io_irq = intbase + i;
690 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
691 * Assume that pins 1-15 are ISA interrupts and that all
692 * other pins are PCI interrupts.
694 if (intpin->io_irq == 0)
695 ioapic_set_extint(io, i);
696 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
697 intpin->io_bus = APIC_BUS_ISA;
698 intpin->io_activehi = 1;
699 intpin->io_edgetrigger = 1;
700 intpin->io_masked = 1;
702 intpin->io_bus = APIC_BUS_PCI;
703 intpin->io_activehi = 0;
704 intpin->io_edgetrigger = 0;
705 intpin->io_masked = 1;
709 * Route interrupts to the BSP by default. Interrupts may
710 * be routed to other CPUs later after they are enabled.
712 intpin->io_cpu = PCPU_GET(apic_id);
713 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
714 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
716 /* dummy, but sets cookie */
717 mtx_unlock_spin(&icu_lock);
718 iommu_map_ioapic_intr(io->io_apic_id,
719 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
720 intpin->io_activehi, intpin->io_irq,
721 &intpin->io_remap_cookie, NULL, NULL);
722 mtx_lock_spin(&icu_lock);
725 mtx_unlock_spin(&icu_lock);
731 ioapic_get_vector(void *cookie, u_int pin)
735 io = (struct ioapic *)cookie;
736 if (pin >= io->io_numintr)
738 return (io->io_pins[pin].io_irq);
742 ioapic_disable_pin(void *cookie, u_int pin)
746 io = (struct ioapic *)cookie;
747 if (pin >= io->io_numintr)
749 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
751 io->io_pins[pin].io_irq = IRQ_DISABLED;
753 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
758 ioapic_remap_vector(void *cookie, u_int pin, int vector)
762 io = (struct ioapic *)cookie;
763 if (pin >= io->io_numintr || vector < 0)
765 if (io->io_pins[pin].io_irq < 0)
767 io->io_pins[pin].io_irq = vector;
769 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
775 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
779 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
781 io = (struct ioapic *)cookie;
782 if (pin >= io->io_numintr)
784 if (io->io_pins[pin].io_irq < 0)
786 if (io->io_pins[pin].io_bus == bus_type)
788 io->io_pins[pin].io_bus = bus_type;
790 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
791 ioapic_bus_string(bus_type));
796 ioapic_set_nmi(void *cookie, u_int pin)
800 io = (struct ioapic *)cookie;
801 if (pin >= io->io_numintr)
803 if (io->io_pins[pin].io_irq == IRQ_NMI)
805 if (io->io_pins[pin].io_irq < 0)
807 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
808 io->io_pins[pin].io_irq = IRQ_NMI;
809 io->io_pins[pin].io_masked = 0;
810 io->io_pins[pin].io_edgetrigger = 1;
811 io->io_pins[pin].io_activehi = 1;
813 printf("ioapic%u: Routing NMI -> intpin %d\n",
819 ioapic_set_smi(void *cookie, u_int pin)
823 io = (struct ioapic *)cookie;
824 if (pin >= io->io_numintr)
826 if (io->io_pins[pin].io_irq == IRQ_SMI)
828 if (io->io_pins[pin].io_irq < 0)
830 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
831 io->io_pins[pin].io_irq = IRQ_SMI;
832 io->io_pins[pin].io_masked = 0;
833 io->io_pins[pin].io_edgetrigger = 1;
834 io->io_pins[pin].io_activehi = 1;
836 printf("ioapic%u: Routing SMI -> intpin %d\n",
842 ioapic_set_extint(void *cookie, u_int pin)
846 io = (struct ioapic *)cookie;
847 if (pin >= io->io_numintr)
849 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
851 if (io->io_pins[pin].io_irq < 0)
853 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
854 io->io_pins[pin].io_irq = IRQ_EXTINT;
856 io->io_pins[pin].io_masked = 0;
858 io->io_pins[pin].io_masked = 1;
859 io->io_pins[pin].io_edgetrigger = 1;
860 io->io_pins[pin].io_activehi = 1;
862 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
868 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
873 io = (struct ioapic *)cookie;
874 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
876 if (io->io_pins[pin].io_irq < 0)
878 activehi = (pol == INTR_POLARITY_HIGH);
879 if (io->io_pins[pin].io_activehi == activehi)
881 io->io_pins[pin].io_activehi = activehi;
883 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
884 pol == INTR_POLARITY_HIGH ? "high" : "low");
889 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
894 io = (struct ioapic *)cookie;
895 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
897 if (io->io_pins[pin].io_irq < 0)
899 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
900 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
902 io->io_pins[pin].io_edgetrigger = edgetrigger;
904 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
905 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
910 * Register a complete I/O APIC object with the interrupt subsystem.
913 ioapic_register(void *cookie)
915 struct ioapic_intsrc *pin;
917 volatile ioapic_t *apic;
921 io = (struct ioapic *)cookie;
923 mtx_lock_spin(&icu_lock);
924 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
925 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
926 mtx_unlock_spin(&icu_lock);
927 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
928 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
929 io->io_intbase + io->io_numintr - 1);
932 * Reprogram pins to handle special case pins (such as NMI and
933 * SMI) and disable normal pins until a handler is registered.
935 intr_register_pic(&io->io_pic);
936 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
937 ioapic_reprogram_intpin(&pin->io_intsrc);
941 * Add interrupt sources for I/O APIC interrupt pins.
944 ioapic_register_sources(struct pic *pic)
946 struct ioapic_intsrc *pin;
950 io = (struct ioapic *)pic;
951 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
952 if (pin->io_irq >= 0)
953 intr_register_source(&pin->io_intsrc);
957 /* A simple new-bus driver to consume PCI I/O APIC devices. */
959 ioapic_pci_probe(device_t dev)
962 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
963 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
964 switch (pci_get_progif(dev)) {
965 case PCIP_BASEPERIPH_PIC_IO_APIC:
966 device_set_desc(dev, "IO APIC");
968 case PCIP_BASEPERIPH_PIC_IOX_APIC:
969 device_set_desc(dev, "IO(x) APIC");
981 ioapic_pci_attach(device_t dev)
983 struct resource *res;
984 volatile ioapic_t *apic;
990 * Try to match the enumerated ioapic. Match BAR start
991 * against io_paddr. Due to a fear that PCI window is not the
992 * same as the MADT reported io window, but an alias, read the
993 * APIC ID from the mapped BAR and match against it.
996 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
997 RF_ACTIVE | RF_SHAREABLE);
1000 device_printf(dev, "cannot activate BAR0\n");
1003 apic = (volatile ioapic_t *)rman_get_virtual(res);
1004 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
1007 "BAR0 too small (%jd) for IOAPIC window\n",
1008 (uintmax_t)rman_get_size(res));
1011 mtx_lock_spin(&icu_lock);
1012 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
1013 /* First match by io window address */
1014 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1015 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
1018 /* Then by apic id */
1019 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1020 if (io->io_apic_id == apic_id)
1023 mtx_unlock_spin(&icu_lock);
1026 "cannot match pci bar apic id %d against MADT\n",
1029 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1032 KASSERT(io->pci_dev == NULL,
1033 ("ioapic %d pci_dev not NULL", io->io_id));
1034 KASSERT(io->pci_wnd == NULL,
1035 ("ioapic %d pci_wnd not NULL", io->io_id));
1039 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1040 io->io_apic_id != apic_id)) {
1041 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1042 "MADT id %d paddr@%jx\n",
1043 pci_get_domain(dev), pci_get_bus(dev),
1044 pci_get_slot(dev), pci_get_function(dev),
1045 (uintmax_t)rman_get_start(res), apic_id,
1046 io->io_apic_id, (uintmax_t)io->io_paddr);
1048 mtx_unlock_spin(&icu_lock);
1052 static device_method_t ioapic_pci_methods[] = {
1053 /* Device interface */
1054 DEVMETHOD(device_probe, ioapic_pci_probe),
1055 DEVMETHOD(device_attach, ioapic_pci_attach),
1060 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1062 static devclass_t ioapic_devclass;
1063 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
1066 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1072 mtx_lock_spin(&icu_lock);
1073 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1074 if (io->io_apic_id == apic_id)
1077 mtx_unlock_spin(&icu_lock);
1078 if (io == NULL || io->pci_dev == NULL)
1080 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1088 * A new-bus driver to consume the memory resources associated with
1089 * the APICs in the system. On some systems ACPI or PnPBIOS system
1090 * resource devices may already claim these resources. To keep from
1091 * breaking those devices, we attach ourself to the nexus device after
1092 * legacy0 and acpi0 and ignore any allocation failures.
1095 apic_identify(driver_t *driver, device_t parent)
1099 * Add at order 12. acpi0 is probed at order 10 and legacy0
1100 * is probed at order 11.
1102 if (lapic_paddr != 0)
1103 BUS_ADD_CHILD(parent, 12, "apic", 0);
1107 apic_probe(device_t dev)
1110 device_set_desc(dev, "APIC resources");
1116 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1120 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1122 panic("apic_add_resource: resource %d failed set with %d", rid,
1124 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1128 apic_attach(device_t dev)
1133 /* Reserve the local APIC. */
1134 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1136 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1137 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1143 static device_method_t apic_methods[] = {
1144 /* Device interface */
1145 DEVMETHOD(device_identify, apic_identify),
1146 DEVMETHOD(device_probe, apic_probe),
1147 DEVMETHOD(device_attach, apic_attach),
1152 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1154 static devclass_t apic_devclass;
1155 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
1157 #include "opt_ddb.h"
1160 #include <ddb/ddb.h>
1163 ioapic_delivery_mode(uint32_t mode)
1167 case IOART_DELFIXED:
1169 case IOART_DELLOPRI:
1170 return ("lowestpri");
1181 case IOART_DELEXINT:
1189 db_ioapic_read(volatile ioapic_t *apic, int reg)
1192 apic->ioregsel = reg;
1193 return (apic->iowin);
1197 db_show_ioapic_one(volatile ioapic_t *io_addr)
1202 r = db_ioapic_read(io_addr, IOAPIC_VER);
1203 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1204 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1205 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1206 for (i = 0; i < mre; i++) {
1207 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1208 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1209 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1210 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1211 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1212 (hi & IOART_DEST) >> 24,
1213 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1214 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1215 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1216 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1217 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1218 ioapic_delivery_mode(lo & IOART_DELMOD),
1219 (lo & IOART_INTVEC));
1223 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1225 struct ioapic *ioapic;
1229 db_printf("usage: show ioapic index\n");
1235 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1237 db_show_ioapic_one(ioapic->io_addr);
1244 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1246 struct ioapic *ioapic;
1248 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1249 db_show_ioapic_one(ioapic->io_addr);