2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
52 #include <x86/apicreg.h>
53 #include <machine/frame.h>
54 #include <machine/intr_machdep.h>
55 #include <x86/apicvar.h>
56 #include <machine/resource.h>
57 #include <machine/segments.h>
58 #include <x86/iommu/iommu_intrmap.h>
60 #define IOAPIC_ISA_INTS 16
61 #define IOAPIC_MEM_REGION 32
62 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
63 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
65 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
68 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
69 * as laid out in the ACPI System Interrupt number model where each I/O
70 * APIC has a contiguous chunk of the System Interrupt address space.
71 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
72 * IRQs behave as PCI IRQs by default. We also assume that the pin for
73 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
74 * configuration of individual pins as indicated by their tables.
76 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
77 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
78 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
81 struct ioapic_intsrc {
82 struct intsrc io_intsrc;
88 u_int io_edgetrigger:1;
92 u_int io_remap_cookie;
97 u_int io_id:8; /* logical ID */
99 u_int io_intbase:8; /* System Interrupt base */
102 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
104 STAILQ_ENTRY(ioapic) io_next;
105 device_t pci_dev; /* matched pci device, if found */
106 struct resource *pci_wnd; /* BAR 0, should be same or alias to
108 struct ioapic_intsrc io_pins[0];
111 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
112 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
113 static const char *ioapic_bus_string(int bus_type);
114 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
115 static void ioapic_enable_source(struct intsrc *isrc);
116 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
117 static void ioapic_eoi_source(struct intsrc *isrc);
118 static void ioapic_enable_intr(struct intsrc *isrc);
119 static void ioapic_disable_intr(struct intsrc *isrc);
120 static int ioapic_vector(struct intsrc *isrc);
121 static int ioapic_source_pending(struct intsrc *isrc);
122 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
123 enum intr_polarity pol);
124 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
125 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
126 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
127 static void ioapic_reprogram_intpin(struct intsrc *isrc);
129 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
130 struct pic ioapic_template = {
131 .pic_enable_source = ioapic_enable_source,
132 .pic_disable_source = ioapic_disable_source,
133 .pic_eoi_source = ioapic_eoi_source,
134 .pic_enable_intr = ioapic_enable_intr,
135 .pic_disable_intr = ioapic_disable_intr,
136 .pic_vector = ioapic_vector,
137 .pic_source_pending = ioapic_source_pending,
139 .pic_resume = ioapic_resume,
140 .pic_config_intr = ioapic_config_intr,
141 .pic_assign_cpu = ioapic_assign_cpu,
142 .pic_reprogram_pin = ioapic_reprogram_intpin,
145 static int next_ioapic_base;
146 static u_int next_id;
148 static int enable_extint;
149 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
150 "Enable the ExtINT pin in the first I/O APIC");
153 _ioapic_eoi_source(struct intsrc *isrc, int locked)
155 struct ioapic_intsrc *src;
157 volatile uint32_t *apic_eoi;
161 if (!lapic_eoi_suppression)
163 src = (struct ioapic_intsrc *)isrc;
164 if (src->io_edgetrigger)
166 io = (struct ioapic *)isrc->is_pic;
169 * Handle targeted EOI for level-triggered pins, if broadcast
170 * EOI suppression is supported by LAPICs.
174 * If IOAPIC has EOI Register, simply write vector
175 * number into the reg.
177 apic_eoi = (volatile uint32_t *)((volatile char *)
178 io->io_addr + IOAPIC_EOIR);
179 *apic_eoi = src->io_vector;
182 * Otherwise, if IO-APIC is too old to provide EOIR,
183 * do what Intel did for the Linux kernel. Temporary
184 * switch the pin to edge-trigger and back, masking
185 * the pin during the trick.
188 mtx_lock_spin(&icu_lock);
189 low1 = src->io_lowreg;
190 low1 &= ~IOART_TRGRLVL;
191 low1 |= IOART_TRGREDG | IOART_INTMSET;
192 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
194 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
197 mtx_unlock_spin(&icu_lock);
202 ioapic_read(volatile ioapic_t *apic, int reg)
205 mtx_assert(&icu_lock, MA_OWNED);
206 apic->ioregsel = reg;
207 return (apic->iowin);
211 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
214 mtx_assert(&icu_lock, MA_OWNED);
215 apic->ioregsel = reg;
220 ioapic_bus_string(int bus_type)
236 ioapic_print_irq(struct ioapic_intsrc *intpin)
239 switch (intpin->io_irq) {
253 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
259 ioapic_enable_source(struct intsrc *isrc)
261 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
262 struct ioapic *io = (struct ioapic *)isrc->is_pic;
265 mtx_lock_spin(&icu_lock);
266 if (intpin->io_masked) {
267 flags = intpin->io_lowreg & ~IOART_INTMASK;
268 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
270 intpin->io_masked = 0;
272 mtx_unlock_spin(&icu_lock);
276 ioapic_disable_source(struct intsrc *isrc, int eoi)
278 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
279 struct ioapic *io = (struct ioapic *)isrc->is_pic;
282 mtx_lock_spin(&icu_lock);
283 if (!intpin->io_masked && !intpin->io_edgetrigger) {
284 flags = intpin->io_lowreg | IOART_INTMSET;
285 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
287 intpin->io_masked = 1;
291 _ioapic_eoi_source(isrc, 1);
293 mtx_unlock_spin(&icu_lock);
297 ioapic_eoi_source(struct intsrc *isrc)
300 _ioapic_eoi_source(isrc, 0);
304 * Completely program an intpin based on the data in its interrupt source
308 ioapic_program_intpin(struct ioapic_intsrc *intpin)
310 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
317 * If a pin is completely invalid or if it is valid but hasn't
318 * been enabled yet, just ensure that the pin is masked.
320 mtx_assert(&icu_lock, MA_OWNED);
321 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
322 intpin->io_vector == 0)) {
323 low = ioapic_read(io->io_addr,
324 IOAPIC_REDTBL_LO(intpin->io_intpin));
325 if ((low & IOART_INTMASK) == IOART_INTMCLR)
326 ioapic_write(io->io_addr,
327 IOAPIC_REDTBL_LO(intpin->io_intpin),
328 low | IOART_INTMSET);
330 mtx_unlock_spin(&icu_lock);
331 iommu_unmap_ioapic_intr(io->io_apic_id,
332 &intpin->io_remap_cookie);
333 mtx_lock_spin(&icu_lock);
339 mtx_unlock_spin(&icu_lock);
340 error = iommu_map_ioapic_intr(io->io_apic_id,
341 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
342 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
344 mtx_lock_spin(&icu_lock);
346 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
348 intpin->io_lowreg = low;
349 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
352 } else if (error != EOPNOTSUPP) {
358 * Set the destination. Note that with Intel interrupt remapping,
359 * the previously reserved bits 55:48 now have a purpose so ensure
363 high = intpin->io_cpu << APIC_ID_SHIFT;
365 /* Program the rest of the low word. */
366 if (intpin->io_edgetrigger)
367 low |= IOART_TRGREDG;
369 low |= IOART_TRGRLVL;
370 if (intpin->io_activehi)
374 if (intpin->io_masked)
375 low |= IOART_INTMSET;
376 switch (intpin->io_irq) {
378 KASSERT(intpin->io_edgetrigger,
379 ("ExtINT not edge triggered"));
380 low |= IOART_DELEXINT;
383 KASSERT(intpin->io_edgetrigger,
384 ("NMI not edge triggered"));
388 KASSERT(intpin->io_edgetrigger,
389 ("SMI not edge triggered"));
393 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
395 low |= IOART_DELFIXED | intpin->io_vector;
398 /* Write the values to the APIC. */
399 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high);
400 intpin->io_lowreg = low;
401 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
405 ioapic_reprogram_intpin(struct intsrc *isrc)
408 mtx_lock_spin(&icu_lock);
409 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
410 mtx_unlock_spin(&icu_lock);
414 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
416 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
417 struct ioapic *io = (struct ioapic *)isrc->is_pic;
418 u_int old_vector, new_vector;
423 * - Stick to the first cpu for all I/O APIC pins.
424 * - And don't allow destination cpu changes.
426 if (vm_guest == VM_GUEST_HV) {
427 if (intpin->io_vector)
434 * keep 1st core as the destination for NMI
436 if (intpin->io_irq == IRQ_NMI)
440 * Set us up to free the old irq.
442 old_vector = intpin->io_vector;
443 old_id = intpin->io_cpu;
444 if (old_vector && apic_id == old_id)
448 * Allocate an APIC vector for this interrupt pin. Once
449 * we have a vector we program the interrupt pin.
451 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
456 * Mask the old intpin if it is enabled while it is migrated.
458 * At least some level-triggered interrupts seem to need the
459 * extra DELAY() to avoid being stuck in a non-EOI'd state.
461 mtx_lock_spin(&icu_lock);
462 if (!intpin->io_masked && !intpin->io_edgetrigger) {
463 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
464 intpin->io_lowreg | IOART_INTMSET);
465 mtx_unlock_spin(&icu_lock);
467 mtx_lock_spin(&icu_lock);
470 intpin->io_cpu = apic_id;
471 intpin->io_vector = new_vector;
472 if (isrc->is_handlers > 0)
473 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
475 printf("ioapic%u: routing intpin %u (", io->io_id,
477 ioapic_print_irq(intpin);
478 printf(") to lapic %u vector %u\n", intpin->io_cpu,
481 ioapic_program_intpin(intpin);
482 mtx_unlock_spin(&icu_lock);
485 * Free the old vector after the new one is established. This is done
486 * to prevent races where we could miss an interrupt.
489 if (isrc->is_handlers > 0)
490 apic_disable_vector(old_id, old_vector);
491 apic_free_vector(old_id, old_vector, intpin->io_irq);
497 ioapic_enable_intr(struct intsrc *isrc)
499 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
501 if (intpin->io_vector == 0)
502 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
503 panic("Couldn't find an APIC vector for IRQ %d",
505 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
510 ioapic_disable_intr(struct intsrc *isrc)
512 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
515 if (intpin->io_vector != 0) {
516 /* Mask this interrupt pin and free its APIC vector. */
517 vector = intpin->io_vector;
518 apic_disable_vector(intpin->io_cpu, vector);
519 mtx_lock_spin(&icu_lock);
520 intpin->io_masked = 1;
521 intpin->io_vector = 0;
522 ioapic_program_intpin(intpin);
523 mtx_unlock_spin(&icu_lock);
524 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
529 ioapic_vector(struct intsrc *isrc)
531 struct ioapic_intsrc *pin;
533 pin = (struct ioapic_intsrc *)isrc;
534 return (pin->io_irq);
538 ioapic_source_pending(struct intsrc *isrc)
540 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
542 if (intpin->io_vector == 0)
544 return (lapic_intr_pending(intpin->io_vector));
548 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
549 enum intr_polarity pol)
551 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
552 struct ioapic *io = (struct ioapic *)isrc->is_pic;
555 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
556 ("%s: Conforming trigger or polarity\n", __func__));
559 * EISA interrupts always use active high polarity, so don't allow
560 * them to be set to active low.
562 * XXX: Should we write to the ELCR if the trigger mode changes for
563 * an EISA IRQ or an ISA IRQ with the ELCR present?
565 mtx_lock_spin(&icu_lock);
566 if (intpin->io_bus == APIC_BUS_EISA)
567 pol = INTR_POLARITY_HIGH;
569 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
571 printf("ioapic%u: Changing trigger for pin %u to %s\n",
572 io->io_id, intpin->io_intpin,
573 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
574 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
577 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
579 printf("ioapic%u: Changing polarity for pin %u to %s\n",
580 io->io_id, intpin->io_intpin,
581 pol == INTR_POLARITY_HIGH ? "high" : "low");
582 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
586 ioapic_program_intpin(intpin);
587 mtx_unlock_spin(&icu_lock);
592 ioapic_resume(struct pic *pic, bool suspend_cancelled)
594 struct ioapic *io = (struct ioapic *)pic;
597 mtx_lock_spin(&icu_lock);
598 for (i = 0; i < io->io_numintr; i++)
599 ioapic_program_intpin(&io->io_pins[i]);
600 mtx_unlock_spin(&icu_lock);
604 * Create a plain I/O APIC object.
607 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
610 struct ioapic_intsrc *intpin;
611 volatile ioapic_t *apic;
615 /* Map the register window so we can access the device. */
616 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
617 mtx_lock_spin(&icu_lock);
618 value = ioapic_read(apic, IOAPIC_VER);
619 mtx_unlock_spin(&icu_lock);
621 /* If it's version register doesn't seem to work, punt. */
622 if (value == 0xffffffff) {
623 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
627 /* Determine the number of vectors and set the APIC ID. */
628 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
629 io = malloc(sizeof(struct ioapic) +
630 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
631 io->io_pic = ioapic_template;
634 mtx_lock_spin(&icu_lock);
635 io->io_id = next_id++;
636 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
637 if (apic_id != -1 && io->io_apic_id != apic_id) {
638 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
639 mtx_unlock_spin(&icu_lock);
640 io->io_apic_id = apic_id;
641 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
644 mtx_unlock_spin(&icu_lock);
646 intbase = next_ioapic_base;
647 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
649 } else if (intbase != next_ioapic_base && bootverbose)
650 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
651 io->io_id, intbase, next_ioapic_base);
652 io->io_intbase = intbase;
653 next_ioapic_base = intbase + numintr;
654 io->io_numintr = numintr;
659 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
660 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
664 * The summary information about IO-APIC versions is taken from
665 * the Linux kernel source:
667 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
668 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
670 * IO-APICs with version >= 0x20 have working EOIR register.
672 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
675 * Initialize pins. Start off with interrupts disabled. Default
676 * to active-hi and edge-triggered for ISA interrupts and active-lo
677 * and level-triggered for all others.
679 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
680 mtx_lock_spin(&icu_lock);
681 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
682 intpin->io_intsrc.is_pic = (struct pic *)io;
683 intpin->io_intpin = i;
684 intpin->io_irq = intbase + i;
687 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
688 * Assume that pins 1-15 are ISA interrupts and that all
689 * other pins are PCI interrupts.
691 if (intpin->io_irq == 0)
692 ioapic_set_extint(io, i);
693 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
694 intpin->io_bus = APIC_BUS_ISA;
695 intpin->io_activehi = 1;
696 intpin->io_edgetrigger = 1;
697 intpin->io_masked = 1;
699 intpin->io_bus = APIC_BUS_PCI;
700 intpin->io_activehi = 0;
701 intpin->io_edgetrigger = 0;
702 intpin->io_masked = 1;
706 * Route interrupts to the BSP by default. Interrupts may
707 * be routed to other CPUs later after they are enabled.
709 intpin->io_cpu = PCPU_GET(apic_id);
710 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
711 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
713 /* dummy, but sets cookie */
714 mtx_unlock_spin(&icu_lock);
715 iommu_map_ioapic_intr(io->io_apic_id,
716 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
717 intpin->io_activehi, intpin->io_irq,
718 &intpin->io_remap_cookie, NULL, NULL);
719 mtx_lock_spin(&icu_lock);
722 mtx_unlock_spin(&icu_lock);
728 ioapic_get_vector(void *cookie, u_int pin)
732 io = (struct ioapic *)cookie;
733 if (pin >= io->io_numintr)
735 return (io->io_pins[pin].io_irq);
739 ioapic_disable_pin(void *cookie, u_int pin)
743 io = (struct ioapic *)cookie;
744 if (pin >= io->io_numintr)
746 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
748 io->io_pins[pin].io_irq = IRQ_DISABLED;
750 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
755 ioapic_remap_vector(void *cookie, u_int pin, int vector)
759 io = (struct ioapic *)cookie;
760 if (pin >= io->io_numintr || vector < 0)
762 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
764 io->io_pins[pin].io_irq = vector;
766 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
772 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
776 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
778 io = (struct ioapic *)cookie;
779 if (pin >= io->io_numintr)
781 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
783 if (io->io_pins[pin].io_bus == bus_type)
785 io->io_pins[pin].io_bus = bus_type;
787 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
788 ioapic_bus_string(bus_type));
793 ioapic_set_nmi(void *cookie, u_int pin)
797 io = (struct ioapic *)cookie;
798 if (pin >= io->io_numintr)
800 if (io->io_pins[pin].io_irq == IRQ_NMI)
802 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
804 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
805 io->io_pins[pin].io_irq = IRQ_NMI;
806 io->io_pins[pin].io_masked = 0;
807 io->io_pins[pin].io_edgetrigger = 1;
808 io->io_pins[pin].io_activehi = 1;
810 printf("ioapic%u: Routing NMI -> intpin %d\n",
816 ioapic_set_smi(void *cookie, u_int pin)
820 io = (struct ioapic *)cookie;
821 if (pin >= io->io_numintr)
823 if (io->io_pins[pin].io_irq == IRQ_SMI)
825 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
827 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
828 io->io_pins[pin].io_irq = IRQ_SMI;
829 io->io_pins[pin].io_masked = 0;
830 io->io_pins[pin].io_edgetrigger = 1;
831 io->io_pins[pin].io_activehi = 1;
833 printf("ioapic%u: Routing SMI -> intpin %d\n",
839 ioapic_set_extint(void *cookie, u_int pin)
843 io = (struct ioapic *)cookie;
844 if (pin >= io->io_numintr)
846 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
848 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
850 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
851 io->io_pins[pin].io_irq = IRQ_EXTINT;
853 io->io_pins[pin].io_masked = 0;
855 io->io_pins[pin].io_masked = 1;
856 io->io_pins[pin].io_edgetrigger = 1;
857 io->io_pins[pin].io_activehi = 1;
859 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
865 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
870 io = (struct ioapic *)cookie;
871 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
873 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
875 activehi = (pol == INTR_POLARITY_HIGH);
876 if (io->io_pins[pin].io_activehi == activehi)
878 io->io_pins[pin].io_activehi = activehi;
880 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
881 pol == INTR_POLARITY_HIGH ? "high" : "low");
886 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
891 io = (struct ioapic *)cookie;
892 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
894 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
896 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
897 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
899 io->io_pins[pin].io_edgetrigger = edgetrigger;
901 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
902 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
907 * Register a complete I/O APIC object with the interrupt subsystem.
910 ioapic_register(void *cookie)
912 struct ioapic_intsrc *pin;
914 volatile ioapic_t *apic;
918 io = (struct ioapic *)cookie;
920 mtx_lock_spin(&icu_lock);
921 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
922 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
923 mtx_unlock_spin(&icu_lock);
924 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
925 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
926 io->io_intbase + io->io_numintr - 1);
929 * Reprogram pins to handle special case pins (such as NMI and
930 * SMI) and register valid pins as interrupt sources.
932 intr_register_pic(&io->io_pic);
933 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
934 ioapic_reprogram_intpin(&pin->io_intsrc);
935 if (pin->io_irq < NUM_IO_INTS)
936 intr_register_source(&pin->io_intsrc);
940 /* A simple new-bus driver to consume PCI I/O APIC devices. */
942 ioapic_pci_probe(device_t dev)
945 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
946 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
947 switch (pci_get_progif(dev)) {
948 case PCIP_BASEPERIPH_PIC_IO_APIC:
949 device_set_desc(dev, "IO APIC");
951 case PCIP_BASEPERIPH_PIC_IOX_APIC:
952 device_set_desc(dev, "IO(x) APIC");
964 ioapic_pci_attach(device_t dev)
966 struct resource *res;
967 volatile ioapic_t *apic;
973 * Try to match the enumerated ioapic. Match BAR start
974 * against io_paddr. Due to a fear that PCI window is not the
975 * same as the MADT reported io window, but an alias, read the
976 * APIC ID from the mapped BAR and match against it.
979 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
980 RF_ACTIVE | RF_SHAREABLE);
983 device_printf(dev, "cannot activate BAR0\n");
986 apic = (volatile ioapic_t *)rman_get_virtual(res);
987 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
990 "BAR0 too small (%jd) for IOAPIC window\n",
991 (uintmax_t)rman_get_size(res));
994 mtx_lock_spin(&icu_lock);
995 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
996 /* First match by io window address */
997 STAILQ_FOREACH(io, &ioapic_list, io_next) {
998 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
1001 /* Then by apic id */
1002 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1003 if (io->io_apic_id == apic_id)
1006 mtx_unlock_spin(&icu_lock);
1009 "cannot match pci bar apic id %d against MADT\n",
1012 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1015 KASSERT(io->pci_dev == NULL,
1016 ("ioapic %d pci_dev not NULL", io->io_id));
1017 KASSERT(io->pci_wnd == NULL,
1018 ("ioapic %d pci_wnd not NULL", io->io_id));
1022 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1023 io->io_apic_id != apic_id)) {
1024 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1025 "MADT id %d paddr@%jx\n",
1026 pci_get_domain(dev), pci_get_bus(dev),
1027 pci_get_slot(dev), pci_get_function(dev),
1028 (uintmax_t)rman_get_start(res), apic_id,
1029 io->io_apic_id, (uintmax_t)io->io_paddr);
1031 mtx_unlock_spin(&icu_lock);
1035 static device_method_t ioapic_pci_methods[] = {
1036 /* Device interface */
1037 DEVMETHOD(device_probe, ioapic_pci_probe),
1038 DEVMETHOD(device_attach, ioapic_pci_attach),
1043 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1045 static devclass_t ioapic_devclass;
1046 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
1049 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1055 mtx_lock_spin(&icu_lock);
1056 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1057 if (io->io_apic_id == apic_id)
1060 mtx_unlock_spin(&icu_lock);
1061 if (io == NULL || io->pci_dev == NULL)
1063 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1071 * A new-bus driver to consume the memory resources associated with
1072 * the APICs in the system. On some systems ACPI or PnPBIOS system
1073 * resource devices may already claim these resources. To keep from
1074 * breaking those devices, we attach ourself to the nexus device after
1075 * legacy0 and acpi0 and ignore any allocation failures.
1078 apic_identify(driver_t *driver, device_t parent)
1082 * Add at order 12. acpi0 is probed at order 10 and legacy0
1083 * is probed at order 11.
1085 if (lapic_paddr != 0)
1086 BUS_ADD_CHILD(parent, 12, "apic", 0);
1090 apic_probe(device_t dev)
1093 device_set_desc(dev, "APIC resources");
1099 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1103 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1105 panic("apic_add_resource: resource %d failed set with %d", rid,
1107 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1111 apic_attach(device_t dev)
1116 /* Reserve the local APIC. */
1117 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1119 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1120 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1126 static device_method_t apic_methods[] = {
1127 /* Device interface */
1128 DEVMETHOD(device_identify, apic_identify),
1129 DEVMETHOD(device_probe, apic_probe),
1130 DEVMETHOD(device_attach, apic_attach),
1135 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1137 static devclass_t apic_devclass;
1138 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
1140 #include "opt_ddb.h"
1143 #include <ddb/ddb.h>
1146 ioapic_delivery_mode(uint32_t mode)
1150 case IOART_DELFIXED:
1152 case IOART_DELLOPRI:
1153 return ("lowestpri");
1164 case IOART_DELEXINT:
1172 db_ioapic_read(volatile ioapic_t *apic, int reg)
1175 apic->ioregsel = reg;
1176 return (apic->iowin);
1180 db_show_ioapic_one(volatile ioapic_t *io_addr)
1185 r = db_ioapic_read(io_addr, IOAPIC_VER);
1186 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1187 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1188 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1189 for (i = 0; i < mre; i++) {
1190 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1191 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1192 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1193 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1194 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1195 (hi & IOART_DEST) >> 24,
1196 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1197 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1198 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1199 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1200 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1201 ioapic_delivery_mode(lo & IOART_DELMOD),
1202 (lo & IOART_INTVEC));
1206 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1208 struct ioapic *ioapic;
1212 db_printf("usage: show ioapic index\n");
1218 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1220 db_show_ioapic_one(ioapic->io_addr);
1227 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1229 struct ioapic *ioapic;
1231 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1232 db_show_ioapic_one(ioapic->io_addr);