2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
52 #include <x86/apicreg.h>
53 #include <machine/frame.h>
54 #include <machine/intr_machdep.h>
55 #include <x86/apicvar.h>
56 #include <machine/resource.h>
57 #include <machine/segments.h>
58 #include <x86/iommu/iommu_intrmap.h>
60 #define IOAPIC_ISA_INTS 16
61 #define IOAPIC_MEM_REGION 32
62 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
63 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
65 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
68 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
69 * as laid out in the ACPI System Interrupt number model where each I/O
70 * APIC has a contiguous chunk of the System Interrupt address space.
71 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
72 * IRQs behave as PCI IRQs by default. We also assume that the pin for
73 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
74 * configuration of individual pins as indicated by their tables.
76 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
77 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
78 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
81 struct ioapic_intsrc {
82 struct intsrc io_intsrc;
88 u_int io_edgetrigger:1;
92 u_int io_remap_cookie;
97 u_int io_id:8; /* logical ID */
99 u_int io_intbase:8; /* System Interrupt base */
102 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
104 STAILQ_ENTRY(ioapic) io_next;
105 device_t pci_dev; /* matched pci device, if found */
106 struct resource *pci_wnd; /* BAR 0, should be same or alias to
108 struct ioapic_intsrc io_pins[0];
111 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
112 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
113 static const char *ioapic_bus_string(int bus_type);
114 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
115 static void ioapic_enable_source(struct intsrc *isrc);
116 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
117 static void ioapic_eoi_source(struct intsrc *isrc);
118 static void ioapic_enable_intr(struct intsrc *isrc);
119 static void ioapic_disable_intr(struct intsrc *isrc);
120 static int ioapic_vector(struct intsrc *isrc);
121 static int ioapic_source_pending(struct intsrc *isrc);
122 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
123 enum intr_polarity pol);
124 static void ioapic_resume(struct pic *pic, bool suspend_cancelled);
125 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
126 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
127 static void ioapic_reprogram_intpin(struct intsrc *isrc);
129 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
130 struct pic ioapic_template = {
131 .pic_enable_source = ioapic_enable_source,
132 .pic_disable_source = ioapic_disable_source,
133 .pic_eoi_source = ioapic_eoi_source,
134 .pic_enable_intr = ioapic_enable_intr,
135 .pic_disable_intr = ioapic_disable_intr,
136 .pic_vector = ioapic_vector,
137 .pic_source_pending = ioapic_source_pending,
139 .pic_resume = ioapic_resume,
140 .pic_config_intr = ioapic_config_intr,
141 .pic_assign_cpu = ioapic_assign_cpu,
142 .pic_reprogram_pin = ioapic_reprogram_intpin,
145 static int next_ioapic_base;
146 static u_int next_id;
148 static int enable_extint;
149 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
150 "Enable the ExtINT pin in the first I/O APIC");
153 _ioapic_eoi_source(struct intsrc *isrc, int locked)
155 struct ioapic_intsrc *src;
157 volatile uint32_t *apic_eoi;
161 if (!lapic_eoi_suppression)
163 src = (struct ioapic_intsrc *)isrc;
164 if (src->io_edgetrigger)
166 io = (struct ioapic *)isrc->is_pic;
169 * Handle targeted EOI for level-triggered pins, if broadcast
170 * EOI suppression is supported by LAPICs.
174 * If IOAPIC has EOI Register, simply write vector
175 * number into the reg.
177 apic_eoi = (volatile uint32_t *)((volatile char *)
178 io->io_addr + IOAPIC_EOIR);
179 *apic_eoi = src->io_vector;
182 * Otherwise, if IO-APIC is too old to provide EOIR,
183 * do what Intel did for the Linux kernel. Temporary
184 * switch the pin to edge-trigger and back, masking
185 * the pin during the trick.
188 mtx_lock_spin(&icu_lock);
189 low1 = src->io_lowreg;
190 low1 &= ~IOART_TRGRLVL;
191 low1 |= IOART_TRGREDG | IOART_INTMSET;
192 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
194 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(src->io_intpin),
197 mtx_unlock_spin(&icu_lock);
202 ioapic_read(volatile ioapic_t *apic, int reg)
205 mtx_assert(&icu_lock, MA_OWNED);
206 apic->ioregsel = reg;
207 return (apic->iowin);
211 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
214 mtx_assert(&icu_lock, MA_OWNED);
215 apic->ioregsel = reg;
220 ioapic_bus_string(int bus_type)
236 ioapic_print_irq(struct ioapic_intsrc *intpin)
239 switch (intpin->io_irq) {
253 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
259 ioapic_enable_source(struct intsrc *isrc)
261 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
262 struct ioapic *io = (struct ioapic *)isrc->is_pic;
265 mtx_lock_spin(&icu_lock);
266 if (intpin->io_masked) {
267 flags = intpin->io_lowreg & ~IOART_INTMASK;
268 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
270 intpin->io_masked = 0;
272 mtx_unlock_spin(&icu_lock);
276 ioapic_disable_source(struct intsrc *isrc, int eoi)
278 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
279 struct ioapic *io = (struct ioapic *)isrc->is_pic;
282 mtx_lock_spin(&icu_lock);
283 if (!intpin->io_masked && !intpin->io_edgetrigger) {
284 flags = intpin->io_lowreg | IOART_INTMSET;
285 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
287 intpin->io_masked = 1;
291 _ioapic_eoi_source(isrc, 1);
293 mtx_unlock_spin(&icu_lock);
297 ioapic_eoi_source(struct intsrc *isrc)
300 _ioapic_eoi_source(isrc, 0);
304 * Completely program an intpin based on the data in its interrupt source
308 ioapic_program_intpin(struct ioapic_intsrc *intpin)
310 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
311 uint32_t low, high, value;
317 * If a pin is completely invalid or if it is valid but hasn't
318 * been enabled yet, just ensure that the pin is masked.
320 mtx_assert(&icu_lock, MA_OWNED);
321 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
322 intpin->io_vector == 0)) {
323 low = ioapic_read(io->io_addr,
324 IOAPIC_REDTBL_LO(intpin->io_intpin));
325 if ((low & IOART_INTMASK) == IOART_INTMCLR)
326 ioapic_write(io->io_addr,
327 IOAPIC_REDTBL_LO(intpin->io_intpin),
328 low | IOART_INTMSET);
330 mtx_unlock_spin(&icu_lock);
331 iommu_unmap_ioapic_intr(io->io_apic_id,
332 &intpin->io_remap_cookie);
333 mtx_lock_spin(&icu_lock);
339 mtx_unlock_spin(&icu_lock);
340 error = iommu_map_ioapic_intr(io->io_apic_id,
341 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
342 intpin->io_activehi, intpin->io_irq, &intpin->io_remap_cookie,
344 mtx_lock_spin(&icu_lock);
346 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin),
348 intpin->io_lowreg = low;
349 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
352 } else if (error != EOPNOTSUPP) {
357 /* Set the destination. */
359 high = intpin->io_cpu << APIC_ID_SHIFT;
361 /* Program the rest of the low word. */
362 if (intpin->io_edgetrigger)
363 low |= IOART_TRGREDG;
365 low |= IOART_TRGRLVL;
366 if (intpin->io_activehi)
370 if (intpin->io_masked)
371 low |= IOART_INTMSET;
372 switch (intpin->io_irq) {
374 KASSERT(intpin->io_edgetrigger,
375 ("ExtINT not edge triggered"));
376 low |= IOART_DELEXINT;
379 KASSERT(intpin->io_edgetrigger,
380 ("NMI not edge triggered"));
384 KASSERT(intpin->io_edgetrigger,
385 ("SMI not edge triggered"));
389 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
391 low |= IOART_DELFIXED | intpin->io_vector;
394 /* Write the values to the APIC. */
395 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
396 value &= ~IOART_DEST;
398 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
399 intpin->io_lowreg = low;
400 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
404 ioapic_reprogram_intpin(struct intsrc *isrc)
407 mtx_lock_spin(&icu_lock);
408 ioapic_program_intpin((struct ioapic_intsrc *)isrc);
409 mtx_unlock_spin(&icu_lock);
413 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
415 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
416 struct ioapic *io = (struct ioapic *)isrc->is_pic;
417 u_int old_vector, new_vector;
422 * - Stick to the first cpu for all I/O APIC pins.
423 * - And don't allow destination cpu changes.
425 if (vm_guest == VM_GUEST_HV) {
426 if (intpin->io_vector)
433 * keep 1st core as the destination for NMI
435 if (intpin->io_irq == IRQ_NMI)
439 * Set us up to free the old irq.
441 old_vector = intpin->io_vector;
442 old_id = intpin->io_cpu;
443 if (old_vector && apic_id == old_id)
447 * Allocate an APIC vector for this interrupt pin. Once
448 * we have a vector we program the interrupt pin.
450 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
455 * Mask the old intpin if it is enabled while it is migrated.
457 * At least some level-triggered interrupts seem to need the
458 * extra DELAY() to avoid being stuck in a non-EOI'd state.
460 mtx_lock_spin(&icu_lock);
461 if (!intpin->io_masked && !intpin->io_edgetrigger) {
462 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
463 intpin->io_lowreg | IOART_INTMSET);
464 mtx_unlock_spin(&icu_lock);
466 mtx_lock_spin(&icu_lock);
469 intpin->io_cpu = apic_id;
470 intpin->io_vector = new_vector;
471 if (isrc->is_handlers > 0)
472 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
474 printf("ioapic%u: routing intpin %u (", io->io_id,
476 ioapic_print_irq(intpin);
477 printf(") to lapic %u vector %u\n", intpin->io_cpu,
480 ioapic_program_intpin(intpin);
481 mtx_unlock_spin(&icu_lock);
484 * Free the old vector after the new one is established. This is done
485 * to prevent races where we could miss an interrupt.
488 if (isrc->is_handlers > 0)
489 apic_disable_vector(old_id, old_vector);
490 apic_free_vector(old_id, old_vector, intpin->io_irq);
496 ioapic_enable_intr(struct intsrc *isrc)
498 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
500 if (intpin->io_vector == 0)
501 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
502 panic("Couldn't find an APIC vector for IRQ %d",
504 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
509 ioapic_disable_intr(struct intsrc *isrc)
511 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
514 if (intpin->io_vector != 0) {
515 /* Mask this interrupt pin and free its APIC vector. */
516 vector = intpin->io_vector;
517 apic_disable_vector(intpin->io_cpu, vector);
518 mtx_lock_spin(&icu_lock);
519 intpin->io_masked = 1;
520 intpin->io_vector = 0;
521 ioapic_program_intpin(intpin);
522 mtx_unlock_spin(&icu_lock);
523 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
528 ioapic_vector(struct intsrc *isrc)
530 struct ioapic_intsrc *pin;
532 pin = (struct ioapic_intsrc *)isrc;
533 return (pin->io_irq);
537 ioapic_source_pending(struct intsrc *isrc)
539 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
541 if (intpin->io_vector == 0)
543 return (lapic_intr_pending(intpin->io_vector));
547 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
548 enum intr_polarity pol)
550 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
551 struct ioapic *io = (struct ioapic *)isrc->is_pic;
554 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
555 ("%s: Conforming trigger or polarity\n", __func__));
558 * EISA interrupts always use active high polarity, so don't allow
559 * them to be set to active low.
561 * XXX: Should we write to the ELCR if the trigger mode changes for
562 * an EISA IRQ or an ISA IRQ with the ELCR present?
564 mtx_lock_spin(&icu_lock);
565 if (intpin->io_bus == APIC_BUS_EISA)
566 pol = INTR_POLARITY_HIGH;
568 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
570 printf("ioapic%u: Changing trigger for pin %u to %s\n",
571 io->io_id, intpin->io_intpin,
572 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
573 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
576 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
578 printf("ioapic%u: Changing polarity for pin %u to %s\n",
579 io->io_id, intpin->io_intpin,
580 pol == INTR_POLARITY_HIGH ? "high" : "low");
581 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
585 ioapic_program_intpin(intpin);
586 mtx_unlock_spin(&icu_lock);
591 ioapic_resume(struct pic *pic, bool suspend_cancelled)
593 struct ioapic *io = (struct ioapic *)pic;
596 mtx_lock_spin(&icu_lock);
597 for (i = 0; i < io->io_numintr; i++)
598 ioapic_program_intpin(&io->io_pins[i]);
599 mtx_unlock_spin(&icu_lock);
603 * Create a plain I/O APIC object.
606 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
609 struct ioapic_intsrc *intpin;
610 volatile ioapic_t *apic;
614 /* Map the register window so we can access the device. */
615 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
616 mtx_lock_spin(&icu_lock);
617 value = ioapic_read(apic, IOAPIC_VER);
618 mtx_unlock_spin(&icu_lock);
620 /* If it's version register doesn't seem to work, punt. */
621 if (value == 0xffffffff) {
622 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
626 /* Determine the number of vectors and set the APIC ID. */
627 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
628 io = malloc(sizeof(struct ioapic) +
629 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
630 io->io_pic = ioapic_template;
633 mtx_lock_spin(&icu_lock);
634 io->io_id = next_id++;
635 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
636 if (apic_id != -1 && io->io_apic_id != apic_id) {
637 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
638 mtx_unlock_spin(&icu_lock);
639 io->io_apic_id = apic_id;
640 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
643 mtx_unlock_spin(&icu_lock);
645 intbase = next_ioapic_base;
646 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
648 } else if (intbase != next_ioapic_base && bootverbose)
649 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
650 io->io_id, intbase, next_ioapic_base);
651 io->io_intbase = intbase;
652 next_ioapic_base = intbase + numintr;
653 io->io_numintr = numintr;
658 printf("ioapic%u: ver 0x%02x maxredir 0x%02x\n", io->io_id,
659 (value & IOART_VER_VERSION), (value & IOART_VER_MAXREDIR)
663 * The summary information about IO-APIC versions is taken from
664 * the Linux kernel source:
666 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
667 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
669 * IO-APICs with version >= 0x20 have working EOIR register.
671 io->io_haseoi = (value & IOART_VER_VERSION) >= 0x20;
674 * Initialize pins. Start off with interrupts disabled. Default
675 * to active-hi and edge-triggered for ISA interrupts and active-lo
676 * and level-triggered for all others.
678 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
679 mtx_lock_spin(&icu_lock);
680 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
681 intpin->io_intsrc.is_pic = (struct pic *)io;
682 intpin->io_intpin = i;
683 intpin->io_irq = intbase + i;
686 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
687 * Assume that pins 1-15 are ISA interrupts and that all
688 * other pins are PCI interrupts.
690 if (intpin->io_irq == 0)
691 ioapic_set_extint(io, i);
692 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
693 intpin->io_bus = APIC_BUS_ISA;
694 intpin->io_activehi = 1;
695 intpin->io_edgetrigger = 1;
696 intpin->io_masked = 1;
698 intpin->io_bus = APIC_BUS_PCI;
699 intpin->io_activehi = 0;
700 intpin->io_edgetrigger = 0;
701 intpin->io_masked = 1;
705 * Route interrupts to the BSP by default. Interrupts may
706 * be routed to other CPUs later after they are enabled.
708 intpin->io_cpu = PCPU_GET(apic_id);
709 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
710 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
712 /* dummy, but sets cookie */
713 mtx_unlock_spin(&icu_lock);
714 iommu_map_ioapic_intr(io->io_apic_id,
715 intpin->io_cpu, intpin->io_vector, intpin->io_edgetrigger,
716 intpin->io_activehi, intpin->io_irq,
717 &intpin->io_remap_cookie, NULL, NULL);
718 mtx_lock_spin(&icu_lock);
721 mtx_unlock_spin(&icu_lock);
727 ioapic_get_vector(void *cookie, u_int pin)
731 io = (struct ioapic *)cookie;
732 if (pin >= io->io_numintr)
734 return (io->io_pins[pin].io_irq);
738 ioapic_disable_pin(void *cookie, u_int pin)
742 io = (struct ioapic *)cookie;
743 if (pin >= io->io_numintr)
745 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
747 io->io_pins[pin].io_irq = IRQ_DISABLED;
749 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
754 ioapic_remap_vector(void *cookie, u_int pin, int vector)
758 io = (struct ioapic *)cookie;
759 if (pin >= io->io_numintr || vector < 0)
761 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
763 io->io_pins[pin].io_irq = vector;
765 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
771 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
775 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
777 io = (struct ioapic *)cookie;
778 if (pin >= io->io_numintr)
780 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
782 if (io->io_pins[pin].io_bus == bus_type)
784 io->io_pins[pin].io_bus = bus_type;
786 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
787 ioapic_bus_string(bus_type));
792 ioapic_set_nmi(void *cookie, u_int pin)
796 io = (struct ioapic *)cookie;
797 if (pin >= io->io_numintr)
799 if (io->io_pins[pin].io_irq == IRQ_NMI)
801 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
803 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
804 io->io_pins[pin].io_irq = IRQ_NMI;
805 io->io_pins[pin].io_masked = 0;
806 io->io_pins[pin].io_edgetrigger = 1;
807 io->io_pins[pin].io_activehi = 1;
809 printf("ioapic%u: Routing NMI -> intpin %d\n",
815 ioapic_set_smi(void *cookie, u_int pin)
819 io = (struct ioapic *)cookie;
820 if (pin >= io->io_numintr)
822 if (io->io_pins[pin].io_irq == IRQ_SMI)
824 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
826 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
827 io->io_pins[pin].io_irq = IRQ_SMI;
828 io->io_pins[pin].io_masked = 0;
829 io->io_pins[pin].io_edgetrigger = 1;
830 io->io_pins[pin].io_activehi = 1;
832 printf("ioapic%u: Routing SMI -> intpin %d\n",
838 ioapic_set_extint(void *cookie, u_int pin)
842 io = (struct ioapic *)cookie;
843 if (pin >= io->io_numintr)
845 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
847 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
849 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
850 io->io_pins[pin].io_irq = IRQ_EXTINT;
852 io->io_pins[pin].io_masked = 0;
854 io->io_pins[pin].io_masked = 1;
855 io->io_pins[pin].io_edgetrigger = 1;
856 io->io_pins[pin].io_activehi = 1;
858 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
864 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
869 io = (struct ioapic *)cookie;
870 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
872 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
874 activehi = (pol == INTR_POLARITY_HIGH);
875 if (io->io_pins[pin].io_activehi == activehi)
877 io->io_pins[pin].io_activehi = activehi;
879 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
880 pol == INTR_POLARITY_HIGH ? "high" : "low");
885 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
890 io = (struct ioapic *)cookie;
891 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
893 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
895 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
896 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
898 io->io_pins[pin].io_edgetrigger = edgetrigger;
900 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
901 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
906 * Register a complete I/O APIC object with the interrupt subsystem.
909 ioapic_register(void *cookie)
911 struct ioapic_intsrc *pin;
913 volatile ioapic_t *apic;
917 io = (struct ioapic *)cookie;
919 mtx_lock_spin(&icu_lock);
920 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
921 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
922 mtx_unlock_spin(&icu_lock);
923 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
924 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
925 io->io_intbase + io->io_numintr - 1);
928 * Reprogram pins to handle special case pins (such as NMI and
929 * SMI) and register valid pins as interrupt sources.
931 intr_register_pic(&io->io_pic);
932 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
933 ioapic_reprogram_intpin(&pin->io_intsrc);
934 if (pin->io_irq < NUM_IO_INTS)
935 intr_register_source(&pin->io_intsrc);
939 /* A simple new-bus driver to consume PCI I/O APIC devices. */
941 ioapic_pci_probe(device_t dev)
944 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
945 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
946 switch (pci_get_progif(dev)) {
947 case PCIP_BASEPERIPH_PIC_IO_APIC:
948 device_set_desc(dev, "IO APIC");
950 case PCIP_BASEPERIPH_PIC_IOX_APIC:
951 device_set_desc(dev, "IO(x) APIC");
963 ioapic_pci_attach(device_t dev)
965 struct resource *res;
966 volatile ioapic_t *apic;
972 * Try to match the enumerated ioapic. Match BAR start
973 * against io_paddr. Due to a fear that PCI window is not the
974 * same as the MADT reported io window, but an alias, read the
975 * APIC ID from the mapped BAR and match against it.
978 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
979 RF_ACTIVE | RF_SHAREABLE);
982 device_printf(dev, "cannot activate BAR0\n");
985 apic = (volatile ioapic_t *)rman_get_virtual(res);
986 if (rman_get_size(res) < IOAPIC_WND_SIZE) {
989 "BAR0 too small (%jd) for IOAPIC window\n",
990 (uintmax_t)rman_get_size(res));
993 mtx_lock_spin(&icu_lock);
994 apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
995 /* First match by io window address */
996 STAILQ_FOREACH(io, &ioapic_list, io_next) {
997 if (io->io_paddr == (vm_paddr_t)rman_get_start(res))
1000 /* Then by apic id */
1001 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1002 if (io->io_apic_id == apic_id)
1005 mtx_unlock_spin(&icu_lock);
1008 "cannot match pci bar apic id %d against MADT\n",
1011 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
1014 KASSERT(io->pci_dev == NULL,
1015 ("ioapic %d pci_dev not NULL", io->io_id));
1016 KASSERT(io->pci_wnd == NULL,
1017 ("ioapic %d pci_wnd not NULL", io->io_id));
1021 if (bootverbose && (io->io_paddr != (vm_paddr_t)rman_get_start(res) ||
1022 io->io_apic_id != apic_id)) {
1023 device_printf(dev, "pci%d:%d:%d:%d pci BAR0@%jx id %d "
1024 "MADT id %d paddr@%jx\n",
1025 pci_get_domain(dev), pci_get_bus(dev),
1026 pci_get_slot(dev), pci_get_function(dev),
1027 (uintmax_t)rman_get_start(res), apic_id,
1028 io->io_apic_id, (uintmax_t)io->io_paddr);
1030 mtx_unlock_spin(&icu_lock);
1034 static device_method_t ioapic_pci_methods[] = {
1035 /* Device interface */
1036 DEVMETHOD(device_probe, ioapic_pci_probe),
1037 DEVMETHOD(device_attach, ioapic_pci_attach),
1042 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
1044 static devclass_t ioapic_devclass;
1045 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
1048 ioapic_get_rid(u_int apic_id, uint16_t *ridp)
1054 mtx_lock_spin(&icu_lock);
1055 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1056 if (io->io_apic_id == apic_id)
1059 mtx_unlock_spin(&icu_lock);
1060 if (io == NULL || io->pci_dev == NULL)
1062 error = pci_get_id(io->pci_dev, PCI_ID_RID, &rid);
1070 * A new-bus driver to consume the memory resources associated with
1071 * the APICs in the system. On some systems ACPI or PnPBIOS system
1072 * resource devices may already claim these resources. To keep from
1073 * breaking those devices, we attach ourself to the nexus device after
1074 * legacy0 and acpi0 and ignore any allocation failures.
1077 apic_identify(driver_t *driver, device_t parent)
1081 * Add at order 12. acpi0 is probed at order 10 and legacy0
1082 * is probed at order 11.
1084 if (lapic_paddr != 0)
1085 BUS_ADD_CHILD(parent, 12, "apic", 0);
1089 apic_probe(device_t dev)
1092 device_set_desc(dev, "APIC resources");
1098 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
1102 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
1104 panic("apic_add_resource: resource %d failed set with %d", rid,
1106 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_SHAREABLE);
1110 apic_attach(device_t dev)
1115 /* Reserve the local APIC. */
1116 apic_add_resource(dev, 0, lapic_paddr, LAPIC_MEM_REGION);
1118 STAILQ_FOREACH(io, &ioapic_list, io_next) {
1119 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
1125 static device_method_t apic_methods[] = {
1126 /* Device interface */
1127 DEVMETHOD(device_identify, apic_identify),
1128 DEVMETHOD(device_probe, apic_probe),
1129 DEVMETHOD(device_attach, apic_attach),
1134 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
1136 static devclass_t apic_devclass;
1137 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
1139 #include "opt_ddb.h"
1142 #include <ddb/ddb.h>
1145 ioapic_delivery_mode(uint32_t mode)
1149 case IOART_DELFIXED:
1151 case IOART_DELLOPRI:
1152 return ("lowestpri");
1163 case IOART_DELEXINT:
1171 db_ioapic_read(volatile ioapic_t *apic, int reg)
1174 apic->ioregsel = reg;
1175 return (apic->iowin);
1179 db_show_ioapic_one(volatile ioapic_t *io_addr)
1184 r = db_ioapic_read(io_addr, IOAPIC_VER);
1185 mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT;
1186 db_printf("Id 0x%08x Ver 0x%02x MRE %d\n",
1187 db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre);
1188 for (i = 0; i < mre; i++) {
1189 lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i));
1190 hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i));
1191 db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d "
1192 "Polarity %s Status %s DeliveryMode %s Vec %d\n", i,
1193 (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy",
1194 (hi & IOART_DEST) >> 24,
1195 (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not",
1196 (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge",
1197 (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0,
1198 (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high",
1199 (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle",
1200 ioapic_delivery_mode(lo & IOART_DELMOD),
1201 (lo & IOART_INTVEC));
1205 DB_SHOW_COMMAND(ioapic, db_show_ioapic)
1207 struct ioapic *ioapic;
1211 db_printf("usage: show ioapic index\n");
1217 STAILQ_FOREACH(ioapic, &ioapic_list, io_next) {
1219 db_show_ioapic_one(ioapic->io_addr);
1226 DB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics)
1228 struct ioapic *ioapic;
1230 STAILQ_FOREACH(ioapic, &ioapic_list, io_next)
1231 db_show_ioapic_one(ioapic->io_addr);